From ccf303ee8a9d08cb80ed230c01fb93153dedf543 Mon Sep 17 00:00:00 2001 From: Archit Taneja Date: Thu, 2 Dec 2010 11:27:13 +0000 Subject: [PATCH] --- yaml --- r: 230496 b: refs/heads/master c: 6ced40bfc01f016de89b65d9c733c1fb5eeb06d0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/video/omap2/dss/dispc.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 1f6ce64888d0..8978e709cf7a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2a205f34b8fb2b86887b177befa7b42efd7a60b9 +refs/heads/master: 6ced40bfc01f016de89b65d9c733c1fb5eeb06d0 diff --git a/trunk/drivers/video/omap2/dss/dispc.c b/trunk/drivers/video/omap2/dss/dispc.c index fe41d891fd42..6171bcc589f8 100644 --- a/trunk/drivers/video/omap2/dss/dispc.c +++ b/trunk/drivers/video/omap2/dss/dispc.c @@ -1922,6 +1922,9 @@ void dispc_enable_channel(enum omap_channel channel, bool enable) void dispc_lcd_enable_signal_polarity(bool act_high) { + if (!dss_has_feature(FEAT_LCDENABLEPOL)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); enable_clocks(0); @@ -1929,6 +1932,9 @@ void dispc_lcd_enable_signal_polarity(bool act_high) void dispc_lcd_enable_signal(bool enable) { + if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); enable_clocks(0); @@ -1936,6 +1942,9 @@ void dispc_lcd_enable_signal(bool enable) void dispc_pck_free_enable(bool enable) { + if (!dss_has_feature(FEAT_PCKFREEENABLE)) + return; + enable_clocks(1); REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); enable_clocks(0); @@ -3246,7 +3255,8 @@ static void _omap_dispc_initial_config(void) dispc_write_reg(DISPC_SYSCONFIG, l); /* FUNCGATED */ - REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); + if (dss_has_feature(FEAT_FUNCGATED)) + REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); /* L3 firewall setting: enable access to OCM RAM */ /* XXX this should be somewhere in plat-omap */