From cd05118a0a8c2ce47eb0def3303c0d6d3b972b50 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 31 Oct 2012 18:12:49 -0200 Subject: [PATCH] --- yaml --- r: 345249 b: refs/heads/master c: 25f3ef11cda25c71e14011990f6ad5e587c3c214 h: refs/heads/master i: 345247: 7921171a16694c1d56dca07b18727fc1a3b197a4 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 4a66f9f22fdf..36763a3450f5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 937bb610b2b4c99946260cd64ab3cb562ec41b65 +refs/heads/master: 25f3ef11cda25c71e14011990f6ad5e587c3c214 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 9c25199a5e4a..43ad1a556b3c 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -1729,16 +1729,15 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_tx_enabled(dev_priv, cpu_transcoder); assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); - val = I915_READ(_TRANSACONF); + val = TRANS_ENABLE; pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); - val &= ~TRANS_INTERLACE_MASK; if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) val |= TRANS_INTERLACED; else val |= TRANS_PROGRESSIVE; - I915_WRITE(_TRANSACONF, val | TRANS_ENABLE); + I915_WRITE(TRANSCONF(TRANSCODER_A), val); if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) DRM_ERROR("Failed to enable PCH transcoder\n"); }