From cd8626fd97d1ea5df1a3e4538d53ec07513c4abc Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Thu, 8 Mar 2007 18:12:17 +0900
Subject: [PATCH] --- yaml --- r: 54343 b: refs/heads/master c:
 45ed285b54930767937deb0eaf718b1d08c3c475 h: refs/heads/master i:   54341:
 5ed3df783aa49de91a7d5c982ffe61a835a76469   54339:
 2d752abe2f9bdaaea217bda9709c17536845a50a   54335:
 602210dfda7922adc25ed4524b10a0e54de0e5e4 v: v3

---
 [refs]                          |  2 +-
 trunk/arch/sh/Kconfig           | 10 ++++++++++
 trunk/arch/sh/kernel/cpu/init.c | 19 +++++++++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index cc0ffb1c4474..d6bc78c0d34e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fc31b80957a14a60513d953cc67a55519a2b09c7
+refs/heads/master: 45ed285b54930767937deb0eaf718b1d08c3c475
diff --git a/trunk/arch/sh/Kconfig b/trunk/arch/sh/Kconfig
index 4d16d8917074..2715834f72be 100644
--- a/trunk/arch/sh/Kconfig
+++ b/trunk/arch/sh/Kconfig
@@ -366,6 +366,16 @@ config SH_STORE_QUEUES
 	  Selecting this option will enable an in-kernel API for manipulating
 	  the store queues integrated in the SH-4 processors.
 
+config SPECULATIVE_EXECUTION
+	bool "Speculative subroutine return"
+	depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
+	help
+	  This enables support for a speculative instruction fetch for
+	  subroutine return. There are various pitfalls associated with
+	  this, as outlined in the SH7780 hardware manual.
+
+	  If unsure, say N.
+
 config CPU_HAS_INTEVT
 	bool
 
diff --git a/trunk/arch/sh/kernel/cpu/init.c b/trunk/arch/sh/kernel/cpu/init.c
index 726acfcb9b77..6451ad630174 100644
--- a/trunk/arch/sh/kernel/cpu/init.c
+++ b/trunk/arch/sh/kernel/cpu/init.c
@@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup);
 onchip_setup(fpu);
 onchip_setup(dsp);
 
+#ifdef CONFIG_SPECULATIVE_EXECUTION
+#define CPUOPM		0xff2f0000
+#define CPUOPM_RABD	(1 << 5)
+
+static void __init speculative_execution_init(void)
+{
+	/* Clear RABD */
+	ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
+
+	/* Flush the update */
+	(void)ctrl_inl(CPUOPM);
+	ctrl_barrier();
+}
+#else
+#define speculative_execution_init()	do { } while (0)
+#endif
+
 /*
  * Generic first-level cache init
  */
@@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void)
 	 */
 	ubc_wakeup();
 #endif
+
+	speculative_execution_init();
 }