From cdcb463007cea71a5c0b89acb0010d933bde94c7 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 16 Jan 2007 12:56:58 +0100 Subject: [PATCH] --- yaml --- r: 45922 b: refs/heads/master c: 30f0e0f4153918a22d802b415980974514139389 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-s3c2410/gpio.c | 11 +++++++---- trunk/arch/arm/mach-s3c2410/pm.c | 7 +++---- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index a170456fbe32..1c5afa73740e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6c3c5bb3c68b932ece9f92b9d201196d537cb99c +refs/heads/master: 30f0e0f4153918a22d802b415980974514139389 diff --git a/trunk/arch/arm/mach-s3c2410/gpio.c b/trunk/arch/arm/mach-s3c2410/gpio.c index d1740643a135..f6fb215bb48c 100644 --- a/trunk/arch/arm/mach-s3c2410/gpio.c +++ b/trunk/arch/arm/mach-s3c2410/gpio.c @@ -84,15 +84,18 @@ EXPORT_SYMBOL(s3c2410_gpio_cfgpin); unsigned int s3c2410_gpio_getcfg(unsigned int pin) { void __iomem *base = S3C24XX_GPIO_BASE(pin); - unsigned long mask; + unsigned long val = __raw_readl(base); if (pin < S3C2410_GPIO_BANKB) { - mask = 1 << S3C2410_GPIO_OFFSET(pin); + val >>= S3C2410_GPIO_OFFSET(pin); + val &= 1; + val += 1; } else { - mask = 3 << S3C2410_GPIO_OFFSET(pin)*2; + val >>= S3C2410_GPIO_OFFSET(pin)*2; + val &= 3; } - return __raw_readl(base) & mask; + return val | S3C2410_GPIO_INPUT; } EXPORT_SYMBOL(s3c2410_gpio_getcfg); diff --git a/trunk/arch/arm/mach-s3c2410/pm.c b/trunk/arch/arm/mach-s3c2410/pm.c index 00834097eb82..ebf294dd31da 100644 --- a/trunk/arch/arm/mach-s3c2410/pm.c +++ b/trunk/arch/arm/mach-s3c2410/pm.c @@ -451,15 +451,14 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) irqstate = s3c_irqwake_eintmask & (1L<>= S3C2410_GPIO_OFFSET(pin)*2; if (!irqstate) { - if (pinstate == 0x02) + if (pinstate == S3C2410_GPIO_IRQ) DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); } else { - if (pinstate == 0x02) { + if (pinstate == S3C2410_GPIO_IRQ) { DBG("Disabling IRQ %d (pin %d)\n", irq, pin); - s3c2410_gpio_cfgpin(pin, 0x00); + s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); } } }