From ce46a6c64be9e59e331d39183037a049c2a90264 Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Wed, 16 Jan 2013 18:36:12 +0530
Subject: [PATCH] --- yaml --- r: 355763 b: refs/heads/master c:
 ecfd6c7f05db5c3f41f846d489861646e0934b56 h: refs/heads/master i:   355761:
 aca2b994ceaad3242afcee3046aa3009fb19be6e   355759:
 5558da24a727e80daf89dd33a4ab57192bbb07a9 v: v3

---
 [refs]                                      |  2 +-
 trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 9ec21412dda0..3747a5cf5e47 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: beb0e325bea1118abe63d21f41825904d86b6fb6
+refs/heads/master: ecfd6c7f05db5c3f41f846d489861646e0934b56
diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi
index bdb2a660f376..ff6b68fe08af 100644
--- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -106,6 +106,15 @@
 				nvidia,slew-rate-rising = <1>;
 				nvidia,slew-rate-falling = <1>;
 			};
+			uart3_txd_pw6 {
+				nvidia,pins =	"uart3_txd_pw6",
+						"uart3_cts_n_pa1",
+						"uart3_rts_n_pc0",
+						"uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
 		};
 	};
 
@@ -114,6 +123,12 @@
 		clock-frequency = <408000000>;
 	};
 
+	serial@70006200 {
+		compatible = "nvidia,tegra30-hsuart";
+		status = "okay";
+		clock-frequency = <408000000>;
+	};
+
 	i2c@7000c000 {
 		status = "okay";
 		clock-frequency = <100000>;