From ce5ccc7a9f772a9783a580e11b0374263edd9a4b Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Sat, 30 May 2009 14:00:18 +0100
Subject: [PATCH] --- yaml --- r: 149315 b: refs/heads/master c:
 85d6943af50537d3aec58b967ffbd3fec88453e9 h: refs/heads/master i:   149313:
 172e1f5e3824a4609580dc102623c6275421a1f4   149311:
 aa65c7e3a047d9e51c53c6a49fd86be224de55ac v: v3

---
 [refs]                         | 2 +-
 trunk/arch/arm/vfp/vfphw.S     | 4 ++++
 trunk/arch/arm/vfp/vfpmodule.c | 2 ++
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 2737a2a32da1..264ee531b2bb 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 26584853a44c58f3d6ac7360d697a2ddcd1a3efa
+refs/heads/master: 85d6943af50537d3aec58b967ffbd3fec88453e9
diff --git a/trunk/arch/arm/vfp/vfphw.S b/trunk/arch/arm/vfp/vfphw.S
index 83c4e384b16d..1aeae38725dd 100644
--- a/trunk/arch/arm/vfp/vfphw.S
+++ b/trunk/arch/arm/vfp/vfphw.S
@@ -100,6 +100,7 @@ ENTRY(vfp_support_entry)
 	beq	no_old_VFP_process
 	VFPFSTMIA r4, r5		@ save the working registers
 	VFPFMRX	r5, FPSCR		@ current status
+#ifndef CONFIG_CPU_FEROCEON
 	tst	r1, #FPEXC_EX		@ is there additional state to save?
 	beq	1f
 	VFPFMRX	r6, FPINST		@ FPINST (only if FPEXC.EX is set)
@@ -107,6 +108,7 @@ ENTRY(vfp_support_entry)
 	beq	1f
 	VFPFMRX	r8, FPINST2		@ FPINST2 if needed (and present)
 1:
+#endif
 	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
 					@ and point r4 at the word at the
 					@ start of the register dump
@@ -119,6 +121,7 @@ no_old_VFP_process:
 	VFPFLDMIA r10, r5		@ reload the working registers while
 					@ FPEXC is in a safe state
 	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
+#ifndef CONFIG_CPU_FEROCEON
 	tst	r1, #FPEXC_EX		@ is there additional state to restore?
 	beq	1f
 	VFPFMXR	FPINST, r6		@ restore FPINST (only if FPEXC.EX is set)
@@ -126,6 +129,7 @@ no_old_VFP_process:
 	beq	1f
 	VFPFMXR	FPINST2, r8		@ FPINST2 if needed (and present)
 1:
+#endif
 	VFPFMXR	FPSCR, r5		@ restore status
 
 check_for_exception:
diff --git a/trunk/arch/arm/vfp/vfpmodule.c b/trunk/arch/arm/vfp/vfpmodule.c
index 01599c4ef726..2d7423af1197 100644
--- a/trunk/arch/arm/vfp/vfpmodule.c
+++ b/trunk/arch/arm/vfp/vfpmodule.c
@@ -253,12 +253,14 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
 	}
 
 	if (fpexc & FPEXC_EX) {
+#ifndef CONFIG_CPU_FEROCEON
 		/*
 		 * Asynchronous exception. The instruction is read from FPINST
 		 * and the interrupted instruction has to be restarted.
 		 */
 		trigger = fmrx(FPINST);
 		regs->ARM_pc -= 4;
+#endif
 	} else if (!(fpexc & FPEXC_DEX)) {
 		/*
 		 * Illegal combination of bits. It can be caused by an