From ce7062faa9212d3928e64668cf1cdd9995f95f9f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 18 Nov 2011 11:55:43 +1000 Subject: [PATCH] --- yaml --- r: 282649 b: refs/heads/master c: abbd3f8e3bea4b2b0490260e67357067a2dc2039 h: refs/heads/master i: 282647: 0673b27c6fe793e17fb5a5d386b8f98560451c15 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_bios.c | 12 ------------ trunk/drivers/gpu/drm/nouveau/nv04_dfp.c | 11 ++++++++--- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/[refs] b/[refs] index 642e82ac791d..af95de7bbd38 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d4c2c99bdc8385a0e51ce4ef2df124d14b6b9c9d +refs/heads/master: abbd3f8e3bea4b2b0490260e67357067a2dc2039 diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c b/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c index 1faa7d9ceb94..f8df37285ba7 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -4304,18 +4304,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b break; } - /* Dell Latitude D620 reports a too-high value for the dual-link - * transition freq, causing us to program the panel incorrectly. - * - * It doesn't appear the VBIOS actually uses its transition freq - * (90000kHz), instead it uses the "Number of LVDS channels" field - * out of the panel ID structure (http://www.spwg.org/). - * - * For the moment, a quirk will do :) - */ - if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2)) - bios->fp.duallink_transition_clk = 80000; - /* set dual_link flag for EDID case */ if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); diff --git a/trunk/drivers/gpu/drm/nouveau/nv04_dfp.c b/trunk/drivers/gpu/drm/nouveau/nv04_dfp.c index dff3ad594e0e..2258746016f8 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv04_dfp.c +++ b/trunk/drivers/gpu/drm/nouveau/nv04_dfp.c @@ -341,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, output_mode->clock > 165000) regp->fp_control |= (2 << 24); if (nv_encoder->dcb->type == OUTPUT_LVDS) { - bool duallink, dummy; + bool duallink = false, dummy; + if (nv_connector->edid && + nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { + duallink = (((u8 *)nv_connector->edid)[121] == 2); + } else { + nouveau_bios_parse_lvds_table(dev, output_mode->clock, + &duallink, &dummy); + } - nouveau_bios_parse_lvds_table(dev, output_mode->clock, - &duallink, &dummy); if (duallink) regp->fp_control |= (8 << 28); } else