From d0af917f107772232dece99ae95dd8b1f241c9bc Mon Sep 17 00:00:00 2001
From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Date: Mon, 11 Jul 2011 10:15:45 +0900
Subject: [PATCH] --- yaml --- r: 261163 b: refs/heads/master c:
 0cab0841dc1400f633a7e1ac1e448518692f927a h: refs/heads/master i:   261161:
 db17f73b8095c987490684e66889a4daea17ec29   261159:
 fc8dbe783ffd0aa2108e885f144420d08638a1b3 v: v3

---
 [refs]                                  |  2 +-
 trunk/drivers/pci/hotplug/pciehp_ctrl.c |  3 +++
 trunk/drivers/pci/hotplug/pciehp_hpc.c  | 11 ++---------
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/[refs] b/[refs]
index 13500c5d5713..12148c85e81b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9b373ed18f745bddf4288f1ec4a51fe822b8610a
+refs/heads/master: 0cab0841dc1400f633a7e1ac1e448518692f927a
diff --git a/trunk/drivers/pci/hotplug/pciehp_ctrl.c b/trunk/drivers/pci/hotplug/pciehp_ctrl.c
index 085dbb5fc168..1e9c9aacc3a6 100644
--- a/trunk/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/trunk/drivers/pci/hotplug/pciehp_ctrl.c
@@ -213,6 +213,9 @@ static int board_added(struct slot *p_slot)
 		goto err_exit;
 	}
 
+	/* Wait for 1 second after checking link training status */
+	msleep(1000);
+
 	/* Check for a power fault */
 	if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
 		ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
diff --git a/trunk/drivers/pci/hotplug/pciehp_hpc.c b/trunk/drivers/pci/hotplug/pciehp_hpc.c
index 50a23da5d24d..96dc4734e4af 100644
--- a/trunk/drivers/pci/hotplug/pciehp_hpc.c
+++ b/trunk/drivers/pci/hotplug/pciehp_hpc.c
@@ -275,16 +275,9 @@ int pciehp_check_link_status(struct controller *ctrl)
          * hot-plug capable downstream port. But old controller might
          * not implement it. In this case, we wait for 1000 ms.
          */
-        if (ctrl->link_active_reporting){
-                /* Wait for Data Link Layer Link Active bit to be set */
+        if (ctrl->link_active_reporting)
                 pcie_wait_link_active(ctrl);
-                /*
-                 * We must wait for 100 ms after the Data Link Layer
-                 * Link Active bit reads 1b before initiating a
-                 * configuration access to the hot added device.
-                 */
-                msleep(100);
-        } else
+        else
                 msleep(1000);
 
 	retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);