From d0c9b7717335d0f227cb2f02342d1b6f139c42c3 Mon Sep 17 00:00:00 2001
From: Marcin Slusarz <marcin.slusarz@gmail.com>
Date: Mon, 11 Jun 2012 00:21:12 +0200
Subject: [PATCH] --- yaml --- r: 318743 b: refs/heads/master c:
 e0dd536a7abbce564eff9929e0a3cf77ba2d2e2e h: refs/heads/master i:   318741:
 f8abbbe4da4d65528aa60002aa334ad4e18009a0   318739:
 46ca76d00373331f1b7980a054b9778757aab0b3   318735:
 b09f3ac61b3b627239142958db5f6d480a17f587 v: v3

---
 [refs]                                     |  2 +-
 trunk/drivers/gpu/drm/nouveau/nv84_crypt.c | 18 +++++++++++++++---
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index edc143f4b709..6649305173a4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 16fde6cd323a4f7654ac76dae12cb36208ed4c5d
+refs/heads/master: e0dd536a7abbce564eff9929e0a3cf77ba2d2e2e
diff --git a/trunk/drivers/gpu/drm/nouveau/nv84_crypt.c b/trunk/drivers/gpu/drm/nouveau/nv84_crypt.c
index edece9c616eb..bbfcc73b6708 100644
--- a/trunk/drivers/gpu/drm/nouveau/nv84_crypt.c
+++ b/trunk/drivers/gpu/drm/nouveau/nv84_crypt.c
@@ -117,18 +117,30 @@ nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
 	nv50_vm_flush_engine(dev, 0x0a);
 }
 
+static struct nouveau_bitfield nv84_crypt_intr[] = {
+	{ 0x00000001, "INVALID_STATE" },
+	{ 0x00000002, "ILLEGAL_MTHD" },
+	{ 0x00000004, "ILLEGAL_CLASS" },
+	{ 0x00000080, "QUERY" },
+	{ 0x00000100, "FAULT" },
+	{}
+};
+
 static void
 nv84_crypt_isr(struct drm_device *dev)
 {
 	u32 stat = nv_rd32(dev, 0x102130);
 	u32 mthd = nv_rd32(dev, 0x102190);
 	u32 data = nv_rd32(dev, 0x102194);
-	u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
+	u64 inst = (u64)(nv_rd32(dev, 0x102188) & 0x7fffffff) << 12;
 	int show = nouveau_ratelimit();
+	int chid = nv50_graph_isr_chid(dev, inst);
 
 	if (show) {
-		NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
-			     stat, mthd, data, inst);
+		NV_INFO(dev, "PCRYPT:");
+		nouveau_bitfield_print(nv84_crypt_intr, stat);
+		printk(KERN_CONT " ch %d (0x%010llx) mthd 0x%04x data 0x%08x\n",
+			chid, inst, mthd, data);
 	}
 
 	nv_wr32(dev, 0x102130, stat);