From d24d15d6696435e3f4f719562f44de95896c2a4c Mon Sep 17 00:00:00 2001 From: David Howells Date: Fri, 28 May 2010 10:41:16 +0100 Subject: [PATCH] --- yaml --- r: 199190 b: refs/heads/master c: 8507bb0062bff1431bbcce921efe5cd1186fcff2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/frv/include/asm/cache.h | 2 -- trunk/arch/frv/include/asm/mem-layout.h | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index f337edfbdf39..b3fe55480c8a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 29d03fa12bc02c0f8085cd6bb06d11359a4bccaf +refs/heads/master: 8507bb0062bff1431bbcce921efe5cd1186fcff2 diff --git a/trunk/arch/frv/include/asm/cache.h b/trunk/arch/frv/include/asm/cache.h index 7dc0f0f85b7c..2797163b8f4f 100644 --- a/trunk/arch/frv/include/asm/cache.h +++ b/trunk/arch/frv/include/asm/cache.h @@ -17,8 +17,6 @@ #define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES - #define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) diff --git a/trunk/arch/frv/include/asm/mem-layout.h b/trunk/arch/frv/include/asm/mem-layout.h index 2947764fc0e0..ccae981876fa 100644 --- a/trunk/arch/frv/include/asm/mem-layout.h +++ b/trunk/arch/frv/include/asm/mem-layout.h @@ -35,8 +35,8 @@ * the slab must be aligned such that load- and store-double instructions don't * fault if used */ -#define ARCH_KMALLOC_MINALIGN 8 -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES /*****************************************************************************/ /*