From d2fe76806d32222cd842ed37fd7c7ec7f4cfc393 Mon Sep 17 00:00:00 2001
From: Martyn Welch <martyn.welch@gefanuc.com>
Date: Mon, 13 Oct 2008 16:16:45 +0100
Subject: [PATCH] --- yaml --- r: 114647 b: refs/heads/master c:
 6675847ea42d5acfaa644ac24eb0d87df5769cd5 h: refs/heads/master i:   114645:
 02cd90eef4f82052381bd9d30faa2779dba207c4   114643:
 0f951eea34fd47afc2d91384afbbc701bd7ef0a3   114639:
 baeabcde70447cb515273d7d913d3a4261134cbe v: v3

---
 [refs]                                        |  2 +-
 trunk/arch/powerpc/boot/dts/gef_sbc610.dts    |  4 ++
 .../arch/powerpc/platforms/86xx/gef_sbc610.c  | 40 +++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index a54d14dd3be3..dcb97c618998 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d6c3db83c5567b3a4d8d0bf33dc5687abdf65274
+refs/heads/master: 6675847ea42d5acfaa644ac24eb0d87df5769cd5
diff --git a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts
index 771a776d6101..6ed608322ddc 100644
--- a/trunk/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/trunk/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -84,6 +84,10 @@
 			  6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
 			  7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
 
+		fpga@4,0 {
+			compatible = "gef,fpga-regs";
+			reg = <0x4 0x0 0x40>;
+		};
 		gef_pic: pic@4,4000 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
diff --git a/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c b/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c
index 3873c2018cc3..821c45fac18b 100644
--- a/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/trunk/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -73,6 +73,7 @@ static void __init gef_sbc610_init_irq(void)
 
 static void __init gef_sbc610_setup_arch(void)
 {
+	struct device_node *regs;
 #ifdef CONFIG_PCI
 	struct device_node *np;
 
@@ -86,8 +87,43 @@ static void __init gef_sbc610_setup_arch(void)
 #ifdef CONFIG_SMP
 	mpc86xx_smp_init();
 #endif
+
+	/* Remap basic board registers */
+	regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
+	if (regs) {
+		sbc610_regs = of_iomap(regs, 0);
+		if (sbc610_regs == NULL)
+			printk(KERN_WARNING "Unable to map board registers\n");
+		of_node_put(regs);
+	}
+}
+
+/* Return the PCB revision */
+static unsigned int gef_sbc610_get_pcb_rev(void)
+{
+	unsigned int reg;
+
+	reg = ioread32(sbc610_regs);
+	return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int gef_sbc610_get_board_rev(void)
+{
+	unsigned int reg;
+
+	reg = ioread32(sbc610_regs);
+	return (reg >> 16) & 0xff;
 }
 
+/* Return the FPGA revision */
+static unsigned int gef_sbc610_get_fpga_rev(void)
+{
+	unsigned int reg;
+
+	reg = ioread32(sbc610_regs);
+	return (reg >> 24) & 0xf;
+}
 
 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 {
@@ -96,6 +132,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 
 	seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
+	seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
+		('A' + gef_sbc610_get_board_rev() - 1));
+	seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
+
 	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 }