From d35b87fdd1a9f0741de9a763453990e155c96e11 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 23 Jan 2013 19:00:25 -0500 Subject: [PATCH] --- yaml --- r: 358135 b: refs/heads/master c: f770d78ac159a96071e3c4e4ab97c262e79506d3 h: refs/heads/master i: 358133: 7be608de3d3ad94aa752250f323f60bdf2756b6b 358131: 2316a536dbb9b5a494fbd440ec07e4ea4c538ad2 358127: bf80aacdaa3db5ec988046fe961c76b99cd163a1 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/si.c | 12 +++++++----- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 33e1f1b1f64b..9262fc68a672 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 90fb87791a698ae16af374aaaa9540fde37f6195 +refs/heads/master: f770d78ac159a96071e3c4e4ab97c262e79506d3 diff --git a/trunk/drivers/gpu/drm/radeon/si.c b/trunk/drivers/gpu/drm/radeon/si.c index 7a8ca728f36f..89b564ec3d34 100644 --- a/trunk/drivers/gpu/drm/radeon/si.c +++ b/trunk/drivers/gpu/drm/radeon/si.c @@ -2220,11 +2220,6 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); - evergreen_mc_stop(rdev, &save); - if (evergreen_mc_wait_for_idle(rdev)) { - dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); - } - /* Disable CP parsing/prefetching */ WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); @@ -2241,6 +2236,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); } + udelay(50); + + evergreen_mc_stop(rdev, &save); + if (evergreen_mc_wait_for_idle(rdev)) { + dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); + } + if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) { grbm_soft_reset = SOFT_RESET_CB | SOFT_RESET_DB |