From d37df01e44a57ce2a8e975c07f827d19724fb520 Mon Sep 17 00:00:00 2001 From: Bastian Hecht Date: Thu, 1 Mar 2012 10:48:35 +0100 Subject: [PATCH] --- yaml --- r: 298139 b: refs/heads/master c: b6a5588b27f21d74ae35709b56e969d536f1eed0 h: refs/heads/master i: 298137: 9dcdc27eaa3f337ab575f0595349addaa64c2294 298135: ee873c1eafb519b8341f10d1c6847b081ef18192 v: v3 --- [refs] | 2 +- trunk/include/linux/mtd/sh_flctl.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2d122391b79f..9ccc759fed5a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9bbf29e4757fb152c8673eda0b1e9d507b953df9 +refs/heads/master: b6a5588b27f21d74ae35709b56e969d536f1eed0 diff --git a/trunk/include/linux/mtd/sh_flctl.h b/trunk/include/linux/mtd/sh_flctl.h index 9cf4c4c79555..b66940593c82 100644 --- a/trunk/include/linux/mtd/sh_flctl.h +++ b/trunk/include/linux/mtd/sh_flctl.h @@ -67,6 +67,30 @@ #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ #define TYPESEL_SET (0x1 << 0) +/* + * Clock settings using the PULSEx registers from FLCMNCR + * + * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E + * to control the clock divider used between the High-Speed Peripheral Clock + * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit + * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 + * bit version the divider is seperate for the pulse width of high and low + * signals. + */ +#define PULSE3 (0x1 << 27) +#define PULSE2 (0x1 << 17) +#define PULSE1 (0x1 << 15) +#define PULSE0 (0x1 << 9) +#define CLK_8B_0_5 PULSE1 +#define CLK_8B_1 0x0 +#define CLK_8B_1_5 (PULSE1 | PULSE2) +#define CLK_8B_2 PULSE0 +#define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2) +#define CLK_8B_4 (PULSE0 | PULSE2) +#define CLK_16B_6L_2H PULSE0 +#define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2) +#define CLK_16B_12L_4H (PULSE0 | PULSE2) + /* FLCMDCR control bits */ #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */ #define ADRMD_E (0x1 << 26) /* Sector address access */