From d3a2e324cf7107baa3d920b6fb60ad593c2f45c9 Mon Sep 17 00:00:00 2001 From: Clemens Ladisch Date: Sat, 15 Oct 2011 18:14:39 +0200 Subject: [PATCH] --- yaml --- r: 272394 b: refs/heads/master c: 32eaeae177bf77fbc224c35262add45bd5e6abb3 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/firewire/ohci.c | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 7799f0996c98..bb91960d2a93 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a74477db9171e677b7a37b89e6e0ac8a15ba1f26 +refs/heads/master: 32eaeae177bf77fbc224c35262add45bd5e6abb3 diff --git a/trunk/drivers/firewire/ohci.c b/trunk/drivers/firewire/ohci.c index bffc2ad7ecab..b6977149394e 100644 --- a/trunk/drivers/firewire/ohci.c +++ b/trunk/drivers/firewire/ohci.c @@ -1860,8 +1860,22 @@ static void bus_reset_work(struct work_struct *work) for (i = 1, j = 0; j < self_id_count; i += 2, j++) { if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { - fw_notify("inconsistent self IDs\n"); - return; + /* + * If the invalid data looks like a cycle start packet, + * it's likely to be the result of the cycle master + * having a wrong gap count. In this case, the self IDs + * so far are valid and should be processed so that the + * bus manager can then correct the gap count. + */ + if (cond_le32_to_cpu(ohci->self_id_cpu[i]) + == 0xffff008f) { + fw_notify("ignoring spurious self IDs\n"); + self_id_count = j; + break; + } else { + fw_notify("inconsistent self IDs\n"); + return; + } } ohci->self_id_buffer[j] = cond_le32_to_cpu(ohci->self_id_cpu[i]);