From d3c6df498388bd7586011521780ab450830050c7 Mon Sep 17 00:00:00 2001 From: Liu Yu Date: Mon, 5 Sep 2011 17:01:22 +0800 Subject: [PATCH] --- yaml --- r: 274217 b: refs/heads/master c: d5755e6f3a412f012377e28b655d89eff3311f1c h: refs/heads/master i: 274215: f103e5bb97d10c66844ec68d94f7aab53b4b0d17 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/math-emu/math_efp.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 1158920e4298..183efa81f37e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b430abc4d10537992a5ba38eff6c46b3c9009a19 +refs/heads/master: d5755e6f3a412f012377e28b655d89eff3311f1c diff --git a/trunk/arch/powerpc/math-emu/math_efp.c b/trunk/arch/powerpc/math-emu/math_efp.c index 10fda0f13a00..96dbbae1a590 100644 --- a/trunk/arch/powerpc/math-emu/math_efp.c +++ b/trunk/arch/powerpc/math-emu/math_efp.c @@ -676,13 +676,20 @@ int speround_handler(struct pt_regs *regs) type = insn_type(speinsn & 0x7ff); if (type == XCR) return -ENOSYS; + __FPU_FPSCR = mfspr(SPRN_SPEFSCR); + pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR); + + /* No need to round if the result is exact */ + if (!(__FPU_FPSCR & FP_EX_INEXACT)) + return 0; + fc = (speinsn >> 21) & 0x1f; s_lo = regs->gpr[fc] & SIGN_BIT_S; s_hi = current->thread.evr[fc] & SIGN_BIT_S; fgpr.wp[0] = current->thread.evr[fc]; fgpr.wp[1] = regs->gpr[fc]; - __FPU_FPSCR = mfspr(SPRN_SPEFSCR); + pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); switch ((speinsn >> 5) & 0x7) { /* Since SPE instructions on E500 core can handle round to nearest @@ -722,6 +729,8 @@ int speround_handler(struct pt_regs *regs) current->thread.evr[fc] = fgpr.wp[0]; regs->gpr[fc] = fgpr.wp[1]; + pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); + return 0; }