diff --git a/[refs] b/[refs]
index 668dcbc33064..66a140c338e6 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d479d2cc0802d5c8546a6a7492646e08228effd5
+refs/heads/master: de90c5ce832b1218042316260ff9268b00fdcba3
diff --git a/trunk/arch/i386/kernel/cpu/mcheck/k7.c b/trunk/arch/i386/kernel/cpu/mcheck/k7.c
index b0862af595aa..7a2472557bbb 100644
--- a/trunk/arch/i386/kernel/cpu/mcheck/k7.c
+++ b/trunk/arch/i386/kernel/cpu/mcheck/k7.c
@@ -82,9 +82,13 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
 	nr_mce_banks = l & 0xff;
 
 	/* Clear status for MC index 0 separately, we don't touch CTL,
-	 * as some Athlons cause spurious MCEs when its enabled. */
-	wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
-	for (i=1; i<nr_mce_banks; i++) {
+	 * as some K7 Athlons cause spurious MCEs when its enabled. */
+	if (boot_cpu_data.x86 == 6) {
+		wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
+		i = 1;
+	} else
+		i = 0;
+	for (; i<nr_mce_banks; i++) {
 		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 	}