From d3d79f6323013fa7f051fac4d50164c83095a65a Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 8 Sep 2010 12:42:03 -0700 Subject: [PATCH] --- yaml --- r: 217977 b: refs/heads/master c: 3969c9c927b0bdb1e477a1eda60743143a75e4a5 h: refs/heads/master i: 217975: 46fb57dc4579ada15f37c00437041a2d4000df6c v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_dp.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 2b666fb90236..ace90c5e7a8a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 33a34e4e5969c5272cd6cb88f2e01c97218dd80b +refs/heads/master: 3969c9c927b0bdb1e477a1eda60743143a75e4a5 diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c index effbbe0915ec..153a5934b2e1 100644 --- a/trunk/drivers/gpu/drm/i915/intel_dp.c +++ b/trunk/drivers/gpu/drm/i915/intel_dp.c @@ -783,7 +783,7 @@ static bool ironlake_edp_panel_on (struct drm_device *dev) DRM_ERROR("panel on wait timed out: 0x%08x\n", I915_READ(PCH_PP_STATUS)); - pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); + pp &= ~(PANEL_UNLOCK_REGS); pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); @@ -811,7 +811,7 @@ static void ironlake_edp_panel_off (struct drm_device *dev) I915_READ(PCH_PP_STATUS)); /* Make sure VDD is enabled so DP AUX will work */ - pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ + pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(PCH_PP_CONTROL, pp); POSTING_READ(PCH_PP_CONTROL); }