From d3ec16240713d3661d39f812c71d5d40cd55adde Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 17 Jan 2013 12:31:05 +0200 Subject: [PATCH] --- yaml --- r: 358778 b: refs/heads/master c: 17a76b4b32aca7c19df6988213dfe2eb4b631431 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/i2c/busses/i2c-designware-core.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 8f45e3ee2b5e..b790a24217fc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5c38dc8911b86b7c49305e2f2b631cd1241f2d87 +refs/heads/master: 17a76b4b32aca7c19df6988213dfe2eb4b631431 diff --git a/trunk/drivers/i2c/busses/i2c-designware-core.c b/trunk/drivers/i2c/busses/i2c-designware-core.c index f5258c205de5..94fd81875409 100644 --- a/trunk/drivers/i2c/busses/i2c-designware-core.c +++ b/trunk/drivers/i2c/busses/i2c-designware-core.c @@ -413,11 +413,23 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { + u32 cmd = 0; + + /* + * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must + * manually set the stop bit. However, it cannot be + * detected from the registers so we set it always + * when writing/reading the last byte. + */ + if (dev->msg_write_idx == dev->msgs_num - 1 && + buf_len == 1) + cmd |= BIT(9); + if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { - dw_writel(dev, 0x100, DW_IC_DATA_CMD); + dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); rx_limit--; } else - dw_writel(dev, *buf++, DW_IC_DATA_CMD); + dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); tx_limit--; buf_len--; }