From d4094d69eecb6e49b4965ecdebe13225e2815b69 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sat, 12 May 2007 14:31:17 +0100 Subject: [PATCH] --- yaml --- r: 59233 b: refs/heads/master c: b3e6a508ed920698d367e5993ed056d70364d91f h: refs/heads/master i: 59231: 65909799530100c10cf23375dd523834b144668c v: v3 --- [refs] | 2 +- trunk/arch/arm/Kconfig | 2 +- trunk/arch/arm/mach-davinci/Makefile | 3 +- trunk/arch/arm/mach-davinci/board-evm.c | 2 - trunk/arch/arm/mach-davinci/clock.c | 323 ------------------ trunk/arch/arm/mach-davinci/clock.h | 33 -- trunk/arch/arm/mach-davinci/gpio.c | 286 ---------------- trunk/arch/arm/mach-davinci/io.c | 6 - trunk/arch/arm/mach-davinci/mux.c | 41 --- trunk/arch/arm/mach-davinci/psc.c | 87 ++--- trunk/arch/arm/mach-imx/generic.c | 118 +++++++ trunk/include/asm-arm/arch-davinci/clock.h | 22 -- trunk/include/asm-arm/arch-davinci/gpio.h | 156 --------- trunk/include/asm-arm/arch-davinci/hardware.h | 38 --- trunk/include/asm-arm/arch-davinci/mux.h | 55 --- trunk/include/asm-arm/arch-imx/gpio.h | 102 ++++++ trunk/include/asm-arm/arch-imx/imx-regs.h | 2 + 17 files changed, 255 insertions(+), 1023 deletions(-) delete mode 100644 trunk/arch/arm/mach-davinci/clock.c delete mode 100644 trunk/arch/arm/mach-davinci/clock.h delete mode 100644 trunk/arch/arm/mach-davinci/gpio.c delete mode 100644 trunk/arch/arm/mach-davinci/mux.c delete mode 100644 trunk/include/asm-arm/arch-davinci/clock.h delete mode 100644 trunk/include/asm-arm/arch-davinci/gpio.h delete mode 100644 trunk/include/asm-arm/arch-davinci/mux.h create mode 100644 trunk/include/asm-arm/arch-imx/gpio.h diff --git a/[refs] b/[refs] index 0828930d7e8d..015051feddee 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 83f53220f8313f097cdf181928be13bafbb697ea +refs/heads/master: b3e6a508ed920698d367e5993ed056d70364d91f diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index d0aaecbcdf72..8b553954365f 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -241,6 +241,7 @@ config ARCH_H720X config ARCH_IMX bool "IMX" + select GENERIC_GPIO help Support for Motorola's i.MX family of processors (MX1, MXL). @@ -384,7 +385,6 @@ config ARCH_DAVINCI bool "TI DaVinci" select GENERIC_TIME select GENERIC_CLOCKEVENTS - select GENERIC_GPIO help Support for TI's DaVinci platform. diff --git a/trunk/arch/arm/mach-davinci/Makefile b/trunk/arch/arm/mach-davinci/Makefile index 99ac2e55774d..a8f88cd29905 100644 --- a/trunk/arch/arm/mach-davinci/Makefile +++ b/trunk/arch/arm/mach-davinci/Makefile @@ -4,8 +4,7 @@ # # Common objects -obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ - gpio.o mux.o +obj-y := time.o irq.o serial.o io.o id.o psc.o # Board specific obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o diff --git a/trunk/arch/arm/mach-davinci/board-evm.c b/trunk/arch/arm/mach-davinci/board-evm.c index 9e4024c4965f..633c12e43044 100644 --- a/trunk/arch/arm/mach-davinci/board-evm.c +++ b/trunk/arch/arm/mach-davinci/board-evm.c @@ -32,7 +32,6 @@ void __init davinci_psc_init(void); void __init davinci_irq_init(void); void __init davinci_map_common_io(void); -void __init davinci_init_common_hw(void); /* NOR Flash base address set to CS0 by default */ #define NOR_FLASH_PHYS 0x02000000 @@ -117,7 +116,6 @@ static __init void davinci_evm_init(void) static __init void davinci_evm_irq_init(void) { - davinci_init_common_hw(); davinci_irq_init(); } diff --git a/trunk/arch/arm/mach-davinci/clock.c b/trunk/arch/arm/mach-davinci/clock.c deleted file mode 100644 index 139ceaa35e24..000000000000 --- a/trunk/arch/arm/mach-davinci/clock.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * TI DaVinci clock config file - * - * Copyright (C) 2006 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include "clock.h" - -/* PLL/Reset register offsets */ -#define PLLM 0x110 - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); -static DEFINE_SPINLOCK(clockfw_lock); - -static unsigned int commonrate; -static unsigned int armrate; -static unsigned int fixedrate = 27000000; /* 27 MHZ */ - -extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable); - -/* - * Returns a clock. Note that we first try to use device id on the bus - * and clock name. If this fails, we try to use clock name only. - */ -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - mutex_lock(&clocks_mutex); - - list_for_each_entry(p, &clocks, node) { - if (p->id == idno && - strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - goto found; - } - } - - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { - clk = p; - break; - } - } - -found: - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - if (clk && !IS_ERR(clk)) - module_put(clk->owner); -} -EXPORT_SYMBOL(clk_put); - -static int __clk_enable(struct clk *clk) -{ - if (clk->flags & ALWAYS_ENABLED) - return 0; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1); - return 0; -} - -static void __clk_disable(struct clk *clk) -{ - if (clk->usecount) - return; - - davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0); -} - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret = 0; - - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - if (clk->usecount++ == 0) { - spin_lock_irqsave(&clockfw_lock, flags); - ret = __clk_enable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (clk == NULL || IS_ERR(clk)) - return; - - if (clk->usecount > 0 && !(--clk->usecount)) { - spin_lock_irqsave(&clockfw_lock, flags); - __clk_disable(clk); - spin_unlock_irqrestore(&clockfw_lock, flags); - } -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - return *(clk->rate); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - return *(clk->rate); -} -EXPORT_SYMBOL(clk_round_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - /* changing the clk rate is not supported */ - return -EINVAL; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_register(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return -EINVAL; - - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - - return 0; -} -EXPORT_SYMBOL(clk_register); - -void clk_unregister(struct clk *clk) -{ - if (clk == NULL || IS_ERR(clk)) - return; - - mutex_lock(&clocks_mutex); - list_del(&clk->node); - mutex_unlock(&clocks_mutex); -} -EXPORT_SYMBOL(clk_unregister); - -static struct clk davinci_clks[] = { - { - .name = "ARMCLK", - .rate = &armrate, - .lpsc = -1, - .flags = ALWAYS_ENABLED, - }, - { - .name = "UART", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_UART0, - }, - { - .name = "EMACCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_EMAC_WRAPPER, - }, - { - .name = "I2CCLK", - .rate = &fixedrate, - .lpsc = DAVINCI_LPSC_I2C, - }, - { - .name = "IDECLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_ATA, - }, - { - .name = "McBSPCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_McBSP, - }, - { - .name = "MMCSDCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_MMC_SD, - }, - { - .name = "SPICLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_SPI, - }, - { - .name = "gpio", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_GPIO, - }, - { - .name = "AEMIFCLK", - .rate = &commonrate, - .lpsc = DAVINCI_LPSC_AEMIF, - .usecount = 1, - } -}; - -int __init davinci_clk_init(void) -{ - struct clk *clkp; - int count = 0; - u32 pll_mult; - - pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - commonrate = ((pll_mult + 1) * 27000000) / 6; - armrate = ((pll_mult + 1) * 27000000) / 2; - - for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks); - count++, clkp++) { - clk_register(clkp); - - /* Turn on clocks that have been enabled in the - * table above */ - if (clkp->usecount) - clk_enable(clkp); - } - - return 0; -} - -#ifdef CONFIG_PROC_FS -#include -#include - -static void *davinci_ck_start(struct seq_file *m, loff_t *pos) -{ - return *pos < 1 ? (void *)1 : NULL; -} - -static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return NULL; -} - -static void davinci_ck_stop(struct seq_file *m, void *v) -{ -} - -static int davinci_ck_show(struct seq_file *m, void *v) -{ - struct clk *cp; - - list_for_each_entry(cp, &clocks, node) - seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount); - - return 0; -} - -static struct seq_operations davinci_ck_op = { - .start = davinci_ck_start, - .next = davinci_ck_next, - .stop = davinci_ck_stop, - .show = davinci_ck_show -}; - -static int davinci_ck_open(struct inode *inode, struct file *file) -{ - return seq_open(file, &davinci_ck_op); -} - -static struct file_operations proc_davinci_ck_operations = { - .open = davinci_ck_open, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release, -}; - -static int __init davinci_ck_proc_init(void) -{ - struct proc_dir_entry *entry; - - entry = create_proc_entry("davinci_clocks", 0, NULL); - if (entry) - entry->proc_fops = &proc_davinci_ck_operations; - return 0; - -} -__initcall(davinci_ck_proc_init); -#endif /* CONFIG_DEBUG_PROC_FS */ diff --git a/trunk/arch/arm/mach-davinci/clock.h b/trunk/arch/arm/mach-davinci/clock.h deleted file mode 100644 index ed47079a52e4..000000000000 --- a/trunk/arch/arm/mach-davinci/clock.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * TI DaVinci clock definitions - * - * Copyright (C) 2006 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_DAVINCI_CLOCK_H -#define __ARCH_ARM_DAVINCI_CLOCK_H - -struct clk { - struct list_head node; - struct module *owner; - const char *name; - unsigned int *rate; - int id; - __s8 usecount; - __u8 flags; - __u8 lpsc; -}; - -/* Clock flags */ -#define RATE_CKCTL 1 -#define RATE_FIXED 2 -#define RATE_PROPAGATES 4 -#define VIRTUAL_CLOCK 8 -#define ALWAYS_ENABLED 16 -#define ENABLE_REG_32BIT 32 - -#endif diff --git a/trunk/arch/arm/mach-davinci/gpio.c b/trunk/arch/arm/mach-davinci/gpio.c deleted file mode 100644 index 9c67886e7189..000000000000 --- a/trunk/arch/arm/mach-davinci/gpio.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * TI DaVinci GPIO Support - * - * Copyright (c) 2006 David Brownell - * Copyright (c) 2007, MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -static DEFINE_SPINLOCK(gpio_lock); -static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO); - -int gpio_request(unsigned gpio, const char *tag) -{ - if (gpio >= DAVINCI_N_GPIO) - return -EINVAL; - - if (test_and_set_bit(gpio, gpio_in_use)) - return -EBUSY; - - return 0; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned gpio) -{ - if (gpio >= DAVINCI_N_GPIO) - return; - - clear_bit(gpio, gpio_in_use); -} -EXPORT_SYMBOL(gpio_free); - -/* create a non-inlined version */ -static struct gpio_controller *__iomem gpio2controller(unsigned gpio) -{ - return __gpio_to_controller(gpio); -} - -/* - * Assuming the pin is muxed as a gpio output, set its output value. - */ -void __gpio_set(unsigned gpio, int value) -{ - struct gpio_controller *__iomem g = gpio2controller(gpio); - - __raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data); -} -EXPORT_SYMBOL(__gpio_set); - - -/* - * Read the pin's value (works even if it's set up as output); - * returns zero/nonzero. - * - * Note that changes are synched to the GPIO clock, so reading values back - * right after you've set them may give old values. - */ -int __gpio_get(unsigned gpio) -{ - struct gpio_controller *__iomem g = gpio2controller(gpio); - - return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); -} -EXPORT_SYMBOL(__gpio_get); - - -/*--------------------------------------------------------------------------*/ - -/* - * board setup code *MUST* set PINMUX0 and PINMUX1 as - * needed, and enable the GPIO clock. - */ - -int gpio_direction_input(unsigned gpio) -{ - struct gpio_controller *__iomem g = gpio2controller(gpio); - u32 temp; - u32 mask; - - if (!g) - return -EINVAL; - - spin_lock(&gpio_lock); - mask = __gpio_mask(gpio); - temp = __raw_readl(&g->dir); - temp |= mask; - __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); - return 0; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned gpio, int value) -{ - struct gpio_controller *__iomem g = gpio2controller(gpio); - u32 temp; - u32 mask; - - if (!g) - return -EINVAL; - - spin_lock(&gpio_lock); - mask = __gpio_mask(gpio); - temp = __raw_readl(&g->dir); - temp &= ~mask; - __raw_writel(mask, value ? &g->set_data : &g->clr_data); - __raw_writel(temp, &g->dir); - spin_unlock(&gpio_lock); - return 0; -} -EXPORT_SYMBOL(gpio_direction_output); - -/* - * We expect irqs will normally be set up as input pins, but they can also be - * used as output pins ... which is convenient for testing. - * - * NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition - * to their GPIOBNK0 irq (but with a bit less overhead). But we don't have - * a good way to hook those up ... - * - * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also - * serve as EDMA event triggers. - */ - -static void gpio_irq_disable(unsigned irq) -{ - struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); - - __raw_writel(mask, &g->clr_falling); - __raw_writel(mask, &g->clr_rising); -} - -static void gpio_irq_enable(unsigned irq) -{ - struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); - - if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING) - __raw_writel(mask, &g->set_falling); - if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING) - __raw_writel(mask, &g->set_rising); -} - -static int gpio_irq_type(unsigned irq, unsigned trigger) -{ - struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = __gpio_mask(irq_to_gpio(irq)); - - if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - return -EINVAL; - - irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; - irq_desc[irq].status |= trigger; - - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); - return 0; -} - -static struct irq_chip gpio_irqchip = { - .name = "GPIO", - .enable = gpio_irq_enable, - .disable = gpio_irq_disable, - .set_type = gpio_irq_type, -}; - -static void -gpio_irq_handler(unsigned irq, struct irq_desc *desc) -{ - struct gpio_controller *__iomem g = get_irq_chip_data(irq); - u32 mask = 0xffff; - - /* we only care about one bank */ - if (irq & 1) - mask <<= 16; - - /* temporarily mask (level sensitive) parent IRQ */ - desc->chip->ack(irq); - while (1) { - u32 status; - struct irq_desc *gpio; - int n; - int res; - - /* ack any irqs */ - status = __raw_readl(&g->intstat) & mask; - if (!status) - break; - __raw_writel(status, &g->intstat); - if (irq & 1) - status >>= 16; - - /* now demux them to the right lowlevel handler */ - n = (int)get_irq_data(irq); - gpio = &irq_desc[n]; - while (status) { - res = ffs(status); - n += res; - gpio += res; - desc_handle_irq(n - 1, gpio - 1); - status >>= res; - } - } - desc->chip->unmask(irq); - /* now it may re-trigger */ -} - -/* - * NOTE: for suspend/resume, probably best to make a sysdev (and class) - * with its suspend/resume calls hooking into the results of the set_wake() - * calls ... so if no gpios are wakeup events the clock can be disabled, - * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 - * can be set appropriately for GPIOV33 pins. - */ - -static int __init davinci_gpio_irq_setup(void) -{ - unsigned gpio, irq, bank; - struct clk *clk; - - clk = clk_get(NULL, "gpio"); - if (IS_ERR(clk)) { - printk(KERN_ERR "Error %ld getting gpio clock?\n", - PTR_ERR(clk)); - return 0; - } - - clk_enable(clk); - - for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0; - gpio < DAVINCI_N_GPIO; bank++) { - struct gpio_controller *__iomem g = gpio2controller(gpio); - unsigned i; - - __raw_writel(~0, &g->clr_falling); - __raw_writel(~0, &g->clr_rising); - - /* set up all irqs in this bank */ - set_irq_chained_handler(bank, gpio_irq_handler); - set_irq_chip_data(bank, g); - set_irq_data(bank, (void *)irq); - - for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO; - i++, irq++, gpio++) { - set_irq_chip(irq, &gpio_irqchip); - set_irq_chip_data(irq, g); - set_irq_handler(irq, handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - } - } - - /* BINTEN -- per-bank interrupt enable. genirq would also let these - * bits be set/cleared dynamically. - */ - __raw_writel(0x1f, (void *__iomem) - IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); - - printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); - - return 0; -} - -arch_initcall(davinci_gpio_irq_setup); diff --git a/trunk/arch/arm/mach-davinci/io.c b/trunk/arch/arm/mach-davinci/io.c index 47787ff84a6a..87fae6fb6ecf 100644 --- a/trunk/arch/arm/mach-davinci/io.c +++ b/trunk/arch/arm/mach-davinci/io.c @@ -17,7 +17,6 @@ #include #include -#include extern void davinci_check_revision(void); @@ -50,8 +49,3 @@ void __init davinci_map_common_io(void) */ davinci_check_revision(); } - -void __init davinci_init_common_hw(void) -{ - davinci_clk_init(); -} diff --git a/trunk/arch/arm/mach-davinci/mux.c b/trunk/arch/arm/mach-davinci/mux.c deleted file mode 100644 index 92d26bd305b7..000000000000 --- a/trunk/arch/arm/mach-davinci/mux.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * DaVinci pin multiplexing configurations - * - * Author: Vladimir Barinov, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#include -#include - -#include - -#include - -/* System control register offsets */ -#define PINMUX0 0x00 -#define PINMUX1 0x04 - -static DEFINE_SPINLOCK(mux_lock); - -void davinci_mux_peripheral(unsigned int mux, unsigned int enable) -{ - u32 pinmux, muxreg = PINMUX0; - - if (mux >= DAVINCI_MUX_LEVEL2) { - muxreg = PINMUX1; - mux -= DAVINCI_MUX_LEVEL2; - } - - spin_lock(&mux_lock); - pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg); - if (enable) - pinmux |= (1 << mux); - else - pinmux &= ~(1 << mux); - davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg); - spin_unlock(&mux_lock); -} diff --git a/trunk/arch/arm/mach-davinci/psc.c b/trunk/arch/arm/mach-davinci/psc.c index 1334416559ad..e1b0050283a6 100644 --- a/trunk/arch/arm/mach-davinci/psc.c +++ b/trunk/arch/arm/mach-davinci/psc.c @@ -25,40 +25,39 @@ #include #include #include -#include -/* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL1 0x304 -#define MDSTAT 0x800 -#define MDCTL 0xA00 +#define PTCMD __REG(0x01C41120) +#define PDSTAT __REG(0x01C41200) +#define PDCTL1 __REG(0x01C41304) +#define EPCPR __REG(0x01C41070) +#define PTSTAT __REG(0x01C41128) -/* System control register offsets */ -#define VDD3P3V_PWDN 0x48 +#define MDSTAT IO_ADDRESS(0x01C41800) +#define MDCTL IO_ADDRESS(0x01C41A00) + +#define PINMUX0 __REG(0x01c40000) +#define PINMUX1 __REG(0x01c40004) +#define VDD3P3V_PWDN __REG(0x01C40048) static void davinci_psc_mux(unsigned int id) { switch (id) { case DAVINCI_LPSC_ATA: - davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1); - davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1); + PINMUX0 |= (1 << 17) | (1 << 16); break; case DAVINCI_LPSC_MMC_SD: /* VDD power manupulations are done in U-Boot for CPMAC * so applies to MMC as well */ /*Set up the pull regiter for MMC */ - davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN); - davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0); + VDD3P3V_PWDN = 0x0; + PINMUX1 &= (~(1 << 9)); break; case DAVINCI_LPSC_I2C: - davinci_mux_peripheral(DAVINCI_MUX_I2C, 1); + PINMUX1 |= (1 << 7); break; case DAVINCI_LPSC_McBSP: - davinci_mux_peripheral(DAVINCI_MUX_ASP, 1); + PINMUX1 |= (1 << 10); break; default: break; @@ -68,59 +67,33 @@ static void davinci_psc_mux(unsigned int id) /* Enable or disable a PSC domain */ void davinci_psc_config(unsigned int domain, unsigned int id, char enable) { - u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask; + volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id); + volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id); if (id < 0) return; - mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); if (enable) - mdctl |= 0x00000003; /* Enable Module */ + *mdctl |= 0x00000003; /* Enable Module */ else - mdctl &= 0xFFFFFFF2; /* Disable Module */ - davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id); - - pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT); - if ((pdstat & 0x00000001) == 0) { - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); - pdctl1 |= 0x1; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); - - ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); + *mdctl &= 0xFFFFFFF2; /* Disable Module */ - do { - epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - EPCPR); - } while ((((epcpr >> domain) & 1) == 0)); + if ((PDSTAT & 0x00000001) == 0) { + PDCTL1 |= 0x1; + PTCMD = (1 << domain); + while ((((EPCPR >> domain) & 1) == 0)); - pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); - pdctl1 |= 0x100; - davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1); - - do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - PTSTAT); - } while (!(((ptstat >> domain) & 1) == 0)); + PDCTL1 |= 0x100; + while (!(((PTSTAT >> domain) & 1) == 0)); } else { - ptcmd = 1 << domain; - davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD); - - do { - ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - PTSTAT); - } while (!(((ptstat >> domain) & 1) == 0)); + PTCMD = (1 << domain); + while (!(((PTSTAT >> domain) & 1) == 0)); } if (enable) - mdstat_mask = 0x3; + while (!((*mdstat & 0x0000001F) == 0x3)); else - mdstat_mask = 0x2; - - do { - mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + - MDSTAT + 4 * id); - } while (!((mdstat & 0x0000001F) == mdstat_mask)); + while (!((*mdstat & 0x0000001F) == 0x2)); if (enable) davinci_psc_mux(id); diff --git a/trunk/arch/arm/mach-imx/generic.c b/trunk/arch/arm/mach-imx/generic.c index 1c474cf709ca..a58b678006df 100644 --- a/trunk/arch/arm/mach-imx/generic.c +++ b/trunk/arch/arm/mach-imx/generic.c @@ -28,12 +28,16 @@ #include #include +#include #include #include #include #include #include +#include + +unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG]; void imx_gpio_mode(int gpio_mode) { @@ -95,6 +99,120 @@ void imx_gpio_mode(int gpio_mode) EXPORT_SYMBOL(imx_gpio_mode); +int imx_gpio_request(unsigned gpio, const char *label) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) + printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n", + gpio, label ? label : "?"); + return -EINVAL; + + if(test_and_set_bit(gpio, imx_gpio_alloc_map)) { + printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n", + gpio, label ? label : "?"); + return -EBUSY; + } + + return 0; +} + +EXPORT_SYMBOL(imx_gpio_request); + +void imx_gpio_free(unsigned gpio) +{ + if(gpio >= (GPIO_PORT_MAX + 1) * 32) + return; + + clear_bit(gpio, imx_gpio_alloc_map); +} + +EXPORT_SYMBOL(imx_gpio_free); + +int imx_gpio_direction_input(unsigned gpio) +{ + imx_gpio_mode(gpio| GPIO_IN); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_input); + +int imx_gpio_direction_output(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); + imx_gpio_mode(gpio| GPIO_OUT); + return 0; +} + +EXPORT_SYMBOL(imx_gpio_direction_output); + +int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label) +{ + const int *p = pin_list; + int i; + unsigned gpio; + unsigned mode; + + for (i = 0; i < count; i++) { + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); + + if (gpio >= (GPIO_PORT_MAX + 1) * 32) + goto setup_error; + + if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE) + imx_gpio_free(gpio); + else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC)) + if (imx_gpio_request(gpio, label)) + if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + goto setup_error; + + if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY | + IMX_GPIO_ALLOC_MODE_RELEASE))) + imx_gpio_mode(gpio | mode); + + p++; + } + return 0; + +setup_error: + if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC | + IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) + return -EINVAL; + + while (p != pin_list) { + p--; + gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); + imx_gpio_free(gpio); + } + + return -EINVAL; +} + +EXPORT_SYMBOL(imx_gpio_setup_multiple_pins); + +void __imx_gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value_inline(gpio, value); +} + +EXPORT_SYMBOL(__imx_gpio_set_value); + +int imx_gpio_to_irq(unsigned gpio) +{ + return IRQ_GPIOA(0) + gpio; +} + +EXPORT_SYMBOL(imx_gpio_to_irq); + +int imx_irq_to_gpio(unsigned irq) +{ + if (irq < IRQ_GPIOA(0)) + return -EINVAL; + return irq - IRQ_GPIOA(0); +} + +EXPORT_SYMBOL(imx_irq_to_gpio); + /* * get the system pll clock in Hz * diff --git a/trunk/include/asm-arm/arch-davinci/clock.h b/trunk/include/asm-arm/arch-davinci/clock.h deleted file mode 100644 index cc168b7a14f2..000000000000 --- a/trunk/include/asm-arm/arch-davinci/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * include/asm-arm/arch-davinci/clock.h - * - * Clock control driver for DaVinci - header file - * - * Authors: Vladimir Barinov - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_DAVINCI_CLOCK_H -#define __ASM_ARCH_DAVINCI_CLOCK_H - -struct clk; - -extern int clk_register(struct clk *clk); -extern void clk_unregister(struct clk *clk); -extern int davinci_clk_init(void); - -#endif diff --git a/trunk/include/asm-arm/arch-davinci/gpio.h b/trunk/include/asm-arm/arch-davinci/gpio.h deleted file mode 100644 index ea24a0e0bfd6..000000000000 --- a/trunk/include/asm-arm/arch-davinci/gpio.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * TI DaVinci GPIO Support - * - * Copyright (c) 2006 David Brownell - * Copyright (c) 2007, MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __DAVINCI_GPIO_H -#define __DAVINCI_GPIO_H - -/* - * basic gpio routines - * - * board-specific init should be done by arch/.../.../board-XXX.c (maybe - * initializing banks together) rather than boot loaders; kexec() won't - * go through boot loaders. - * - * the gpio clock will be turned on when gpios are used, and you may also - * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are - * used as gpios, not with other peripherals. - * - * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe - * for later updates, code should write GPIO(N) or: - * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) - * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) - * - * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc - * for now, that's != GPIO(N) - */ -#define GPIO(X) (X) /* 0 <= X <= 70 */ -#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ -#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ - -struct gpio_controller { - u32 dir; - u32 out_data; - u32 set_data; - u32 clr_data; - u32 in_data; - u32 set_rising; - u32 clr_rising; - u32 set_falling; - u32 clr_falling; - u32 intstat; -}; - -/* The __gpio_to_controller() and __gpio_mask() functions inline to constants - * with constant parameters; or in outlined code they execute at runtime. - * - * You'd access the controller directly when reading or writing more than - * one gpio value at a time, and to support wired logic where the value - * being driven by the cpu need not match the value read back. - * - * These are NOT part of the cross-platform GPIO interface - */ -static inline struct gpio_controller *__iomem -__gpio_to_controller(unsigned gpio) -{ - void *__iomem ptr; - - if (gpio < 32) - ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); - else if (gpio < 64) - ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); - else if (gpio < DAVINCI_N_GPIO) - ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); - else - ptr = NULL; - return ptr; -} - -static inline u32 __gpio_mask(unsigned gpio) -{ - return 1 << (gpio % 32); -} - -/* The get/set/clear functions will inline when called with constant - * parameters, for low-overhead bitbanging. Illegal constant parameters - * cause link-time errors. - * - * Otherwise, calls with variable parameters use outlined functions. - */ -extern int __error_inval_gpio(void); - -extern void __gpio_set(unsigned gpio, int value); -extern int __gpio_get(unsigned gpio); - -static inline void gpio_set_value(unsigned gpio, int value) -{ - if (__builtin_constant_p(value)) { - struct gpio_controller *__iomem g; - u32 mask; - - if (gpio >= DAVINCI_N_GPIO) - __error_inval_gpio(); - - g = __gpio_to_controller(gpio); - mask = __gpio_mask(gpio); - if (value) - __raw_writel(mask, &g->set_data); - else - __raw_writel(mask, &g->clr_data); - return; - } - - __gpio_set(gpio, value); -} - -/* Returns zero or nonzero; works for gpios configured as inputs OR - * as outputs. - * - * NOTE: changes in reported values are synchronized to the GPIO clock. - * This is most easily seen after calling gpio_set_value() and then immediatly - * gpio_get_value(), where the gpio_get_value() would return the old value - * until the GPIO clock ticks and the new value gets latched. - */ - -static inline int gpio_get_value(unsigned gpio) -{ - struct gpio_controller *__iomem g; - - if (!__builtin_constant_p(gpio)) - return __gpio_get(gpio); - - if (gpio >= DAVINCI_N_GPIO) - return __error_inval_gpio(); - - g = __gpio_to_controller(gpio); - return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); -} - -/* powerup default direction is IN */ -extern int gpio_direction_input(unsigned gpio); -extern int gpio_direction_output(unsigned gpio, int value); - -#include /* cansleep wrappers */ - -extern int gpio_request(unsigned gpio, const char *tag); -extern void gpio_free(unsigned gpio); - -static inline int gpio_to_irq(unsigned gpio) -{ - return DAVINCI_N_AINTC_IRQ + gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq - DAVINCI_N_AINTC_IRQ; -} - -#endif /* __DAVINCI_GPIO_H */ diff --git a/trunk/include/asm-arm/arch-davinci/hardware.h b/trunk/include/asm-arm/arch-davinci/hardware.h index a2e8969afaca..60362d80229e 100644 --- a/trunk/include/asm-arm/arch-davinci/hardware.h +++ b/trunk/include/asm-arm/arch-davinci/hardware.h @@ -11,42 +11,4 @@ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H -/* - * Base register addresses - */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) - #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/trunk/include/asm-arm/arch-davinci/mux.h b/trunk/include/asm-arm/arch-davinci/mux.h deleted file mode 100644 index c24b6782804d..000000000000 --- a/trunk/include/asm-arm/arch-davinci/mux.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * DaVinci pin multiplexing defines - * - * Author: Vladimir Barinov, MontaVista Software, Inc. - * - * 2007 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -#define DAVINCI_MUX_AEAW0 0 -#define DAVINCI_MUX_AEAW1 1 -#define DAVINCI_MUX_AEAW2 2 -#define DAVINCI_MUX_AEAW3 3 -#define DAVINCI_MUX_AEAW4 4 -#define DAVINCI_MUX_AECS4 10 -#define DAVINCI_MUX_AECS5 11 -#define DAVINCI_MUX_VLYNQWD0 12 -#define DAVINCI_MUX_VLYNQWD1 13 -#define DAVINCI_MUX_VLSCREN 14 -#define DAVINCI_MUX_VLYNQEN 15 -#define DAVINCI_MUX_HDIREN 16 -#define DAVINCI_MUX_ATAEN 17 -#define DAVINCI_MUX_RGB666 22 -#define DAVINCI_MUX_RGB888 23 -#define DAVINCI_MUX_LOEEN 24 -#define DAVINCI_MUX_LFLDEN 25 -#define DAVINCI_MUX_CWEN 26 -#define DAVINCI_MUX_CFLDEN 27 -#define DAVINCI_MUX_HPIEN 29 -#define DAVINCI_MUX_1394EN 30 -#define DAVINCI_MUX_EMACEN 31 - -#define DAVINCI_MUX_LEVEL2 32 -#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) -#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) -#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) -#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) -#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) -#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) -#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) -#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) -#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) -#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) -#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) -#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) -#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) -#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) - -extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); - -#endif /* __ASM_ARCH_MUX_H */ diff --git a/trunk/include/asm-arm/arch-imx/gpio.h b/trunk/include/asm-arm/arch-imx/gpio.h new file mode 100644 index 000000000000..486023263f32 --- /dev/null +++ b/trunk/include/asm-arm/arch-imx/gpio.h @@ -0,0 +1,102 @@ +#ifndef _IMX_GPIO_H + +#include + +#define IMX_GPIO_ALLOC_MODE_NORMAL 0 +#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 +#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 +#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 +#define IMX_GPIO_ALLOC_MODE_RELEASE 8 + +extern int imx_gpio_request(unsigned gpio, const char *label); + +extern void imx_gpio_free(unsigned gpio); + +extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + int alloc_mode, const char *label); + +extern int imx_gpio_direction_input(unsigned gpio); + +extern int imx_gpio_direction_output(unsigned gpio, int value); + +extern void __imx_gpio_set_value(unsigned gpio, int value); + +static inline int imx_gpio_get_value(unsigned gpio) +{ + return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); +} + +static inline void imx_gpio_set_value_inline(unsigned gpio, int value) +{ + unsigned long flags; + + raw_local_irq_save(flags); + if(value) + DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); + else + DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); + raw_local_irq_restore(flags); +} + +static inline void imx_gpio_set_value(unsigned gpio, int value) +{ + if(__builtin_constant_p(gpio)) + imx_gpio_set_value_inline(gpio, value); + else + __imx_gpio_set_value(gpio, value); +} + +extern int imx_gpio_to_irq(unsigned gpio); + +extern int imx_irq_to_gpio(unsigned irq); + +/*-------------------------------------------------------------------------*/ + +/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions + * to allow future extension of GPIO logic. + */ + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return imx_gpio_request(gpio, label); +} + +static inline void gpio_free(unsigned gpio) +{ + imx_gpio_free(gpio); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return imx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return imx_gpio_direction_output(gpio, value); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return imx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + imx_gpio_set_value(gpio, value); +} + +#include /* cansleep wrappers */ + +static inline int gpio_to_irq(unsigned gpio) +{ + return imx_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return imx_irq_to_gpio(irq); +} + + +#endif diff --git a/trunk/include/asm-arm/arch-imx/imx-regs.h b/trunk/include/asm-arm/arch-imx/imx-regs.h index 30de404c61f5..fb9de2733879 100644 --- a/trunk/include/asm-arm/arch-imx/imx-regs.h +++ b/trunk/include/asm-arm/arch-imx/imx-regs.h @@ -77,6 +77,8 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define GPIO_PORT_MAX 3 + #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5)