From d4377a64e52ae9883885dad5d511522511d3b64e Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 16 Sep 2006 00:12:53 +0100 Subject: [PATCH] --- yaml --- r: 36572 b: refs/heads/master c: 34148c6990d2f0107b53fe4ddf29b1ba30e613d3 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/asm-arm/arch-s3c2410/regs-lcd.h | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index eac23d6c8b4d..d613e40f49dd 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3e9fc8e5de0fb00226325cf34eb08411eb72ec6d +refs/heads/master: 34148c6990d2f0107b53fe4ddf29b1ba30e613d3 diff --git a/trunk/include/asm-arm/arch-s3c2410/regs-lcd.h b/trunk/include/asm-arm/arch-s3c2410/regs-lcd.h index d8f1adfd17f0..6d7881c8cfc8 100644 --- a/trunk/include/asm-arm/arch-s3c2410/regs-lcd.h +++ b/trunk/include/asm-arm/arch-s3c2410/regs-lcd.h @@ -63,6 +63,8 @@ #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) +/* LDCCON4 changes for STN mode on the S3C2412 */ + #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) #define S3C2410_LCDCON4_WLH(x) ((x) << 0) @@ -124,6 +126,27 @@ #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) +/* S3C2412 registers */ + +#define S3C2412_TPAL S3C2410_LCDREG(0x20) + +#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) +#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) +#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) + +#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) + +#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) +#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) +#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) +#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) + +#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) +#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) +#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) + +#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) + #endif /* ___ASM_ARCH_REGS_LCD_H */