diff --git a/[refs] b/[refs] index 3e8a6a6ab122..b964e8d913da 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 03cfbdf9f7a1d392146718f67e50fa9ab2844f22 +refs/heads/master: d4686c654bb1d7ea226578d5725ca34911d6e34c diff --git a/trunk/drivers/video/sh_mobile_hdmi.c b/trunk/drivers/video/sh_mobile_hdmi.c index b19941d37ed4..d7df10315d8d 100644 --- a/trunk/drivers/video/sh_mobile_hdmi.c +++ b/trunk/drivers/video/sh_mobile_hdmi.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include diff --git a/trunk/include/sound/soc-dapm.h b/trunk/include/sound/soc-dapm.h index 8031769ac485..2f76a51bbaac 100644 --- a/trunk/include/sound/soc-dapm.h +++ b/trunk/include/sound/soc-dapm.h @@ -93,9 +93,6 @@ #define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ { .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1} -#define SND_SOC_DAPM_VIRT_MUX(wname, wreg, wshift, winvert, wcontrols) \ -{ .id = snd_soc_dapm_virt_mux, .name = wname, .reg = wreg, .shift = wshift, \ - .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1} #define SND_SOC_DAPM_VALUE_MUX(wname, wreg, wshift, winvert, wcontrols) \ { .id = snd_soc_dapm_value_mux, .name = wname, .reg = wreg, \ .shift = wshift, .invert = winvert, .kcontrols = wcontrols, \ @@ -151,11 +148,6 @@ { .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1, \ .event = wevent, .event_flags = wflags} -#define SND_SOC_DAPM_VIRT_MUX_E(wname, wreg, wshift, winvert, wcontrols, \ - wevent, wflags) \ -{ .id = snd_soc_dapm_virt_mux, .name = wname, .reg = wreg, .shift = wshift, \ - .invert = winvert, .kcontrols = wcontrols, .num_kcontrols = 1, \ - .event = wevent, .event_flags = wflags} /* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ #define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ @@ -235,6 +227,13 @@ .info = snd_soc_info_volsw, \ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } +#define SOC_DAPM_DOUBLE(xname, reg, shift_left, shift_right, max, invert, \ + power) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) |\ + ((max) << 16) | ((invert) << 24) } #define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_soc_info_volsw, \ @@ -242,6 +241,15 @@ .tlv.p = (tlv_array), \ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } +#define SOC_DAPM_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, \ + power, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) |\ + ((max) << 16) | ((invert) << 24) } #define SOC_DAPM_ENUM(xname, xenum) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_soc_info_enum_double, \ @@ -365,7 +373,6 @@ enum snd_soc_dapm_type { snd_soc_dapm_input = 0, /* input pin */ snd_soc_dapm_output, /* output pin */ snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ - snd_soc_dapm_virt_mux, /* virtual version of snd_soc_dapm_mux */ snd_soc_dapm_value_mux, /* selects 1 analog signal from many inputs */ snd_soc_dapm_mixer, /* mixes several analog signals together */ snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ @@ -469,32 +476,18 @@ struct snd_soc_dapm_widget { struct list_head power_list; }; -struct snd_soc_dapm_update { - struct snd_soc_dapm_widget *widget; - struct snd_kcontrol *kcontrol; - int reg; - int mask; - int val; -}; - /* DAPM context */ struct snd_soc_dapm_context { - int n_widgets; /* number of widgets in this context */ + struct list_head widgets; + struct list_head paths; enum snd_soc_bias_level bias_level; enum snd_soc_bias_level suspend_bias_level; struct delayed_work delayed_work; unsigned int idle_bias_off:1; /* Use BIAS_OFF instead of STANDBY */ - struct snd_soc_dapm_update *update; - struct device *dev; /* from parent - for debug */ struct snd_soc_codec *codec; /* parent codec */ struct snd_soc_card *card; /* parent card */ - - /* used during DAPM updates */ - int dev_power; - struct list_head list; - #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_dapm; #endif diff --git a/trunk/include/sound/soc.h b/trunk/include/sound/soc.h index 74921f20a1d8..7e65b015f8dd 100644 --- a/trunk/include/sound/soc.h +++ b/trunk/include/sound/soc.h @@ -661,10 +661,6 @@ struct snd_soc_card { struct list_head platform_dev_list; struct list_head dai_dev_list; - struct list_head widgets; - struct list_head paths; - struct list_head dapm_list; - #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_card_root; struct dentry *debugfs_pop_time; diff --git a/trunk/sound/soc/Kconfig b/trunk/sound/soc/Kconfig index a3efc52a34da..21a5465ceb65 100644 --- a/trunk/sound/soc/Kconfig +++ b/trunk/sound/soc/Kconfig @@ -4,6 +4,8 @@ menuconfig SND_SOC tristate "ALSA for SoC audio support" + select LZO_COMPRESS + select LZO_DECOMPRESS select SND_PCM select AC97_BUS if SND_SOC_AC97_BUS select SND_JACK if INPUT=y || INPUT=SND @@ -20,21 +22,6 @@ menuconfig SND_SOC if SND_SOC -config SND_SOC_CACHE_LZO - bool "Support LZO compression for register caches" - select LZO_COMPRESS - select LZO_DECOMPRESS - ---help--- - Select this to enable LZO compression for register caches. - This will allow machine or CODEC drivers to compress register - caches in memory, reducing the memory consumption at the - expense of performance. If this is not present and is used - the system will fall back to uncompressed caches. - - Usually it is safe to disable this option, where cache - compression in used the rbtree option will typically perform - better. - config SND_SOC_AC97_BUS bool diff --git a/trunk/sound/soc/codecs/88pm860x-codec.c b/trunk/sound/soc/codecs/88pm860x-codec.c index 06b6981b8d6d..08e15dee9182 100644 --- a/trunk/sound/soc/codecs/88pm860x-codec.c +++ b/trunk/sound/soc/codecs/88pm860x-codec.c @@ -22,7 +22,6 @@ #include #include #include -#include #include "88pm860x-codec.h" @@ -146,6 +145,7 @@ struct pm860x_priv { int irq[4]; unsigned char name[4][MAX_NAME_LEN]; + unsigned char reg_cache[REG_CACHE_SIZE]; }; /* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */ @@ -1262,12 +1262,6 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data) mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt | pm860x->det.hp_det; -#ifndef CONFIG_SND_SOC_88PM860X_MODULE - if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 | - SHORT_LO1 | SHORT_LO2)) - trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev)); -#endif - if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) && (status & HEADSET_STATUS)) report |= SND_JACK_HEADPHONE; diff --git a/trunk/sound/soc/codecs/Kconfig b/trunk/sound/soc/codecs/Kconfig index 054191ed08ef..0f33db2be25a 100644 --- a/trunk/sound/soc/codecs/Kconfig +++ b/trunk/sound/soc/codecs/Kconfig @@ -78,7 +78,6 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8990 if I2C select SND_SOC_WM8993 if I2C select SND_SOC_WM8994 if MFD_WM8994 - select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI select SND_SOC_WM9081 if I2C select SND_SOC_WM9090 if I2C select SND_SOC_WM9705 if SND_SOC_AC97_BUS @@ -307,9 +306,6 @@ config SND_SOC_WM8993 config SND_SOC_WM8994 tristate -config SND_SOC_WM8995 - tristate - config SND_SOC_WM9081 tristate diff --git a/trunk/sound/soc/codecs/Makefile b/trunk/sound/soc/codecs/Makefile index 6a1e17bbbf83..10e5e099334a 100644 --- a/trunk/sound/soc/codecs/Makefile +++ b/trunk/sound/soc/codecs/Makefile @@ -62,7 +62,6 @@ snd-soc-wm8988-objs := wm8988.o snd-soc-wm8990-objs := wm8990.o snd-soc-wm8993-objs := wm8993.o snd-soc-wm8994-objs := wm8994.o wm8994-tables.o -snd-soc-wm8995-objs := wm8995.o snd-soc-wm9081-objs := wm9081.o snd-soc-wm9705-objs := wm9705.o snd-soc-wm9712-objs := wm9712.o @@ -141,7 +140,6 @@ obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o -obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o diff --git a/trunk/sound/soc/codecs/ad193x.c b/trunk/sound/soc/codecs/ad193x.c index da46479bfcfa..a007bd7326fd 100644 --- a/trunk/sound/soc/codecs/ad193x.c +++ b/trunk/sound/soc/codecs/ad193x.c @@ -23,6 +23,7 @@ /* codec private data */ struct ad193x_priv { + u8 reg_cache[AD193X_NUM_REGS]; enum snd_soc_control_type bus_type; void *control_data; int sysclk; diff --git a/trunk/sound/soc/codecs/ak4671.c b/trunk/sound/soc/codecs/ak4671.c index 2ec75abfa3e9..4faf10553a30 100644 --- a/trunk/sound/soc/codecs/ak4671.c +++ b/trunk/sound/soc/codecs/ak4671.c @@ -27,6 +27,7 @@ struct ak4671_priv { enum snd_soc_control_type control_type; void *control_data; + u8 reg_cache[AK4671_CACHEREGNUM]; }; /* ak4671 register cache & default register settings */ diff --git a/trunk/sound/soc/codecs/cs4270.c b/trunk/sound/soc/codecs/cs4270.c index 3a582caa6ef9..6d4bdc609ac8 100644 --- a/trunk/sound/soc/codecs/cs4270.c +++ b/trunk/sound/soc/codecs/cs4270.c @@ -114,6 +114,7 @@ static const char *supply_names[] = { struct cs4270_private { enum snd_soc_control_type control_type; void *control_data; + u8 reg_cache[CS4270_NUMREGS]; unsigned int mclk; /* Input frequency of the MCLK pin */ unsigned int mode; /* The mode (I2S or left-justified) */ unsigned int slave_mode; diff --git a/trunk/sound/soc/codecs/cs42l51.c b/trunk/sound/soc/codecs/cs42l51.c index 8fb7070108dd..d4e60dc45bf6 100644 --- a/trunk/sound/soc/codecs/cs42l51.c +++ b/trunk/sound/soc/codecs/cs42l51.c @@ -46,6 +46,7 @@ struct cs42l51_private { unsigned int mclk; unsigned int audio_mode; /* The mode (I2S or left-justified) */ enum master_slave_mode func; + u8 reg_cache[CS42L51_NUMREGS]; }; #define CS42L51_FORMATS ( \ diff --git a/trunk/sound/soc/codecs/cx20442.c b/trunk/sound/soc/codecs/cx20442.c index 03d1e860d229..a9521acad99c 100644 --- a/trunk/sound/soc/codecs/cx20442.c +++ b/trunk/sound/soc/codecs/cx20442.c @@ -26,6 +26,7 @@ struct cx20442_priv { enum snd_soc_control_type control_type; void *control_data; + u8 reg_cache[1]; }; #define CX20442_PM 0x0 diff --git a/trunk/sound/soc/codecs/max98088.c b/trunk/sound/soc/codecs/max98088.c index 37133c40e762..335a002aaf0e 100644 --- a/trunk/sound/soc/codecs/max98088.c +++ b/trunk/sound/soc/codecs/max98088.c @@ -39,6 +39,7 @@ struct max98088_cdata { }; struct max98088_priv { + u8 reg_cache[M98088_REG_CNT]; enum max98088_type devtype; void *control_data; struct max98088_pdata *pdata; @@ -1588,7 +1589,7 @@ static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, static void max98088_sync_cache(struct snd_soc_codec *codec) { - u16 *reg_cache = codec->reg_cache; + struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); int i; if (!codec->cache_sync) @@ -1599,14 +1600,14 @@ static void max98088_sync_cache(struct snd_soc_codec *codec) /* write back cached values if they're writeable and * different from the hardware default. */ - for (i = 1; i < codec->driver->reg_cache_size; i++) { + for (i = 1; i < ARRAY_SIZE(max98088->reg_cache); i++) { if (!max98088_access[i].writable) continue; - if (reg_cache[i] == max98088_reg[i]) + if (max98088->reg_cache[i] == max98088_reg[i]) continue; - snd_soc_write(codec, i, reg_cache[i]); + snd_soc_write(codec, i, max98088->reg_cache[i]); } codec->cache_sync = 0; @@ -1951,6 +1952,7 @@ static int max98088_probe(struct snd_soc_codec *codec) int ret = 0; codec->cache_sync = 1; + memcpy(codec->reg_cache, max98088_reg, sizeof(max98088_reg)); ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); if (ret != 0) { diff --git a/trunk/sound/soc/codecs/tlv320aic26.c b/trunk/sound/soc/codecs/tlv320aic26.c index e2a7608d3944..68f0ae47f608 100644 --- a/trunk/sound/soc/codecs/tlv320aic26.c +++ b/trunk/sound/soc/codecs/tlv320aic26.c @@ -30,6 +30,7 @@ MODULE_LICENSE("GPL"); struct aic26 { struct spi_device *spi; struct snd_soc_codec codec; + u16 reg_cache[AIC26_NUM_REGS]; /* shadow registers */ int master; int datfm; int mclk; @@ -353,6 +354,7 @@ static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set); */ static int aic26_probe(struct snd_soc_codec *codec) { + struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); int ret, err, i, reg; dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n"); @@ -370,7 +372,7 @@ static int aic26_probe(struct snd_soc_codec *codec) aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); /* Fill register cache */ - for (i = 0; i < codec->driver->reg_cache_size; i++) + for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++) aic26_reg_read(codec, i); /* Register the sysfs files for debugging */ diff --git a/trunk/sound/soc/codecs/tlv320aic3x.c b/trunk/sound/soc/codecs/tlv320aic3x.c index 3bedab26892f..8cd4cf5c44dc 100644 --- a/trunk/sound/soc/codecs/tlv320aic3x.c +++ b/trunk/sound/soc/codecs/tlv320aic3x.c @@ -185,7 +185,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->card->paths, list) { + list_for_each_entry(path, &widget->dapm->paths, list) { if (path->kcontrol != kcontrol) continue; diff --git a/trunk/sound/soc/codecs/uda1380.c b/trunk/sound/soc/codecs/uda1380.c index c5ca8cfea60f..800980e2e9ab 100644 --- a/trunk/sound/soc/codecs/uda1380.c +++ b/trunk/sound/soc/codecs/uda1380.c @@ -35,6 +35,7 @@ /* codec private data */ struct uda1380_priv { struct snd_soc_codec *codec; + u16 reg_cache[UDA1380_CACHEREGNUM]; unsigned int dac_clk; struct work_struct work; void *control_data; diff --git a/trunk/sound/soc/codecs/wm8350.c b/trunk/sound/soc/codecs/wm8350.c index 6d6dc9efe914..07ba7e3f6a8c 100644 --- a/trunk/sound/soc/codecs/wm8350.c +++ b/trunk/sound/soc/codecs/wm8350.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "wm8350.h" @@ -54,7 +53,6 @@ struct wm8350_output { struct wm8350_jack_data { struct snd_soc_jack *jack; - struct delayed_work work; int report; int short_report; }; @@ -1337,69 +1335,45 @@ static int wm8350_resume(struct snd_soc_codec *codec) return 0; } -static void wm8350_hp_work(struct wm8350_data *priv, - struct wm8350_jack_data *jack, - u16 mask) -{ - struct wm8350 *wm8350 = priv->codec.control_data; - u16 reg; - int report; - - reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); - if (reg & mask) - report = jack->report; - else - report = 0; - - snd_soc_jack_report(jack->jack, report, jack->report); - -} - -static void wm8350_hpl_work(struct work_struct *work) -{ - struct wm8350_data *priv = - container_of(work, struct wm8350_data, hpl.work.work); - - wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL); -} - -static void wm8350_hpr_work(struct work_struct *work) -{ - struct wm8350_data *priv = - container_of(work, struct wm8350_data, hpr.work.work); - - wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); -} - static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) { struct wm8350_data *priv = data; struct wm8350 *wm8350 = priv->codec.control_data; + u16 reg; + int report; + int mask; struct wm8350_jack_data *jack = NULL; switch (irq - wm8350->irq_base) { case WM8350_IRQ_CODEC_JCK_DET_L: -#ifndef CONFIG_SND_SOC_WM8350_MODULE - trace_snd_soc_jack_irq("WM8350 HPL"); -#endif jack = &priv->hpl; + mask = WM8350_JACK_L_LVL; break; case WM8350_IRQ_CODEC_JCK_DET_R: -#ifndef CONFIG_SND_SOC_WM8350_MODULE - trace_snd_soc_jack_irq("WM8350 HPR"); -#endif jack = &priv->hpr; + mask = WM8350_JACK_R_LVL; break; default: BUG(); } - if (device_may_wakeup(wm8350->dev)) - pm_wakeup_event(wm8350->dev, 250); + if (!jack->jack) { + dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); + return IRQ_NONE; + } - schedule_delayed_work(&jack->work, 200); + /* Debounce */ + msleep(200); + + reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); + if (reg & mask) + report = jack->report; + else + report = 0; + + snd_soc_jack_report(jack->jack, report, jack->report); return IRQ_HANDLED; } @@ -1463,10 +1437,6 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data) u16 reg; int report = 0; -#ifndef CONFIG_SND_SOC_WM8350_MODULE - trace_snd_soc_jack_irq("WM8350 mic"); -#endif - reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); if (reg & WM8350_JACK_MICSCD_LVL) report |= priv->mic.short_report; @@ -1582,8 +1552,6 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec) wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); - INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work); - INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work); /* Enable the codec */ wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); @@ -1673,9 +1641,6 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec) priv->hpr.jack = NULL; priv->mic.jack = NULL; - cancel_delayed_work_sync(&priv->hpl.work); - cancel_delayed_work_sync(&priv->hpr.work); - /* if there was any work waiting then we run it now and * wait for its completion */ flush_delayed_work_sync(&codec->dapm.delayed_work); diff --git a/trunk/sound/soc/codecs/wm8523.c b/trunk/sound/soc/codecs/wm8523.c index 5eb2f501ce32..08f3189f4b3f 100644 --- a/trunk/sound/soc/codecs/wm8523.c +++ b/trunk/sound/soc/codecs/wm8523.c @@ -40,6 +40,7 @@ static const char *wm8523_supply_names[WM8523_NUM_SUPPLIES] = { /* codec private data */ struct wm8523_priv { enum snd_soc_control_type control_type; + u16 reg_cache[WM8523_REGISTER_COUNT]; struct regulator_bulk_data supplies[WM8523_NUM_SUPPLIES]; unsigned int sysclk; unsigned int rate_constraint_list[WM8523_NUM_RATES]; @@ -313,7 +314,6 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int ret, i; switch (level) { @@ -344,7 +344,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec, /* Sync back default/cached values */ for (i = WM8523_AIF_CTRL1; i < WM8523_MAX_REGISTER; i++) - snd_soc_write(codec, i, reg_cache[i]); + snd_soc_write(codec, i, wm8523->reg_cache[i]); msleep(100); @@ -414,7 +414,6 @@ static int wm8523_resume(struct snd_soc_codec *codec) static int wm8523_probe(struct snd_soc_codec *codec) { struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int ret, i; codec->hw_write = (hw_write_t)i2c_master_send; @@ -471,8 +470,8 @@ static int wm8523_probe(struct snd_soc_codec *codec) } /* Change some default settings - latch VU and enable ZC */ - reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU; - reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC; + wm8523->reg_cache[WM8523_DAC_GAINR] |= WM8523_DACR_VU; + wm8523->reg_cache[WM8523_DAC_CTRL3] |= WM8523_ZC; wm8523_set_bias_level(codec, SND_SOC_BIAS_STANDBY); diff --git a/trunk/sound/soc/codecs/wm8580.c b/trunk/sound/soc/codecs/wm8580.c index 8f6b5ee6645b..0ebdecfd27a9 100644 --- a/trunk/sound/soc/codecs/wm8580.c +++ b/trunk/sound/soc/codecs/wm8580.c @@ -190,6 +190,7 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { struct wm8580_priv { enum snd_soc_control_type control_type; struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; + u16 reg_cache[WM8580_MAX_REGISTER + 1]; struct pll_state a; struct pll_state b; int sysclk[2]; diff --git a/trunk/sound/soc/codecs/wm8711.c b/trunk/sound/soc/codecs/wm8711.c index 97c30382d3ff..fec37ebfdb34 100644 --- a/trunk/sound/soc/codecs/wm8711.c +++ b/trunk/sound/soc/codecs/wm8711.c @@ -33,6 +33,7 @@ /* codec private data */ struct wm8711_priv { enum snd_soc_control_type bus_type; + u16 reg_cache[WM8711_CACHEREGNUM]; unsigned int sysclk; }; diff --git a/trunk/sound/soc/codecs/wm8731.c b/trunk/sound/soc/codecs/wm8731.c index 0a67c31b2663..71122dc36826 100644 --- a/trunk/sound/soc/codecs/wm8731.c +++ b/trunk/sound/soc/codecs/wm8731.c @@ -43,6 +43,7 @@ static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = { struct wm8731_priv { enum snd_soc_control_type control_type; struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES]; + u16 reg_cache[WM8731_CACHEREGNUM]; unsigned int sysclk; int sysclk_type; int playback_fs; diff --git a/trunk/sound/soc/codecs/wm8741.c b/trunk/sound/soc/codecs/wm8741.c index 494f2d31d75b..35789b7dcacf 100644 --- a/trunk/sound/soc/codecs/wm8741.c +++ b/trunk/sound/soc/codecs/wm8741.c @@ -40,6 +40,7 @@ static const char *wm8741_supply_names[WM8741_NUM_SUPPLIES] = { /* codec private data */ struct wm8741_priv { enum snd_soc_control_type control_type; + u16 reg_cache[WM8741_REGISTER_COUNT]; struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES]; unsigned int sysclk; struct snd_pcm_hw_constraint_list *sysclk_constraints; @@ -421,7 +422,6 @@ static int wm8741_resume(struct snd_soc_codec *codec) static int wm8741_probe(struct snd_soc_codec *codec) { struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int ret = 0; ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8741->control_type); @@ -437,10 +437,10 @@ static int wm8741_probe(struct snd_soc_codec *codec) } /* Change some default settings - latch VU */ - reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL; - reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM; - reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL; - reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM; + wm8741->reg_cache[WM8741_DACLLSB_ATTENUATION] |= WM8741_UPDATELL; + wm8741->reg_cache[WM8741_DACLMSB_ATTENUATION] |= WM8741_UPDATELM; + wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERL; + wm8741->reg_cache[WM8741_DACRLSB_ATTENUATION] |= WM8741_UPDATERM; snd_soc_add_controls(codec, wm8741_snd_controls, ARRAY_SIZE(wm8741_snd_controls)); diff --git a/trunk/sound/soc/codecs/wm8750.c b/trunk/sound/soc/codecs/wm8750.c index 38f38fddd190..51280e96d721 100644 --- a/trunk/sound/soc/codecs/wm8750.c +++ b/trunk/sound/soc/codecs/wm8750.c @@ -52,6 +52,7 @@ static const u16 wm8750_reg[] = { struct wm8750_priv { unsigned int sysclk; enum snd_soc_control_type control_type; + u16 reg_cache[ARRAY_SIZE(wm8750_reg)]; }; #define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0) diff --git a/trunk/sound/soc/codecs/wm8753.c b/trunk/sound/soc/codecs/wm8753.c index 79b02ae125c5..73507e71cb79 100644 --- a/trunk/sound/soc/codecs/wm8753.c +++ b/trunk/sound/soc/codecs/wm8753.c @@ -64,22 +64,22 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec, * are using 2 wire for device control, so we cache them instead. */ static const u16 wm8753_reg[] = { - 0x0000, 0x0008, 0x0000, 0x000a, - 0x000a, 0x0033, 0x0000, 0x0007, - 0x00ff, 0x00ff, 0x000f, 0x000f, - 0x007b, 0x0000, 0x0032, 0x0000, - 0x00c3, 0x00c3, 0x00c0, 0x0000, + 0x0008, 0x0000, 0x000a, 0x000a, + 0x0033, 0x0000, 0x0007, 0x00ff, + 0x00ff, 0x000f, 0x000f, 0x007b, + 0x0000, 0x0032, 0x0000, 0x00c3, + 0x00c3, 0x00c0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, - 0x0055, 0x0005, 0x0050, 0x0055, - 0x0050, 0x0055, 0x0050, 0x0055, + 0x0000, 0x0000, 0x0000, 0x0055, + 0x0005, 0x0050, 0x0055, 0x0050, + 0x0055, 0x0050, 0x0055, 0x0079, 0x0079, 0x0079, 0x0079, 0x0079, - 0x0079, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0097, 0x0097, 0x0000, - 0x0004, 0x0000, 0x0083, 0x0024, - 0x01ba, 0x0000, 0x0083, 0x0024, - 0x01ba, 0x0000, 0x0000, 0x0000 + 0x0000, 0x0000, 0x0000, 0x0000, + 0x0097, 0x0097, 0x0000, 0x0004, + 0x0000, 0x0083, 0x0024, 0x01ba, + 0x0000, 0x0083, 0x0024, 0x01ba, + 0x0000, 0x0000, 0x0000 }; /* codec private data */ @@ -87,10 +87,57 @@ struct wm8753_priv { enum snd_soc_control_type control_type; unsigned int sysclk; unsigned int pcmclk; + u16 reg_cache[ARRAY_SIZE(wm8753_reg)]; int dai_func; }; -#define wm8753_reset(c) snd_soc_write(c, WM8753_RESET, 0) +/* + * read wm8753 register cache + */ +static inline unsigned int wm8753_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1)) + return -1; + return cache[reg - 1]; +} + +/* + * write wm8753 register cache + */ +static inline void wm8753_write_reg_cache(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1)) + return; + cache[reg - 1] = value; +} + +/* + * write to the WM8753 register space + */ +static int wm8753_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + /* data is + * D15..D9 WM8753 register offset + * D8...D0 register data + */ + data[0] = (reg << 1) | ((value >> 8) & 0x0001); + data[1] = value & 0x00ff; + + wm8753_write_reg_cache(codec, reg, value); + if (codec->hw_write(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +#define wm8753_reset(c) wm8753_write(c, WM8753_RESET, 0) /* * WM8753 Controls @@ -170,7 +217,7 @@ static int wm8753_get_dai(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - int mode = snd_soc_read(codec, WM8753_IOCTL); + int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL); ucontrol->value.integer.value[0] = (mode & 0xc) >> 2; return 0; @@ -180,7 +227,7 @@ static int wm8753_set_dai(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - int mode = snd_soc_read(codec, WM8753_IOCTL); + int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL); struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0]) @@ -691,17 +738,17 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, if (pll_id == WM8753_PLL1) { offset = 0; enable = 0x10; - reg = snd_soc_read(codec, WM8753_CLOCK) & 0xffef; + reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xffef; } else { offset = 4; enable = 0x8; - reg = snd_soc_read(codec, WM8753_CLOCK) & 0xfff7; + reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfff7; } if (!freq_in || !freq_out) { /* disable PLL */ - snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0026); - snd_soc_write(codec, WM8753_CLOCK, reg); + wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0026); + wm8753_write(codec, WM8753_CLOCK, reg); return 0; } else { u16 value = 0; @@ -712,20 +759,20 @@ static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, /* set up N and K PLL divisor ratios */ /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */ value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18); - snd_soc_write(codec, WM8753_PLL1CTL2 + offset, value); + wm8753_write(codec, WM8753_PLL1CTL2 + offset, value); /* bits 8:0 = PLL_K[17:9] */ value = (pll_div.k & 0x03fe00) >> 9; - snd_soc_write(codec, WM8753_PLL1CTL3 + offset, value); + wm8753_write(codec, WM8753_PLL1CTL3 + offset, value); /* bits 8:0 = PLL_K[8:0] */ value = pll_div.k & 0x0001ff; - snd_soc_write(codec, WM8753_PLL1CTL4 + offset, value); + wm8753_write(codec, WM8753_PLL1CTL4 + offset, value); /* set PLL as input and enable */ - snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 | + wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 | (pll_div.div2 << 3)); - snd_soc_write(codec, WM8753_CLOCK, reg | enable); + wm8753_write(codec, WM8753_CLOCK, reg | enable); } return 0; } @@ -832,7 +879,7 @@ static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; - u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01ec; + u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01ec; /* interface format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -854,7 +901,7 @@ static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai, return -EINVAL; } - snd_soc_write(codec, WM8753_PCM, voice); + wm8753_write(codec, WM8753_PCM, voice); return 0; } @@ -875,8 +922,8 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); - u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3; - u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f; + u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01f3; + u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x017f; /* bit size */ switch (params_format(params)) { @@ -896,9 +943,9 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream, /* sample rate */ if (params_rate(params) * 384 == wm8753->pcmclk) srate |= 0x80; - snd_soc_write(codec, WM8753_SRATE1, srate); + wm8753_write(codec, WM8753_SRATE1, srate); - snd_soc_write(codec, WM8753_PCM, voice); + wm8753_write(codec, WM8753_PCM, voice); return 0; } @@ -911,8 +958,8 @@ static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai, struct snd_soc_codec *codec = codec_dai->codec; u16 voice, ioctl; - voice = snd_soc_read(codec, WM8753_PCM) & 0x011f; - ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x015d; + voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x011f; + ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x015d; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -966,8 +1013,8 @@ static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai, return -EINVAL; } - snd_soc_write(codec, WM8753_PCM, voice); - snd_soc_write(codec, WM8753_IOCTL, ioctl); + wm8753_write(codec, WM8753_PCM, voice); + wm8753_write(codec, WM8753_IOCTL, ioctl); return 0; } @@ -979,16 +1026,16 @@ static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai, switch (div_id) { case WM8753_PCMDIV: - reg = snd_soc_read(codec, WM8753_CLOCK) & 0x003f; - snd_soc_write(codec, WM8753_CLOCK, reg | div); + reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0x003f; + wm8753_write(codec, WM8753_CLOCK, reg | div); break; case WM8753_BCLKDIV: - reg = snd_soc_read(codec, WM8753_SRATE2) & 0x01c7; - snd_soc_write(codec, WM8753_SRATE2, reg | div); + reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x01c7; + wm8753_write(codec, WM8753_SRATE2, reg | div); break; case WM8753_VXCLKDIV: - reg = snd_soc_read(codec, WM8753_SRATE2) & 0x003f; - snd_soc_write(codec, WM8753_SRATE2, reg | div); + reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x003f; + wm8753_write(codec, WM8753_SRATE2, reg | div); break; default: return -EINVAL; @@ -1003,7 +1050,7 @@ static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; - u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01e0; + u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01e0; /* interface format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { @@ -1025,7 +1072,7 @@ static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai, return -EINVAL; } - snd_soc_write(codec, WM8753_HIFI, hifi); + wm8753_write(codec, WM8753_HIFI, hifi); return 0; } @@ -1038,8 +1085,8 @@ static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai, struct snd_soc_codec *codec = codec_dai->codec; u16 ioctl, hifi; - hifi = snd_soc_read(codec, WM8753_HIFI) & 0x011f; - ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x00ae; + hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x011f; + ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x00ae; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { @@ -1093,8 +1140,8 @@ static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai, return -EINVAL; } - snd_soc_write(codec, WM8753_HIFI, hifi); - snd_soc_write(codec, WM8753_IOCTL, ioctl); + wm8753_write(codec, WM8753_HIFI, hifi); + wm8753_write(codec, WM8753_IOCTL, ioctl); return 0; } @@ -1115,8 +1162,8 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); - u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0; - u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3; + u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x01c0; + u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01f3; int coeff; /* is digital filter coefficient valid ? */ @@ -1125,7 +1172,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream, printk(KERN_ERR "wm8753 invalid MCLK or rate\n"); return coeff; } - snd_soc_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) | + wm8753_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb); /* bit size */ @@ -1143,7 +1190,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream, break; } - snd_soc_write(codec, WM8753_HIFI, hifi); + wm8753_write(codec, WM8753_HIFI, hifi); return 0; } @@ -1154,8 +1201,8 @@ static int wm8753_mode1v_set_dai_fmt(struct snd_soc_dai *codec_dai, u16 clock; /* set clk source as pcmclk */ - clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; - snd_soc_write(codec, WM8753_CLOCK, clock); + clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; + wm8753_write(codec, WM8753_CLOCK, clock); if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0) return -EINVAL; @@ -1177,8 +1224,8 @@ static int wm8753_mode2_set_dai_fmt(struct snd_soc_dai *codec_dai, u16 clock; /* set clk source as pcmclk */ - clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; - snd_soc_write(codec, WM8753_CLOCK, clock); + clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; + wm8753_write(codec, WM8753_CLOCK, clock); if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0) return -EINVAL; @@ -1192,8 +1239,8 @@ static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai, u16 clock; /* set clk source as mclk */ - clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb; - snd_soc_write(codec, WM8753_CLOCK, clock | 0x4); + clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb; + wm8753_write(codec, WM8753_CLOCK, clock | 0x4); if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0) return -EINVAL; @@ -1205,19 +1252,19 @@ static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai, static int wm8753_mute(struct snd_soc_dai *dai, int mute) { struct snd_soc_codec *codec = dai->codec; - u16 mute_reg = snd_soc_read(codec, WM8753_DAC) & 0xfff7; + u16 mute_reg = wm8753_read_reg_cache(codec, WM8753_DAC) & 0xfff7; struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); /* the digital mute covers the HiFi and Voice DAC's on the WM8753. * make sure we check if they are not both active when we mute */ if (mute && wm8753->dai_func == 1) { if (!codec->active) - snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8); + wm8753_write(codec, WM8753_DAC, mute_reg | 0x8); } else { if (mute) - snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8); + wm8753_write(codec, WM8753_DAC, mute_reg | 0x8); else - snd_soc_write(codec, WM8753_DAC, mute_reg); + wm8753_write(codec, WM8753_DAC, mute_reg); } return 0; @@ -1226,23 +1273,23 @@ static int wm8753_mute(struct snd_soc_dai *dai, int mute) static int wm8753_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { - u16 pwr_reg = snd_soc_read(codec, WM8753_PWR1) & 0xfe3e; + u16 pwr_reg = wm8753_read_reg_cache(codec, WM8753_PWR1) & 0xfe3e; switch (level) { case SND_SOC_BIAS_ON: /* set vmid to 50k and unmute dac */ - snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x00c0); + wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x00c0); break; case SND_SOC_BIAS_PREPARE: /* set vmid to 5k for quick power up */ - snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x01c1); + wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x01c1); break; case SND_SOC_BIAS_STANDBY: /* mute dac and set vmid to 500k, enable VREF */ - snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x0141); + wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x0141); break; case SND_SOC_BIAS_OFF: - snd_soc_write(codec, WM8753_PWR1, 0x0001); + wm8753_write(codec, WM8753_PWR1, 0x0001); break; } codec->dapm.bias_level = level; @@ -1430,7 +1477,7 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec, else dai->driver = &wm8753_all_dai[(wm8753->dai_func << 1) + 1]; } - snd_soc_write(codec, WM8753_IOCTL, wm8753->dai_func); + wm8753_write(codec, WM8753_IOCTL, wm8753->dai_func); } static void wm8753_work(struct work_struct *work) @@ -1450,19 +1497,22 @@ static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state) static int wm8753_resume(struct snd_soc_codec *codec) { - u16 *reg_cache = codec->reg_cache; int i; + u8 data[2]; + u16 *cache = codec->reg_cache; /* Sync reg_cache with the hardware */ - for (i = 1; i < ARRAY_SIZE(wm8753_reg); i++) { - if (i == WM8753_RESET) + for (i = 0; i < ARRAY_SIZE(wm8753_reg); i++) { + if (i + 1 == WM8753_RESET) continue; /* No point in writing hardware default values back */ - if (reg_cache[i] == wm8753_reg[i]) + if (cache[i] == wm8753_reg[i]) continue; - snd_soc_write(codec, i, reg_cache[i]); + data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); + data[1] = cache[i] & 0x00ff; + codec->hw_write(codec->control_data, data, 2); } wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY); @@ -1481,7 +1531,7 @@ static int wm8753_resume(struct snd_soc_codec *codec) static int wm8753_probe(struct snd_soc_codec *codec) { struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); - int ret; + int ret = 0, reg; INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work); @@ -1506,16 +1556,26 @@ static int wm8753_probe(struct snd_soc_codec *codec) msecs_to_jiffies(caps_charge)); /* set the update bits */ - snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_LOUT1V, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_ROUT1V, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_LOUT2V, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_ROUT2V, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_LINVOL, 0x0100, 0x0100); - snd_soc_update_bits(codec, WM8753_RINVOL, 0x0100, 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_LDAC); + wm8753_write(codec, WM8753_LDAC, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_RDAC); + wm8753_write(codec, WM8753_RDAC, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_LADC); + wm8753_write(codec, WM8753_LADC, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_RADC); + wm8753_write(codec, WM8753_RADC, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_LOUT1V); + wm8753_write(codec, WM8753_LOUT1V, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_ROUT1V); + wm8753_write(codec, WM8753_ROUT1V, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_LOUT2V); + wm8753_write(codec, WM8753_LOUT2V, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_ROUT2V); + wm8753_write(codec, WM8753_ROUT2V, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_LINVOL); + wm8753_write(codec, WM8753_LINVOL, reg | 0x0100); + reg = wm8753_read_reg_cache(codec, WM8753_RINVOL); + wm8753_write(codec, WM8753_RINVOL, reg | 0x0100); snd_soc_add_controls(codec, wm8753_snd_controls, ARRAY_SIZE(wm8753_snd_controls)); diff --git a/trunk/sound/soc/codecs/wm8900.c b/trunk/sound/soc/codecs/wm8900.c index cd0959926d12..cfbaac1a0ead 100644 --- a/trunk/sound/soc/codecs/wm8900.c +++ b/trunk/sound/soc/codecs/wm8900.c @@ -139,6 +139,7 @@ struct wm8900_priv { enum snd_soc_control_type control_type; + u16 reg_cache[WM8900_MAXREG]; u32 fll_in; /* FLL input frequency */ u32 fll_out; /* FLL output frequency */ diff --git a/trunk/sound/soc/codecs/wm8903.c b/trunk/sound/soc/codecs/wm8903.c index 987476a5895f..d015745a886b 100644 --- a/trunk/sound/soc/codecs/wm8903.c +++ b/trunk/sound/soc/codecs/wm8903.c @@ -31,7 +31,6 @@ #include #include #include -#include #include "wm8903.h" @@ -214,6 +213,8 @@ static u16 wm8903_reg_defaults[] = { struct wm8903_priv { + u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; + int sysclk; int irq; @@ -1012,7 +1013,7 @@ static int wm8903_add_widgets(struct snd_soc_codec *codec) static int wm8903_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { - u16 reg; + u16 reg, reg2; switch (level) { case SND_SOC_BIAS_ON: @@ -1036,15 +1037,23 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec, wm8903_run_sequence(codec, 0); wm8903_sync_reg_cache(codec, codec->reg_cache); + /* Enable low impedence charge pump output */ + reg = snd_soc_read(codec, + WM8903_CONTROL_INTERFACE_TEST_1); + snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, + reg | WM8903_TEST_KEY); + reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); + snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, + reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); + snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, + reg); + /* By default no bypass paths are enabled so * enable Class W support. */ dev_dbg(codec->dev, "Enabling Class W\n"); - snd_soc_update_bits(codec, WM8903_CLASS_W_0, - WM8903_CP_DYN_FREQ | - WM8903_CP_DYN_V, - WM8903_CP_DYN_FREQ | - WM8903_CP_DYN_V); + snd_soc_write(codec, WM8903_CLASS_W_0, reg | + WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); } reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); @@ -1524,11 +1533,6 @@ static irqreturn_t wm8903_irq(int irq, void *data) mic_report = wm8903->mic_last_report; int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); -#ifndef CONFIG_SND_SOC_WM8903_MODULE - if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) - trace_snd_soc_jack_irq(dev_name(codec->dev)); -#endif - if (int_val & WM8903_MICSHRT_EINT) { dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); diff --git a/trunk/sound/soc/codecs/wm8903.h b/trunk/sound/soc/codecs/wm8903.h index e8490f3edd03..996435e681e5 100644 --- a/trunk/sound/soc/codecs/wm8903.h +++ b/trunk/sound/soc/codecs/wm8903.h @@ -19,6 +19,10 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, int det, int shrt); +#define WM8903_MCLK_DIV_2 1 +#define WM8903_CLK_SYS 2 +#define WM8903_BCLK 3 +#define WM8903_LRCLK 4 /* * Register values. @@ -94,6 +98,8 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, #define WM8903_INTERRUPT_STATUS_1_MASK 0x7A #define WM8903_INTERRUPT_POLARITY_1 0x7B #define WM8903_INTERRUPT_CONTROL 0x7E +#define WM8903_CONTROL_INTERFACE_TEST_1 0x81 +#define WM8903_CHARGE_PUMP_TEST_1 0x95 #define WM8903_CLOCK_RATE_TEST_4 0xA4 #define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC @@ -1199,6 +1205,25 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec, #define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */ #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ +/* + * R129 (0x81) - Control Interface Test 1 + */ +#define WM8903_USER_KEY 0x0002 /* USER_KEY */ +#define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */ +#define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */ +#define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */ +#define WM8903_TEST_KEY 0x0001 /* TEST_KEY */ +#define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */ +#define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */ +#define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */ + +/* + * R149 (0x95) - Charge Pump Test 1 + */ +#define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */ +#define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */ +#define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */ + /* * R164 (0xA4) - Clock Rate Test 4 */ diff --git a/trunk/sound/soc/codecs/wm8904.c b/trunk/sound/soc/codecs/wm8904.c index 9de44a4c05c0..8ba142abd8e6 100644 --- a/trunk/sound/soc/codecs/wm8904.c +++ b/trunk/sound/soc/codecs/wm8904.c @@ -49,6 +49,8 @@ static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { /* codec private data */ struct wm8904_priv { + u16 reg_cache[WM8904_MAX_REGISTER + 1]; + enum wm8904_type devtype; void *control_data; @@ -2092,7 +2094,7 @@ static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) static void wm8904_sync_cache(struct snd_soc_codec *codec) { - u16 *reg_cache = codec->reg_cache; + struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); int i; if (!codec->cache_sync) @@ -2103,14 +2105,14 @@ static void wm8904_sync_cache(struct snd_soc_codec *codec) /* Sync back cached values if they're different from the * hardware default. */ - for (i = 1; i < codec->driver->reg_cache_size; i++) { + for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { if (!wm8904_access[i].writable) continue; - if (reg_cache[i] == wm8904_reg[i]) + if (wm8904->reg_cache[i] == wm8904_reg[i]) continue; - snd_soc_write(codec, i, reg_cache[i]); + snd_soc_write(codec, i, wm8904->reg_cache[i]); } codec->cache_sync = 0; @@ -2369,7 +2371,6 @@ static int wm8904_probe(struct snd_soc_codec *codec) { struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); struct wm8904_pdata *pdata = wm8904->pdata; - u16 *reg_cache = codec->reg_cache; int ret, i; codec->cache_sync = 1; @@ -2436,19 +2437,19 @@ static int wm8904_probe(struct snd_soc_codec *codec) } /* Change some default settings - latch VU and enable ZC */ - reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; - reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; - reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; - reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; - reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | + wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; + wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; + wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; + wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; + wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | WM8904_HPOUTLZC; - reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | + wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | WM8904_HPOUTRZC; - reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | + wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | WM8904_LINEOUTLZC; - reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | + wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | WM8904_LINEOUTRZC; - reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; + wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; /* Apply configuration from the platform data. */ if (wm8904->pdata) { @@ -2456,23 +2457,23 @@ static int wm8904_probe(struct snd_soc_codec *codec) if (!pdata->gpio_cfg[i]) continue; - reg_cache[WM8904_GPIO_CONTROL_1 + i] + wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i] = pdata->gpio_cfg[i] & 0xffff; } /* Zero is the default value for these anyway */ for (i = 0; i < WM8904_MIC_REGS; i++) - reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] + wm8904->reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] = pdata->mic_cfg[i]; } /* Set Class W by default - this will be managed by the Class * G widget at runtime where bypass paths are available. */ - reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; + wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; /* Use normal bias source */ - reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; + wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); diff --git a/trunk/sound/soc/codecs/wm8940.c b/trunk/sound/soc/codecs/wm8940.c index 25580e3ee7c4..381934fff4ec 100644 --- a/trunk/sound/soc/codecs/wm8940.c +++ b/trunk/sound/soc/codecs/wm8940.c @@ -42,6 +42,7 @@ struct wm8940_priv { unsigned int sysclk; + u16 reg_cache[WM8940_CACHEREGNUM]; enum snd_soc_control_type control_type; void *control_data; }; @@ -766,7 +767,6 @@ static __devinit int wm8940_i2c_probe(struct i2c_client *i2c, i2c_set_clientdata(i2c, wm8940); wm8940->control_data = i2c; - wm8940->control_type = SND_SOC_I2C; ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_wm8940, &wm8940_dai, 1); diff --git a/trunk/sound/soc/codecs/wm8955.c b/trunk/sound/soc/codecs/wm8955.c index 7167dfc96aa7..ca0265f008d2 100644 --- a/trunk/sound/soc/codecs/wm8955.c +++ b/trunk/sound/soc/codecs/wm8955.c @@ -41,6 +41,8 @@ static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = { struct wm8955_priv { enum snd_soc_control_type control_type; + u16 reg_cache[WM8955_MAX_REGISTER + 1]; + unsigned int mclk_rate; int deemph; @@ -766,7 +768,6 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int ret, i; switch (level) { @@ -799,14 +800,14 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec, /* Sync back cached values if they're * different from the hardware default. */ - for (i = 0; i < codec->driver->reg_cache_size; i++) { + for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) { if (i == WM8955_RESET) continue; - if (reg_cache[i] == wm8955_reg[i]) + if (wm8955->reg_cache[i] == wm8955_reg[i]) continue; - snd_soc_write(codec, i, reg_cache[i]); + snd_soc_write(codec, i, wm8955->reg_cache[i]); } /* Enable VREF and VMID */ @@ -901,7 +902,6 @@ static int wm8955_probe(struct snd_soc_codec *codec) { struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); struct wm8955_pdata *pdata = dev_get_platdata(codec->dev); - u16 *reg_cache = codec->reg_cache; int ret, i; ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type); @@ -934,25 +934,25 @@ static int wm8955_probe(struct snd_soc_codec *codec) } /* Change some default settings - latch VU and enable ZC */ - reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU; - reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU; - reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC; - reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC; - reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC; - reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC; - reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC; + wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU; + wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU; + wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC; + wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC; + wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC; + wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC; + wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC; /* Also enable adaptive bass boost by default */ - reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB; + wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB; /* Set platform data values */ if (pdata) { if (pdata->out2_speaker) - reg_cache[WM8955_ADDITIONAL_CONTROL_2] + wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2] |= WM8955_ROUT2INV; if (pdata->monoin_diff) - reg_cache[WM8955_MONO_OUT_MIX_1] + wm8955->reg_cache[WM8955_MONO_OUT_MIX_1] |= WM8955_DMEN; } @@ -1003,7 +1003,6 @@ static __devinit int wm8955_i2c_probe(struct i2c_client *i2c, return -ENOMEM; i2c_set_clientdata(i2c, wm8955); - wm8955->control_type = SND_SOC_I2C; ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_wm8955, &wm8955_dai, 1); diff --git a/trunk/sound/soc/codecs/wm8960.c b/trunk/sound/soc/codecs/wm8960.c index 4393394b7bc1..2c5712dce1d5 100644 --- a/trunk/sound/soc/codecs/wm8960.c +++ b/trunk/sound/soc/codecs/wm8960.c @@ -71,6 +71,7 @@ static const u16 wm8960_reg[WM8960_CACHEREGNUM] = { }; struct wm8960_priv { + u16 reg_cache[WM8960_CACHEREGNUM]; enum snd_soc_control_type control_type; void *control_data; int (*set_bias_level)(struct snd_soc_codec *, @@ -417,9 +418,7 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec) * list each time to find the desired power state do so now * and save the result. */ - list_for_each_entry(w, &codec->card->widgets, list) { - if (w->dapm != &codec->dapm) - continue; + list_for_each_entry(w, &codec->dapm.widgets, list) { if (strcmp(w->name, "LOUT1 PGA") == 0) wm8960->lout1 = w; if (strcmp(w->name, "ROUT1 PGA") == 0) @@ -1014,7 +1013,6 @@ static __devinit int wm8960_i2c_probe(struct i2c_client *i2c, return -ENOMEM; i2c_set_clientdata(i2c, wm8960); - wm8960->control_type = SND_SOC_I2C; wm8960->control_data = i2c; ret = snd_soc_register_codec(&i2c->dev, diff --git a/trunk/sound/soc/codecs/wm8961.c b/trunk/sound/soc/codecs/wm8961.c index 55252e7d02c9..6b22ef200e20 100644 --- a/trunk/sound/soc/codecs/wm8961.c +++ b/trunk/sound/soc/codecs/wm8961.c @@ -289,6 +289,7 @@ static u16 wm8961_reg_defaults[] = { struct wm8961_priv { enum snd_soc_control_type control_type; int sysclk; + u16 reg_cache[WM8961_MAX_REGISTER]; }; static int wm8961_volatile_register(unsigned int reg) diff --git a/trunk/sound/soc/codecs/wm8962.c b/trunk/sound/soc/codecs/wm8962.c index b9cb1fcf8c92..f0c9d2691842 100644 --- a/trunk/sound/soc/codecs/wm8962.c +++ b/trunk/sound/soc/codecs/wm8962.c @@ -32,7 +32,6 @@ #include #include #include -#include #include "wm8962.h" @@ -52,6 +51,8 @@ static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { struct wm8962_priv { struct snd_soc_codec *codec; + u16 reg_cache[WM8962_MAX_REGISTER + 1]; + int sysclk; int sysclk_rate; @@ -1989,7 +1990,8 @@ static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - u16 *reg_cache = codec->reg_cache; + struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); + u16 *reg_cache = wm8962->reg_cache; int ret; /* Apply the update (if any) */ @@ -2017,7 +2019,8 @@ static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - u16 *reg_cache = codec->reg_cache; + struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); + u16 *reg_cache = wm8962->reg_cache; int ret; /* Apply the update (if any) */ @@ -2325,7 +2328,8 @@ static int out_pga_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_codec *codec = w->codec; - u16 *reg_cache = codec->reg_cache; + struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); + u16 *reg_cache = wm8962->reg_cache; int reg; switch (w->shift) { @@ -2715,7 +2719,7 @@ static int wm8962_add_widgets(struct snd_soc_codec *codec) static void wm8962_sync_cache(struct snd_soc_codec *codec) { - u16 *reg_cache = codec->reg_cache; + struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); int i; if (!codec->cache_sync) @@ -2728,13 +2732,13 @@ static void wm8962_sync_cache(struct snd_soc_codec *codec) /* Sync back cached values if they're different from the * hardware default. */ - for (i = 1; i < codec->driver->reg_cache_size; i++) { + for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { if (i == WM8962_SOFTWARE_RESET) continue; - if (reg_cache[i] == wm8962_reg[i]) + if (wm8962->reg_cache[i] == wm8962_reg[i]) continue; - snd_soc_write(codec, i, reg_cache[i]); + snd_soc_write(codec, i, wm8962->reg_cache[i]); } codec->cache_sync = 0; @@ -3349,10 +3353,6 @@ static irqreturn_t wm8962_irq(int irq, void *data) if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { dev_dbg(codec->dev, "Microphone event detected\n"); -#ifndef CONFIG_SND_SOC_WM8962_MODULE - trace_snd_soc_jack_irq(dev_name(codec->dev)); -#endif - pm_wakeup_event(codec->dev, 300); schedule_delayed_work(&wm8962->mic_work, @@ -3408,11 +3408,12 @@ EXPORT_SYMBOL_GPL(wm8962_mic_detect); #ifdef CONFIG_PM static int wm8962_resume(struct snd_soc_codec *codec) { + struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); u16 *reg_cache = codec->reg_cache; int i; /* Restore the registers */ - for (i = 1; i < codec->driver->reg_cache_size; i++) { + for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) { switch (i) { case WM8962_SOFTWARE_RESET: continue; @@ -3707,7 +3708,6 @@ static int wm8962_probe(struct snd_soc_codec *codec) struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); struct i2c_client *i2c = container_of(codec->dev, struct i2c_client, dev); - u16 *reg_cache = codec->reg_cache; int i, trigger, irq_pol; wm8962->codec = codec; @@ -3807,7 +3807,7 @@ static int wm8962_probe(struct snd_soc_codec *codec) /* Put the speakers into mono mode? */ if (pdata->spk_mono) - reg_cache[WM8962_CLASS_D_CONTROL_2] + wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2] |= WM8962_SPK_MONO; /* Micbias setup, detection enable and detection @@ -3822,16 +3822,16 @@ static int wm8962_probe(struct snd_soc_codec *codec) } /* Latch volume update bits */ - reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU; - reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU; - reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU; - reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU; - reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU; - reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU; - reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU; - reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU; - reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU; - reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU; + wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU; + wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU; + wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU; + wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU; + wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU; + wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU; + wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU; + wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU; + wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU; + wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU; wm8962_add_widgets(codec); diff --git a/trunk/sound/soc/codecs/wm8971.c b/trunk/sound/soc/codecs/wm8971.c index 572bb80627a4..8805636bda53 100644 --- a/trunk/sound/soc/codecs/wm8971.c +++ b/trunk/sound/soc/codecs/wm8971.c @@ -720,7 +720,6 @@ static __devinit int wm8971_i2c_probe(struct i2c_client *i2c, if (wm8971 == NULL) return -ENOMEM; - wm8971->control_type = SND_SOC_I2C; i2c_set_clientdata(i2c, wm8971); ret = snd_soc_register_codec(&i2c->dev, diff --git a/trunk/sound/soc/codecs/wm8974.c b/trunk/sound/soc/codecs/wm8974.c index ca646a822444..5d286427532a 100644 --- a/trunk/sound/soc/codecs/wm8974.c +++ b/trunk/sound/soc/codecs/wm8974.c @@ -51,6 +51,7 @@ static const u16 wm8974_reg[WM8974_CACHEREGNUM] = { struct wm8974_priv { enum snd_soc_control_type control_type; + u16 reg_cache[WM8974_CACHEREGNUM]; }; #define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0) diff --git a/trunk/sound/soc/codecs/wm8978.c b/trunk/sound/soc/codecs/wm8978.c index 4bbc3442703f..a195af92b425 100644 --- a/trunk/sound/soc/codecs/wm8978.c +++ b/trunk/sound/soc/codecs/wm8978.c @@ -59,6 +59,7 @@ struct wm8978_priv { unsigned int f_opclk; int mclk_idx; enum wm8978_sysclk_src sysclk; + u16 reg_cache[WM8978_CACHEREGNUM]; }; static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; diff --git a/trunk/sound/soc/codecs/wm8988.c b/trunk/sound/soc/codecs/wm8988.c index d7170f1381aa..65807b15a2cc 100644 --- a/trunk/sound/soc/codecs/wm8988.c +++ b/trunk/sound/soc/codecs/wm8988.c @@ -53,6 +53,7 @@ struct wm8988_priv { unsigned int sysclk; enum snd_soc_control_type control_type; struct snd_pcm_hw_constraint_list *sysclk_constraints; + u16 reg_cache[WM8988_NUM_REG]; }; diff --git a/trunk/sound/soc/codecs/wm8993.c b/trunk/sound/soc/codecs/wm8993.c index 18c0d9ce7c32..15f34a26debf 100644 --- a/trunk/sound/soc/codecs/wm8993.c +++ b/trunk/sound/soc/codecs/wm8993.c @@ -225,6 +225,7 @@ static struct { struct wm8993_priv { struct wm_hubs_data hubs_data; + u16 reg_cache[WM8993_REGISTER_COUNT]; struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; struct wm8993_platform_data pdata; enum snd_soc_control_type control_type; diff --git a/trunk/sound/soc/codecs/wm8994.c b/trunk/sound/soc/codecs/wm8994.c index 247a6a99feb8..af104acd75f8 100644 --- a/trunk/sound/soc/codecs/wm8994.c +++ b/trunk/sound/soc/codecs/wm8994.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -870,15 +869,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), -SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, +SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 8, 1, 0), SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 8, 1, 0), -SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, +SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 10, 15, 0, wm8994_3d_tlv), -SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, +SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 8, 1, 0), }; @@ -2756,10 +2755,6 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data) int reg; int report; -#ifndef CONFIG_SND_SOC_WM8994_MODULE - trace_snd_soc_jack_irq(dev_name(codec->dev)); -#endif - reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); if (reg < 0) { dev_err(codec->dev, "Failed to read microphone status: %d\n", @@ -2906,10 +2901,6 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data) goto out; } -#ifndef CONFIG_SND_SOC_WM8994_MODULE - trace_snd_soc_jack_irq(dev_name(codec->dev)); -#endif - if (wm8994->jack_cb) wm8994->jack_cb(reg, wm8994->jack_cb_data); else diff --git a/trunk/sound/soc/codecs/wm8995.c b/trunk/sound/soc/codecs/wm8995.c deleted file mode 100644 index 6045cbde492b..000000000000 --- a/trunk/sound/soc/codecs/wm8995.c +++ /dev/null @@ -1,1818 +0,0 @@ -/* - * wm8995.c -- WM8995 ALSA SoC Audio driver - * - * Copyright 2010 Wolfson Microelectronics plc - * - * Author: Dimitris Papastamos - * - * Based on wm8994.c and wm_hubs.c by Mark Brown - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "wm8995.h" - -static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = { - [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, - [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, - [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, - [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25, - [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060, - [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083, - [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050, - [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040, - [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000, - [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0, - [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0, - [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200, - [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098, - [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318, - [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8, - [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5, - [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558, - [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103, - [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318, - [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8, - [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5, - [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558, - [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103, - [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0, - [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200, - [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318, - [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8, - [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5, - [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558, - [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103, - [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002, - [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101, - [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101, - [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101, - [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff, - [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002, - [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001, - [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f, - [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104, - [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050, - [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003, - [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b, - [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff, - [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff, - [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001, - [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001, - [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003, - [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401, - [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060, - [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff, - [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff, - [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff, - [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006, - [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006, - [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061, - [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003, - [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106, - [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502, - [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff, - [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff, - [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001, - [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f, - [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106, - [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050, - [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b, - [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff, - [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff, - [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff, - [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100, - [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff, - [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff, - [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff, - [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff, - [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102, - [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff, - [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff, - [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff, - [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff, - [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601, - [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304, - [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100 -}; - -struct fll_config { - int src; - int in; - int out; -}; - -struct wm8995_priv { - enum snd_soc_control_type control_type; - int sysclk[2]; - int mclk[2]; - int aifclk[2]; - struct fll_config fll[2], fll_suspend[2]; -}; - -static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); -static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); -static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); -static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); - -static const char *in1l_text[] = { - "Differential", "Single-ended IN1LN", "Single-ended IN1LP" -}; - -static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, - 2, in1l_text); - -static const char *in1r_text[] = { - "Differential", "Single-ended IN1RN", "Single-ended IN1RP" -}; - -static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, - 0, in1r_text); - -static const char *dmic_src_text[] = { - "DMICDAT1", "DMICDAT2", "DMICDAT3" -}; - -static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, - 8, dmic_src_text); -static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, - 6, dmic_src_text); - -static const struct snd_kcontrol_new wm8995_snd_controls[] = { - SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, - WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, - WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), - - SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, - WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, - WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), - - SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, - WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, - WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, - WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - - SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, - WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), - - SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, - 4, 3, 0, in1l_boost_tlv), - - SOC_ENUM("IN1L Mode", in1l_enum), - SOC_ENUM("IN1R Mode", in1r_enum), - - SOC_ENUM("DMIC1 SRC", dmic_src1_enum), - SOC_ENUM("DMIC2 SRC", dmic_src2_enum), - - SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, - 24, 0, sidetone_tlv), - SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, - 24, 0, sidetone_tlv), - - SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, - WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, - WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), - SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, - WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) -}; - -static void wm8995_update_class_w(struct snd_soc_codec *codec) -{ - int enable = 1; - int source = 0; /* GCC flow analysis can't track enable */ - int reg, reg_r; - - /* We also need the same setting for L/R and only one path */ - reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); - switch (reg) { - case WM8995_AIF2DACL_TO_DAC1L: - dev_dbg(codec->dev, "Class W source AIF2DAC\n"); - source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; - break; - case WM8995_AIF1DAC2L_TO_DAC1L: - dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); - source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; - break; - case WM8995_AIF1DAC1L_TO_DAC1L: - dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); - source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; - break; - default: - dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); - enable = 0; - break; - } - - reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); - if (reg_r != reg) { - dev_dbg(codec->dev, "Left and right DAC mixers different\n"); - enable = 0; - } - - if (enable) { - dev_dbg(codec->dev, "Class W enabled\n"); - snd_soc_update_bits(codec, WM8995_CLASS_W_1, - WM8995_CP_DYN_PWR_MASK | - WM8995_CP_DYN_SRC_SEL_MASK, - source | WM8995_CP_DYN_PWR); - } else { - dev_dbg(codec->dev, "Class W disabled\n"); - snd_soc_update_bits(codec, WM8995_CLASS_W_1, - WM8995_CP_DYN_PWR_MASK, 0); - } -} - -static int check_clk_sys(struct snd_soc_dapm_widget *source, - struct snd_soc_dapm_widget *sink) -{ - unsigned int reg; - const char *clk; - - reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); - /* Check what we're currently using for CLK_SYS */ - if (reg & WM8995_SYSCLK_SRC) - clk = "AIF2CLK"; - else - clk = "AIF1CLK"; - return !strcmp(source->name, clk); -} - -static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_dapm_widget *w; - struct snd_soc_codec *codec; - int ret; - - w = snd_kcontrol_chip(kcontrol); - codec = w->codec; - ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); - wm8995_update_class_w(codec); - return ret; -} - -static int hp_supply_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec; - struct wm8995_priv *wm8995; - - codec = w->codec; - wm8995 = snd_soc_codec_get_drvdata(codec); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - /* Enable the headphone amp */ - snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, - WM8995_HPOUT1L_ENA_MASK | - WM8995_HPOUT1R_ENA_MASK, - WM8995_HPOUT1L_ENA | - WM8995_HPOUT1R_ENA); - - /* Enable the second stage */ - snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, - WM8995_HPOUT1L_DLY_MASK | - WM8995_HPOUT1R_DLY_MASK, - WM8995_HPOUT1L_DLY | - WM8995_HPOUT1R_DLY); - break; - case SND_SOC_DAPM_PRE_PMD: - snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, - WM8995_CP_ENA_MASK, 0); - break; - } - - return 0; -} - -static void dc_servo_cmd(struct snd_soc_codec *codec, - unsigned int reg, unsigned int val, unsigned int mask) -{ - int timeout = 10; - - dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", - __func__, reg, val, mask); - - snd_soc_write(codec, reg, val); - while (timeout--) { - msleep(10); - val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); - if ((val & mask) == mask) - return; - } - - dev_err(codec->dev, "Timed out waiting for DC Servo\n"); -} - -static int hp_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec; - unsigned int reg; - - codec = w->codec; - reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); - - switch (event) { - case SND_SOC_DAPM_POST_PMU: - snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, - WM8995_CP_ENA_MASK, WM8995_CP_ENA); - - msleep(5); - - snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, - WM8995_HPOUT1L_ENA_MASK | - WM8995_HPOUT1R_ENA_MASK, - WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); - - udelay(20); - - reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; - snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); - - snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | - WM8995_DCS_ENA_CHAN_1); - - dc_servo_cmd(codec, WM8995_DC_SERVO_2, - WM8995_DCS_TRIG_STARTUP_0 | - WM8995_DCS_TRIG_STARTUP_1, - WM8995_DCS_TRIG_DAC_WR_0 | - WM8995_DCS_TRIG_DAC_WR_1); - - reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | - WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; - snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); - - break; - case SND_SOC_DAPM_PRE_PMD: - snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, - WM8995_HPOUT1L_OUTP_MASK | - WM8995_HPOUT1R_OUTP_MASK | - WM8995_HPOUT1L_RMV_SHORT_MASK | - WM8995_HPOUT1R_RMV_SHORT_MASK, 0); - - snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, - WM8995_HPOUT1L_DLY_MASK | - WM8995_HPOUT1R_DLY_MASK, 0); - - snd_soc_write(codec, WM8995_DC_SERVO_1, 0); - - snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, - WM8995_HPOUT1L_ENA_MASK | - WM8995_HPOUT1R_ENA_MASK, - 0); - break; - } - - return 0; -} - -static int configure_aif_clock(struct snd_soc_codec *codec, int aif) -{ - struct wm8995_priv *wm8995; - int rate; - int reg1 = 0; - int offset; - - wm8995 = snd_soc_codec_get_drvdata(codec); - - if (aif) - offset = 4; - else - offset = 0; - - switch (wm8995->sysclk[aif]) { - case WM8995_SYSCLK_MCLK1: - rate = wm8995->mclk[0]; - break; - case WM8995_SYSCLK_MCLK2: - reg1 |= 0x8; - rate = wm8995->mclk[1]; - break; - case WM8995_SYSCLK_FLL1: - reg1 |= 0x10; - rate = wm8995->fll[0].out; - break; - case WM8995_SYSCLK_FLL2: - reg1 |= 0x18; - rate = wm8995->fll[1].out; - break; - default: - return -EINVAL; - } - - if (rate >= 13500000) { - rate /= 2; - reg1 |= WM8995_AIF1CLK_DIV; - - dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", - aif + 1, rate); - } - - wm8995->aifclk[aif] = rate; - - snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, - WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, - reg1); - return 0; -} - -static int configure_clock(struct snd_soc_codec *codec) -{ - struct wm8995_priv *wm8995; - int old, new; - - wm8995 = snd_soc_codec_get_drvdata(codec); - - /* Bring up the AIF clocks first */ - configure_aif_clock(codec, 0); - configure_aif_clock(codec, 1); - - /* - * Then switch CLK_SYS over to the higher of them; a change - * can only happen as a result of a clocking change which can - * only be made outside of DAPM so we can safely redo the - * clocking. - */ - - /* If they're equal it doesn't matter which is used */ - if (wm8995->aifclk[0] == wm8995->aifclk[1]) - return 0; - - if (wm8995->aifclk[0] < wm8995->aifclk[1]) - new = WM8995_SYSCLK_SRC; - else - new = 0; - - old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC; - - /* If there's no change then we're done. */ - if (old == new) - return 0; - - snd_soc_update_bits(codec, WM8995_CLOCKING_1, - WM8995_SYSCLK_SRC_MASK, new); - - snd_soc_dapm_sync(&codec->dapm); - - return 0; -} - -static int clk_sys_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec; - - codec = w->codec; - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - return configure_clock(codec); - - case SND_SOC_DAPM_POST_PMD: - configure_clock(codec); - break; - } - - return 0; -} - -static const char *sidetone_text[] = { - "ADC/DMIC1", "DMIC2", -}; - -static const struct soc_enum sidetone1_enum = - SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); - -static const struct snd_kcontrol_new sidetone1_mux = - SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); - -static const struct soc_enum sidetone2_enum = - SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); - -static const struct snd_kcontrol_new sidetone2_mux = - SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); - -static const struct snd_kcontrol_new aif1adc1l_mix[] = { - SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new aif1adc1r_mix[] = { - SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new aif1adc2l_mix[] = { - SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new aif1adc2r_mix[] = { - SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new dac1l_mix[] = { - WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, - 5, 1, 0), - WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, - 4, 1, 0), - WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, - 2, 1, 0), - WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, - 1, 1, 0), - WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new dac1r_mix[] = { - WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, - 5, 1, 0), - WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, - 4, 1, 0), - WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, - 2, 1, 0), - WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, - 1, 1, 0), - WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new aif2dac2l_mix[] = { - SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, - 5, 1, 0), - SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, - 4, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, - 2, 1, 0), - SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new aif2dac2r_mix[] = { - SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, - 5, 1, 0), - SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, - 4, 1, 0), - SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, - 2, 1, 0), - SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, - 1, 1, 0), - SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, - 0, 1, 0), -}; - -static const struct snd_kcontrol_new in1l_pga = - SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); - -static const struct snd_kcontrol_new in1r_pga = - SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); - -static const char *adc_mux_text[] = { - "ADC", - "DMIC", -}; - -static const struct soc_enum adc_enum = - SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); - -static const struct snd_kcontrol_new adcl_mux = - SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); - -static const struct snd_kcontrol_new adcr_mux = - SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); - -static const char *spk_src_text[] = { - "DAC1L", "DAC1R", "DAC2L", "DAC2R" -}; - -static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, - 0, spk_src_text); -static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, - 0, spk_src_text); -static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, - 0, spk_src_text); -static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, - 0, spk_src_text); - -static const struct snd_kcontrol_new spk1l_mux = - SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); -static const struct snd_kcontrol_new spk1r_mux = - SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); -static const struct snd_kcontrol_new spk2l_mux = - SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); -static const struct snd_kcontrol_new spk2r_mux = - SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); - -static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { - SND_SOC_DAPM_INPUT("DMIC1DAT"), - SND_SOC_DAPM_INPUT("DMIC2DAT"), - - SND_SOC_DAPM_INPUT("IN1L"), - SND_SOC_DAPM_INPUT("IN1R"), - - SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, - &in1l_pga, 1), - SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, - &in1r_pga, 1), - - SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0), - SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0), - - SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - - SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, - WM8995_POWER_MANAGEMENT_3, 9, 0), - SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, - WM8995_POWER_MANAGEMENT_3, 8, 0), - SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, - SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", - 0, WM8995_POWER_MANAGEMENT_3, 11, 0), - SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", - 0, WM8995_POWER_MANAGEMENT_3, 10, 0), - - SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, - &adcl_mux), - SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, - &adcr_mux), - - SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), - SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), - SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), - SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), - - SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), - SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), - - SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, - aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), - SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, - aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), - SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, - aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), - SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, - aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), - - SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, - 9, 0), - SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, - 8, 0), - SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, - 0, 0), - - SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, - 11, 0), - SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, - 10, 0), - - SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, - aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), - SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, - aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), - - SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), - SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), - SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), - SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), - - SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, - ARRAY_SIZE(dac1l_mix)), - SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, - ARRAY_SIZE(dac1r_mix)), - - SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), - SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), - - SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, - hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), - - SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, - hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), - - SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, - 4, 0, &spk1l_mux), - SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, - 4, 0, &spk1r_mux), - SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, - 4, 0, &spk2l_mux), - SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, - 4, 0, &spk2r_mux), - - SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), - - SND_SOC_DAPM_OUTPUT("HP1L"), - SND_SOC_DAPM_OUTPUT("HP1R"), - SND_SOC_DAPM_OUTPUT("SPK1L"), - SND_SOC_DAPM_OUTPUT("SPK1R"), - SND_SOC_DAPM_OUTPUT("SPK2L"), - SND_SOC_DAPM_OUTPUT("SPK2R") -}; - -static const struct snd_soc_dapm_route wm8995_intercon[] = { - { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, - { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, - - { "DSP1CLK", NULL, "CLK_SYS" }, - { "DSP2CLK", NULL, "CLK_SYS" }, - { "SYSDSPCLK", NULL, "CLK_SYS" }, - - { "AIF1ADC1L", NULL, "AIF1CLK" }, - { "AIF1ADC1L", NULL, "DSP1CLK" }, - { "AIF1ADC1R", NULL, "AIF1CLK" }, - { "AIF1ADC1R", NULL, "DSP1CLK" }, - { "AIF1ADC1R", NULL, "SYSDSPCLK" }, - - { "AIF1ADC2L", NULL, "AIF1CLK" }, - { "AIF1ADC2L", NULL, "DSP1CLK" }, - { "AIF1ADC2R", NULL, "AIF1CLK" }, - { "AIF1ADC2R", NULL, "DSP1CLK" }, - { "AIF1ADC2R", NULL, "SYSDSPCLK" }, - - { "DMIC1L", NULL, "DMIC1DAT" }, - { "DMIC1L", NULL, "CLK_SYS" }, - { "DMIC1R", NULL, "DMIC1DAT" }, - { "DMIC1R", NULL, "CLK_SYS" }, - { "DMIC2L", NULL, "DMIC2DAT" }, - { "DMIC2L", NULL, "CLK_SYS" }, - { "DMIC2R", NULL, "DMIC2DAT" }, - { "DMIC2R", NULL, "CLK_SYS" }, - - { "ADCL", NULL, "AIF1CLK" }, - { "ADCL", NULL, "DSP1CLK" }, - { "ADCL", NULL, "SYSDSPCLK" }, - - { "ADCR", NULL, "AIF1CLK" }, - { "ADCR", NULL, "DSP1CLK" }, - { "ADCR", NULL, "SYSDSPCLK" }, - - { "IN1L PGA", "IN1L Switch", "IN1L" }, - { "IN1R PGA", "IN1R Switch", "IN1R" }, - { "IN1L PGA", NULL, "LDO2" }, - { "IN1R PGA", NULL, "LDO2" }, - - { "ADCL", NULL, "IN1L PGA" }, - { "ADCR", NULL, "IN1R PGA" }, - - { "ADCL Mux", "ADC", "ADCL" }, - { "ADCL Mux", "DMIC", "DMIC1L" }, - { "ADCR Mux", "ADC", "ADCR" }, - { "ADCR Mux", "DMIC", "DMIC1R" }, - - /* AIF1 outputs */ - { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, - { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, - - { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, - { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, - - { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, - { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, - - { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, - { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, - - /* Sidetone */ - { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, - { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, - { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, - { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, - - { "AIF1DAC1L", NULL, "AIF1CLK" }, - { "AIF1DAC1L", NULL, "DSP1CLK" }, - { "AIF1DAC1R", NULL, "AIF1CLK" }, - { "AIF1DAC1R", NULL, "DSP1CLK" }, - { "AIF1DAC1R", NULL, "SYSDSPCLK" }, - - { "AIF1DAC2L", NULL, "AIF1CLK" }, - { "AIF1DAC2L", NULL, "DSP1CLK" }, - { "AIF1DAC2R", NULL, "AIF1CLK" }, - { "AIF1DAC2R", NULL, "DSP1CLK" }, - { "AIF1DAC2R", NULL, "SYSDSPCLK" }, - - { "DAC1L", NULL, "AIF1CLK" }, - { "DAC1L", NULL, "DSP1CLK" }, - { "DAC1L", NULL, "SYSDSPCLK" }, - - { "DAC1R", NULL, "AIF1CLK" }, - { "DAC1R", NULL, "DSP1CLK" }, - { "DAC1R", NULL, "SYSDSPCLK" }, - - { "AIF1DAC1L", NULL, "AIF1DACDAT" }, - { "AIF1DAC1R", NULL, "AIF1DACDAT" }, - { "AIF1DAC2L", NULL, "AIF1DACDAT" }, - { "AIF1DAC2R", NULL, "AIF1DACDAT" }, - - /* DAC1 inputs */ - { "DAC1L", NULL, "DAC1L Mixer" }, - { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, - { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, - { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, - { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, - - { "DAC1R", NULL, "DAC1R Mixer" }, - { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, - { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, - { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, - { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, - - /* DAC2/AIF2 outputs */ - { "DAC2L", NULL, "AIF2DAC2L Mixer" }, - { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, - { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, - - { "DAC2R", NULL, "AIF2DAC2R Mixer" }, - { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, - { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, - - /* Output stages */ - { "Headphone PGA", NULL, "DAC1L" }, - { "Headphone PGA", NULL, "DAC1R" }, - - { "Headphone PGA", NULL, "DAC2L" }, - { "Headphone PGA", NULL, "DAC2R" }, - - { "Headphone PGA", NULL, "Headphone Supply" }, - { "Headphone PGA", NULL, "CLK_SYS" }, - { "Headphone PGA", NULL, "LDO2" }, - - { "HP1L", NULL, "Headphone PGA" }, - { "HP1R", NULL, "Headphone PGA" }, - - { "SPK1L Driver", "DAC1L", "DAC1L" }, - { "SPK1L Driver", "DAC1R", "DAC1R" }, - { "SPK1L Driver", "DAC2L", "DAC2L" }, - { "SPK1L Driver", "DAC2R", "DAC2R" }, - { "SPK1L Driver", NULL, "CLK_SYS" }, - - { "SPK1R Driver", "DAC1L", "DAC1L" }, - { "SPK1R Driver", "DAC1R", "DAC1R" }, - { "SPK1R Driver", "DAC2L", "DAC2L" }, - { "SPK1R Driver", "DAC2R", "DAC2R" }, - { "SPK1R Driver", NULL, "CLK_SYS" }, - - { "SPK2L Driver", "DAC1L", "DAC1L" }, - { "SPK2L Driver", "DAC1R", "DAC1R" }, - { "SPK2L Driver", "DAC2L", "DAC2L" }, - { "SPK2L Driver", "DAC2R", "DAC2R" }, - { "SPK2L Driver", NULL, "CLK_SYS" }, - - { "SPK2R Driver", "DAC1L", "DAC1L" }, - { "SPK2R Driver", "DAC1R", "DAC1R" }, - { "SPK2R Driver", "DAC2L", "DAC2L" }, - { "SPK2R Driver", "DAC2R", "DAC2R" }, - { "SPK2R Driver", NULL, "CLK_SYS" }, - - { "SPK1L", NULL, "SPK1L Driver" }, - { "SPK1R", NULL, "SPK1R Driver" }, - { "SPK2L", NULL, "SPK2L Driver" }, - { "SPK2R", NULL, "SPK2R Driver" } -}; - -static int wm8995_volatile(unsigned int reg) -{ - /* out of bounds registers are generally considered - * volatile to support register banks that are partially - * owned by something else for e.g. a DSP - */ - if (reg > WM8995_MAX_CACHED_REGISTER) - return 1; - - switch (reg) { - case WM8995_SOFTWARE_RESET: - case WM8995_DC_SERVO_READBACK_0: - case WM8995_INTERRUPT_STATUS_1: - case WM8995_INTERRUPT_STATUS_2: - case WM8995_INTERRUPT_STATUS_1_MASK: - case WM8995_INTERRUPT_STATUS_2_MASK: - case WM8995_INTERRUPT_CONTROL: - case WM8995_ACCESSORY_DETECT_MODE1: - case WM8995_ACCESSORY_DETECT_MODE2: - case WM8995_HEADPHONE_DETECT1: - case WM8995_HEADPHONE_DETECT2: - return 1; - } - - return 0; -} - -static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) -{ - struct snd_soc_codec *codec = dai->codec; - int mute_reg; - - switch (dai->id) { - case 0: - mute_reg = WM8995_AIF1_DAC1_FILTERS_1; - break; - case 1: - mute_reg = WM8995_AIF2_DAC_FILTERS_1; - break; - default: - return -EINVAL; - } - - snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, - !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); - return 0; -} - -static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) -{ - struct snd_soc_codec *codec; - int master; - int aif; - - codec = dai->codec; - - master = 0; - switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { - case SND_SOC_DAIFMT_CBS_CFS: - break; - case SND_SOC_DAIFMT_CBM_CFM: - master = WM8995_AIF1_MSTR; - break; - default: - dev_err(dai->dev, "Unknown master/slave configuration\n"); - return -EINVAL; - } - - aif = 0; - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_DSP_B: - aif |= WM8995_AIF1_LRCLK_INV; - case SND_SOC_DAIFMT_DSP_A: - aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); - break; - case SND_SOC_DAIFMT_I2S: - aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); - break; - case SND_SOC_DAIFMT_RIGHT_J: - break; - case SND_SOC_DAIFMT_LEFT_J: - aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); - break; - default: - dev_err(dai->dev, "Unknown dai format\n"); - return -EINVAL; - } - - switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { - case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: - /* frame inversion not valid for DSP modes */ - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_NB_NF: - break; - case SND_SOC_DAIFMT_IB_NF: - aif |= WM8995_AIF1_BCLK_INV; - break; - default: - return -EINVAL; - } - break; - - case SND_SOC_DAIFMT_I2S: - case SND_SOC_DAIFMT_RIGHT_J: - case SND_SOC_DAIFMT_LEFT_J: - switch (fmt & SND_SOC_DAIFMT_INV_MASK) { - case SND_SOC_DAIFMT_NB_NF: - break; - case SND_SOC_DAIFMT_IB_IF: - aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; - break; - case SND_SOC_DAIFMT_IB_NF: - aif |= WM8995_AIF1_BCLK_INV; - break; - case SND_SOC_DAIFMT_NB_IF: - aif |= WM8995_AIF1_LRCLK_INV; - break; - default: - return -EINVAL; - } - break; - default: - return -EINVAL; - } - - snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, - WM8995_AIF1_BCLK_INV_MASK | - WM8995_AIF1_LRCLK_INV_MASK | - WM8995_AIF1_FMT_MASK, aif); - snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, - WM8995_AIF1_MSTR_MASK, master); - return 0; -} - -static const int srs[] = { - 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, - 48000, 88200, 96000 -}; - -static const int fs_ratios[] = { - -1 /* reserved */, - 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 -}; - -static const int bclk_divs[] = { - 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 -}; - -static int wm8995_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -{ - struct snd_soc_codec *codec; - struct wm8995_priv *wm8995; - int aif1_reg; - int bclk_reg; - int lrclk_reg; - int rate_reg; - int bclk_rate; - int aif1; - int lrclk, bclk; - int i, rate_val, best, best_val, cur_val; - - codec = dai->codec; - wm8995 = snd_soc_codec_get_drvdata(codec); - - switch (dai->id) { - case 0: - aif1_reg = WM8995_AIF1_CONTROL_1; - bclk_reg = WM8995_AIF1_BCLK; - rate_reg = WM8995_AIF1_RATE; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || - wm8995->lrclk_shared[0] */) { - lrclk_reg = WM8995_AIF1DAC_LRCLK; - } else { - lrclk_reg = WM8995_AIF1ADC_LRCLK; - dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); - } - break; - case 1: - aif1_reg = WM8995_AIF2_CONTROL_1; - bclk_reg = WM8995_AIF2_BCLK; - rate_reg = WM8995_AIF2_RATE; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || - wm8995->lrclk_shared[1] */) { - lrclk_reg = WM8995_AIF2DAC_LRCLK; - } else { - lrclk_reg = WM8995_AIF2ADC_LRCLK; - dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); - } - break; - default: - return -EINVAL; - } - - bclk_rate = snd_soc_params_to_bclk(params); - if (bclk_rate < 0) - return bclk_rate; - - aif1 = 0; - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - break; - case SNDRV_PCM_FORMAT_S20_3LE: - aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); - break; - case SNDRV_PCM_FORMAT_S24_LE: - aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); - break; - case SNDRV_PCM_FORMAT_S32_LE: - aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); - break; - default: - dev_err(dai->dev, "Unsupported word length %u\n", - params_format(params)); - return -EINVAL; - } - - /* try to find a suitable sample rate */ - for (i = 0; i < ARRAY_SIZE(srs); ++i) - if (srs[i] == params_rate(params)) - break; - if (i == ARRAY_SIZE(srs)) { - dev_err(dai->dev, "Sample rate %d is not supported\n", - params_rate(params)); - return -EINVAL; - } - rate_val = i << WM8995_AIF1_SR_SHIFT; - - dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); - dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", - dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); - - /* AIFCLK/fs ratio; look for a close match in either direction */ - best = 1; - best_val = abs((fs_ratios[1] * params_rate(params)) - - wm8995->aifclk[dai->id]); - for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { - cur_val = abs((fs_ratios[i] * params_rate(params)) - - wm8995->aifclk[dai->id]); - if (cur_val >= best_val) - continue; - best = i; - best_val = cur_val; - } - rate_val |= best; - - dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", - dai->id + 1, fs_ratios[best]); - - /* - * We may not get quite the right frequency if using - * approximate clocks so look for the closest match that is - * higher than the target (we need to ensure that there enough - * BCLKs to clock out the samples). - */ - best = 0; - bclk = 0; - for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { - cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; - if (cur_val < 0) /* BCLK table is sorted */ - break; - best = i; - } - bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; - - bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; - dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", - bclk_divs[best], bclk_rate); - - lrclk = bclk_rate / params_rate(params); - dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", - lrclk, bclk_rate / lrclk); - - snd_soc_update_bits(codec, aif1_reg, - WM8995_AIF1_WL_MASK, aif1); - snd_soc_update_bits(codec, bclk_reg, - WM8995_AIF1_BCLK_DIV_MASK, bclk); - snd_soc_update_bits(codec, lrclk_reg, - WM8995_AIF1DAC_RATE_MASK, lrclk); - snd_soc_update_bits(codec, rate_reg, - WM8995_AIF1_SR_MASK | - WM8995_AIF1CLK_RATE_MASK, rate_val); - return 0; -} - -static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) -{ - struct snd_soc_codec *codec = codec_dai->codec; - int reg, val, mask; - - switch (codec_dai->id) { - case 0: - reg = WM8995_AIF1_MASTER_SLAVE; - mask = WM8995_AIF1_TRI; - break; - case 1: - reg = WM8995_AIF2_MASTER_SLAVE; - mask = WM8995_AIF2_TRI; - break; - case 2: - reg = WM8995_POWER_MANAGEMENT_5; - mask = WM8995_AIF3_TRI; - break; - default: - return -EINVAL; - } - - if (tristate) - val = mask; - else - val = 0; - - return snd_soc_update_bits(codec, reg, mask, reg); -} - -/* The size in bits of the FLL divide multiplied by 10 - * to allow rounding later */ -#define FIXED_FLL_SIZE ((1 << 16) * 10) - -struct fll_div { - u16 outdiv; - u16 n; - u16 k; - u16 clk_ref_div; - u16 fll_fratio; -}; - -static int wm8995_get_fll_config(struct fll_div *fll, - int freq_in, int freq_out) -{ - u64 Kpart; - unsigned int K, Ndiv, Nmod; - - pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); - - /* Scale the input frequency down to <= 13.5MHz */ - fll->clk_ref_div = 0; - while (freq_in > 13500000) { - fll->clk_ref_div++; - freq_in /= 2; - - if (fll->clk_ref_div > 3) - return -EINVAL; - } - pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); - - /* Scale the output to give 90MHz<=Fvco<=100MHz */ - fll->outdiv = 3; - while (freq_out * (fll->outdiv + 1) < 90000000) { - fll->outdiv++; - if (fll->outdiv > 63) - return -EINVAL; - } - freq_out *= fll->outdiv + 1; - pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); - - if (freq_in > 1000000) { - fll->fll_fratio = 0; - } else if (freq_in > 256000) { - fll->fll_fratio = 1; - freq_in *= 2; - } else if (freq_in > 128000) { - fll->fll_fratio = 2; - freq_in *= 4; - } else if (freq_in > 64000) { - fll->fll_fratio = 3; - freq_in *= 8; - } else { - fll->fll_fratio = 4; - freq_in *= 16; - } - pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); - - /* Now, calculate N.K */ - Ndiv = freq_out / freq_in; - - fll->n = Ndiv; - Nmod = freq_out % freq_in; - pr_debug("Nmod=%d\n", Nmod); - - /* Calculate fractional part - scale up so we can round. */ - Kpart = FIXED_FLL_SIZE * (long long)Nmod; - - do_div(Kpart, freq_in); - - K = Kpart & 0xFFFFFFFF; - - if ((K % 10) >= 5) - K += 5; - - /* Move down to proper range now rounding is done */ - fll->k = K / 10; - - pr_debug("N=%x K=%x\n", fll->n, fll->k); - - return 0; -} - -static int wm8995_set_fll(struct snd_soc_dai *dai, int id, - int src, unsigned int freq_in, - unsigned int freq_out) -{ - struct snd_soc_codec *codec; - struct wm8995_priv *wm8995; - int reg_offset, ret; - struct fll_div fll; - u16 reg, aif1, aif2; - - codec = dai->codec; - wm8995 = snd_soc_codec_get_drvdata(codec); - - aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) - & WM8995_AIF1CLK_ENA; - - aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) - & WM8995_AIF2CLK_ENA; - - switch (id) { - case WM8995_FLL1: - reg_offset = 0; - id = 0; - break; - case WM8995_FLL2: - reg_offset = 0x20; - id = 1; - break; - default: - return -EINVAL; - } - - switch (src) { - case 0: - /* Allow no source specification when stopping */ - if (freq_out) - return -EINVAL; - break; - case WM8995_FLL_SRC_MCLK1: - case WM8995_FLL_SRC_MCLK2: - case WM8995_FLL_SRC_LRCLK: - case WM8995_FLL_SRC_BCLK: - break; - default: - return -EINVAL; - } - - /* Are we changing anything? */ - if (wm8995->fll[id].src == src && - wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) - return 0; - - /* If we're stopping the FLL redo the old config - no - * registers will actually be written but we avoid GCC flow - * analysis bugs spewing warnings. - */ - if (freq_out) - ret = wm8995_get_fll_config(&fll, freq_in, freq_out); - else - ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, - wm8995->fll[id].out); - if (ret < 0) - return ret; - - /* Gate the AIF clocks while we reclock */ - snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, - WM8995_AIF1CLK_ENA_MASK, 0); - snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, - WM8995_AIF2CLK_ENA_MASK, 0); - - /* We always need to disable the FLL while reconfiguring */ - snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, - WM8995_FLL1_ENA_MASK, 0); - - reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | - (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); - snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, - WM8995_FLL1_OUTDIV_MASK | - WM8995_FLL1_FRATIO_MASK, reg); - - snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); - - snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, - WM8995_FLL1_N_MASK, - fll.n << WM8995_FLL1_N_SHIFT); - - snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, - WM8995_FLL1_REFCLK_DIV_MASK | - WM8995_FLL1_REFCLK_SRC_MASK, - (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | - (src - 1)); - - if (freq_out) - snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, - WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); - - wm8995->fll[id].in = freq_in; - wm8995->fll[id].out = freq_out; - wm8995->fll[id].src = src; - - /* Enable any gated AIF clocks */ - snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, - WM8995_AIF1CLK_ENA_MASK, aif1); - snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, - WM8995_AIF2CLK_ENA_MASK, aif2); - - configure_clock(codec); - - return 0; -} - -static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, - int clk_id, unsigned int freq, int dir) -{ - struct snd_soc_codec *codec; - struct wm8995_priv *wm8995; - - codec = dai->codec; - wm8995 = snd_soc_codec_get_drvdata(codec); - - switch (dai->id) { - case 0: - case 1: - break; - default: - /* AIF3 shares clocking with AIF1/2 */ - return -EINVAL; - } - - switch (clk_id) { - case WM8995_SYSCLK_MCLK1: - wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; - wm8995->mclk[0] = freq; - dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", - dai->id + 1, freq); - break; - case WM8995_SYSCLK_MCLK2: - wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; - wm8995->mclk[1] = freq; - dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", - dai->id + 1, freq); - break; - case WM8995_SYSCLK_FLL1: - wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; - dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); - break; - case WM8995_SYSCLK_FLL2: - wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; - dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); - break; - case WM8995_SYSCLK_OPCLK: - default: - dev_err(dai->dev, "Unknown clock source %d\n", clk_id); - return -EINVAL; - } - - configure_clock(codec); - - return 0; -} - -static int wm8995_set_bias_level(struct snd_soc_codec *codec, - enum snd_soc_bias_level level) -{ - struct wm8995_priv *wm8995; - int ret; - - wm8995 = snd_soc_codec_get_drvdata(codec); - switch (level) { - case SND_SOC_BIAS_ON: - case SND_SOC_BIAS_PREPARE: - break; - case SND_SOC_BIAS_STANDBY: - if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { - ret = snd_soc_cache_sync(codec); - if (ret) { - dev_err(codec->dev, - "Failed to sync cache: %d\n", ret); - return ret; - } - - snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, - WM8995_BG_ENA_MASK, WM8995_BG_ENA); - - } - break; - case SND_SOC_BIAS_OFF: - snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, - WM8995_BG_ENA_MASK, 0); - break; - } - - codec->dapm.bias_level = level; - return 0; -} - -#ifdef CONFIG_PM -static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state) -{ - wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); - return 0; -} - -static int wm8995_resume(struct snd_soc_codec *codec) -{ - wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - return 0; -} -#else -#define wm8995_suspend NULL -#define wm8995_resume NULL -#endif - -static int wm8995_remove(struct snd_soc_codec *codec) -{ - struct wm8995_priv *wm8995; - struct i2c_client *i2c; - - i2c = container_of(codec->dev, struct i2c_client, dev); - wm8995 = snd_soc_codec_get_drvdata(codec); - wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); - return 0; -} - -static int wm8995_probe(struct snd_soc_codec *codec) -{ - struct wm8995_priv *wm8995; - int ret; - - codec->dapm.idle_bias_off = 1; - wm8995 = snd_soc_codec_get_drvdata(codec); - - ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type); - if (ret < 0) { - dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); - return ret; - } - - ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); - if (ret < 0) { - dev_err(codec->dev, "Failed to read device ID: %d\n", ret); - return ret; - } - - if (ret != 0x8995) { - dev_err(codec->dev, "Invalid device ID: %#x\n", ret); - return -EINVAL; - } - - ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); - if (ret < 0) { - dev_err(codec->dev, "Failed to issue reset: %d\n", ret); - return ret; - } - - wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); - - /* Latch volume updates (right only; we always do left then right). */ - snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, - WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); - snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, - WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); - snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, - WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); - snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, - WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); - snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, - WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); - snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, - WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); - snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, - WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); - snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, - WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); - snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, - WM8995_IN1_VU_MASK, WM8995_IN1_VU); - - wm8995_update_class_w(codec); - - snd_soc_add_controls(codec, wm8995_snd_controls, - ARRAY_SIZE(wm8995_snd_controls)); - snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, - ARRAY_SIZE(wm8995_dapm_widgets)); - snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, - ARRAY_SIZE(wm8995_intercon)); - - return 0; -} - -#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ - SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) - -static struct snd_soc_dai_ops wm8995_aif1_dai_ops = { - .set_sysclk = wm8995_set_dai_sysclk, - .set_fmt = wm8995_set_dai_fmt, - .hw_params = wm8995_hw_params, - .digital_mute = wm8995_aif_mute, - .set_pll = wm8995_set_fll, - .set_tristate = wm8995_set_tristate, -}; - -static struct snd_soc_dai_ops wm8995_aif2_dai_ops = { - .set_sysclk = wm8995_set_dai_sysclk, - .set_fmt = wm8995_set_dai_fmt, - .hw_params = wm8995_hw_params, - .digital_mute = wm8995_aif_mute, - .set_pll = wm8995_set_fll, - .set_tristate = wm8995_set_tristate, -}; - -static struct snd_soc_dai_ops wm8995_aif3_dai_ops = { - .set_tristate = wm8995_set_tristate, -}; - -static struct snd_soc_dai_driver wm8995_dai[] = { - { - .name = "wm8995-aif1", - .playback = { - .stream_name = "AIF1 Playback", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_96000, - .formats = WM8995_FORMATS - }, - .capture = { - .stream_name = "AIF1 Capture", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = WM8995_FORMATS - }, - .ops = &wm8995_aif1_dai_ops - }, - { - .name = "wm8995-aif2", - .playback = { - .stream_name = "AIF2 Playback", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_96000, - .formats = WM8995_FORMATS - }, - .capture = { - .stream_name = "AIF2 Capture", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = WM8995_FORMATS - }, - .ops = &wm8995_aif2_dai_ops - }, - { - .name = "wm8995-aif3", - .playback = { - .stream_name = "AIF3 Playback", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_96000, - .formats = WM8995_FORMATS - }, - .capture = { - .stream_name = "AIF3 Capture", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = WM8995_FORMATS - }, - .ops = &wm8995_aif3_dai_ops - } -}; - -static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { - .probe = wm8995_probe, - .remove = wm8995_remove, - .suspend = wm8995_suspend, - .resume = wm8995_resume, - .set_bias_level = wm8995_set_bias_level, - .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs), - .reg_word_size = sizeof(u16), - .reg_cache_default = wm8995_reg_defs, - .volatile_register = wm8995_volatile, - .compress_type = SND_SOC_RBTREE_COMPRESSION -}; - -#if defined(CONFIG_SPI_MASTER) -static int __devinit wm8995_spi_probe(struct spi_device *spi) -{ - struct wm8995_priv *wm8995; - int ret; - - wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); - if (!wm8995) - return -ENOMEM; - - wm8995->control_type = SND_SOC_SPI; - spi_set_drvdata(spi, wm8995); - - ret = snd_soc_register_codec(&spi->dev, - &soc_codec_dev_wm8995, wm8995_dai, - ARRAY_SIZE(wm8995_dai)); - if (ret < 0) - kfree(wm8995); - return ret; -} - -static int __devexit wm8995_spi_remove(struct spi_device *spi) -{ - snd_soc_unregister_codec(&spi->dev); - kfree(spi_get_drvdata(spi)); - return 0; -} - -static struct spi_driver wm8995_spi_driver = { - .driver = { - .name = "wm8995", - .owner = THIS_MODULE, - }, - .probe = wm8995_spi_probe, - .remove = __devexit_p(wm8995_spi_remove) -}; -#endif - -#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) -static __devinit int wm8995_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) -{ - struct wm8995_priv *wm8995; - int ret; - - wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); - if (!wm8995) - return -ENOMEM; - - wm8995->control_type = SND_SOC_I2C; - i2c_set_clientdata(i2c, wm8995); - - ret = snd_soc_register_codec(&i2c->dev, - &soc_codec_dev_wm8995, wm8995_dai, - ARRAY_SIZE(wm8995_dai)); - if (ret < 0) - kfree(wm8995); - return ret; -} - -static __devexit int wm8995_i2c_remove(struct i2c_client *client) -{ - snd_soc_unregister_codec(&client->dev); - kfree(i2c_get_clientdata(client)); - return 0; -} - -static const struct i2c_device_id wm8995_i2c_id[] = { - {"wm8995", 0}, - {} -}; - -MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); - -static struct i2c_driver wm8995_i2c_driver = { - .driver = { - .name = "wm8995", - .owner = THIS_MODULE, - }, - .probe = wm8995_i2c_probe, - .remove = __devexit_p(wm8995_i2c_remove), - .id_table = wm8995_i2c_id -}; -#endif - -static int __init wm8995_modinit(void) -{ - int ret = 0; - -#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) - ret = i2c_add_driver(&wm8995_i2c_driver); - if (ret) { - printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", - ret); - } -#endif -#if defined(CONFIG_SPI_MASTER) - ret = spi_register_driver(&wm8995_spi_driver); - if (ret) { - printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", - ret); - } -#endif - return ret; -} - -module_init(wm8995_modinit); - -static void __exit wm8995_exit(void) -{ -#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) - i2c_del_driver(&wm8995_i2c_driver); -#endif -#if defined(CONFIG_SPI_MASTER) - spi_unregister_driver(&wm8995_spi_driver); -#endif -} - -module_exit(wm8995_exit); - -MODULE_DESCRIPTION("ASoC WM8995 driver"); -MODULE_AUTHOR("Dimitris Papastamos "); -MODULE_LICENSE("GPL"); diff --git a/trunk/sound/soc/codecs/wm8995.h b/trunk/sound/soc/codecs/wm8995.h deleted file mode 100644 index 5642121c4977..000000000000 --- a/trunk/sound/soc/codecs/wm8995.h +++ /dev/null @@ -1,4269 +0,0 @@ -/* - * wm8995.h -- WM8995 ALSA SoC Audio driver - * - * Copyright 2010 Wolfson Microelectronics plc - * - * Author: Dimitris Papastamos - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _WM8995_H -#define _WM8995_H - -#include - -/* - * Register values. - */ -#define WM8995_SOFTWARE_RESET 0x00 -#define WM8995_POWER_MANAGEMENT_1 0x01 -#define WM8995_POWER_MANAGEMENT_2 0x02 -#define WM8995_POWER_MANAGEMENT_3 0x03 -#define WM8995_POWER_MANAGEMENT_4 0x04 -#define WM8995_POWER_MANAGEMENT_5 0x05 -#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10 -#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11 -#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12 -#define WM8995_DAC1_LEFT_VOLUME 0x18 -#define WM8995_DAC1_RIGHT_VOLUME 0x19 -#define WM8995_DAC2_LEFT_VOLUME 0x1A -#define WM8995_DAC2_RIGHT_VOLUME 0x1B -#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C -#define WM8995_MICBIAS_1 0x20 -#define WM8995_MICBIAS_2 0x21 -#define WM8995_LDO_1 0x28 -#define WM8995_LDO_2 0x29 -#define WM8995_ACCESSORY_DETECT_MODE1 0x30 -#define WM8995_ACCESSORY_DETECT_MODE2 0x31 -#define WM8995_HEADPHONE_DETECT1 0x34 -#define WM8995_HEADPHONE_DETECT2 0x35 -#define WM8995_MIC_DETECT_1 0x38 -#define WM8995_MIC_DETECT_2 0x39 -#define WM8995_CHARGE_PUMP_1 0x40 -#define WM8995_CLASS_W_1 0x45 -#define WM8995_DC_SERVO_1 0x50 -#define WM8995_DC_SERVO_2 0x51 -#define WM8995_DC_SERVO_3 0x52 -#define WM8995_DC_SERVO_5 0x54 -#define WM8995_DC_SERVO_6 0x55 -#define WM8995_DC_SERVO_7 0x56 -#define WM8995_DC_SERVO_READBACK_0 0x57 -#define WM8995_ANALOGUE_HP_1 0x60 -#define WM8995_ANALOGUE_HP_2 0x61 -#define WM8995_CHIP_REVISION 0x100 -#define WM8995_CONTROL_INTERFACE_1 0x101 -#define WM8995_CONTROL_INTERFACE_2 0x102 -#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110 -#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111 -#define WM8995_AIF1_CLOCKING_1 0x200 -#define WM8995_AIF1_CLOCKING_2 0x201 -#define WM8995_AIF2_CLOCKING_1 0x204 -#define WM8995_AIF2_CLOCKING_2 0x205 -#define WM8995_CLOCKING_1 0x208 -#define WM8995_CLOCKING_2 0x209 -#define WM8995_AIF1_RATE 0x210 -#define WM8995_AIF2_RATE 0x211 -#define WM8995_RATE_STATUS 0x212 -#define WM8995_FLL1_CONTROL_1 0x220 -#define WM8995_FLL1_CONTROL_2 0x221 -#define WM8995_FLL1_CONTROL_3 0x222 -#define WM8995_FLL1_CONTROL_4 0x223 -#define WM8995_FLL1_CONTROL_5 0x224 -#define WM8995_FLL2_CONTROL_1 0x240 -#define WM8995_FLL2_CONTROL_2 0x241 -#define WM8995_FLL2_CONTROL_3 0x242 -#define WM8995_FLL2_CONTROL_4 0x243 -#define WM8995_FLL2_CONTROL_5 0x244 -#define WM8995_AIF1_CONTROL_1 0x300 -#define WM8995_AIF1_CONTROL_2 0x301 -#define WM8995_AIF1_MASTER_SLAVE 0x302 -#define WM8995_AIF1_BCLK 0x303 -#define WM8995_AIF1ADC_LRCLK 0x304 -#define WM8995_AIF1DAC_LRCLK 0x305 -#define WM8995_AIF1DAC_DATA 0x306 -#define WM8995_AIF1ADC_DATA 0x307 -#define WM8995_AIF2_CONTROL_1 0x310 -#define WM8995_AIF2_CONTROL_2 0x311 -#define WM8995_AIF2_MASTER_SLAVE 0x312 -#define WM8995_AIF2_BCLK 0x313 -#define WM8995_AIF2ADC_LRCLK 0x314 -#define WM8995_AIF2DAC_LRCLK 0x315 -#define WM8995_AIF2DAC_DATA 0x316 -#define WM8995_AIF2ADC_DATA 0x317 -#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400 -#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401 -#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402 -#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403 -#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404 -#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405 -#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406 -#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407 -#define WM8995_AIF1_ADC1_FILTERS 0x410 -#define WM8995_AIF1_ADC2_FILTERS 0x411 -#define WM8995_AIF1_DAC1_FILTERS_1 0x420 -#define WM8995_AIF1_DAC1_FILTERS_2 0x421 -#define WM8995_AIF1_DAC2_FILTERS_1 0x422 -#define WM8995_AIF1_DAC2_FILTERS_2 0x423 -#define WM8995_AIF1_DRC1_1 0x440 -#define WM8995_AIF1_DRC1_2 0x441 -#define WM8995_AIF1_DRC1_3 0x442 -#define WM8995_AIF1_DRC1_4 0x443 -#define WM8995_AIF1_DRC1_5 0x444 -#define WM8995_AIF1_DRC2_1 0x450 -#define WM8995_AIF1_DRC2_2 0x451 -#define WM8995_AIF1_DRC2_3 0x452 -#define WM8995_AIF1_DRC2_4 0x453 -#define WM8995_AIF1_DRC2_5 0x454 -#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480 -#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481 -#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482 -#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483 -#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484 -#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485 -#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486 -#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487 -#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488 -#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489 -#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A -#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B -#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C -#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D -#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E -#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F -#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490 -#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491 -#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492 -#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493 -#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0 -#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1 -#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2 -#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3 -#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 -#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5 -#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6 -#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7 -#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 -#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9 -#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA -#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB -#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC -#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD -#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE -#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF -#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 -#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1 -#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2 -#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 -#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500 -#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501 -#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502 -#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503 -#define WM8995_AIF2_ADC_FILTERS 0x510 -#define WM8995_AIF2_DAC_FILTERS_1 0x520 -#define WM8995_AIF2_DAC_FILTERS_2 0x521 -#define WM8995_AIF2_DRC_1 0x540 -#define WM8995_AIF2_DRC_2 0x541 -#define WM8995_AIF2_DRC_3 0x542 -#define WM8995_AIF2_DRC_4 0x543 -#define WM8995_AIF2_DRC_5 0x544 -#define WM8995_AIF2_EQ_GAINS_1 0x580 -#define WM8995_AIF2_EQ_GAINS_2 0x581 -#define WM8995_AIF2_EQ_BAND_1_A 0x582 -#define WM8995_AIF2_EQ_BAND_1_B 0x583 -#define WM8995_AIF2_EQ_BAND_1_PG 0x584 -#define WM8995_AIF2_EQ_BAND_2_A 0x585 -#define WM8995_AIF2_EQ_BAND_2_B 0x586 -#define WM8995_AIF2_EQ_BAND_2_C 0x587 -#define WM8995_AIF2_EQ_BAND_2_PG 0x588 -#define WM8995_AIF2_EQ_BAND_3_A 0x589 -#define WM8995_AIF2_EQ_BAND_3_B 0x58A -#define WM8995_AIF2_EQ_BAND_3_C 0x58B -#define WM8995_AIF2_EQ_BAND_3_PG 0x58C -#define WM8995_AIF2_EQ_BAND_4_A 0x58D -#define WM8995_AIF2_EQ_BAND_4_B 0x58E -#define WM8995_AIF2_EQ_BAND_4_C 0x58F -#define WM8995_AIF2_EQ_BAND_4_PG 0x590 -#define WM8995_AIF2_EQ_BAND_5_A 0x591 -#define WM8995_AIF2_EQ_BAND_5_B 0x592 -#define WM8995_AIF2_EQ_BAND_5_PG 0x593 -#define WM8995_DAC1_MIXER_VOLUMES 0x600 -#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601 -#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602 -#define WM8995_DAC2_MIXER_VOLUMES 0x603 -#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604 -#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605 -#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 -#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 -#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 -#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 -#define WM8995_DAC_SOFTMUTE 0x610 -#define WM8995_OVERSAMPLING 0x620 -#define WM8995_SIDETONE 0x621 -#define WM8995_GPIO_1 0x700 -#define WM8995_GPIO_2 0x701 -#define WM8995_GPIO_3 0x702 -#define WM8995_GPIO_4 0x703 -#define WM8995_GPIO_5 0x704 -#define WM8995_GPIO_6 0x705 -#define WM8995_GPIO_7 0x706 -#define WM8995_GPIO_8 0x707 -#define WM8995_GPIO_9 0x708 -#define WM8995_GPIO_10 0x709 -#define WM8995_GPIO_11 0x70A -#define WM8995_GPIO_12 0x70B -#define WM8995_GPIO_13 0x70C -#define WM8995_GPIO_14 0x70D -#define WM8995_PULL_CONTROL_1 0x720 -#define WM8995_PULL_CONTROL_2 0x721 -#define WM8995_INTERRUPT_STATUS_1 0x730 -#define WM8995_INTERRUPT_STATUS_2 0x731 -#define WM8995_INTERRUPT_RAW_STATUS_2 0x732 -#define WM8995_INTERRUPT_STATUS_1_MASK 0x738 -#define WM8995_INTERRUPT_STATUS_2_MASK 0x739 -#define WM8995_INTERRUPT_CONTROL 0x740 -#define WM8995_LEFT_PDM_SPEAKER_1 0x800 -#define WM8995_RIGHT_PDM_SPEAKER_1 0x801 -#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802 -#define WM8995_LEFT_PDM_SPEAKER_2 0x808 -#define WM8995_RIGHT_PDM_SPEAKER_2 0x809 -#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A -#define WM8995_WRITE_SEQUENCER_0 0x3000 -#define WM8995_WRITE_SEQUENCER_1 0x3001 -#define WM8995_WRITE_SEQUENCER_2 0x3002 -#define WM8995_WRITE_SEQUENCER_3 0x3003 -#define WM8995_WRITE_SEQUENCER_4 0x3004 -#define WM8995_WRITE_SEQUENCER_5 0x3005 -#define WM8995_WRITE_SEQUENCER_6 0x3006 -#define WM8995_WRITE_SEQUENCER_7 0x3007 -#define WM8995_WRITE_SEQUENCER_8 0x3008 -#define WM8995_WRITE_SEQUENCER_9 0x3009 -#define WM8995_WRITE_SEQUENCER_10 0x300A -#define WM8995_WRITE_SEQUENCER_11 0x300B -#define WM8995_WRITE_SEQUENCER_12 0x300C -#define WM8995_WRITE_SEQUENCER_13 0x300D -#define WM8995_WRITE_SEQUENCER_14 0x300E -#define WM8995_WRITE_SEQUENCER_15 0x300F -#define WM8995_WRITE_SEQUENCER_16 0x3010 -#define WM8995_WRITE_SEQUENCER_17 0x3011 -#define WM8995_WRITE_SEQUENCER_18 0x3012 -#define WM8995_WRITE_SEQUENCER_19 0x3013 -#define WM8995_WRITE_SEQUENCER_20 0x3014 -#define WM8995_WRITE_SEQUENCER_21 0x3015 -#define WM8995_WRITE_SEQUENCER_22 0x3016 -#define WM8995_WRITE_SEQUENCER_23 0x3017 -#define WM8995_WRITE_SEQUENCER_24 0x3018 -#define WM8995_WRITE_SEQUENCER_25 0x3019 -#define WM8995_WRITE_SEQUENCER_26 0x301A -#define WM8995_WRITE_SEQUENCER_27 0x301B -#define WM8995_WRITE_SEQUENCER_28 0x301C -#define WM8995_WRITE_SEQUENCER_29 0x301D -#define WM8995_WRITE_SEQUENCER_30 0x301E -#define WM8995_WRITE_SEQUENCER_31 0x301F -#define WM8995_WRITE_SEQUENCER_32 0x3020 -#define WM8995_WRITE_SEQUENCER_33 0x3021 -#define WM8995_WRITE_SEQUENCER_34 0x3022 -#define WM8995_WRITE_SEQUENCER_35 0x3023 -#define WM8995_WRITE_SEQUENCER_36 0x3024 -#define WM8995_WRITE_SEQUENCER_37 0x3025 -#define WM8995_WRITE_SEQUENCER_38 0x3026 -#define WM8995_WRITE_SEQUENCER_39 0x3027 -#define WM8995_WRITE_SEQUENCER_40 0x3028 -#define WM8995_WRITE_SEQUENCER_41 0x3029 -#define WM8995_WRITE_SEQUENCER_42 0x302A -#define WM8995_WRITE_SEQUENCER_43 0x302B -#define WM8995_WRITE_SEQUENCER_44 0x302C -#define WM8995_WRITE_SEQUENCER_45 0x302D -#define WM8995_WRITE_SEQUENCER_46 0x302E -#define WM8995_WRITE_SEQUENCER_47 0x302F -#define WM8995_WRITE_SEQUENCER_48 0x3030 -#define WM8995_WRITE_SEQUENCER_49 0x3031 -#define WM8995_WRITE_SEQUENCER_50 0x3032 -#define WM8995_WRITE_SEQUENCER_51 0x3033 -#define WM8995_WRITE_SEQUENCER_52 0x3034 -#define WM8995_WRITE_SEQUENCER_53 0x3035 -#define WM8995_WRITE_SEQUENCER_54 0x3036 -#define WM8995_WRITE_SEQUENCER_55 0x3037 -#define WM8995_WRITE_SEQUENCER_56 0x3038 -#define WM8995_WRITE_SEQUENCER_57 0x3039 -#define WM8995_WRITE_SEQUENCER_58 0x303A -#define WM8995_WRITE_SEQUENCER_59 0x303B -#define WM8995_WRITE_SEQUENCER_60 0x303C -#define WM8995_WRITE_SEQUENCER_61 0x303D -#define WM8995_WRITE_SEQUENCER_62 0x303E -#define WM8995_WRITE_SEQUENCER_63 0x303F -#define WM8995_WRITE_SEQUENCER_64 0x3040 -#define WM8995_WRITE_SEQUENCER_65 0x3041 -#define WM8995_WRITE_SEQUENCER_66 0x3042 -#define WM8995_WRITE_SEQUENCER_67 0x3043 -#define WM8995_WRITE_SEQUENCER_68 0x3044 -#define WM8995_WRITE_SEQUENCER_69 0x3045 -#define WM8995_WRITE_SEQUENCER_70 0x3046 -#define WM8995_WRITE_SEQUENCER_71 0x3047 -#define WM8995_WRITE_SEQUENCER_72 0x3048 -#define WM8995_WRITE_SEQUENCER_73 0x3049 -#define WM8995_WRITE_SEQUENCER_74 0x304A -#define WM8995_WRITE_SEQUENCER_75 0x304B -#define WM8995_WRITE_SEQUENCER_76 0x304C -#define WM8995_WRITE_SEQUENCER_77 0x304D -#define WM8995_WRITE_SEQUENCER_78 0x304E -#define WM8995_WRITE_SEQUENCER_79 0x304F -#define WM8995_WRITE_SEQUENCER_80 0x3050 -#define WM8995_WRITE_SEQUENCER_81 0x3051 -#define WM8995_WRITE_SEQUENCER_82 0x3052 -#define WM8995_WRITE_SEQUENCER_83 0x3053 -#define WM8995_WRITE_SEQUENCER_84 0x3054 -#define WM8995_WRITE_SEQUENCER_85 0x3055 -#define WM8995_WRITE_SEQUENCER_86 0x3056 -#define WM8995_WRITE_SEQUENCER_87 0x3057 -#define WM8995_WRITE_SEQUENCER_88 0x3058 -#define WM8995_WRITE_SEQUENCER_89 0x3059 -#define WM8995_WRITE_SEQUENCER_90 0x305A -#define WM8995_WRITE_SEQUENCER_91 0x305B -#define WM8995_WRITE_SEQUENCER_92 0x305C -#define WM8995_WRITE_SEQUENCER_93 0x305D -#define WM8995_WRITE_SEQUENCER_94 0x305E -#define WM8995_WRITE_SEQUENCER_95 0x305F -#define WM8995_WRITE_SEQUENCER_96 0x3060 -#define WM8995_WRITE_SEQUENCER_97 0x3061 -#define WM8995_WRITE_SEQUENCER_98 0x3062 -#define WM8995_WRITE_SEQUENCER_99 0x3063 -#define WM8995_WRITE_SEQUENCER_100 0x3064 -#define WM8995_WRITE_SEQUENCER_101 0x3065 -#define WM8995_WRITE_SEQUENCER_102 0x3066 -#define WM8995_WRITE_SEQUENCER_103 0x3067 -#define WM8995_WRITE_SEQUENCER_104 0x3068 -#define WM8995_WRITE_SEQUENCER_105 0x3069 -#define WM8995_WRITE_SEQUENCER_106 0x306A -#define WM8995_WRITE_SEQUENCER_107 0x306B -#define WM8995_WRITE_SEQUENCER_108 0x306C -#define WM8995_WRITE_SEQUENCER_109 0x306D -#define WM8995_WRITE_SEQUENCER_110 0x306E -#define WM8995_WRITE_SEQUENCER_111 0x306F -#define WM8995_WRITE_SEQUENCER_112 0x3070 -#define WM8995_WRITE_SEQUENCER_113 0x3071 -#define WM8995_WRITE_SEQUENCER_114 0x3072 -#define WM8995_WRITE_SEQUENCER_115 0x3073 -#define WM8995_WRITE_SEQUENCER_116 0x3074 -#define WM8995_WRITE_SEQUENCER_117 0x3075 -#define WM8995_WRITE_SEQUENCER_118 0x3076 -#define WM8995_WRITE_SEQUENCER_119 0x3077 -#define WM8995_WRITE_SEQUENCER_120 0x3078 -#define WM8995_WRITE_SEQUENCER_121 0x3079 -#define WM8995_WRITE_SEQUENCER_122 0x307A -#define WM8995_WRITE_SEQUENCER_123 0x307B -#define WM8995_WRITE_SEQUENCER_124 0x307C -#define WM8995_WRITE_SEQUENCER_125 0x307D -#define WM8995_WRITE_SEQUENCER_126 0x307E -#define WM8995_WRITE_SEQUENCER_127 0x307F -#define WM8995_WRITE_SEQUENCER_128 0x3080 -#define WM8995_WRITE_SEQUENCER_129 0x3081 -#define WM8995_WRITE_SEQUENCER_130 0x3082 -#define WM8995_WRITE_SEQUENCER_131 0x3083 -#define WM8995_WRITE_SEQUENCER_132 0x3084 -#define WM8995_WRITE_SEQUENCER_133 0x3085 -#define WM8995_WRITE_SEQUENCER_134 0x3086 -#define WM8995_WRITE_SEQUENCER_135 0x3087 -#define WM8995_WRITE_SEQUENCER_136 0x3088 -#define WM8995_WRITE_SEQUENCER_137 0x3089 -#define WM8995_WRITE_SEQUENCER_138 0x308A -#define WM8995_WRITE_SEQUENCER_139 0x308B -#define WM8995_WRITE_SEQUENCER_140 0x308C -#define WM8995_WRITE_SEQUENCER_141 0x308D -#define WM8995_WRITE_SEQUENCER_142 0x308E -#define WM8995_WRITE_SEQUENCER_143 0x308F -#define WM8995_WRITE_SEQUENCER_144 0x3090 -#define WM8995_WRITE_SEQUENCER_145 0x3091 -#define WM8995_WRITE_SEQUENCER_146 0x3092 -#define WM8995_WRITE_SEQUENCER_147 0x3093 -#define WM8995_WRITE_SEQUENCER_148 0x3094 -#define WM8995_WRITE_SEQUENCER_149 0x3095 -#define WM8995_WRITE_SEQUENCER_150 0x3096 -#define WM8995_WRITE_SEQUENCER_151 0x3097 -#define WM8995_WRITE_SEQUENCER_152 0x3098 -#define WM8995_WRITE_SEQUENCER_153 0x3099 -#define WM8995_WRITE_SEQUENCER_154 0x309A -#define WM8995_WRITE_SEQUENCER_155 0x309B -#define WM8995_WRITE_SEQUENCER_156 0x309C -#define WM8995_WRITE_SEQUENCER_157 0x309D -#define WM8995_WRITE_SEQUENCER_158 0x309E -#define WM8995_WRITE_SEQUENCER_159 0x309F -#define WM8995_WRITE_SEQUENCER_160 0x30A0 -#define WM8995_WRITE_SEQUENCER_161 0x30A1 -#define WM8995_WRITE_SEQUENCER_162 0x30A2 -#define WM8995_WRITE_SEQUENCER_163 0x30A3 -#define WM8995_WRITE_SEQUENCER_164 0x30A4 -#define WM8995_WRITE_SEQUENCER_165 0x30A5 -#define WM8995_WRITE_SEQUENCER_166 0x30A6 -#define WM8995_WRITE_SEQUENCER_167 0x30A7 -#define WM8995_WRITE_SEQUENCER_168 0x30A8 -#define WM8995_WRITE_SEQUENCER_169 0x30A9 -#define WM8995_WRITE_SEQUENCER_170 0x30AA -#define WM8995_WRITE_SEQUENCER_171 0x30AB -#define WM8995_WRITE_SEQUENCER_172 0x30AC -#define WM8995_WRITE_SEQUENCER_173 0x30AD -#define WM8995_WRITE_SEQUENCER_174 0x30AE -#define WM8995_WRITE_SEQUENCER_175 0x30AF -#define WM8995_WRITE_SEQUENCER_176 0x30B0 -#define WM8995_WRITE_SEQUENCER_177 0x30B1 -#define WM8995_WRITE_SEQUENCER_178 0x30B2 -#define WM8995_WRITE_SEQUENCER_179 0x30B3 -#define WM8995_WRITE_SEQUENCER_180 0x30B4 -#define WM8995_WRITE_SEQUENCER_181 0x30B5 -#define WM8995_WRITE_SEQUENCER_182 0x30B6 -#define WM8995_WRITE_SEQUENCER_183 0x30B7 -#define WM8995_WRITE_SEQUENCER_184 0x30B8 -#define WM8995_WRITE_SEQUENCER_185 0x30B9 -#define WM8995_WRITE_SEQUENCER_186 0x30BA -#define WM8995_WRITE_SEQUENCER_187 0x30BB -#define WM8995_WRITE_SEQUENCER_188 0x30BC -#define WM8995_WRITE_SEQUENCER_189 0x30BD -#define WM8995_WRITE_SEQUENCER_190 0x30BE -#define WM8995_WRITE_SEQUENCER_191 0x30BF -#define WM8995_WRITE_SEQUENCER_192 0x30C0 -#define WM8995_WRITE_SEQUENCER_193 0x30C1 -#define WM8995_WRITE_SEQUENCER_194 0x30C2 -#define WM8995_WRITE_SEQUENCER_195 0x30C3 -#define WM8995_WRITE_SEQUENCER_196 0x30C4 -#define WM8995_WRITE_SEQUENCER_197 0x30C5 -#define WM8995_WRITE_SEQUENCER_198 0x30C6 -#define WM8995_WRITE_SEQUENCER_199 0x30C7 -#define WM8995_WRITE_SEQUENCER_200 0x30C8 -#define WM8995_WRITE_SEQUENCER_201 0x30C9 -#define WM8995_WRITE_SEQUENCER_202 0x30CA -#define WM8995_WRITE_SEQUENCER_203 0x30CB -#define WM8995_WRITE_SEQUENCER_204 0x30CC -#define WM8995_WRITE_SEQUENCER_205 0x30CD -#define WM8995_WRITE_SEQUENCER_206 0x30CE -#define WM8995_WRITE_SEQUENCER_207 0x30CF -#define WM8995_WRITE_SEQUENCER_208 0x30D0 -#define WM8995_WRITE_SEQUENCER_209 0x30D1 -#define WM8995_WRITE_SEQUENCER_210 0x30D2 -#define WM8995_WRITE_SEQUENCER_211 0x30D3 -#define WM8995_WRITE_SEQUENCER_212 0x30D4 -#define WM8995_WRITE_SEQUENCER_213 0x30D5 -#define WM8995_WRITE_SEQUENCER_214 0x30D6 -#define WM8995_WRITE_SEQUENCER_215 0x30D7 -#define WM8995_WRITE_SEQUENCER_216 0x30D8 -#define WM8995_WRITE_SEQUENCER_217 0x30D9 -#define WM8995_WRITE_SEQUENCER_218 0x30DA -#define WM8995_WRITE_SEQUENCER_219 0x30DB -#define WM8995_WRITE_SEQUENCER_220 0x30DC -#define WM8995_WRITE_SEQUENCER_221 0x30DD -#define WM8995_WRITE_SEQUENCER_222 0x30DE -#define WM8995_WRITE_SEQUENCER_223 0x30DF -#define WM8995_WRITE_SEQUENCER_224 0x30E0 -#define WM8995_WRITE_SEQUENCER_225 0x30E1 -#define WM8995_WRITE_SEQUENCER_226 0x30E2 -#define WM8995_WRITE_SEQUENCER_227 0x30E3 -#define WM8995_WRITE_SEQUENCER_228 0x30E4 -#define WM8995_WRITE_SEQUENCER_229 0x30E5 -#define WM8995_WRITE_SEQUENCER_230 0x30E6 -#define WM8995_WRITE_SEQUENCER_231 0x30E7 -#define WM8995_WRITE_SEQUENCER_232 0x30E8 -#define WM8995_WRITE_SEQUENCER_233 0x30E9 -#define WM8995_WRITE_SEQUENCER_234 0x30EA -#define WM8995_WRITE_SEQUENCER_235 0x30EB -#define WM8995_WRITE_SEQUENCER_236 0x30EC -#define WM8995_WRITE_SEQUENCER_237 0x30ED -#define WM8995_WRITE_SEQUENCER_238 0x30EE -#define WM8995_WRITE_SEQUENCER_239 0x30EF -#define WM8995_WRITE_SEQUENCER_240 0x30F0 -#define WM8995_WRITE_SEQUENCER_241 0x30F1 -#define WM8995_WRITE_SEQUENCER_242 0x30F2 -#define WM8995_WRITE_SEQUENCER_243 0x30F3 -#define WM8995_WRITE_SEQUENCER_244 0x30F4 -#define WM8995_WRITE_SEQUENCER_245 0x30F5 -#define WM8995_WRITE_SEQUENCER_246 0x30F6 -#define WM8995_WRITE_SEQUENCER_247 0x30F7 -#define WM8995_WRITE_SEQUENCER_248 0x30F8 -#define WM8995_WRITE_SEQUENCER_249 0x30F9 -#define WM8995_WRITE_SEQUENCER_250 0x30FA -#define WM8995_WRITE_SEQUENCER_251 0x30FB -#define WM8995_WRITE_SEQUENCER_252 0x30FC -#define WM8995_WRITE_SEQUENCER_253 0x30FD -#define WM8995_WRITE_SEQUENCER_254 0x30FE -#define WM8995_WRITE_SEQUENCER_255 0x30FF -#define WM8995_WRITE_SEQUENCER_256 0x3100 -#define WM8995_WRITE_SEQUENCER_257 0x3101 -#define WM8995_WRITE_SEQUENCER_258 0x3102 -#define WM8995_WRITE_SEQUENCER_259 0x3103 -#define WM8995_WRITE_SEQUENCER_260 0x3104 -#define WM8995_WRITE_SEQUENCER_261 0x3105 -#define WM8995_WRITE_SEQUENCER_262 0x3106 -#define WM8995_WRITE_SEQUENCER_263 0x3107 -#define WM8995_WRITE_SEQUENCER_264 0x3108 -#define WM8995_WRITE_SEQUENCER_265 0x3109 -#define WM8995_WRITE_SEQUENCER_266 0x310A -#define WM8995_WRITE_SEQUENCER_267 0x310B -#define WM8995_WRITE_SEQUENCER_268 0x310C -#define WM8995_WRITE_SEQUENCER_269 0x310D -#define WM8995_WRITE_SEQUENCER_270 0x310E -#define WM8995_WRITE_SEQUENCER_271 0x310F -#define WM8995_WRITE_SEQUENCER_272 0x3110 -#define WM8995_WRITE_SEQUENCER_273 0x3111 -#define WM8995_WRITE_SEQUENCER_274 0x3112 -#define WM8995_WRITE_SEQUENCER_275 0x3113 -#define WM8995_WRITE_SEQUENCER_276 0x3114 -#define WM8995_WRITE_SEQUENCER_277 0x3115 -#define WM8995_WRITE_SEQUENCER_278 0x3116 -#define WM8995_WRITE_SEQUENCER_279 0x3117 -#define WM8995_WRITE_SEQUENCER_280 0x3118 -#define WM8995_WRITE_SEQUENCER_281 0x3119 -#define WM8995_WRITE_SEQUENCER_282 0x311A -#define WM8995_WRITE_SEQUENCER_283 0x311B -#define WM8995_WRITE_SEQUENCER_284 0x311C -#define WM8995_WRITE_SEQUENCER_285 0x311D -#define WM8995_WRITE_SEQUENCER_286 0x311E -#define WM8995_WRITE_SEQUENCER_287 0x311F -#define WM8995_WRITE_SEQUENCER_288 0x3120 -#define WM8995_WRITE_SEQUENCER_289 0x3121 -#define WM8995_WRITE_SEQUENCER_290 0x3122 -#define WM8995_WRITE_SEQUENCER_291 0x3123 -#define WM8995_WRITE_SEQUENCER_292 0x3124 -#define WM8995_WRITE_SEQUENCER_293 0x3125 -#define WM8995_WRITE_SEQUENCER_294 0x3126 -#define WM8995_WRITE_SEQUENCER_295 0x3127 -#define WM8995_WRITE_SEQUENCER_296 0x3128 -#define WM8995_WRITE_SEQUENCER_297 0x3129 -#define WM8995_WRITE_SEQUENCER_298 0x312A -#define WM8995_WRITE_SEQUENCER_299 0x312B -#define WM8995_WRITE_SEQUENCER_300 0x312C -#define WM8995_WRITE_SEQUENCER_301 0x312D -#define WM8995_WRITE_SEQUENCER_302 0x312E -#define WM8995_WRITE_SEQUENCER_303 0x312F -#define WM8995_WRITE_SEQUENCER_304 0x3130 -#define WM8995_WRITE_SEQUENCER_305 0x3131 -#define WM8995_WRITE_SEQUENCER_306 0x3132 -#define WM8995_WRITE_SEQUENCER_307 0x3133 -#define WM8995_WRITE_SEQUENCER_308 0x3134 -#define WM8995_WRITE_SEQUENCER_309 0x3135 -#define WM8995_WRITE_SEQUENCER_310 0x3136 -#define WM8995_WRITE_SEQUENCER_311 0x3137 -#define WM8995_WRITE_SEQUENCER_312 0x3138 -#define WM8995_WRITE_SEQUENCER_313 0x3139 -#define WM8995_WRITE_SEQUENCER_314 0x313A -#define WM8995_WRITE_SEQUENCER_315 0x313B -#define WM8995_WRITE_SEQUENCER_316 0x313C -#define WM8995_WRITE_SEQUENCER_317 0x313D -#define WM8995_WRITE_SEQUENCER_318 0x313E -#define WM8995_WRITE_SEQUENCER_319 0x313F -#define WM8995_WRITE_SEQUENCER_320 0x3140 -#define WM8995_WRITE_SEQUENCER_321 0x3141 -#define WM8995_WRITE_SEQUENCER_322 0x3142 -#define WM8995_WRITE_SEQUENCER_323 0x3143 -#define WM8995_WRITE_SEQUENCER_324 0x3144 -#define WM8995_WRITE_SEQUENCER_325 0x3145 -#define WM8995_WRITE_SEQUENCER_326 0x3146 -#define WM8995_WRITE_SEQUENCER_327 0x3147 -#define WM8995_WRITE_SEQUENCER_328 0x3148 -#define WM8995_WRITE_SEQUENCER_329 0x3149 -#define WM8995_WRITE_SEQUENCER_330 0x314A -#define WM8995_WRITE_SEQUENCER_331 0x314B -#define WM8995_WRITE_SEQUENCER_332 0x314C -#define WM8995_WRITE_SEQUENCER_333 0x314D -#define WM8995_WRITE_SEQUENCER_334 0x314E -#define WM8995_WRITE_SEQUENCER_335 0x314F -#define WM8995_WRITE_SEQUENCER_336 0x3150 -#define WM8995_WRITE_SEQUENCER_337 0x3151 -#define WM8995_WRITE_SEQUENCER_338 0x3152 -#define WM8995_WRITE_SEQUENCER_339 0x3153 -#define WM8995_WRITE_SEQUENCER_340 0x3154 -#define WM8995_WRITE_SEQUENCER_341 0x3155 -#define WM8995_WRITE_SEQUENCER_342 0x3156 -#define WM8995_WRITE_SEQUENCER_343 0x3157 -#define WM8995_WRITE_SEQUENCER_344 0x3158 -#define WM8995_WRITE_SEQUENCER_345 0x3159 -#define WM8995_WRITE_SEQUENCER_346 0x315A -#define WM8995_WRITE_SEQUENCER_347 0x315B -#define WM8995_WRITE_SEQUENCER_348 0x315C -#define WM8995_WRITE_SEQUENCER_349 0x315D -#define WM8995_WRITE_SEQUENCER_350 0x315E -#define WM8995_WRITE_SEQUENCER_351 0x315F -#define WM8995_WRITE_SEQUENCER_352 0x3160 -#define WM8995_WRITE_SEQUENCER_353 0x3161 -#define WM8995_WRITE_SEQUENCER_354 0x3162 -#define WM8995_WRITE_SEQUENCER_355 0x3163 -#define WM8995_WRITE_SEQUENCER_356 0x3164 -#define WM8995_WRITE_SEQUENCER_357 0x3165 -#define WM8995_WRITE_SEQUENCER_358 0x3166 -#define WM8995_WRITE_SEQUENCER_359 0x3167 -#define WM8995_WRITE_SEQUENCER_360 0x3168 -#define WM8995_WRITE_SEQUENCER_361 0x3169 -#define WM8995_WRITE_SEQUENCER_362 0x316A -#define WM8995_WRITE_SEQUENCER_363 0x316B -#define WM8995_WRITE_SEQUENCER_364 0x316C -#define WM8995_WRITE_SEQUENCER_365 0x316D -#define WM8995_WRITE_SEQUENCER_366 0x316E -#define WM8995_WRITE_SEQUENCER_367 0x316F -#define WM8995_WRITE_SEQUENCER_368 0x3170 -#define WM8995_WRITE_SEQUENCER_369 0x3171 -#define WM8995_WRITE_SEQUENCER_370 0x3172 -#define WM8995_WRITE_SEQUENCER_371 0x3173 -#define WM8995_WRITE_SEQUENCER_372 0x3174 -#define WM8995_WRITE_SEQUENCER_373 0x3175 -#define WM8995_WRITE_SEQUENCER_374 0x3176 -#define WM8995_WRITE_SEQUENCER_375 0x3177 -#define WM8995_WRITE_SEQUENCER_376 0x3178 -#define WM8995_WRITE_SEQUENCER_377 0x3179 -#define WM8995_WRITE_SEQUENCER_378 0x317A -#define WM8995_WRITE_SEQUENCER_379 0x317B -#define WM8995_WRITE_SEQUENCER_380 0x317C -#define WM8995_WRITE_SEQUENCER_381 0x317D -#define WM8995_WRITE_SEQUENCER_382 0x317E -#define WM8995_WRITE_SEQUENCER_383 0x317F -#define WM8995_WRITE_SEQUENCER_384 0x3180 -#define WM8995_WRITE_SEQUENCER_385 0x3181 -#define WM8995_WRITE_SEQUENCER_386 0x3182 -#define WM8995_WRITE_SEQUENCER_387 0x3183 -#define WM8995_WRITE_SEQUENCER_388 0x3184 -#define WM8995_WRITE_SEQUENCER_389 0x3185 -#define WM8995_WRITE_SEQUENCER_390 0x3186 -#define WM8995_WRITE_SEQUENCER_391 0x3187 -#define WM8995_WRITE_SEQUENCER_392 0x3188 -#define WM8995_WRITE_SEQUENCER_393 0x3189 -#define WM8995_WRITE_SEQUENCER_394 0x318A -#define WM8995_WRITE_SEQUENCER_395 0x318B -#define WM8995_WRITE_SEQUENCER_396 0x318C -#define WM8995_WRITE_SEQUENCER_397 0x318D -#define WM8995_WRITE_SEQUENCER_398 0x318E -#define WM8995_WRITE_SEQUENCER_399 0x318F -#define WM8995_WRITE_SEQUENCER_400 0x3190 -#define WM8995_WRITE_SEQUENCER_401 0x3191 -#define WM8995_WRITE_SEQUENCER_402 0x3192 -#define WM8995_WRITE_SEQUENCER_403 0x3193 -#define WM8995_WRITE_SEQUENCER_404 0x3194 -#define WM8995_WRITE_SEQUENCER_405 0x3195 -#define WM8995_WRITE_SEQUENCER_406 0x3196 -#define WM8995_WRITE_SEQUENCER_407 0x3197 -#define WM8995_WRITE_SEQUENCER_408 0x3198 -#define WM8995_WRITE_SEQUENCER_409 0x3199 -#define WM8995_WRITE_SEQUENCER_410 0x319A -#define WM8995_WRITE_SEQUENCER_411 0x319B -#define WM8995_WRITE_SEQUENCER_412 0x319C -#define WM8995_WRITE_SEQUENCER_413 0x319D -#define WM8995_WRITE_SEQUENCER_414 0x319E -#define WM8995_WRITE_SEQUENCER_415 0x319F -#define WM8995_WRITE_SEQUENCER_416 0x31A0 -#define WM8995_WRITE_SEQUENCER_417 0x31A1 -#define WM8995_WRITE_SEQUENCER_418 0x31A2 -#define WM8995_WRITE_SEQUENCER_419 0x31A3 -#define WM8995_WRITE_SEQUENCER_420 0x31A4 -#define WM8995_WRITE_SEQUENCER_421 0x31A5 -#define WM8995_WRITE_SEQUENCER_422 0x31A6 -#define WM8995_WRITE_SEQUENCER_423 0x31A7 -#define WM8995_WRITE_SEQUENCER_424 0x31A8 -#define WM8995_WRITE_SEQUENCER_425 0x31A9 -#define WM8995_WRITE_SEQUENCER_426 0x31AA -#define WM8995_WRITE_SEQUENCER_427 0x31AB -#define WM8995_WRITE_SEQUENCER_428 0x31AC -#define WM8995_WRITE_SEQUENCER_429 0x31AD -#define WM8995_WRITE_SEQUENCER_430 0x31AE -#define WM8995_WRITE_SEQUENCER_431 0x31AF -#define WM8995_WRITE_SEQUENCER_432 0x31B0 -#define WM8995_WRITE_SEQUENCER_433 0x31B1 -#define WM8995_WRITE_SEQUENCER_434 0x31B2 -#define WM8995_WRITE_SEQUENCER_435 0x31B3 -#define WM8995_WRITE_SEQUENCER_436 0x31B4 -#define WM8995_WRITE_SEQUENCER_437 0x31B5 -#define WM8995_WRITE_SEQUENCER_438 0x31B6 -#define WM8995_WRITE_SEQUENCER_439 0x31B7 -#define WM8995_WRITE_SEQUENCER_440 0x31B8 -#define WM8995_WRITE_SEQUENCER_441 0x31B9 -#define WM8995_WRITE_SEQUENCER_442 0x31BA -#define WM8995_WRITE_SEQUENCER_443 0x31BB -#define WM8995_WRITE_SEQUENCER_444 0x31BC -#define WM8995_WRITE_SEQUENCER_445 0x31BD -#define WM8995_WRITE_SEQUENCER_446 0x31BE -#define WM8995_WRITE_SEQUENCER_447 0x31BF -#define WM8995_WRITE_SEQUENCER_448 0x31C0 -#define WM8995_WRITE_SEQUENCER_449 0x31C1 -#define WM8995_WRITE_SEQUENCER_450 0x31C2 -#define WM8995_WRITE_SEQUENCER_451 0x31C3 -#define WM8995_WRITE_SEQUENCER_452 0x31C4 -#define WM8995_WRITE_SEQUENCER_453 0x31C5 -#define WM8995_WRITE_SEQUENCER_454 0x31C6 -#define WM8995_WRITE_SEQUENCER_455 0x31C7 -#define WM8995_WRITE_SEQUENCER_456 0x31C8 -#define WM8995_WRITE_SEQUENCER_457 0x31C9 -#define WM8995_WRITE_SEQUENCER_458 0x31CA -#define WM8995_WRITE_SEQUENCER_459 0x31CB -#define WM8995_WRITE_SEQUENCER_460 0x31CC -#define WM8995_WRITE_SEQUENCER_461 0x31CD -#define WM8995_WRITE_SEQUENCER_462 0x31CE -#define WM8995_WRITE_SEQUENCER_463 0x31CF -#define WM8995_WRITE_SEQUENCER_464 0x31D0 -#define WM8995_WRITE_SEQUENCER_465 0x31D1 -#define WM8995_WRITE_SEQUENCER_466 0x31D2 -#define WM8995_WRITE_SEQUENCER_467 0x31D3 -#define WM8995_WRITE_SEQUENCER_468 0x31D4 -#define WM8995_WRITE_SEQUENCER_469 0x31D5 -#define WM8995_WRITE_SEQUENCER_470 0x31D6 -#define WM8995_WRITE_SEQUENCER_471 0x31D7 -#define WM8995_WRITE_SEQUENCER_472 0x31D8 -#define WM8995_WRITE_SEQUENCER_473 0x31D9 -#define WM8995_WRITE_SEQUENCER_474 0x31DA -#define WM8995_WRITE_SEQUENCER_475 0x31DB -#define WM8995_WRITE_SEQUENCER_476 0x31DC -#define WM8995_WRITE_SEQUENCER_477 0x31DD -#define WM8995_WRITE_SEQUENCER_478 0x31DE -#define WM8995_WRITE_SEQUENCER_479 0x31DF -#define WM8995_WRITE_SEQUENCER_480 0x31E0 -#define WM8995_WRITE_SEQUENCER_481 0x31E1 -#define WM8995_WRITE_SEQUENCER_482 0x31E2 -#define WM8995_WRITE_SEQUENCER_483 0x31E3 -#define WM8995_WRITE_SEQUENCER_484 0x31E4 -#define WM8995_WRITE_SEQUENCER_485 0x31E5 -#define WM8995_WRITE_SEQUENCER_486 0x31E6 -#define WM8995_WRITE_SEQUENCER_487 0x31E7 -#define WM8995_WRITE_SEQUENCER_488 0x31E8 -#define WM8995_WRITE_SEQUENCER_489 0x31E9 -#define WM8995_WRITE_SEQUENCER_490 0x31EA -#define WM8995_WRITE_SEQUENCER_491 0x31EB -#define WM8995_WRITE_SEQUENCER_492 0x31EC -#define WM8995_WRITE_SEQUENCER_493 0x31ED -#define WM8995_WRITE_SEQUENCER_494 0x31EE -#define WM8995_WRITE_SEQUENCER_495 0x31EF -#define WM8995_WRITE_SEQUENCER_496 0x31F0 -#define WM8995_WRITE_SEQUENCER_497 0x31F1 -#define WM8995_WRITE_SEQUENCER_498 0x31F2 -#define WM8995_WRITE_SEQUENCER_499 0x31F3 -#define WM8995_WRITE_SEQUENCER_500 0x31F4 -#define WM8995_WRITE_SEQUENCER_501 0x31F5 -#define WM8995_WRITE_SEQUENCER_502 0x31F6 -#define WM8995_WRITE_SEQUENCER_503 0x31F7 -#define WM8995_WRITE_SEQUENCER_504 0x31F8 -#define WM8995_WRITE_SEQUENCER_505 0x31F9 -#define WM8995_WRITE_SEQUENCER_506 0x31FA -#define WM8995_WRITE_SEQUENCER_507 0x31FB -#define WM8995_WRITE_SEQUENCER_508 0x31FC -#define WM8995_WRITE_SEQUENCER_509 0x31FD -#define WM8995_WRITE_SEQUENCER_510 0x31FE -#define WM8995_WRITE_SEQUENCER_511 0x31FF - -#define WM8995_REGISTER_COUNT 725 -#define WM8995_MAX_REGISTER 0x31FF - -#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER - -/* - * Field Definitions. - */ - -/* - * R0 (0x00) - Software Reset - */ -#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ -#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ -#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ - -/* - * R1 (0x01) - Power Management (1) - */ -#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */ -#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ -#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ -#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ -#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */ -#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ -#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ -#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ -#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ -#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ -#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ -#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ -#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ -#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ -#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ -#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ -#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ -#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ -#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ -#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ -#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ -#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ -#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ -#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ -#define WM8995_BG_ENA 0x0001 /* BG_ENA */ -#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */ -#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */ -#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */ - -/* - * R2 (0x02) - Power Management (2) - */ -#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */ -#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ -#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ -#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ -#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */ -#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */ -#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */ -#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ -#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */ -#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ -#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ -#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ -#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */ -#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ -#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ -#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ - -/* - * R3 (0x03) - Power Management (3) - */ -#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ -#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ -#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ -#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ -#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ -#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ -#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ -#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ -#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ -#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ -#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ -#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ -#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ -#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ -#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ -#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ -#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ -#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ -#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ -#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ -#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ -#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ -#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ -#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ -#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */ -#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */ -#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */ -#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */ -#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */ -#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */ -#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */ -#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */ -#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ -#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ -#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ -#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ -#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ -#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ -#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ -#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ -#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ -#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ -#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ -#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ -#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ -#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ -#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ -#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ -#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */ -#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ -#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ -#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ -#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */ -#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ -#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ -#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ - -/* - * R4 (0x04) - Power Management (4) - */ -#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ -#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ -#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ -#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ -#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ -#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ -#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ -#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ -#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ -#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ -#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ -#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ -#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ -#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ -#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ -#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ -#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ -#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ -#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ -#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ -#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ -#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ -#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ -#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ -#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */ -#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ -#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ -#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ -#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */ -#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ -#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ -#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ -#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */ -#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ -#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ -#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ -#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */ -#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ -#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ -#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ - -/* - * R5 (0x05) - Power Management (5) - */ -#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */ -#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */ -#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */ -#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */ -#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */ -#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */ -#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */ -#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ -#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ -#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ -#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ -#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ -#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ -#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ -#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ -#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ -#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ -#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ -#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ -#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ -#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ -#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ -#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ -#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ -#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ - -/* - * R16 (0x10) - Left Line Input 1 Volume - */ -#define WM8995_IN1_VU 0x0080 /* IN1_VU */ -#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ -#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ -#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ -#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */ -#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ -#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ -#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ -#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ -#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ -#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ - -/* - * R17 (0x11) - Right Line Input 1 Volume - */ -#define WM8995_IN1_VU 0x0080 /* IN1_VU */ -#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ -#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ -#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ -#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */ -#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ -#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ -#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ -#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ -#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ -#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ - -/* - * R18 (0x12) - Left Line Input Control - */ -#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */ -#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */ -#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */ -#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */ -#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */ -#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */ -#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */ -#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */ -#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */ - -/* - * R24 (0x18) - DAC1 Left Volume - */ -#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ -#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ -#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ -#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ -#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ -#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ -#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ - -/* - * R25 (0x19) - DAC1 Right Volume - */ -#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ -#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ -#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ -#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ -#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ -#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ -#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ -#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ -#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ -#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ -#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ - -/* - * R26 (0x1A) - DAC2 Left Volume - */ -#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ -#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ -#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ -#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ -#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ -#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ -#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ - -/* - * R27 (0x1B) - DAC2 Right Volume - */ -#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ -#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ -#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ -#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ -#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ -#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ -#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ -#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ -#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ -#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ -#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ - -/* - * R28 (0x1C) - Output Volume ZC (1) - */ -#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */ -#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */ -#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */ -#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ -#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */ -#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */ -#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */ -#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ -#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */ -#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */ -#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */ -#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ -#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */ -#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */ -#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */ -#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ - -/* - * R32 (0x20) - MICBIAS (1) - */ -#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */ -#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */ -#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */ -#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ -#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */ -#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */ -#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */ -#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */ -#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ -#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ -#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ - -/* - * R33 (0x21) - MICBIAS (2) - */ -#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */ -#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */ -#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */ -#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ -#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */ -#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */ -#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */ -#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */ -#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ -#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ -#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ - -/* - * R40 (0x28) - LDO 1 - */ -#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */ -#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ -#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ -#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ -#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ -#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ -#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ -#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */ -#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ -#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ -#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ - -/* - * R41 (0x29) - LDO 2 - */ -#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */ -#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ -#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ -#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ -#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ -#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ -#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ -#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */ -#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ -#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ -#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ - -/* - * R48 (0x30) - Accessory Detect Mode1 - */ -#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ -#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ -#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ - -/* - * R49 (0x31) - Accessory Detect Mode2 - */ -#define WM8995_VID_ENA 0x0001 /* VID_ENA */ -#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */ -#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */ -#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */ - -/* - * R52 (0x34) - Headphone Detect1 - */ -#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */ -#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */ -#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */ -#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */ -#define WM8995_HP_POLL 0x0001 /* HP_POLL */ -#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */ -#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */ -#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */ - -/* - * R53 (0x35) - Headphone Detect2 - */ -#define WM8995_HP_DONE 0x0080 /* HP_DONE */ -#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */ -#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */ -#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */ -#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ -#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ -#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ - -/* - * R56 (0x38) - Mic Detect (1) - */ -#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */ -#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */ -#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */ -#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */ -#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */ -#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */ -#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */ -#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ -#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ -#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ -#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */ -#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */ -#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */ -#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */ - -/* - * R57 (0x39) - Mic Detect (2) - */ -#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */ -#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */ -#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */ -#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */ -#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */ -#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */ -#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */ -#define WM8995_MICD_STS 0x0001 /* MICD_STS */ -#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */ -#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */ -#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */ - -/* - * R64 (0x40) - Charge Pump (1) - */ -#define WM8995_CP_ENA 0x8000 /* CP_ENA */ -#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */ -#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */ -#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */ - -/* - * R69 (0x45) - Class W (1) - */ -#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ -#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ -#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ -#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ -#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ -#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ -#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ - -/* - * R80 (0x50) - DC Servo (1) - */ -#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ -#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ -#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ -#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ -#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ -#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ -#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ -#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ -#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ -#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ -#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ -#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ -#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ -#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ -#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ -#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ - -/* - * R81 (0x51) - DC Servo (2) - */ -#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ -#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ -#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ -#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ -#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ -#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ -#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ -#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ -#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ -#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ -#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ -#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ -#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ -#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ -#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ -#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ -#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ -#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ -#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ -#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ -#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ -#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ -#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ -#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ -#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ -#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ -#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ -#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ -#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ -#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ -#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ -#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ -#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ -#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ -#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ -#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ -#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ -#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ -#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ -#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ -#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ -#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ -#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ -#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ -#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ -#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ -#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ -#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ -#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ -#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ -#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ -#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ -#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ -#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ -#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ -#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ -#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ -#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ -#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ -#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ -#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ -#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ -#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ -#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ - -/* - * R82 (0x52) - DC Servo (3) - */ -#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ -#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ -#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ -#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ - -/* - * R84 (0x54) - DC Servo (5) - */ -#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ -#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ -#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ -#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ - -/* - * R85 (0x55) - DC Servo (6) - */ -#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ -#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ -#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ - -/* - * R86 (0x56) - DC Servo (7) - */ -#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ -#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ -#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ -#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ - -/* - * R87 (0x57) - DC Servo Readback 0 - */ -#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ -#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ -#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ -#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ -#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ - -/* - * R96 (0x60) - Analogue HP (1) - */ -#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ -#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ -#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ -#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ -#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ -#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ -#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ -#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ -#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ -#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ -#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ -#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ -#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ -#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ -#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ -#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ -#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ -#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ -#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ -#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ -#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ -#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ -#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ -#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ - -/* - * R97 (0x61) - Analogue HP (2) - */ -#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ -#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ -#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ -#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ -#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ -#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ -#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ -#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ -#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ -#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ -#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ -#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ -#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ -#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ -#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ -#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ -#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ -#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ -#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ -#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ -#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ -#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ -#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ -#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ - -/* - * R256 (0x100) - Chip Revision - */ -#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ -#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ -#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ - -/* - * R257 (0x101) - Control Interface (1) - */ -#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */ -#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */ -#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */ -#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */ -#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */ -#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ -#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ -#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ -#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */ -#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ -#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ -#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ -#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */ -#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */ -#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */ -#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */ -#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */ -#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */ -#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */ -#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */ - -/* - * R258 (0x102) - Control Interface (2) - */ -#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */ -#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */ -#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */ -#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */ - -/* - * R272 (0x110) - Write Sequencer Ctrl (1) - */ -#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */ -#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ -#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ -#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ -#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ -#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ -#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ -#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ -#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */ -#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */ -#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */ -#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */ -#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ -#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ -#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ - -/* - * R273 (0x111) - Write Sequencer Ctrl (2) - */ -#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ -#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ -#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ -#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ -#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ -#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ -#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ - -/* - * R512 (0x200) - AIF1 Clocking (1) - */ -#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ -#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ -#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ -#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ -#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ -#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ -#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ -#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ -#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ -#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ -#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ -#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ -#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ -#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ -#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ - -/* - * R513 (0x201) - AIF1 Clocking (2) - */ -#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ -#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ -#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ -#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ -#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ -#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ - -/* - * R516 (0x204) - AIF2 Clocking (1) - */ -#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ -#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ -#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ -#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ -#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ -#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ -#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ -#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ -#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ -#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ -#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ -#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ -#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ -#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ -#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ - -/* - * R517 (0x205) - AIF2 Clocking (2) - */ -#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ -#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ -#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ -#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ -#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ -#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ - -/* - * R520 (0x208) - Clocking (1) - */ -#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */ -#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ -#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ -#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ -#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */ -#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ -#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ -#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ -#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ -#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ -#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ -#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ -#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ -#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ -#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ -#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ -#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ -#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ -#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ -#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ -#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ -#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ -#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ -#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ - -/* - * R521 (0x209) - Clocking (2) - */ -#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ -#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ -#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ -#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ -#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ -#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ -#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ -#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ -#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ - -/* - * R528 (0x210) - AIF1 Rate - */ -#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ -#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ -#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ -#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ -#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ -#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ - -/* - * R529 (0x211) - AIF2 Rate - */ -#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ -#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ -#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ -#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ -#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ -#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ - -/* - * R530 (0x212) - Rate Status - */ -#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ -#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ -#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ - -/* - * R544 (0x220) - FLL1 Control (1) - */ -#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ -#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ -#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ -#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ -#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */ -#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ -#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ -#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ - -/* - * R545 (0x221) - FLL1 Control (2) - */ -#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ -#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ -#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ -#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ -#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ -#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ -#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ -#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ -#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ - -/* - * R546 (0x222) - FLL1 Control (3) - */ -#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ -#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ -#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ - -/* - * R547 (0x223) - FLL1 Control (4) - */ -#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ -#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ -#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ -#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ -#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ -#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ - -/* - * R548 (0x224) - FLL1 Control (5) - */ -#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ -#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ -#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ -#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ -#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ -#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ -#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ -#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ -#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ -#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ - -/* - * R576 (0x240) - FLL2 Control (1) - */ -#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ -#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ -#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ -#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ -#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */ -#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ -#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ -#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ - -/* - * R577 (0x241) - FLL2 Control (2) - */ -#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ -#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ -#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ -#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ -#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ -#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ -#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ -#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ -#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ - -/* - * R578 (0x242) - FLL2 Control (3) - */ -#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ -#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ -#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ - -/* - * R579 (0x243) - FLL2 Control (4) - */ -#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ -#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ -#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ -#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ -#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ -#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ - -/* - * R580 (0x244) - FLL2 Control (5) - */ -#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ -#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ -#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ -#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ -#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ -#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ -#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ -#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ -#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ -#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ -#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ - -/* - * R768 (0x300) - AIF1 Control (1) - */ -#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ -#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ -#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ -#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ -#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ -#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ -#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ -#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ -#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ -#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ -#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ -#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ -#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ -#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ -#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ -#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ -#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ -#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ -#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ -#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ -#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ -#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ -#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ -#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ -#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ -#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ - -/* - * R769 (0x301) - AIF1 Control (2) - */ -#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ -#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ -#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ -#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ -#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ -#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ -#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ -#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ -#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ -#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ -#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ -#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ -#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ -#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ -#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ -#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ -#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ -#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ -#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ -#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ -#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ -#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ -#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ -#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ -#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ -#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ -#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ -#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ -#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ -#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ -#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ - -/* - * R770 (0x302) - AIF1 Master/Slave - */ -#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */ -#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ -#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ -#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ -#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */ -#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ -#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ -#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ -#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ -#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ -#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ -#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ -#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ -#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ -#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ -#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ - -/* - * R771 (0x303) - AIF1 BCLK - */ -#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */ -#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */ -#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */ - -/* - * R772 (0x304) - AIF1ADC LRCLK - */ -#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ -#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ -#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ -#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ -#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ -#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ -#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ - -/* - * R773 (0x305) - AIF1DAC LRCLK - */ -#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ -#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ -#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ -#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ -#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ -#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ -#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ - -/* - * R774 (0x306) - AIF1DAC Data - */ -#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ -#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ -#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ -#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ -#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ -#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ -#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ -#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ - -/* - * R775 (0x307) - AIF1ADC Data - */ -#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ -#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ -#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ -#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ -#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ -#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ -#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ -#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ - -/* - * R784 (0x310) - AIF2 Control (1) - */ -#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ -#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ -#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ -#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ -#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ -#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ -#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ -#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ -#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ -#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ -#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ -#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ -#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ -#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ -#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ -#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ -#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ -#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ -#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ -#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ -#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ -#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ -#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ -#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ -#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ -#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ -#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ -#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ -#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ -#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ - -/* - * R785 (0x311) - AIF2 Control (2) - */ -#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ -#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ -#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ -#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ -#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ -#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ -#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ -#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ -#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ -#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ -#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ -#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ -#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ -#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ -#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ -#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ -#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ -#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ -#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ -#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ -#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ -#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ -#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ -#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ -#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ -#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ -#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ -#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ -#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ -#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ -#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ -#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ -#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ -#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ -#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ -#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ -#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ -#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ -#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ - -/* - * R786 (0x312) - AIF2 Master/Slave - */ -#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */ -#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ -#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ -#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ -#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */ -#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ -#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ -#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ -#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ -#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ -#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ -#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ -#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ -#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ -#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ -#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ - -/* - * R787 (0x313) - AIF2 BCLK - */ -#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */ -#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */ -#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */ - -/* - * R788 (0x314) - AIF2ADC LRCLK - */ -#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ -#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ -#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ -#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ -#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ -#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ -#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ - -/* - * R789 (0x315) - AIF2DAC LRCLK - */ -#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ -#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ -#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ -#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ -#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ -#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ -#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ - -/* - * R790 (0x316) - AIF2DAC Data - */ -#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ -#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ -#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ -#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ -#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ -#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ -#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ -#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ - -/* - * R791 (0x317) - AIF2ADC Data - */ -#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ -#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ -#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ -#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ -#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ -#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ -#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ -#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ - -/* - * R1024 (0x400) - AIF1 ADC1 Left Volume - */ -#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ -#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ -#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ - -/* - * R1025 (0x401) - AIF1 ADC1 Right Volume - */ -#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ -#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ -#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ -#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ - -/* - * R1026 (0x402) - AIF1 DAC1 Left Volume - */ -#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ -#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ -#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ - -/* - * R1027 (0x403) - AIF1 DAC1 Right Volume - */ -#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ -#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ -#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ -#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ - -/* - * R1028 (0x404) - AIF1 ADC2 Left Volume - */ -#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ -#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ -#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ - -/* - * R1029 (0x405) - AIF1 ADC2 Right Volume - */ -#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ -#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ -#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ -#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ - -/* - * R1030 (0x406) - AIF1 DAC2 Left Volume - */ -#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ -#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ -#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ - -/* - * R1031 (0x407) - AIF1 DAC2 Right Volume - */ -#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ -#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ -#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ -#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ - -/* - * R1040 (0x410) - AIF1 ADC1 Filters - */ -#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ -#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ -#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ -#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ -#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ -#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ -#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ -#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ -#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ -#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ -#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ -#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ -#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */ -#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */ -#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */ -#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */ -#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */ -#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */ -#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */ - -/* - * R1041 (0x411) - AIF1 ADC2 Filters - */ -#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ -#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ -#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ -#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ -#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ -#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ -#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ -#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ -#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */ -#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */ -#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */ -#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */ -#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */ -#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */ -#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */ - -/* - * R1056 (0x420) - AIF1 DAC1 Filters (1) - */ -#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ -#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ -#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ -#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ -#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ -#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ -#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ -#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ -#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ -#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ -#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ -#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ -#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ -#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ -#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ -#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ -#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ -#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ -#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ - -/* - * R1057 (0x421) - AIF1 DAC1 Filters (2) - */ -#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ -#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ -#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ -#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ - -/* - * R1058 (0x422) - AIF1 DAC2 Filters (1) - */ -#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ -#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ -#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ -#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ -#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ -#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ -#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ -#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ -#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ -#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ -#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ -#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ -#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ -#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ -#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ -#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ -#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ -#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ -#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ - -/* - * R1059 (0x423) - AIF1 DAC2 Filters (2) - */ -#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ -#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ -#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ -#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ -#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ - -/* - * R1088 (0x440) - AIF1 DRC1 (1) - */ -#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ -#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ -#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ -#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ -#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ -#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ -#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ -#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ -#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ -#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ -#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ -#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ -#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ -#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ -#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ -#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ -#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ -#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ -#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ -#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ -#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ -#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ -#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ -#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ -#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ -#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ -#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ -#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ -#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ -#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ -#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ -#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ - -/* - * R1089 (0x441) - AIF1 DRC1 (2) - */ -#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ -#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ -#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ -#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ -#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ -#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ -#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ -#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ -#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ - -/* - * R1090 (0x442) - AIF1 DRC1 (3) - */ -#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ -#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ -#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ -#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ -#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ -#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ - -/* - * R1091 (0x443) - AIF1 DRC1 (4) - */ -#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ -#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ -#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ - -/* - * R1092 (0x444) - AIF1 DRC1 (5) - */ -#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ -#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ -#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ - -/* - * R1104 (0x450) - AIF1 DRC2 (1) - */ -#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ -#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ -#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ -#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ -#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ -#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ -#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ -#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ -#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ -#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ -#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ -#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ -#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ -#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ -#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ -#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ -#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ -#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ -#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ -#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ -#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ -#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ -#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ -#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ -#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ -#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ -#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ -#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ -#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ -#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ -#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ -#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ -#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ -#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ - -/* - * R1105 (0x451) - AIF1 DRC2 (2) - */ -#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ -#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ -#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ -#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ -#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ -#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ -#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ -#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ -#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ -#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ - -/* - * R1106 (0x452) - AIF1 DRC2 (3) - */ -#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ -#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ -#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ -#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ -#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ -#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ -#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ -#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ -#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ -#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ - -/* - * R1107 (0x453) - AIF1 DRC2 (4) - */ -#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ -#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ -#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ -#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ - -/* - * R1108 (0x454) - AIF1 DRC2 (5) - */ -#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ -#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ -#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ -#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ - -/* - * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) - */ -#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ -#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ -#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ -#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ - -/* - * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) - */ -#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ - -/* - * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A - */ -#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ - -/* - * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B - */ -#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ - -/* - * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG - */ -#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ - -/* - * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A - */ -#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ - -/* - * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B - */ -#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ - -/* - * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C - */ -#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ - -/* - * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG - */ -#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ - -/* - * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A - */ -#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ - -/* - * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B - */ -#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ - -/* - * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C - */ -#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ - -/* - * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG - */ -#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ - -/* - * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A - */ -#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ - -/* - * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B - */ -#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ - -/* - * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C - */ -#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ - -/* - * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG - */ -#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ - -/* - * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A - */ -#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ - -/* - * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B - */ -#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ - -/* - * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG - */ -#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ -#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ - -/* - * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) - */ -#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ -#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ -#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ -#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ - -/* - * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) - */ -#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ - -/* - * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A - */ -#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ - -/* - * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B - */ -#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ - -/* - * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG - */ -#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ - -/* - * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A - */ -#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ - -/* - * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B - */ -#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ - -/* - * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C - */ -#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ - -/* - * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG - */ -#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ - -/* - * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A - */ -#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ - -/* - * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B - */ -#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ - -/* - * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C - */ -#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ - -/* - * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG - */ -#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ - -/* - * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A - */ -#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ - -/* - * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B - */ -#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ - -/* - * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C - */ -#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ - -/* - * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG - */ -#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ - -/* - * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A - */ -#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ - -/* - * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B - */ -#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ - -/* - * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG - */ -#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ -#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ - -/* - * R1280 (0x500) - AIF2 ADC Left Volume - */ -#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ -#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ -#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ -#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ - -/* - * R1281 (0x501) - AIF2 ADC Right Volume - */ -#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ -#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ -#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ -#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ -#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ - -/* - * R1282 (0x502) - AIF2 DAC Left Volume - */ -#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ -#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ -#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ -#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ - -/* - * R1283 (0x503) - AIF2 DAC Right Volume - */ -#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ -#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ -#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ -#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ -#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ - -/* - * R1296 (0x510) - AIF2 ADC Filters - */ -#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ -#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ -#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ -#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ -#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ -#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ -#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ -#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ -#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ -#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ -#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ -#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ -#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */ -#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */ -#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */ -#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */ -#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */ -#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */ -#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */ - -/* - * R1312 (0x520) - AIF2 DAC Filters (1) - */ -#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ -#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ -#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ -#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ -#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ -#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ -#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ -#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ -#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ -#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ -#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ -#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ -#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ -#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ -#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ -#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ -#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ -#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ -#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ - -/* - * R1313 (0x521) - AIF2 DAC Filters (2) - */ -#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ -#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ -#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ -#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ -#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ -#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ -#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ - -/* - * R1344 (0x540) - AIF2 DRC (1) - */ -#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ -#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ -#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ -#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ -#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ -#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ -#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ -#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ -#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ -#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ -#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ -#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ -#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ -#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ -#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ -#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ -#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ -#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ -#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ -#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ -#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ -#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ -#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ -#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ -#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ -#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ -#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ -#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ -#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ -#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ -#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ -#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ -#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ -#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ -#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ -#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ -#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ -#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ -#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ -#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ - -/* - * R1345 (0x541) - AIF2 DRC (2) - */ -#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ -#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ -#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ -#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ -#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ -#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ -#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ -#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ -#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ -#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ -#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ -#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ - -/* - * R1346 (0x542) - AIF2 DRC (3) - */ -#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ -#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ -#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ -#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ -#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ -#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ -#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ -#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ -#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ -#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ -#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ -#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ -#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ -#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ -#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ -#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ -#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ -#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ - -/* - * R1347 (0x543) - AIF2 DRC (4) - */ -#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ -#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ -#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ -#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ -#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ -#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ - -/* - * R1348 (0x544) - AIF2 DRC (5) - */ -#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ -#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ -#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ -#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ -#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ -#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ - -/* - * R1408 (0x580) - AIF2 EQ Gains (1) - */ -#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ -#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ -#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ -#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ -#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ -#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ - -/* - * R1409 (0x581) - AIF2 EQ Gains (2) - */ -#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ -#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ -#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ - -/* - * R1410 (0x582) - AIF2 EQ Band 1 A - */ -#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ - -/* - * R1411 (0x583) - AIF2 EQ Band 1 B - */ -#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ - -/* - * R1412 (0x584) - AIF2 EQ Band 1 PG - */ -#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ - -/* - * R1413 (0x585) - AIF2 EQ Band 2 A - */ -#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ - -/* - * R1414 (0x586) - AIF2 EQ Band 2 B - */ -#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ - -/* - * R1415 (0x587) - AIF2 EQ Band 2 C - */ -#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ - -/* - * R1416 (0x588) - AIF2 EQ Band 2 PG - */ -#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ - -/* - * R1417 (0x589) - AIF2 EQ Band 3 A - */ -#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ - -/* - * R1418 (0x58A) - AIF2 EQ Band 3 B - */ -#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ - -/* - * R1419 (0x58B) - AIF2 EQ Band 3 C - */ -#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ - -/* - * R1420 (0x58C) - AIF2 EQ Band 3 PG - */ -#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ - -/* - * R1421 (0x58D) - AIF2 EQ Band 4 A - */ -#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ - -/* - * R1422 (0x58E) - AIF2 EQ Band 4 B - */ -#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ - -/* - * R1423 (0x58F) - AIF2 EQ Band 4 C - */ -#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ - -/* - * R1424 (0x590) - AIF2 EQ Band 4 PG - */ -#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ - -/* - * R1425 (0x591) - AIF2 EQ Band 5 A - */ -#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ - -/* - * R1426 (0x592) - AIF2 EQ Band 5 B - */ -#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ - -/* - * R1427 (0x593) - AIF2 EQ Band 5 PG - */ -#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ -#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ - -/* - * R1536 (0x600) - DAC1 Mixer Volumes - */ -#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ -#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ -#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ -#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ - -/* - * R1537 (0x601) - DAC1 Left Mixer Routing - */ -#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ -#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ -#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ -#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ -#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ -#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ -#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ -#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ -#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ -#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ -#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ -#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ -#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ -#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ -#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ -#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ -#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ -#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ -#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ -#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ - -/* - * R1538 (0x602) - DAC1 Right Mixer Routing - */ -#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ -#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ -#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ -#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ -#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ -#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ -#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ -#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ -#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ -#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ -#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ -#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ -#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ -#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ -#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ -#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ -#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ -#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ -#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ -#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ - -/* - * R1539 (0x603) - DAC2 Mixer Volumes - */ -#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ -#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ -#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ -#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ - -/* - * R1540 (0x604) - DAC2 Left Mixer Routing - */ -#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ -#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ -#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ -#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ -#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ -#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ -#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ -#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ -#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ -#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ -#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ -#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ -#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ -#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ -#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ -#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ -#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ -#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ -#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ -#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ - -/* - * R1541 (0x605) - DAC2 Right Mixer Routing - */ -#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ -#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ -#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ -#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ -#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ -#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ -#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ -#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ -#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ -#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ -#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ -#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ -#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ -#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ -#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ -#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ -#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ -#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ -#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ -#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ - -/* - * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing - */ -#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ -#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ -#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ -#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ -#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ -#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ -#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ -#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ - -/* - * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing - */ -#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ -#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ -#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ -#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ -#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ -#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ -#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ -#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ - -/* - * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing - */ -#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ -#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ -#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ -#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ -#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ -#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ -#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ -#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ - -/* - * R1545 (0x609) - AIF1 ADC2 Right mixer Routing - */ -#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ -#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ -#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ -#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ -#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ -#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ -#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ -#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ - -/* - * R1552 (0x610) - DAC Softmute - */ -#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ -#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ -#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ -#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ -#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ -#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ -#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ -#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ - -/* - * R1568 (0x620) - Oversampling - */ -#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */ -#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ -#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ -#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ -#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */ -#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ -#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ -#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ - -/* - * R1569 (0x621) - Sidetone - */ -#define WM8995_ST_LPF 0x1000 /* ST_LPF */ -#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */ -#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */ -#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */ -#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ -#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ -#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ -#define WM8995_ST_HPF 0x0040 /* ST_HPF */ -#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */ -#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */ -#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */ -#define WM8995_STR_SEL 0x0002 /* STR_SEL */ -#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */ -#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */ -#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */ -#define WM8995_STL_SEL 0x0001 /* STL_SEL */ -#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */ -#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */ -#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */ - -/* - * R1792 (0x700) - GPIO 1 - */ -#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */ -#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */ -#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */ -#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */ -#define WM8995_GP1_PU 0x4000 /* GP1_PU */ -#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */ -#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */ -#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */ -#define WM8995_GP1_PD 0x2000 /* GP1_PD */ -#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */ -#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */ -#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */ -#define WM8995_GP1_POL 0x0400 /* GP1_POL */ -#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */ -#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */ -#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */ -#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ -#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ -#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ -#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ -#define WM8995_GP1_DB 0x0100 /* GP1_DB */ -#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */ -#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */ -#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */ -#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */ -#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */ -#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */ -#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */ -#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */ -#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */ -#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */ - -/* - * R1793 (0x701) - GPIO 2 - */ -#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */ -#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */ -#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */ -#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */ -#define WM8995_GP2_PU 0x4000 /* GP2_PU */ -#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */ -#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */ -#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */ -#define WM8995_GP2_PD 0x2000 /* GP2_PD */ -#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */ -#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */ -#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */ -#define WM8995_GP2_POL 0x0400 /* GP2_POL */ -#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */ -#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */ -#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */ -#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ -#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ -#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ -#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ -#define WM8995_GP2_DB 0x0100 /* GP2_DB */ -#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */ -#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */ -#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */ -#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */ -#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */ -#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */ -#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */ -#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ -#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ -#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ - -/* - * R1794 (0x702) - GPIO 3 - */ -#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */ -#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */ -#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */ -#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */ -#define WM8995_GP3_PU 0x4000 /* GP3_PU */ -#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */ -#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */ -#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */ -#define WM8995_GP3_PD 0x2000 /* GP3_PD */ -#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */ -#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */ -#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */ -#define WM8995_GP3_POL 0x0400 /* GP3_POL */ -#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */ -#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */ -#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */ -#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ -#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ -#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ -#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ -#define WM8995_GP3_DB 0x0100 /* GP3_DB */ -#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */ -#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */ -#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */ -#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */ -#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */ -#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */ -#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */ -#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ -#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ -#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ - -/* - * R1795 (0x703) - GPIO 4 - */ -#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */ -#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */ -#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */ -#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */ -#define WM8995_GP4_PU 0x4000 /* GP4_PU */ -#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */ -#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */ -#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */ -#define WM8995_GP4_PD 0x2000 /* GP4_PD */ -#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */ -#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */ -#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */ -#define WM8995_GP4_POL 0x0400 /* GP4_POL */ -#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */ -#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */ -#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */ -#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ -#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ -#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ -#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ -#define WM8995_GP4_DB 0x0100 /* GP4_DB */ -#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */ -#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */ -#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */ -#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */ -#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */ -#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */ -#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */ -#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */ -#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */ -#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */ - -/* - * R1796 (0x704) - GPIO 5 - */ -#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */ -#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */ -#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */ -#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */ -#define WM8995_GP5_PU 0x4000 /* GP5_PU */ -#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */ -#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */ -#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */ -#define WM8995_GP5_PD 0x2000 /* GP5_PD */ -#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */ -#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */ -#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */ -#define WM8995_GP5_POL 0x0400 /* GP5_POL */ -#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */ -#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */ -#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */ -#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ -#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ -#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ -#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ -#define WM8995_GP5_DB 0x0100 /* GP5_DB */ -#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */ -#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */ -#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */ -#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */ -#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */ -#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */ -#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */ -#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ -#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ -#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ - -/* - * R1797 (0x705) - GPIO 6 - */ -#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */ -#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */ -#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */ -#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */ -#define WM8995_GP6_PU 0x4000 /* GP6_PU */ -#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */ -#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */ -#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */ -#define WM8995_GP6_PD 0x2000 /* GP6_PD */ -#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */ -#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */ -#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */ -#define WM8995_GP6_POL 0x0400 /* GP6_POL */ -#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */ -#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */ -#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */ -#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ -#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ -#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ -#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ -#define WM8995_GP6_DB 0x0100 /* GP6_DB */ -#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */ -#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */ -#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */ -#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */ -#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */ -#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */ -#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */ -#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ -#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ -#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ - -/* - * R1798 (0x706) - GPIO 7 - */ -#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */ -#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */ -#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */ -#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */ -#define WM8995_GP7_PU 0x4000 /* GP7_PU */ -#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */ -#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */ -#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */ -#define WM8995_GP7_PD 0x2000 /* GP7_PD */ -#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */ -#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */ -#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */ -#define WM8995_GP7_POL 0x0400 /* GP7_POL */ -#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */ -#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */ -#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */ -#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */ -#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */ -#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */ -#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */ -#define WM8995_GP7_DB 0x0100 /* GP7_DB */ -#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */ -#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */ -#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */ -#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */ -#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */ -#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */ -#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */ -#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */ -#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */ -#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */ - -/* - * R1799 (0x707) - GPIO 8 - */ -#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */ -#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */ -#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */ -#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */ -#define WM8995_GP8_PU 0x4000 /* GP8_PU */ -#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */ -#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */ -#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */ -#define WM8995_GP8_PD 0x2000 /* GP8_PD */ -#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */ -#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */ -#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */ -#define WM8995_GP8_POL 0x0400 /* GP8_POL */ -#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */ -#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */ -#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */ -#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */ -#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */ -#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */ -#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */ -#define WM8995_GP8_DB 0x0100 /* GP8_DB */ -#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */ -#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */ -#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */ -#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */ -#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */ -#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */ -#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */ -#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */ -#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */ -#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */ - -/* - * R1800 (0x708) - GPIO 9 - */ -#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */ -#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */ -#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */ -#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */ -#define WM8995_GP9_PU 0x4000 /* GP9_PU */ -#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */ -#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */ -#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */ -#define WM8995_GP9_PD 0x2000 /* GP9_PD */ -#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */ -#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */ -#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */ -#define WM8995_GP9_POL 0x0400 /* GP9_POL */ -#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */ -#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */ -#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */ -#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */ -#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */ -#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */ -#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */ -#define WM8995_GP9_DB 0x0100 /* GP9_DB */ -#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */ -#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */ -#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */ -#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */ -#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */ -#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */ -#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */ -#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */ -#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */ -#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */ - -/* - * R1801 (0x709) - GPIO 10 - */ -#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */ -#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */ -#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */ -#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */ -#define WM8995_GP10_PU 0x4000 /* GP10_PU */ -#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */ -#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */ -#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */ -#define WM8995_GP10_PD 0x2000 /* GP10_PD */ -#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */ -#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */ -#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */ -#define WM8995_GP10_POL 0x0400 /* GP10_POL */ -#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */ -#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */ -#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */ -#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */ -#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */ -#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */ -#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */ -#define WM8995_GP10_DB 0x0100 /* GP10_DB */ -#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */ -#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */ -#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */ -#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */ -#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */ -#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */ -#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */ -#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */ -#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */ -#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */ - -/* - * R1802 (0x70A) - GPIO 11 - */ -#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */ -#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */ -#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */ -#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */ -#define WM8995_GP11_PU 0x4000 /* GP11_PU */ -#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */ -#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */ -#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */ -#define WM8995_GP11_PD 0x2000 /* GP11_PD */ -#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */ -#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */ -#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */ -#define WM8995_GP11_POL 0x0400 /* GP11_POL */ -#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */ -#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */ -#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */ -#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */ -#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */ -#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */ -#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */ -#define WM8995_GP11_DB 0x0100 /* GP11_DB */ -#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */ -#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */ -#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */ -#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */ -#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */ -#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */ -#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */ -#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */ -#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */ -#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */ - -/* - * R1803 (0x70B) - GPIO 12 - */ -#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */ -#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */ -#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */ -#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */ -#define WM8995_GP12_PU 0x4000 /* GP12_PU */ -#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */ -#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */ -#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */ -#define WM8995_GP12_PD 0x2000 /* GP12_PD */ -#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */ -#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */ -#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */ -#define WM8995_GP12_POL 0x0400 /* GP12_POL */ -#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */ -#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */ -#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */ -#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */ -#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */ -#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */ -#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */ -#define WM8995_GP12_DB 0x0100 /* GP12_DB */ -#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */ -#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */ -#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */ -#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */ -#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */ -#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */ -#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */ -#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */ -#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */ -#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */ - -/* - * R1804 (0x70C) - GPIO 13 - */ -#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */ -#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */ -#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */ -#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */ -#define WM8995_GP13_PU 0x4000 /* GP13_PU */ -#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */ -#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */ -#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */ -#define WM8995_GP13_PD 0x2000 /* GP13_PD */ -#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */ -#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */ -#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */ -#define WM8995_GP13_POL 0x0400 /* GP13_POL */ -#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */ -#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */ -#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */ -#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */ -#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */ -#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */ -#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */ -#define WM8995_GP13_DB 0x0100 /* GP13_DB */ -#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */ -#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */ -#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */ -#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */ -#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */ -#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */ -#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */ -#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */ -#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */ -#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */ - -/* - * R1805 (0x70D) - GPIO 14 - */ -#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */ -#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */ -#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */ -#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */ -#define WM8995_GP14_PU 0x4000 /* GP14_PU */ -#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */ -#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */ -#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */ -#define WM8995_GP14_PD 0x2000 /* GP14_PD */ -#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */ -#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */ -#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */ -#define WM8995_GP14_POL 0x0400 /* GP14_POL */ -#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */ -#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */ -#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */ -#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */ -#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */ -#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */ -#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */ -#define WM8995_GP14_DB 0x0100 /* GP14_DB */ -#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */ -#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */ -#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */ -#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */ -#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */ -#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */ -#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */ -#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */ -#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */ -#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */ - -/* - * R1824 (0x720) - Pull Control (1) - */ -#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */ -#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */ -#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */ -#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ -#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ -#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ -#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ -#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ -#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ -#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ -#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ -#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ -#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */ -#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ -#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ -#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ -#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */ -#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ -#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ -#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ -#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */ -#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ -#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ -#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ -#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */ -#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ -#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ -#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ -#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */ -#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ -#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ -#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ -#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */ -#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ -#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ -#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ -#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ -#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ -#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ -#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ -#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ -#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ -#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ -#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ -#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */ -#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ -#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ -#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ -#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */ -#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ -#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ -#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ - -/* - * R1825 (0x721) - Pull Control (2) - */ -#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ -#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ -#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ -#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ -#define WM8995_MODE_PD 0x0004 /* MODE_PD */ -#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */ -#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */ -#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */ -#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */ -#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */ -#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */ -#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ - -/* - * R1840 (0x730) - Interrupt Status 1 - */ -#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */ -#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */ -#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */ -#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */ -#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */ -#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */ -#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */ -#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */ -#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */ -#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */ -#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */ -#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */ -#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */ -#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */ -#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */ -#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */ -#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */ -#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */ -#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */ -#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */ -#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */ -#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */ -#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */ -#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */ -#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */ -#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */ -#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */ -#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */ -#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */ -#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */ -#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */ -#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */ -#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */ -#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */ -#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */ -#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */ -#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */ -#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */ -#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */ -#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */ -#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */ -#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */ -#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */ -#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */ -#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */ -#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */ -#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */ -#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */ -#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */ -#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */ -#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */ -#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */ -#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */ -#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */ -#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */ -#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */ - -/* - * R1841 (0x731) - Interrupt Status 2 - */ -#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ -#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ -#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ -#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ -#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ -#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ -#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ -#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ -#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ -#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ -#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ -#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ -#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ -#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ -#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ -#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ -#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */ -#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */ -#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */ -#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ -#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */ -#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */ -#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */ -#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ -#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */ -#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */ -#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */ -#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ -#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */ -#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */ -#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */ -#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ -#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */ -#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */ -#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */ -#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ -#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ -#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ -#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ -#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ -#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ -#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ -#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ -#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ -#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ -#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ -#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ -#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ -#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */ -#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */ -#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */ -#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */ - -/* - * R1842 (0x732) - Interrupt Raw Status 2 - */ -#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ -#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ -#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ -#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ -#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ -#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ -#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ -#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ -#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ -#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ -#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ -#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ -#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ -#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ -#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ -#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ -#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */ -#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */ -#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */ -#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ -#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */ -#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */ -#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */ -#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ -#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */ -#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */ -#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */ -#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ -#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */ -#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */ -#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */ -#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ -#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */ -#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */ -#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */ -#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ -#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ -#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ -#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ -#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ -#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ -#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ -#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ -#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ - -/* - * R1848 (0x738) - Interrupt Status 1 Mask - */ -#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ -#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ -#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ -#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ -#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ -#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ -#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ -#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ -#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ -#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ -#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ -#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ -#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ -#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ -#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ -#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ -#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ -#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ -#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ -#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ -#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ -#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ -#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ -#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ -#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ -#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ -#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ -#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ -#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ -#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ -#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ -#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ -#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ -#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ -#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ -#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ -#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ -#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ -#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ -#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ -#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ -#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ -#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ -#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ -#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ -#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ -#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ -#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ -#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ -#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ -#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ -#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ -#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ -#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ -#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ -#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ - -/* - * R1849 (0x739) - Interrupt Status 2 Mask - */ -#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ -#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ -#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ -#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ -#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ -#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ -#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ -#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ -#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ -#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ -#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ -#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ -#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ -#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ -#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ -#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ -#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ -#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ -#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */ -#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */ -#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ -#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */ -#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */ -#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */ -#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ -#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */ -#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */ -#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */ -#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ -#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ -#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ -#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ -#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ -#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ -#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ -#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ -#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ -#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ -#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ -#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ -#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ -#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ -#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ -#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ -#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ - -/* - * R1856 (0x740) - Interrupt Control - */ -#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */ -#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */ -#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */ -#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */ - -/* - * R2048 (0x800) - Left PDM Speaker 1 - */ -#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */ -#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */ -#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */ -#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */ -#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */ -#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */ -#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */ -#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ -#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */ -#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */ -#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */ -#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */ -#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */ -#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */ -#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */ - -/* - * R2049 (0x801) - Right PDM Speaker 1 - */ -#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */ -#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */ -#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */ -#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */ -#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */ -#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */ -#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */ -#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ -#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */ -#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */ -#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */ -#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */ -#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */ -#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */ -#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */ - -/* - * R2050 (0x802) - PDM Speaker 1 Mute Sequence - */ -#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ -#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ -#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ - -/* - * R2056 (0x808) - Left PDM Speaker 2 - */ -#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */ -#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */ -#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */ -#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */ -#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */ -#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */ -#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */ -#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ -#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */ -#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */ -#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */ -#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */ -#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */ -#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */ -#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */ - -/* - * R2057 (0x809) - Right PDM Speaker 2 - */ -#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */ -#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */ -#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */ -#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */ -#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */ -#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */ -#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */ -#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ -#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */ -#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */ -#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */ -#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */ -#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */ -#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */ -#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */ - -/* - * R2058 (0x80A) - PDM Speaker 2 Mute Sequence - */ -#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ -#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ -#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ - -#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ -{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ - .info = snd_soc_info_volsw, \ - .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \ - .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \ -} - -struct wm8995_reg_access { - u16 read; - u16 write; - u16 vol; -}; - -/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ -enum clk_src { - WM8995_SYSCLK_MCLK1 = 1, - WM8995_SYSCLK_MCLK2, - WM8995_SYSCLK_FLL1, - WM8995_SYSCLK_FLL2, - WM8995_SYSCLK_OPCLK -}; - -#define WM8995_FLL1 1 -#define WM8995_FLL2 2 - -#define WM8995_FLL_SRC_MCLK1 1 -#define WM8995_FLL_SRC_MCLK2 2 -#define WM8995_FLL_SRC_LRCLK 3 -#define WM8995_FLL_SRC_BCLK 4 - -#endif /* _WM8995_H */ diff --git a/trunk/sound/soc/codecs/wm9081.c b/trunk/sound/soc/codecs/wm9081.c index 43825b2102a5..e5055b28c638 100644 --- a/trunk/sound/soc/codecs/wm9081.c +++ b/trunk/sound/soc/codecs/wm9081.c @@ -157,6 +157,7 @@ static struct { struct wm9081_priv { enum snd_soc_control_type control_type; void *control_data; + u16 reg_cache[WM9081_MAX_REGISTER + 1]; int sysclk_source; int mclk_rate; int sysclk_rate; @@ -1338,7 +1339,6 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c, return -ENOMEM; i2c_set_clientdata(i2c, wm9081); - wm9081->control_type = SND_SOC_I2C; wm9081->control_data = i2c; ret = snd_soc_register_codec(&i2c->dev, diff --git a/trunk/sound/soc/codecs/wm9090.c b/trunk/sound/soc/codecs/wm9090.c index a788c4297046..7ba5807cac36 100644 --- a/trunk/sound/soc/codecs/wm9090.c +++ b/trunk/sound/soc/codecs/wm9090.c @@ -140,6 +140,7 @@ static const u16 wm9090_reg_defaults[] = { /* This struct is used to save the context */ struct wm9090_priv { struct mutex mutex; + u16 reg_cache[WM9090_MAX_REGISTER + 1]; struct wm9090_platform_data pdata; void *control_data; }; @@ -551,7 +552,6 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec, static int wm9090_probe(struct snd_soc_codec *codec) { struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec); - u16 *reg_cache = codec->reg_cache; int ret; codec->control_data = wm9090->control_data; @@ -576,22 +576,22 @@ static int wm9090_probe(struct snd_soc_codec *codec) /* Configure some defaults; they will be written out when we * bring the bias up. */ - reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU + wm9090->reg_cache[WM9090_IN1_LINE_INPUT_A_VOLUME] |= WM9090_IN1_VU | WM9090_IN1A_ZC; - reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU + wm9090->reg_cache[WM9090_IN1_LINE_INPUT_B_VOLUME] |= WM9090_IN1_VU | WM9090_IN1B_ZC; - reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU + wm9090->reg_cache[WM9090_IN2_LINE_INPUT_A_VOLUME] |= WM9090_IN2_VU | WM9090_IN2A_ZC; - reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU + wm9090->reg_cache[WM9090_IN2_LINE_INPUT_B_VOLUME] |= WM9090_IN2_VU | WM9090_IN2B_ZC; - reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |= + wm9090->reg_cache[WM9090_SPEAKER_VOLUME_LEFT] |= WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC; - reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |= + wm9090->reg_cache[WM9090_LEFT_OUTPUT_VOLUME] |= WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC; - reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |= + wm9090->reg_cache[WM9090_RIGHT_OUTPUT_VOLUME] |= WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC; - reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA; + wm9090->reg_cache[WM9090_CLOCKING_1] |= WM9090_TOCLK_ENA; wm9090_set_bias_level(codec, SND_SOC_BIAS_STANDBY); diff --git a/trunk/sound/soc/davinci/davinci-evm.c b/trunk/sound/soc/davinci/davinci-evm.c index 0c2d6bacc681..24b031e26342 100644 --- a/trunk/sound/soc/davinci/davinci-evm.c +++ b/trunk/sound/soc/davinci/davinci-evm.c @@ -26,6 +26,7 @@ #include #include +#include "../codecs/tlv320aic3x.h" #include "davinci-pcm.h" #include "davinci-i2s.h" #include "davinci-mcasp.h" diff --git a/trunk/sound/soc/omap/n810.c b/trunk/sound/soc/omap/n810.c index 83d213bfd3d1..fe215f3e8afc 100644 --- a/trunk/sound/soc/omap/n810.c +++ b/trunk/sound/soc/omap/n810.c @@ -35,6 +35,7 @@ #include "omap-mcbsp.h" #include "omap-pcm.h" +#include "../codecs/tlv320aic3x.h" #define N810_HEADSET_AMP_GPIO 10 #define N810_SPEAKER_AMP_GPIO 101 diff --git a/trunk/sound/soc/omap/omap-mcbsp.c b/trunk/sound/soc/omap/omap-mcbsp.c index 7e84f24b9a88..d203f4da18a0 100644 --- a/trunk/sound/soc/omap/omap-mcbsp.c +++ b/trunk/sound/soc/omap/omap-mcbsp.c @@ -102,6 +102,17 @@ static const int omap24xx_dma_reqs[][2] = { static const int omap24xx_dma_reqs[][2] = {}; #endif +#if defined(CONFIG_ARCH_OMAP4) +static const int omap44xx_dma_reqs[][2] = { + { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX }, + { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX }, + { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX }, + { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX }, +}; +#else +static const int omap44xx_dma_reqs[][2] = {}; +#endif + #if defined(CONFIG_ARCH_OMAP2420) static const unsigned long omap2420_mcbsp_port[][2] = { { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, @@ -147,6 +158,21 @@ static const unsigned long omap34xx_mcbsp_port[][2] = { static const unsigned long omap34xx_mcbsp_port[][2] = {}; #endif +#if defined(CONFIG_ARCH_OMAP4) +static const unsigned long omap44xx_mcbsp_port[][2] = { + { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, + OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, + { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, + OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, + { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, + OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, + { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, + OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, +}; +#else +static const unsigned long omap44xx_mcbsp_port[][2] = {}; +#endif + static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; @@ -224,7 +250,7 @@ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) */ - if (cpu_is_omap343x()) { + if (cpu_is_omap343x() || cpu_is_omap44xx()) { /* * Rule for the buffer size. We should not allow * smaller buffer than the FIFO size to avoid underruns @@ -332,6 +358,9 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, } else if (cpu_is_omap343x()) { dma = omap24xx_dma_reqs[bus_id][substream->stream]; port = omap34xx_mcbsp_port[bus_id][substream->stream]; + } else if (cpu_is_omap44xx()) { + dma = omap44xx_dma_reqs[bus_id][substream->stream]; + port = omap44xx_mcbsp_port[bus_id][substream->stream]; } else { return -ENODEV; } @@ -498,11 +527,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, regs->spcr2 |= XINTM(3) | FREE; regs->spcr1 |= RINTM(3); /* RFIG and XFIG are not defined in 34xx */ - if (!cpu_is_omap34xx()) { + if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) { regs->rcr2 |= RFIG; regs->xcr2 |= XFIG; } - if (cpu_is_omap2430() || cpu_is_omap34xx()) { + if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; } diff --git a/trunk/sound/soc/omap/omap-mcbsp.h b/trunk/sound/soc/omap/omap-mcbsp.h index ffdcc5abb7b9..110c106611d3 100644 --- a/trunk/sound/soc/omap/omap-mcbsp.h +++ b/trunk/sound/soc/omap/omap-mcbsp.h @@ -50,6 +50,10 @@ enum omap_mcbsp_div { #undef NUM_LINKS #define NUM_LINKS 3 #endif +#if defined(CONFIG_ARCH_OMAP4) +#undef NUM_LINKS +#define NUM_LINKS 4 +#endif #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) #undef NUM_LINKS #define NUM_LINKS 5 diff --git a/trunk/sound/soc/omap/rx51.c b/trunk/sound/soc/omap/rx51.c index 09fb0df8d416..150042a785d0 100644 --- a/trunk/sound/soc/omap/rx51.c +++ b/trunk/sound/soc/omap/rx51.c @@ -36,6 +36,7 @@ #include "omap-mcbsp.h" #include "omap-pcm.h" +#include "../codecs/tlv320aic3x.h" #define RX51_TVOUT_SEL_GPIO 40 #define RX51_JACK_DETECT_GPIO 177 diff --git a/trunk/sound/soc/s6000/s6105-ipcam.c b/trunk/sound/soc/s6000/s6105-ipcam.c index 5890e431852f..bf3f3f9165e4 100644 --- a/trunk/sound/soc/s6000/s6105-ipcam.c +++ b/trunk/sound/soc/s6000/s6105-ipcam.c @@ -21,6 +21,7 @@ #include +#include "../codecs/tlv320aic3x.h" #include "s6000-pcm.h" #include "s6000-i2s.h" diff --git a/trunk/sound/soc/samsung/Kconfig b/trunk/sound/soc/samsung/Kconfig index a6a6b5fa2f2f..67cdad4ee535 100644 --- a/trunk/sound/soc/samsung/Kconfig +++ b/trunk/sound/soc/samsung/Kconfig @@ -1,6 +1,6 @@ -config SND_SOC_SAMSUNG +config ASOC_SAMSUNG tristate "ASoC support for Samsung" - depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PV310 + depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 select S3C64XX_DMA if ARCH_S3C64XX select S3C2410_DMA if ARCH_S3C2410 help @@ -34,51 +34,43 @@ config SND_SAMSUNG_SPDIF config SND_SAMSUNG_I2S tristate -config SND_SOC_SAMSUNG_NEO1973_WM8753 +config ASOC_SAMSUNG_NEO1973_WM8753 tristate "SoC I2S Audio support for NEO1973 - WM8753" - depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA01 + depends on ASOC_SAMSUNG && MACH_NEO1973_GTA01 select SND_S3C24XX_I2S select SND_SOC_WM8753 help Say Y if you want to add support for SoC audio on smdk2440 with the WM8753. -config SND_SOC_SAMSUNG_NEO1973_GTA02_WM8753 +config ASOC_SAMSUNG_NEO1973_GTA02_WM8753 tristate "Audio support for the Openmoko Neo FreeRunner (GTA02)" - depends on SND_SOC_SAMSUNG && MACH_NEO1973_GTA02 + depends on ASOC_SAMSUNG && MACH_NEO1973_GTA02 select SND_S3C24XX_I2S select SND_SOC_WM8753 help This driver provides audio support for the Openmoko Neo FreeRunner smartphone. -config SND_SOC_SAMSUNG_JIVE_WM8750 +config ASOC_SAMSUNG_JIVE_WM8750 tristate "SoC I2S Audio support for Jive" - depends on SND_SOC_SAMSUNG && MACH_JIVE + depends on ASOC_SAMSUNG && MACH_JIVE select SND_SOC_WM8750 select SND_S3C2412_SOC_I2S help Sat Y if you want to add support for SoC audio on the Jive. -config SND_SOC_SAMSUNG_SMDK_WM8580 +config ASOC_SAMSUNG_SMDK_WM8580 tristate "SoC I2S Audio support for WM8580 on SMDK" - depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDK6440 || MACH_SMDK6450 || MACH_SMDK6442 || MACH_SMDKV210 || MACH_SMDKC110) + depends on ASOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100) select SND_SOC_WM8580 select SND_SAMSUNG_I2S help Say Y if you want to add support for SoC audio on the SMDKs. -config SND_SOC_SAMSUNG_SMDK_WM8994 - tristate "SoC I2S Audio support for WM8994 on SMDK" - depends on SND_SOC_SAMSUNG && (MACH_SMDKV310 || MACH_SMDKC210) - select SND_SOC_WM8994 - select SND_SAMSUNG_I2S - help - Say Y if you want to add support for SoC audio on the SMDKs. - -config SND_SOC_SAMSUNG_SMDK2443_WM9710 +config ASOC_SAMSUNG_SMDK2443_WM9710 tristate "SoC AC97 Audio support for SMDK2443 - WM9710" - depends on SND_SOC_SAMSUNG && MACH_SMDK2443 + depends on ASOC_SAMSUNG && MACH_SMDK2443 select S3C2410_DMA select AC97_BUS select SND_SOC_AC97_CODEC @@ -87,9 +79,9 @@ config SND_SOC_SAMSUNG_SMDK2443_WM9710 Say Y if you want to add support for SoC audio on smdk2443 with the WM9710. -config SND_SOC_SAMSUNG_LN2440SBC_ALC650 +config ASOC_SAMSUNG_LN2440SBC_ALC650 tristate "SoC AC97 Audio support for LN2440SBC - ALC650" - depends on SND_SOC_SAMSUNG && ARCH_S3C2410 + depends on ASOC_SAMSUNG && ARCH_S3C2410 select S3C2410_DMA select AC97_BUS select SND_SOC_AC97_CODEC @@ -98,74 +90,74 @@ config SND_SOC_SAMSUNG_LN2440SBC_ALC650 Say Y if you want to add support for SoC audio on ln2440sbc with the ALC650. -config SND_SOC_SAMSUNG_S3C24XX_UDA134X +config ASOC_SAMSUNG_S3C24XX_UDA134X tristate "SoC I2S Audio support UDA134X wired to a S3C24XX" - depends on SND_SOC_SAMSUNG && ARCH_S3C2410 + depends on ASOC_SAMSUNG && ARCH_S3C2410 select SND_S3C24XX_I2S select SND_SOC_L3 select SND_SOC_UDA134X -config SND_SOC_SAMSUNG_SIMTEC +config ASOC_SAMSUNG_SIMTEC tristate help Internal node for common S3C24XX/Simtec suppor -config SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23 +config ASOC_SAMSUNG_SIMTEC_TLV320AIC23 tristate "SoC I2S Audio support for TLV320AIC23 on Simtec boards" - depends on SND_SOC_SAMSUNG && ARCH_S3C2410 + depends on ASOC_SAMSUNG && ARCH_S3C2410 select SND_S3C24XX_I2S select SND_SOC_TLV320AIC23 - select SND_SOC_SAMSUNG_SIMTEC + select ASOC_SAMSUNG_SIMTEC -config SND_SOC_SAMSUNG_SIMTEC_HERMES +config ASOC_SAMSUNG_SIMTEC_HERMES tristate "SoC I2S Audio support for Simtec Hermes board" - depends on SND_SOC_SAMSUNG && ARCH_S3C2410 + depends on ASOC_SAMSUNG && ARCH_S3C2410 select SND_S3C24XX_I2S select SND_SOC_TLV320AIC3X - select SND_SOC_SAMSUNG_SIMTEC + select ASOC_SAMSUNG_SIMTEC -config SND_SOC_SAMSUNG_H1940_UDA1380 +config ASOC_SAMSUNG_H1940_UDA1380 tristate "Audio support for the HP iPAQ H1940" - depends on SND_SOC_SAMSUNG && ARCH_H1940 + depends on ASOC_SAMSUNG && ARCH_H1940 select SND_S3C24XX_I2S select SND_SOC_UDA1380 help This driver provides audio support for HP iPAQ h1940 PDA. -config SND_SOC_SAMSUNG_RX1950_UDA1380 +config ASOC_SAMSUNG_RX1950_UDA1380 tristate "Audio support for the HP iPAQ RX1950" - depends on SND_SOC_SAMSUNG && MACH_RX1950 + depends on ASOC_SAMSUNG && MACH_RX1950 select SND_S3C24XX_I2S select SND_SOC_UDA1380 help This driver provides audio support for HP iPAQ RX1950 PDA. -config SND_SOC_SAMSUNG_SMDK_WM9713 +config ASOC_SAMSUNG_SMDK_WM9713 tristate "SoC AC97 Audio support for SMDK with WM9713" - depends on SND_SOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDKV210 || MACH_SMDKC110 || MACH_SMDKV310 || MACH_SMDKC210) + depends on ASOC_SAMSUNG && (MACH_SMDK6410 || MACH_SMDKC100 || MACH_SMDKV210 || MACH_SMDKC110) select SND_SOC_WM9713 select SND_SAMSUNG_AC97 help Sat Y if you want to add support for SoC audio on the SMDK. -config SND_SOC_SMARTQ +config ASOC_SMARTQ tristate "SoC I2S Audio support for SmartQ board" - depends on SND_SOC_SAMSUNG && MACH_SMARTQ + depends on ASOC_SAMSUNG && MACH_SMARTQ select SND_SAMSUNG_I2S select SND_SOC_WM8750 -config SND_SOC_GONI_AQUILA_WM8994 +config ASOC_GONI_AQUILA_WM8994 tristate "SoC I2S Audio support for AQUILA/GONI - WM8994" - depends on SND_SOC_SAMSUNG && (MACH_GONI || MACH_AQUILA) + depends on ASOC_SAMSUNG && (MACH_GONI || MACH_AQUILA) select SND_SAMSUNG_I2S select SND_SOC_WM8994 help Say Y if you want to add support for SoC audio on goni or aquila with the WM8994. -config SND_SOC_SAMSUNG_SMDK_SPDIF +config ASOC_SAMSUNG_SMDK_SPDIF tristate "SoC S/PDIF Audio support for SMDK" - depends on SND_SOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210) + depends on ASOC_SAMSUNG && (MACH_SMDKC100 || MACH_SMDKC110 || MACH_SMDKV210) select SND_SAMSUNG_SPDIF help Say Y if you want to add support for SoC S/PDIF audio on the SMDK. diff --git a/trunk/sound/soc/samsung/Makefile b/trunk/sound/soc/samsung/Makefile index 705d4e8a6724..622e76eb9775 100644 --- a/trunk/sound/soc/samsung/Makefile +++ b/trunk/sound/soc/samsung/Makefile @@ -8,7 +8,7 @@ snd-soc-samsung-spdif-objs := spdif.o snd-soc-pcm-objs := pcm.o snd-soc-i2s-objs := i2s.o -obj-$(CONFIG_SND_SOC_SAMSUNG) += snd-soc-s3c24xx.o +obj-$(CONFIG_ASOC_SAMSUNG) += snd-soc-s3c24xx.o obj-$(CONFIG_SND_S3C24XX_I2S) += snd-soc-s3c24xx-i2s.o obj-$(CONFIG_SND_SAMSUNG_AC97) += snd-soc-ac97.o obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd-soc-s3c2412-i2s.o @@ -30,26 +30,24 @@ snd-soc-s3c24xx-simtec-tlv320aic23-objs := s3c24xx_simtec_tlv320aic23.o snd-soc-h1940-uda1380-objs := h1940_uda1380.o snd-soc-rx1950-uda1380-objs := rx1950_uda1380.o snd-soc-smdk-wm8580-objs := smdk_wm8580.o -snd-soc-smdk-wm8994-objs := smdk_wm8994.o snd-soc-smdk-wm9713-objs := smdk_wm9713.o snd-soc-s3c64xx-smartq-wm8987-objs := smartq_wm8987.o snd-soc-goni-wm8994-objs := goni_wm8994.o snd-soc-smdk-spdif-objs := smdk_spdif.o -obj-$(CONFIG_SND_SOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o -obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o -obj-$(CONFIG_SND_SOC_SAMSUNG_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o -obj-$(CONFIG_SND_SOC_SAMSUNG_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o -obj-$(CONFIG_SND_SOC_SAMSUNG_S3C24XX_UDA134X) += snd-soc-s3c24xx-uda134x.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC) += snd-soc-s3c24xx-simtec.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_HERMES) += snd-soc-s3c24xx-simtec-hermes.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SIMTEC_TLV320AIC23) += snd-soc-s3c24xx-simtec-tlv320aic23.o -obj-$(CONFIG_SND_SOC_SAMSUNG_H1940_UDA1380) += snd-soc-h1940-uda1380.o -obj-$(CONFIG_SND_SOC_SAMSUNG_RX1950_UDA1380) += snd-soc-rx1950-uda1380.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8580) += snd-soc-smdk-wm8580.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994) += snd-soc-smdk-wm8994.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_WM9713) += snd-soc-smdk-wm9713.o -obj-$(CONFIG_SND_SOC_SMARTQ) += snd-soc-s3c64xx-smartq-wm8987.o -obj-$(CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF) += snd-soc-smdk-spdif.o -obj-$(CONFIG_SND_SOC_GONI_AQUILA_WM8994) += snd-soc-goni-wm8994.o +obj-$(CONFIG_ASOC_SAMSUNG_JIVE_WM8750) += snd-soc-jive-wm8750.o +obj-$(CONFIG_ASOC_SAMSUNG_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o +obj-$(CONFIG_ASOC_SAMSUNG_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o +obj-$(CONFIG_ASOC_SAMSUNG_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o +obj-$(CONFIG_ASOC_SAMSUNG_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o +obj-$(CONFIG_ASOC_SAMSUNG_S3C24XX_UDA134X) += snd-soc-s3c24xx-uda134x.o +obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC) += snd-soc-s3c24xx-simtec.o +obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC_HERMES) += snd-soc-s3c24xx-simtec-hermes.o +obj-$(CONFIG_ASOC_SAMSUNG_SIMTEC_TLV320AIC23) += snd-soc-s3c24xx-simtec-tlv320aic23.o +obj-$(CONFIG_ASOC_SAMSUNG_H1940_UDA1380) += snd-soc-h1940-uda1380.o +obj-$(CONFIG_ASOC_SAMSUNG_RX1950_UDA1380) += snd-soc-rx1950-uda1380.o +obj-$(CONFIG_ASOC_SAMSUNG_SMDK_WM8580) += snd-soc-smdk-wm8580.o +obj-$(CONFIG_ASOC_SAMSUNG_SMDK_WM9713) += snd-soc-smdk-wm9713.o +obj-$(CONFIG_ASOC_SMARTQ) += snd-soc-s3c64xx-smartq-wm8987.o +obj-$(CONFIG_ASOC_SAMSUNG_SMDK_SPDIF) += snd-soc-smdk-spdif.o +obj-$(CONFIG_ASOC_GONI_AQUILA_WM8994) += snd-soc-goni-wm8994.o diff --git a/trunk/sound/soc/samsung/goni_wm8994.c b/trunk/sound/soc/samsung/goni_wm8994.c index 34dd9ef1b9c0..cc8528c0a49a 100644 --- a/trunk/sound/soc/samsung/goni_wm8994.c +++ b/trunk/sound/soc/samsung/goni_wm8994.c @@ -131,7 +131,7 @@ static int goni_wm8994_init(struct snd_soc_pcm_runtime *rtd) snd_soc_dapm_sync(dapm); /* Headset jack detection */ - ret = snd_soc_jack_new(codec, "Headset Jack", + ret = snd_soc_jack_new(&goni, "Headset Jack", SND_JACK_HEADSET | SND_JACK_MECHANICAL | SND_JACK_AVOUT, &jack); if (ret) diff --git a/trunk/sound/soc/samsung/i2s.c b/trunk/sound/soc/samsung/i2s.c index d00ac3a7102c..d6de3f0eeff8 100644 --- a/trunk/sound/soc/samsung/i2s.c +++ b/trunk/sound/soc/samsung/i2s.c @@ -525,8 +525,6 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai, clk_disable(i2s->op_clk); clk_put(i2s->op_clk); } else { - i2s->rclk_srcrate = - clk_get_rate(i2s->op_clk); return 0; } } @@ -843,6 +841,11 @@ static int i2s_trigger(struct snd_pcm_substream *substream, case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: local_irq_save(flags); + if (capture) + i2s_fifo(i2s, FIC_RXFLUSH); + else + i2s_fifo(i2s, FIC_TXFLUSH); + if (config_setup(i2s)) { local_irq_restore(flags); return -EINVAL; @@ -865,11 +868,6 @@ static int i2s_trigger(struct snd_pcm_substream *substream, else i2s_txctrl(i2s, 0); - if (capture) - i2s_fifo(i2s, FIC_RXFLUSH); - else - i2s_fifo(i2s, FIC_TXFLUSH); - local_irq_restore(flags); break; } diff --git a/trunk/sound/soc/samsung/s3c24xx_simtec_hermes.c b/trunk/sound/soc/samsung/s3c24xx_simtec_hermes.c index bb4292e3596c..0083aff5a83d 100644 --- a/trunk/sound/soc/samsung/s3c24xx_simtec_hermes.c +++ b/trunk/sound/soc/samsung/s3c24xx_simtec_hermes.c @@ -21,6 +21,8 @@ #include "s3c24xx-i2s.h" #include "s3c24xx_simtec.h" +#include "../codecs/tlv320aic3x.h" + static const struct snd_soc_dapm_widget dapm_widgets[] = { SND_SOC_DAPM_LINE("GSM Out", NULL), SND_SOC_DAPM_LINE("GSM In", NULL), diff --git a/trunk/sound/soc/samsung/smdk_wm8580.c b/trunk/sound/soc/samsung/smdk_wm8580.c index b2cff1a44aed..e2d56b9bac5a 100644 --- a/trunk/sound/soc/samsung/smdk_wm8580.c +++ b/trunk/sound/soc/samsung/smdk_wm8580.c @@ -212,7 +212,7 @@ static struct snd_soc_dai_link smdk_dai[] = { [PRI_PLAYBACK] = { /* Primary Playback i/f */ .name = "WM8580 PAIF RX", .stream_name = "Playback", - .cpu_dai_name = "samsung-i2s.0", + .cpu_dai_name = "samsung-i2s.2", .codec_dai_name = "wm8580-hifi-playback", .platform_name = "samsung-audio", .codec_name = "wm8580-codec.0-001b", @@ -222,7 +222,7 @@ static struct snd_soc_dai_link smdk_dai[] = { [PRI_CAPTURE] = { /* Primary Capture i/f */ .name = "WM8580 PAIF TX", .stream_name = "Capture", - .cpu_dai_name = "samsung-i2s.0", + .cpu_dai_name = "samsung-i2s.2", .codec_dai_name = "wm8580-hifi-capture", .platform_name = "samsung-audio", .codec_name = "wm8580-codec.0-001b", @@ -254,17 +254,16 @@ static int __init smdk_audio_init(void) int ret; char *str; - if (machine_is_smdkc100() || machine_is_smdk6442() - || machine_is_smdkv210() || machine_is_smdkc110()) { + if (machine_is_smdkc100()) { smdk.num_links = 3; + /* S5PC100 has I2S0 as v5 */ + str = (char *)smdk_dai[PRI_PLAYBACK].cpu_dai_name; + str[strlen(str) - 1] = '0'; + str = (char *)smdk_dai[PRI_CAPTURE].cpu_dai_name; + str[strlen(str) - 1] = '0'; /* Secondary is at offset SAMSUNG_I2S_SECOFF from Primary */ str = (char *)smdk_dai[SEC_PLAYBACK].cpu_dai_name; str[strlen(str) - 1] = '0' + SAMSUNG_I2S_SECOFF; - } else if (machine_is_smdk6410()) { - str = (char *)smdk_dai[PRI_PLAYBACK].cpu_dai_name; - str[strlen(str) - 1] = '2'; - str = (char *)smdk_dai[PRI_CAPTURE].cpu_dai_name; - str[strlen(str) - 1] = '2'; } smdk_snd_device = platform_device_alloc("soc-audio", -1); diff --git a/trunk/sound/soc/samsung/smdk_wm8994.c b/trunk/sound/soc/samsung/smdk_wm8994.c deleted file mode 100644 index e7c1009a1e1d..000000000000 --- a/trunk/sound/soc/samsung/smdk_wm8994.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * smdk_wm8994.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include "../codecs/wm8994.h" - - /* - * Default CFG switch settings to use this driver: - * SMDKV310: CFG5-1000, CFG7-111111 - */ - - /* - * Configure audio route as :- - * $ amixer sset 'DAC1' on,on - * $ amixer sset 'Right Headphone Mux' 'DAC' - * $ amixer sset 'Left Headphone Mux' 'DAC' - * $ amixer sset 'DAC1R Mixer AIF1.1' on - * $ amixer sset 'DAC1L Mixer AIF1.1' on - * $ amixer sset 'IN2L' on - * $ amixer sset 'IN2L PGA IN2LN' on - * $ amixer sset 'MIXINL IN2L' on - * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on - * $ amixer sset 'IN2R' on - * $ amixer sset 'IN2R PGA IN2RN' on - * $ amixer sset 'MIXINR IN2R' on - * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on - */ - -/* SMDK has a 16.934MHZ crystal attached to WM8994 */ -#define SMDK_WM8994_FREQ 16934000 - -static int smdk_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - unsigned int pll_out; - int ret; - - /* AIF1CLK should be >=3MHz for optimal performance */ - if (params_rate(params) == 8000 || params_rate(params) == 11025) - pll_out = params_rate(params) * 512; - else - pll_out = params_rate(params) * 256; - - ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S - | SND_SOC_DAIFMT_NB_NF - | SND_SOC_DAIFMT_CBM_CFM); - if (ret < 0) - return ret; - - ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S - | SND_SOC_DAIFMT_NB_NF - | SND_SOC_DAIFMT_CBM_CFM); - if (ret < 0) - return ret; - - ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1, - SMDK_WM8994_FREQ, pll_out); - if (ret < 0) - return ret; - - ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1, - pll_out, SND_SOC_CLOCK_IN); - if (ret < 0) - return ret; - - return 0; -} - -/* - * SMDK WM8994 DAI operations. - */ -static struct snd_soc_ops smdk_ops = { - .hw_params = smdk_hw_params, -}; - -static int smdk_wm8994_init_paiftx(struct snd_soc_pcm_runtime *rtd) -{ - struct snd_soc_codec *codec = rtd->codec; - struct snd_soc_dapm_context *dapm = &codec->dapm; - - /* HeadPhone */ - snd_soc_dapm_enable_pin(dapm, "HPOUT1R"); - snd_soc_dapm_enable_pin(dapm, "HPOUT1L"); - - /* MicIn */ - snd_soc_dapm_enable_pin(dapm, "IN1LN"); - snd_soc_dapm_enable_pin(dapm, "IN1RN"); - - /* LineIn */ - snd_soc_dapm_enable_pin(dapm, "IN2LN"); - snd_soc_dapm_enable_pin(dapm, "IN2RN"); - - /* Other pins NC */ - snd_soc_dapm_nc_pin(dapm, "HPOUT2P"); - snd_soc_dapm_nc_pin(dapm, "HPOUT2N"); - snd_soc_dapm_nc_pin(dapm, "SPKOUTLN"); - snd_soc_dapm_nc_pin(dapm, "SPKOUTLP"); - snd_soc_dapm_nc_pin(dapm, "SPKOUTRP"); - snd_soc_dapm_nc_pin(dapm, "SPKOUTRN"); - snd_soc_dapm_nc_pin(dapm, "LINEOUT1N"); - snd_soc_dapm_nc_pin(dapm, "LINEOUT1P"); - snd_soc_dapm_nc_pin(dapm, "LINEOUT2N"); - snd_soc_dapm_nc_pin(dapm, "LINEOUT2P"); - snd_soc_dapm_nc_pin(dapm, "IN1LP"); - snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN"); - snd_soc_dapm_nc_pin(dapm, "IN1RP"); - snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP"); - - snd_soc_dapm_sync(dapm); - - return 0; -} - -static struct snd_soc_dai_link smdk_dai[] = { - { /* Primary DAI i/f */ - .name = "WM8994 AIF1", - .stream_name = "Pri_Dai", - .cpu_dai_name = "samsung-i2s.0", - .codec_dai_name = "wm8994-aif1", - .platform_name = "samsung-audio", - .codec_name = "wm8994-codec", - .init = smdk_wm8994_init_paiftx, - .ops = &smdk_ops, - }, { /* Sec_Fifo Playback i/f */ - .name = "Sec_FIFO TX", - .stream_name = "Sec_Dai", - .cpu_dai_name = "samsung-i2s.4", - .codec_dai_name = "wm8994-aif1", - .platform_name = "samsung-audio", - .codec_name = "wm8994-codec", - .ops = &smdk_ops, - }, -}; - -static struct snd_soc_card smdk = { - .name = "SMDK-I2S", - .dai_link = smdk_dai, - .num_links = ARRAY_SIZE(smdk_dai), -}; - -static struct platform_device *smdk_snd_device; - -static int __init smdk_audio_init(void) -{ - int ret; - - smdk_snd_device = platform_device_alloc("soc-audio", -1); - if (!smdk_snd_device) - return -ENOMEM; - - platform_set_drvdata(smdk_snd_device, &smdk); - - ret = platform_device_add(smdk_snd_device); - if (ret) - platform_device_put(smdk_snd_device); - - return ret; -} -module_init(smdk_audio_init); - -static void __exit smdk_audio_exit(void) -{ - platform_device_unregister(smdk_snd_device); -} -module_exit(smdk_audio_exit); - -MODULE_DESCRIPTION("ALSA SoC SMDK WM8994"); -MODULE_LICENSE("GPL"); diff --git a/trunk/sound/soc/samsung/smdk_wm9713.c b/trunk/sound/soc/samsung/smdk_wm9713.c index ae5fed6f772f..238cb3a38c5d 100644 --- a/trunk/sound/soc/samsung/smdk_wm9713.c +++ b/trunk/sound/soc/samsung/smdk_wm9713.c @@ -27,7 +27,6 @@ static struct snd_soc_card smdk; * SMDKC100: Set CFG6 1-3 On, CFG7 1 On * SMDKC110: Set CFGB10 1-2 Off, CFGB12 1-3 On * SMDKV210: Set CFGB10 1-2 Off, CFGB12 1-3 On - * SMDKV310: Set CFG2 1-2 Off, CFG4 All On, CFG7 All Off, CFG8 1-On */ /* diff --git a/trunk/sound/soc/sh/Kconfig b/trunk/sound/soc/sh/Kconfig index d8e06a607a22..7f0a496e07ce 100644 --- a/trunk/sound/soc/sh/Kconfig +++ b/trunk/sound/soc/sh/Kconfig @@ -48,7 +48,7 @@ config SND_SH7760_AC97 config SND_FSI_AK4642 tristate "FSI-AK4642 sound support" - depends on SND_SOC_SH4_FSI && I2C + depends on SND_SOC_SH4_FSI && I2C_SH_MOBILE select SND_SOC_AK4642 help This option enables generic sound support for the @@ -56,7 +56,7 @@ config SND_FSI_AK4642 config SND_FSI_DA7210 tristate "FSI-DA7210 sound support" - depends on SND_SOC_SH4_FSI && I2C + depends on SND_SOC_SH4_FSI && I2C_SH_MOBILE select SND_SOC_DA7210 help This option enables generic sound support for the diff --git a/trunk/sound/soc/sh/fsi-da7210.c b/trunk/sound/soc/sh/fsi-da7210.c index e8df9da92f71..a6adb6e43250 100644 --- a/trunk/sound/soc/sh/fsi-da7210.c +++ b/trunk/sound/soc/sh/fsi-da7210.c @@ -18,7 +18,7 @@ static int fsi_da7210_init(struct snd_soc_pcm_runtime *rtd) struct snd_soc_dai *dai = rtd->codec_dai; return snd_soc_dai_set_fmt(dai, - SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); } diff --git a/trunk/sound/soc/sh/fsi.c b/trunk/sound/soc/sh/fsi.c index 2b06402801ef..97c5394aa7d7 100644 --- a/trunk/sound/soc/sh/fsi.c +++ b/trunk/sound/soc/sh/fsi.c @@ -134,9 +134,6 @@ struct fsi_stream { int buff_len; int period_len; int period_num; - - int uerr_num; - int oerr_num; }; struct fsi_priv { @@ -329,29 +326,17 @@ static void fsi_stream_push(struct fsi_priv *fsi, io->buff_offset = 0; io->period_len = period_len; io->period_num = 0; - io->oerr_num = -1; /* ignore 1st err */ - io->uerr_num = -1; /* ignore 1st err */ } static void fsi_stream_pop(struct fsi_priv *fsi, int is_play) { struct fsi_stream *io = fsi_get_stream(fsi, is_play); - struct snd_soc_dai *dai = fsi_get_dai(io->substream); - - - if (io->oerr_num > 0) - dev_err(dai->dev, "over_run = %d\n", io->oerr_num); - - if (io->uerr_num > 0) - dev_err(dai->dev, "under_run = %d\n", io->uerr_num); io->substream = NULL; io->buff_len = 0; io->buff_offset = 0; io->period_len = 0; io->period_num = 0; - io->oerr_num = 0; - io->uerr_num = 0; } static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play) @@ -390,27 +375,6 @@ static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play) return frames_to_bytes(runtime, 1) / io->chan_num; } -static void fsi_count_fifo_err(struct fsi_priv *fsi) -{ - u32 ostatus = fsi_reg_read(fsi, DOFF_ST); - u32 istatus = fsi_reg_read(fsi, DIFF_ST); - - if (ostatus & ERR_OVER) - fsi->playback.oerr_num++; - - if (ostatus & ERR_UNDER) - fsi->playback.uerr_num++; - - if (istatus & ERR_OVER) - fsi->capture.oerr_num++; - - if (istatus & ERR_UNDER) - fsi->capture.uerr_num++; - - fsi_reg_write(fsi, DOFF_ST, 0); - fsi_reg_write(fsi, DIFF_ST, 0); -} - /* * dma function */ @@ -610,7 +574,7 @@ static void fsi_soft_all_reset(struct fsi_master *master) mdelay(10); } -static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) +static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream) { struct snd_pcm_runtime *runtime; struct snd_pcm_substream *substream = NULL; @@ -703,20 +667,40 @@ static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream) /* update buff_offset */ io->buff_offset += fsi_num2offset(data_num, ch_width); + /* check fifo status */ + if (!startup) { + struct snd_soc_dai *dai = fsi_get_dai(substream); + u32 status = is_play ? + fsi_reg_read(fsi, DOFF_ST) : + fsi_reg_read(fsi, DIFF_ST); + + if (status & ERR_OVER) + dev_err(dai->dev, "over run\n"); + if (status & ERR_UNDER) + dev_err(dai->dev, "under run\n"); + } + + is_play ? + fsi_reg_write(fsi, DOFF_ST, 0) : + fsi_reg_write(fsi, DIFF_ST, 0); + + /* re-enable irq */ + fsi_irq_enable(fsi, is_play); + if (over_period) snd_pcm_period_elapsed(substream); return 0; } -static int fsi_data_pop(struct fsi_priv *fsi) +static int fsi_data_pop(struct fsi_priv *fsi, int startup) { - return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE); + return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE); } -static int fsi_data_push(struct fsi_priv *fsi) +static int fsi_data_push(struct fsi_priv *fsi, int startup) { - return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK); + return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK); } static irqreturn_t fsi_interrupt(int irq, void *data) @@ -729,16 +713,13 @@ static irqreturn_t fsi_interrupt(int irq, void *data) fsi_master_mask_set(master, SOFT_RST, IR, IR); if (int_st & AB_IO(1, AO_SHIFT)) - fsi_data_push(&master->fsia); + fsi_data_push(&master->fsia, 0); if (int_st & AB_IO(1, BO_SHIFT)) - fsi_data_push(&master->fsib); + fsi_data_push(&master->fsib, 0); if (int_st & AB_IO(1, AI_SHIFT)) - fsi_data_pop(&master->fsia); + fsi_data_pop(&master->fsia, 0); if (int_st & AB_IO(1, BI_SHIFT)) - fsi_data_pop(&master->fsib); - - fsi_count_fifo_err(&master->fsia); - fsi_count_fifo_err(&master->fsib); + fsi_data_pop(&master->fsib, 0); fsi_irq_clear_status(&master->fsia); fsi_irq_clear_status(&master->fsib); @@ -877,8 +858,7 @@ static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, fsi_stream_push(fsi, is_play, substream, frames_to_bytes(runtime, runtime->buffer_size), frames_to_bytes(runtime, runtime->period_size)); - ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi); - fsi_irq_enable(fsi, is_play); + ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1); break; case SNDRV_PCM_TRIGGER_STOP: fsi_irq_disable(fsi, is_play); diff --git a/trunk/sound/soc/soc-cache.c b/trunk/sound/soc/soc-cache.c index a9ebc078bea8..0e17b4050425 100644 --- a/trunk/sound/soc/soc-cache.c +++ b/trunk/sound/soc/soc-cache.c @@ -988,7 +988,6 @@ static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec) return 0; } -#ifdef CONFIG_SND_SOC_CACHE_LZO struct snd_soc_lzo_ctx { void *wmem; void *dst; @@ -1400,7 +1399,6 @@ static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec) } return ret; } -#endif static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec) { @@ -1533,7 +1531,6 @@ static int snd_soc_flat_cache_init(struct snd_soc_codec *codec) /* an array of all supported compression types */ static const struct snd_soc_cache_ops cache_types[] = { - /* Flat *must* be the first entry for fallback */ { .id = SND_SOC_FLAT_COMPRESSION, .name = "flat", @@ -1543,7 +1540,6 @@ static const struct snd_soc_cache_ops cache_types[] = { .write = snd_soc_flat_cache_write, .sync = snd_soc_flat_cache_sync }, -#ifdef CONFIG_SND_SOC_CACHE_LZO { .id = SND_SOC_LZO_COMPRESSION, .name = "LZO", @@ -1553,7 +1549,6 @@ static const struct snd_soc_cache_ops cache_types[] = { .write = snd_soc_lzo_cache_write, .sync = snd_soc_lzo_cache_sync }, -#endif { .id = SND_SOC_RBTREE_COMPRESSION, .name = "rbtree", @@ -1572,12 +1567,10 @@ int snd_soc_cache_init(struct snd_soc_codec *codec) for (i = 0; i < ARRAY_SIZE(cache_types); ++i) if (cache_types[i].id == codec->compress_type) break; - - /* Fall back to flat compression */ if (i == ARRAY_SIZE(cache_types)) { - dev_warn(codec->dev, "Could not match compress type: %d\n", - codec->compress_type); - i = 0; + dev_err(codec->dev, "Could not match compress type: %d\n", + codec->compress_type); + return -EINVAL; } mutex_init(&codec->cache_rw_mutex); diff --git a/trunk/sound/soc/soc-core.c b/trunk/sound/soc/soc-core.c index bac7291b6ff6..1dc4b11c1988 100644 --- a/trunk/sound/soc/soc-core.c +++ b/trunk/sound/soc/soc-core.c @@ -1259,6 +1259,9 @@ static int soc_bind_dai_link(struct snd_soc_card *card, int num) if (!strcmp(codec->name, dai_link->codec_name)) { rtd->codec = codec; + if (!try_module_get(codec->dev->driver->owner)) + return -ENODEV; + /* CODEC found, so find CODEC DAI from registered DAIs from this CODEC*/ list_for_each_entry(codec_dai, &dai_list, list) { if (codec->dev == codec_dai->dev && @@ -1284,6 +1287,10 @@ static int soc_bind_dai_link(struct snd_soc_card *card, int num) /* no, then find CPU DAI from registered DAIs*/ list_for_each_entry(platform, &platform_list, list) { if (!strcmp(platform->name, dai_link->platform_name)) { + + if (!try_module_get(platform->dev->driver->owner)) + return -ENODEV; + rtd->platform = platform; goto out; } @@ -1418,12 +1425,8 @@ static int soc_probe_codec(struct snd_soc_card *card, soc_init_codec_debugfs(codec); /* mark codec as probed and add to card codec list */ - if (!try_module_get(codec->dev->driver->owner)) - return -ENODEV; - codec->probed = 1; list_add(&codec->card_list, &card->codec_dev_list); - list_add(&codec->dapm.list, &card->dapm_list); return ret; } @@ -1552,10 +1555,6 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) } } /* mark platform as probed and add to card platform list */ - - if (!try_module_get(platform->dev->driver->owner)) - return -ENODEV; - platform->probed = 1; list_add(&platform->card_list, &card->platform_dev_list); } @@ -1880,9 +1879,6 @@ static int soc_probe(struct platform_device *pdev) INIT_LIST_HEAD(&card->dai_dev_list); INIT_LIST_HEAD(&card->codec_dev_list); INIT_LIST_HEAD(&card->platform_dev_list); - INIT_LIST_HEAD(&card->widgets); - INIT_LIST_HEAD(&card->paths); - INIT_LIST_HEAD(&card->dapm_list); soc_init_card_debugfs(card); @@ -3484,6 +3480,8 @@ int snd_soc_register_codec(struct device *dev, else codec->compress_type = SND_SOC_FLAT_COMPRESSION; + INIT_LIST_HEAD(&codec->dapm.widgets); + INIT_LIST_HEAD(&codec->dapm.paths); codec->write = codec_drv->write; codec->read = codec_drv->read; codec->dapm.bias_level = SND_SOC_BIAS_OFF; diff --git a/trunk/sound/soc/soc-dapm.c b/trunk/sound/soc/soc-dapm.c index 499730ab5638..3d310af28907 100644 --- a/trunk/sound/soc/soc-dapm.c +++ b/trunk/sound/soc/soc-dapm.c @@ -56,7 +56,6 @@ static int dapm_up_seq[] = { [snd_soc_dapm_aif_out] = 3, [snd_soc_dapm_mic] = 4, [snd_soc_dapm_mux] = 5, - [snd_soc_dapm_virt_mux] = 5, [snd_soc_dapm_value_mux] = 5, [snd_soc_dapm_dac] = 6, [snd_soc_dapm_mixer] = 7, @@ -82,7 +81,6 @@ static int dapm_down_seq[] = { [snd_soc_dapm_mic] = 7, [snd_soc_dapm_micbias] = 8, [snd_soc_dapm_mux] = 9, - [snd_soc_dapm_virt_mux] = 9, [snd_soc_dapm_value_mux] = 9, [snd_soc_dapm_aif_in] = 10, [snd_soc_dapm_aif_out] = 10, @@ -110,7 +108,7 @@ static void pop_dbg(struct device *dev, u32 pop_time, const char *fmt, ...) va_start(args, fmt); vsnprintf(buf, PAGE_SIZE, fmt, args); - dev_info(dev, "%s", buf); + dev_info(dev, buf); va_end(args); kfree(buf); @@ -218,20 +216,6 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, } } break; - case snd_soc_dapm_virt_mux: { - struct soc_enum *e = (struct soc_enum *)w->kcontrols[i].private_value; - - p->connect = 0; - /* since a virtual mux has no backing registers to - * decide which path to connect, it will try to match - * with the first enumeration. This is to ensure - * that the default mux choice (the first) will be - * correctly powered up during initialization. - */ - if (!strcmp(p->name, e->texts[0])) - p->connect = 1; - } - break; case snd_soc_dapm_value_mux: { struct soc_enum *e = (struct soc_enum *) w->kcontrols[i].private_value; @@ -288,7 +272,7 @@ static int dapm_connect_mux(struct snd_soc_dapm_context *dapm, for (i = 0; i < e->max; i++) { if (!(strcmp(control_name, e->texts[i]))) { - list_add(&path->list, &dapm->card->paths); + list_add(&path->list, &dapm->paths); list_add(&path->list_sink, &dest->sources); list_add(&path->list_source, &src->sinks); path->name = (char*)e->texts[i]; @@ -310,7 +294,7 @@ static int dapm_connect_mixer(struct snd_soc_dapm_context *dapm, /* search for mixer kcontrol */ for (i = 0; i < dest->num_kcontrols; i++) { if (!strcmp(control_name, dest->kcontrols[i].name)) { - list_add(&path->list, &dapm->card->paths); + list_add(&path->list, &dapm->paths); list_add(&path->list_sink, &dest->sources); list_add(&path->list_source, &src->sinks); path->name = dest->kcontrols[i].name; @@ -469,7 +453,7 @@ static inline void dapm_clear_walk(struct snd_soc_dapm_context *dapm) { struct snd_soc_dapm_path *p; - list_for_each_entry(p, &dapm->card->paths, list) + list_for_each_entry(p, &dapm->paths, list) p->walked = 0; } @@ -863,22 +847,19 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm, LIST_HEAD(pending); int cur_sort = -1; int cur_reg = SND_SOC_NOPM; - struct snd_soc_dapm_context *cur_dapm = NULL; int ret; list_for_each_entry_safe(w, n, list, power_list) { ret = 0; /* Do we need to apply any queued changes? */ - if (sort[w->id] != cur_sort || w->reg != cur_reg || - w->dapm != cur_dapm) { + if (sort[w->id] != cur_sort || w->reg != cur_reg) { if (!list_empty(&pending)) - dapm_seq_run_coalesced(cur_dapm, &pending); + dapm_seq_run_coalesced(dapm, &pending); INIT_LIST_HEAD(&pending); cur_sort = -1; cur_reg = SND_SOC_NOPM; - cur_dapm = NULL; } switch (w->id) { @@ -922,7 +903,6 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm, /* Queue it up for application */ cur_sort = sort[w->id]; cur_reg = w->reg; - cur_dapm = w->dapm; list_move(&w->power_list, &pending); break; } @@ -936,41 +916,6 @@ static void dapm_seq_run(struct snd_soc_dapm_context *dapm, dapm_seq_run_coalesced(dapm, &pending); } -static void dapm_widget_update(struct snd_soc_dapm_context *dapm) -{ - struct snd_soc_dapm_update *update = dapm->update; - struct snd_soc_dapm_widget *w; - int ret; - - if (!update) - return; - - w = update->widget; - - if (w->event && - (w->event_flags & SND_SOC_DAPM_PRE_REG)) { - ret = w->event(w, update->kcontrol, SND_SOC_DAPM_PRE_REG); - if (ret != 0) - pr_err("%s DAPM pre-event failed: %d\n", - w->name, ret); - } - - ret = snd_soc_update_bits(w->codec, update->reg, update->mask, - update->val); - if (ret < 0) - pr_err("%s DAPM update failed: %d\n", w->name, ret); - - if (w->event && - (w->event_flags & SND_SOC_DAPM_POST_REG)) { - ret = w->event(w, update->kcontrol, SND_SOC_DAPM_POST_REG); - if (ret != 0) - pr_err("%s DAPM post-event failed: %d\n", - w->name, ret); - } -} - - - /* * Scan each dapm widget for complete audio path. * A complete path is a route that has valid endpoints i.e.:- @@ -984,22 +929,18 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) { struct snd_soc_card *card = dapm->codec->card; struct snd_soc_dapm_widget *w; - struct snd_soc_dapm_context *d; LIST_HEAD(up_list); LIST_HEAD(down_list); int ret = 0; int power; + int sys_power = 0; trace_snd_soc_dapm_start(card); - list_for_each_entry(d, &card->dapm_list, list) - if (d->n_widgets) - d->dev_power = 0; - /* Check which widgets we need to power and store them in * lists indicating if they should be powered up or down. */ - list_for_each_entry(w, &card->widgets, list) { + list_for_each_entry(w, &dapm->widgets, list) { switch (w->id) { case snd_soc_dapm_pre: dapm_seq_insert(w, &down_list, dapm_down_seq); @@ -1017,7 +958,7 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) else power = 1; if (power) - w->dapm->dev_power = 1; + sys_power = 1; if (w->power == power) continue; @@ -1037,26 +978,26 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) /* If there are no DAPM widgets then try to figure out power from the * event type. */ - if (!dapm->n_widgets) { + if (list_empty(&dapm->widgets)) { switch (event) { case SND_SOC_DAPM_STREAM_START: case SND_SOC_DAPM_STREAM_RESUME: - dapm->dev_power = 1; + sys_power = 1; break; case SND_SOC_DAPM_STREAM_STOP: - dapm->dev_power = !!dapm->codec->active; + sys_power = !!dapm->codec->active; break; case SND_SOC_DAPM_STREAM_SUSPEND: - dapm->dev_power = 0; + sys_power = 0; break; case SND_SOC_DAPM_STREAM_NOP: switch (dapm->bias_level) { case SND_SOC_BIAS_STANDBY: case SND_SOC_BIAS_OFF: - dapm->dev_power = 0; + sys_power = 0; break; default: - dapm->dev_power = 1; + sys_power = 1; break; } break; @@ -1065,64 +1006,52 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) } } - list_for_each_entry(d, &dapm->card->dapm_list, list) { - if (d->dev_power && d->bias_level == SND_SOC_BIAS_OFF) { - ret = snd_soc_dapm_set_bias_level(card, d, - SND_SOC_BIAS_STANDBY); - if (ret != 0) - dev_err(d->dev, - "Failed to turn on bias: %d\n", ret); - } + if (sys_power && dapm->bias_level == SND_SOC_BIAS_OFF) { + ret = snd_soc_dapm_set_bias_level(card, dapm, + SND_SOC_BIAS_STANDBY); + if (ret != 0) + dev_err(dapm->dev, + "Failed to turn on bias: %d\n", ret); + } - /* If we're changing to all on or all off then prepare */ - if ((d->dev_power && d->bias_level == SND_SOC_BIAS_STANDBY) || - (!d->dev_power && d->bias_level == SND_SOC_BIAS_ON)) { - ret = snd_soc_dapm_set_bias_level(card, d, - SND_SOC_BIAS_PREPARE); - if (ret != 0) - dev_err(d->dev, - "Failed to prepare bias: %d\n", ret); - } + /* If we're changing to all on or all off then prepare */ + if ((sys_power && dapm->bias_level == SND_SOC_BIAS_STANDBY) || + (!sys_power && dapm->bias_level == SND_SOC_BIAS_ON)) { + ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_PREPARE); + if (ret != 0) + dev_err(dapm->dev, + "Failed to prepare bias: %d\n", ret); } /* Power down widgets first; try to avoid amplifying pops. */ dapm_seq_run(dapm, &down_list, event, dapm_down_seq); - dapm_widget_update(dapm); - /* Now power up. */ dapm_seq_run(dapm, &up_list, event, dapm_up_seq); - list_for_each_entry(d, &dapm->card->dapm_list, list) { - /* If we just powered the last thing off drop to standby bias */ - if (d->bias_level == SND_SOC_BIAS_PREPARE && !d->dev_power) { - ret = snd_soc_dapm_set_bias_level(card, d, - SND_SOC_BIAS_STANDBY); - if (ret != 0) - dev_err(d->dev, - "Failed to apply standby bias: %d\n", - ret); - } + /* If we just powered the last thing off drop to standby bias */ + if (dapm->bias_level == SND_SOC_BIAS_PREPARE && !sys_power) { + ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_STANDBY); + if (ret != 0) + dev_err(dapm->dev, + "Failed to apply standby bias: %d\n", ret); + } - /* If we're in standby and can support bias off then do that */ - if (d->bias_level == SND_SOC_BIAS_STANDBY && - d->idle_bias_off) { - ret = snd_soc_dapm_set_bias_level(card, d, - SND_SOC_BIAS_OFF); - if (ret != 0) - dev_err(d->dev, - "Failed to turn off bias: %d\n", ret); - } + /* If we're in standby and can support bias off then do that */ + if (dapm->bias_level == SND_SOC_BIAS_STANDBY && + dapm->idle_bias_off) { + ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_OFF); + if (ret != 0) + dev_err(dapm->dev, + "Failed to turn off bias: %d\n", ret); + } - /* If we just powered up then move to active bias */ - if (d->bias_level == SND_SOC_BIAS_PREPARE && d->dev_power) { - ret = snd_soc_dapm_set_bias_level(card, d, - SND_SOC_BIAS_ON); - if (ret != 0) - dev_err(d->dev, - "Failed to apply active bias: %d\n", - ret); - } + /* If we just powered up then move to active bias */ + if (dapm->bias_level == SND_SOC_BIAS_PREPARE && sys_power) { + ret = snd_soc_dapm_set_bias_level(card, dapm, SND_SOC_BIAS_ON); + if (ret != 0) + dev_err(dapm->dev, + "Failed to apply active bias: %d\n", ret); } pop_dbg(dapm->dev, card->pop_time, @@ -1216,8 +1145,8 @@ void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm) if (!dapm->debugfs_dapm) return; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (!w->name || w->dapm != dapm) + list_for_each_entry(w, &dapm->widgets, list) { + if (!w->name) continue; d = debugfs_create_file(w->name, 0444, @@ -1244,7 +1173,6 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, int found = 0; if (widget->id != snd_soc_dapm_mux && - widget->id != snd_soc_dapm_virt_mux && widget->id != snd_soc_dapm_value_mux) return -ENODEV; @@ -1252,7 +1180,7 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, return 0; /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->card->paths, list) { + list_for_each_entry(path, &widget->dapm->paths, list) { if (path->kcontrol != kcontrol) continue; @@ -1286,7 +1214,7 @@ static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, return -ENODEV; /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->card->paths, list) { + list_for_each_entry(path, &widget->dapm->paths, list) { if (path->kcontrol != kcontrol) continue; @@ -1313,9 +1241,7 @@ static ssize_t dapm_widget_show(struct device *dev, int count = 0; char *state = "not set"; - list_for_each_entry(w, &codec->card->widgets, list) { - if (w->dapm != &codec->dapm) - continue; + list_for_each_entry(w, &codec->dapm.widgets, list) { /* only display widgets that burnm power */ switch (w->id) { @@ -1377,32 +1303,17 @@ static void dapm_free_widgets(struct snd_soc_dapm_context *dapm) struct snd_soc_dapm_widget *w, *next_w; struct snd_soc_dapm_path *p, *next_p; - list_for_each_entry_safe(w, next_w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry_safe(w, next_w, &dapm->widgets, list) { list_del(&w->list); - /* - * remove source and sink paths associated to this widget. - * While removing the path, remove reference to it from both - * source and sink widgets so that path is removed only once. - */ - list_for_each_entry_safe(p, next_p, &w->sources, list_sink) { - list_del(&p->list_sink); - list_del(&p->list_source); - list_del(&p->list); - kfree(p->long_name); - kfree(p); - } - list_for_each_entry_safe(p, next_p, &w->sinks, list_source) { - list_del(&p->list_sink); - list_del(&p->list_source); - list_del(&p->list); - kfree(p->long_name); - kfree(p); - } kfree(w->name); kfree(w); } + + list_for_each_entry_safe(p, next_p, &dapm->paths, list) { + list_del(&p->list); + kfree(p->long_name); + kfree(p); + } } static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm, @@ -1410,9 +1321,7 @@ static int snd_soc_dapm_set_pin(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry(w, &dapm->widgets, list) { if (!strcmp(w->name, pin)) { dev_dbg(w->dapm->dev, "dapm: pin %s = %d\n", pin, status); @@ -1448,7 +1357,6 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_path *path; struct snd_soc_dapm_widget *wsource = NULL, *wsink = NULL, *w; - struct snd_soc_dapm_widget *wtsource = NULL, *wtsink = NULL; const char *sink; const char *control = route->control; const char *source; @@ -1468,28 +1376,17 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, source = route->source; } - /* - * find src and dest widgets over all widgets but favor a widget from - * current DAPM context - */ - list_for_each_entry(w, &dapm->card->widgets, list) { + /* find src and dest widgets */ + list_for_each_entry(w, &dapm->widgets, list) { + if (!wsink && !(strcmp(w->name, sink))) { - wtsink = w; - if (w->dapm == dapm) - wsink = w; + wsink = w; continue; } if (!wsource && !(strcmp(w->name, source))) { - wtsource = w; - if (w->dapm == dapm) - wsource = w; + wsource = w; } } - /* use widget from another DAPM context if not found from this */ - if (!wsink) - wsink = wtsink; - if (!wsource) - wsource = wtsource; if (wsource == NULL || wsink == NULL) return -ENODEV; @@ -1523,7 +1420,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, /* connect static paths */ if (control == NULL) { - list_add(&path->list, &dapm->card->paths); + list_add(&path->list, &dapm->paths); list_add(&path->list_sink, &wsink->sources); list_add(&path->list_source, &wsource->sinks); path->connect = 1; @@ -1545,13 +1442,12 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, case snd_soc_dapm_supply: case snd_soc_dapm_aif_in: case snd_soc_dapm_aif_out: - list_add(&path->list, &dapm->card->paths); + list_add(&path->list, &dapm->paths); list_add(&path->list_sink, &wsink->sources); list_add(&path->list_source, &wsource->sinks); path->connect = 1; return 0; case snd_soc_dapm_mux: - case snd_soc_dapm_virt_mux: case snd_soc_dapm_value_mux: ret = dapm_connect_mux(dapm, wsource, wsink, path, control, &wsink->kcontrols[0]); @@ -1569,7 +1465,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, case snd_soc_dapm_mic: case snd_soc_dapm_line: case snd_soc_dapm_spk: - list_add(&path->list, &dapm->card->paths); + list_add(&path->list, &dapm->paths); list_add(&path->list_sink, &wsink->sources); list_add(&path->list_source, &wsource->sinks); path->connect = 0; @@ -1628,7 +1524,7 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm) { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) + list_for_each_entry(w, &dapm->widgets, list) { if (w->new) continue; @@ -1641,7 +1537,6 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm) dapm_new_mixer(dapm, w); break; case snd_soc_dapm_mux: - case snd_soc_dapm_virt_mux: case snd_soc_dapm_value_mux: w->power_check = dapm_generic_check_power; dapm_new_mux(dapm, w); @@ -1739,12 +1634,13 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, (struct soc_mixer_control *)kcontrol->private_value; unsigned int reg = mc->reg; unsigned int shift = mc->shift; + unsigned int rshift = mc->rshift; int max = mc->max; unsigned int mask = (1 << fls(max)) - 1; unsigned int invert = mc->invert; - unsigned int val, val_mask; - int connect, change; - struct snd_soc_dapm_update update; + unsigned int val, val2, val_mask; + int connect; + int ret; val = (ucontrol->value.integer.value[0] & mask); @@ -1752,12 +1648,18 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, val = max - val; val_mask = mask << shift; val = val << shift; + if (shift != rshift) { + val2 = (ucontrol->value.integer.value[1] & mask); + if (invert) + val2 = max - val2; + val_mask |= mask << rshift; + val |= val2 << rshift; + } mutex_lock(&widget->codec->mutex); widget->value = val; - change = snd_soc_test_bits(widget->codec, reg, val_mask, val); - if (change) { + if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { if (val) /* new connection */ connect = invert ? 0:1; @@ -1765,20 +1667,28 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, /* old connection must be powered down */ connect = invert ? 1:0; - update.kcontrol = kcontrol; - update.widget = widget; - update.reg = reg; - update.mask = mask; - update.val = val; - widget->dapm->update = &update; - dapm_mixer_update_power(widget, kcontrol, connect); - - widget->dapm->update = NULL; } + if (widget->event) { + if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { + ret = widget->event(widget, kcontrol, + SND_SOC_DAPM_PRE_REG); + if (ret < 0) { + ret = 1; + goto out; + } + } + ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); + if (widget->event_flags & SND_SOC_DAPM_POST_REG) + ret = widget->event(widget, kcontrol, + SND_SOC_DAPM_POST_REG); + } else + ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); + +out: mutex_unlock(&widget->codec->mutex); - return 0; + return ret; } EXPORT_SYMBOL_GPL(snd_soc_dapm_put_volsw); @@ -1826,7 +1736,7 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; unsigned int val, mux, change; unsigned int mask, bitmask; - struct snd_soc_dapm_update update; + int ret = 0; for (bitmask = 1; bitmask < e->max; bitmask <<= 1) ; @@ -1845,20 +1755,24 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; change = snd_soc_test_bits(widget->codec, e->reg, mask, val); + dapm_mux_update_power(widget, kcontrol, change, mux, e); - update.kcontrol = kcontrol; - update.widget = widget; - update.reg = e->reg; - update.mask = mask; - update.val = val; - widget->dapm->update = &update; + if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { + ret = widget->event(widget, + kcontrol, SND_SOC_DAPM_PRE_REG); + if (ret < 0) + goto out; + } - dapm_mux_update_power(widget, kcontrol, change, mux, e); + ret = snd_soc_update_bits(widget->codec, e->reg, mask, val); - widget->dapm->update = NULL; + if (widget->event_flags & SND_SOC_DAPM_POST_REG) + ret = widget->event(widget, + kcontrol, SND_SOC_DAPM_POST_REG); +out: mutex_unlock(&widget->codec->mutex); - return change; + return ret; } EXPORT_SYMBOL_GPL(snd_soc_dapm_put_enum_double); @@ -1970,7 +1884,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; unsigned int val, mux, change; unsigned int mask; - struct snd_soc_dapm_update update; + int ret = 0; if (ucontrol->value.enumerated.item[0] > e->max - 1) return -EINVAL; @@ -1987,20 +1901,24 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; change = snd_soc_test_bits(widget->codec, e->reg, mask, val); + dapm_mux_update_power(widget, kcontrol, change, mux, e); - update.kcontrol = kcontrol; - update.widget = widget; - update.reg = e->reg; - update.mask = mask; - update.val = val; - widget->dapm->update = &update; + if (widget->event_flags & SND_SOC_DAPM_PRE_REG) { + ret = widget->event(widget, + kcontrol, SND_SOC_DAPM_PRE_REG); + if (ret < 0) + goto out; + } - dapm_mux_update_power(widget, kcontrol, change, mux, e); + ret = snd_soc_update_bits(widget->codec, e->reg, mask, val); - widget->dapm->update = NULL; + if (widget->event_flags & SND_SOC_DAPM_POST_REG) + ret = widget->event(widget, + kcontrol, SND_SOC_DAPM_POST_REG); +out: mutex_unlock(&widget->codec->mutex); - return change; + return ret; } EXPORT_SYMBOL_GPL(snd_soc_dapm_put_value_enum_double); @@ -2106,13 +2024,12 @@ int snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, else snprintf(w->name, name_len, "%s", widget->name); - dapm->n_widgets++; w->dapm = dapm; w->codec = dapm->codec; INIT_LIST_HEAD(&w->sources); INIT_LIST_HEAD(&w->sinks); INIT_LIST_HEAD(&w->list); - list_add(&w->list, &dapm->card->widgets); + list_add(&w->list, &dapm->widgets); /* machine layer set ups unconnected pins and insertions */ w->connected = 1; @@ -2155,9 +2072,9 @@ static void soc_dapm_stream_event(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) + list_for_each_entry(w, &dapm->widgets, list) { - if (!w->sname || w->dapm != dapm) + if (!w->sname) continue; dev_dbg(w->dapm->dev, "widget %s\n %s stream %s event %d\n", w->name, w->sname, stream, event); @@ -2240,9 +2157,7 @@ int snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry(w, &dapm->widgets, list) { if (!strcmp(w->name, pin)) { dev_dbg(w->dapm->dev, "dapm: force enable pin %s\n", pin); @@ -2307,9 +2222,7 @@ int snd_soc_dapm_get_pin_status(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry(w, &dapm->widgets, list) { if (!strcmp(w->name, pin)) return w->connected; } @@ -2334,9 +2247,7 @@ int snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry(w, &dapm->widgets, list) { if (!strcmp(w->name, pin)) { w->ignore_suspend = 1; return 0; @@ -2358,7 +2269,6 @@ void snd_soc_dapm_free(struct snd_soc_dapm_context *dapm) { snd_soc_dapm_sys_remove(dapm->dev); dapm_free_widgets(dapm); - list_del(&dapm->list); } EXPORT_SYMBOL_GPL(snd_soc_dapm_free); @@ -2368,9 +2278,7 @@ static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm) LIST_HEAD(down_list); int powerdown = 0; - list_for_each_entry(w, &dapm->card->widgets, list) { - if (w->dapm != dapm) - continue; + list_for_each_entry(w, &dapm->widgets, list) { if (w->power) { dapm_seq_insert(w, &down_list, dapm_down_seq); w->power = 0;