From d562b30db9b44e75e236fe73d8832a192ed468aa Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 13 Mar 2012 13:28:02 -0600
Subject: [PATCH] --- yaml --- r: 303308 b: refs/heads/master c:
 e5cbeef0a4d450787169e29b610455b7d9392b7e h: refs/heads/master v: v3

---
 [refs]                                   |  2 +-
 trunk/arch/arm/boot/dts/tegra-cardhu.dts | 44 ++++++++++++++++++++++++
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 8956adfac399..9eff0763c9a9 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b7449d95b0cbfb06b9ca9de8c322c470fbc2a873
+refs/heads/master: e5cbeef0a4d450787169e29b610455b7d9392b7e
diff --git a/trunk/arch/arm/boot/dts/tegra-cardhu.dts b/trunk/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..0a9f34a2c3aa 100644
--- a/trunk/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/trunk/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
 		reg = < 0x80000000 0x40000000 >;
 	};
 
+	pinmux@70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins =	"sdmmc1_cmd_pz1",
+						"sdmmc1_dat0_py7",
+						"sdmmc1_dat1_py6",
+						"sdmmc1_dat2_py5",
+						"sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins =	"sdmmc4_clk_pcc4",
+						"sdmmc4_rst_n_pcc3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc4_dat0_paa0 {
+				nvidia,pins =	"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
 	serial@70006000 {
 		clock-frequency = < 408000000 >;
 	};