From d66e59c84b617d00de576cb75c7258304a0e1a6f Mon Sep 17 00:00:00 2001 From: Pavel Hofman Date: Tue, 24 Apr 2007 12:27:36 +0200 Subject: [PATCH] --- yaml --- r: 56187 b: refs/heads/master c: c5a30f85fd56c06efddbe6f4885c7968245c2d8a h: refs/heads/master i: 56185: d66b4fc89a861bb7324e6fcddfb8ee6ee6d33e17 56183: 00341c266eea5f005681e37394f47775d18c4251 v: v3 --- [refs] | 2 +- trunk/sound/pci/ice1712/ice1724.c | 5 +++++ trunk/sound/pci/ice1712/prodigy192.c | 12 +++++++++++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 6ea09f419b5f..9f45bf900b7f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bccad14e9a931027b72f20fe7caba68fea760e7b +refs/heads/master: c5a30f85fd56c06efddbe6f4885c7968245c2d8a diff --git a/trunk/sound/pci/ice1712/ice1724.c b/trunk/sound/pci/ice1712/ice1724.c index 6a29bcf19042..ee620dea7ef3 100644 --- a/trunk/sound/pci/ice1712/ice1724.c +++ b/trunk/sound/pci/ice1712/ice1724.c @@ -1666,7 +1666,12 @@ static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol, spin_lock_irq(&ice->reg_lock); oval = inb(ICEMT1724(ice, RATE)); if (ucontrol->value.enumerated.item[0] == spdif) { + unsigned char i2s_oval; outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); + /* setting 256fs */ + i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT)); + outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, + ICEMT1724(ice, I2S_FORMAT)); } else { rate = rates[ucontrol->value.integer.value[0] % 15]; if (rate <= get_max_rate(ice)) { diff --git a/trunk/sound/pci/ice1712/prodigy192.c b/trunk/sound/pci/ice1712/prodigy192.c index ae08a079a413..f03c02c07743 100644 --- a/trunk/sound/pci/ice1712/prodigy192.c +++ b/trunk/sound/pci/ice1712/prodigy192.c @@ -26,6 +26,13 @@ * CCLK (pin 34) -- GPIO9 pin 76 * CSN (pin 35) -- GPIO8 pin 75 * - output data Mode 7 (24bit, I2S, slave) + * - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which + * outputs master clock to SPMCLKIN of ice1724. + * Experimentally I found out that only a combination of + * OCKS0=1, OCKS1=1 (128fs, 64fs output) and ice1724 - + * VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct + * sampling rate. That means the the FPGA doubles the + * MCK01 rate. * * Copyright (c) 2003 Takashi Iwai * Copyright (c) 2003 Dimitromanolakis Apostolos @@ -714,7 +721,10 @@ static int prodigy192_ak4114_init(struct snd_ice1712 *ice) { static const unsigned char ak4114_init_vals[] = { AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1, - AK4114_DIF_I24I2S, /* ice1724 expects I2S and provides clock */ + /* ice1724 expects I2S and provides clock, + * DEM0 disables the deemphasis filter + */ + AK4114_DIF_I24I2S | AK4114_DEM0 , AK4114_TX1E, AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */ 0,