From d67a9f078945e8ab93664f5ec13e950b6836eda4 Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Fri, 8 May 2009 07:42:12 +0000 Subject: [PATCH] --- yaml --- r: 148554 b: refs/heads/master c: e522c8466d6f8437cf02a34287c8707ef53081ed h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/blackfin/kernel/cplb-mpu/cacheinit.c | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 89bad129320a..629aa7df24ef 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a9a59e3096443ea4d6f50db978d7d3bbb47708b4 +refs/heads/master: e522c8466d6f8437cf02a34287c8707ef53081ed diff --git a/trunk/arch/blackfin/kernel/cplb-mpu/cacheinit.c b/trunk/arch/blackfin/kernel/cplb-mpu/cacheinit.c index c6ff947f9d37..d5a86c3017f7 100644 --- a/trunk/arch/blackfin/kernel/cplb-mpu/cacheinit.c +++ b/trunk/arch/blackfin/kernel/cplb-mpu/cacheinit.c @@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) } ctrl = bfin_read_DMEM_CONTROL(); - ctrl |= DMEM_CNTR; + + /* + * Anomaly notes: + * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL + * register, so that the port preferences for DAG0 and DAG1 are set + * to port B + */ + ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0); bfin_write_DMEM_CONTROL(ctrl); SSYNC(); }