From d6a9e6786b2453fe149c4764e2b73dc9ac4857c5 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 16 Dec 2008 15:25:45 -0800 Subject: [PATCH] --- yaml --- r: 122736 b: refs/heads/master c: 257d938a0c17838c740eb68f0005b041444ac2c2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/net/gianfar.c | 14 +------------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/[refs] b/[refs] index 554ffcf459b1..5ee3a2f6476b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5eeabf5150878018d7c7092042f3b681f5b554b5 +refs/heads/master: 257d938a0c17838c740eb68f0005b041444ac2c2 diff --git a/trunk/drivers/net/gianfar.c b/trunk/drivers/net/gianfar.c index 2635f5bed77f..55e319fa7fe6 100644 --- a/trunk/drivers/net/gianfar.c +++ b/trunk/drivers/net/gianfar.c @@ -225,19 +225,7 @@ static int gfar_probe(struct platform_device *pdev) /* Stop the DMA engine now, in case it was running before */ /* (The firmware could have used it, and left it running). */ - /* To do this, we write Graceful Receive Stop and Graceful */ - /* Transmit Stop, and then wait until the corresponding bits */ - /* in IEVENT indicate the stops have completed. */ - tempval = gfar_read(&priv->regs->dmactrl); - tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); - gfar_write(&priv->regs->dmactrl, tempval); - - tempval = gfar_read(&priv->regs->dmactrl); - tempval |= (DMACTRL_GRS | DMACTRL_GTS); - gfar_write(&priv->regs->dmactrl, tempval); - - while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))) - cpu_relax(); + gfar_halt(dev); /* Reset MAC layer */ gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);