From d90f8a5afaeb8d2b699c3b0b1c55b5717fcb4f6e Mon Sep 17 00:00:00 2001 From: Jingoo Han Date: Mon, 16 Apr 2012 09:33:12 +0900 Subject: [PATCH] --- yaml --- r: 310255 b: refs/heads/master c: 8affaf5c7698c627b133bfcafd9869ef17faff31 h: refs/heads/master i: 310253: 5293125365222a36369356b61bae9cae91a04255 310251: 501a6b07777fb62ad318d0fd25d7306d7a052a69 310247: e30e9744354065f1a79d55debd4474cfd49e0217 310239: 11219bc3db2d74d3b83a204a14f2055fefc90d1b v: v3 --- [refs] | 2 +- trunk/drivers/video/exynos/exynos_dp_core.h | 1 + trunk/drivers/video/exynos/exynos_dp_reg.c | 23 ++++++++++++++++ trunk/drivers/video/exynos/exynos_dp_reg.h | 29 +++++++++++++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index b44cc408aa83..1c0e168cdaf0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8f802da33a842bc9e511d2a9c8259fbee8a6d17e +refs/heads/master: 8affaf5c7698c627b133bfcafd9869ef17faff31 diff --git a/trunk/drivers/video/exynos/exynos_dp_core.h b/trunk/drivers/video/exynos/exynos_dp_core.h index 90ceaca0fa24..519c3a6a5c58 100644 --- a/trunk/drivers/video/exynos/exynos_dp_core.h +++ b/trunk/drivers/video/exynos/exynos_dp_core.h @@ -39,6 +39,7 @@ struct exynos_dp_device { void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable); void exynos_dp_stop_video(struct exynos_dp_device *dp); void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable); +void exynos_dp_init_analog_param(struct exynos_dp_device *dp); void exynos_dp_init_interrupt(struct exynos_dp_device *dp); void exynos_dp_reset(struct exynos_dp_device *dp); void exynos_dp_config_interrupt(struct exynos_dp_device *dp); diff --git a/trunk/drivers/video/exynos/exynos_dp_reg.c b/trunk/drivers/video/exynos/exynos_dp_reg.c index 169d1810d30c..3863726f5874 100644 --- a/trunk/drivers/video/exynos/exynos_dp_reg.c +++ b/trunk/drivers/video/exynos/exynos_dp_reg.c @@ -65,6 +65,28 @@ void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable) writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); } +void exynos_dp_init_analog_param(struct exynos_dp_device *dp) +{ + u32 reg; + + reg = TX_TERMINAL_CTRL_50_OHM; + writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); + + reg = SEL_24M | TX_DVDD_BIT_1_0625V; + writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); + + reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; + writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); + + reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | + TX_CUR1_2X | TX_CUR_8_MA; + writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); + + reg = CH3_AMP_400_MV | CH2_AMP_400_MV | + CH1_AMP_400_MV | CH0_AMP_400_MV; + writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); +} + void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ @@ -131,6 +153,7 @@ void exynos_dp_reset(struct exynos_dp_device *dp) writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); + exynos_dp_init_analog_param(dp); exynos_dp_init_interrupt(dp); } diff --git a/trunk/drivers/video/exynos/exynos_dp_reg.h b/trunk/drivers/video/exynos/exynos_dp_reg.h index 42f608e2a43e..125b27cd57ae 100644 --- a/trunk/drivers/video/exynos/exynos_dp_reg.h +++ b/trunk/drivers/video/exynos/exynos_dp_reg.h @@ -24,6 +24,12 @@ #define EXYNOS_DP_LANE_MAP 0x35C +#define EXYNOS_DP_ANALOG_CTL_1 0x370 +#define EXYNOS_DP_ANALOG_CTL_2 0x374 +#define EXYNOS_DP_ANALOG_CTL_3 0x378 +#define EXYNOS_DP_PLL_FILTER_CTL_1 0x37C +#define EXYNOS_DP_TX_AMP_TUNING_CTL 0x380 + #define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 #define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 @@ -166,6 +172,29 @@ #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) +/* EXYNOS_DP_ANALOG_CTL_1 */ +#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) + +/* EXYNOS_DP_ANALOG_CTL_2 */ +#define SEL_24M (0x1 << 3) +#define TX_DVDD_BIT_1_0625V (0x4 << 0) + +/* EXYNOS_DP_ANALOG_CTL_3 */ +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define VCO_BIT_600_MICRO (0x5 << 0) + +/* EXYNOS_DP_PLL_FILTER_CTL_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR_8_MA (0x2 << 0) + +/* EXYNOS_DP_TX_AMP_TUNING_CTL */ +#define CH3_AMP_400_MV (0x0 << 24) +#define CH2_AMP_400_MV (0x0 << 16) +#define CH1_AMP_400_MV (0x0 << 8) +#define CH0_AMP_400_MV (0x0 << 0) + /* EXYNOS_DP_AUX_HW_RETRY_CTL */ #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)