From da81b1f3a407c32dfddbd49cd196e791fd4f80e7 Mon Sep 17 00:00:00 2001 From: Eugeni Dodonov Date: Mon, 2 Jul 2012 11:51:06 -0300 Subject: [PATCH] --- yaml --- r: 318644 b: refs/heads/master c: 7cf50fc8d7a491d9aa47e1a0262ed7d265f2bec3 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_pm.c | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index a8a332b33077..2933ed02e9db 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 5a7dc92a0b55ccaa6e342ec212657d6fc806e790 +refs/heads/master: 7cf50fc8d7a491d9aa47e1a0262ed7d265f2bec3 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index 4c6c26c5ad32..e4c7eac656bd 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -3240,7 +3240,7 @@ void intel_disable_gt_powersave(struct drm_device *dev) { if (IS_IRONLAKE_M(dev)) ironlake_disable_drps(dev); - if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) + else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) gen6_disable_rps(dev); } @@ -3250,9 +3250,7 @@ void intel_enable_gt_powersave(struct drm_device *dev) ironlake_enable_drps(dev); ironlake_enable_rc6(dev); intel_init_emon(dev); - } - - if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { + } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { gen6_enable_rps(dev); gen6_update_ring_freq(dev); }