From dab4127bda0eafe6f097f2093b42c1edf4213825 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 3 Dec 2009 16:18:19 -0500 Subject: [PATCH] --- yaml --- r: 174619 b: refs/heads/master c: 722f29434e72188b2d20f9b41f4b5952073ed568 h: refs/heads/master i: 174617: ee202d3c92dae5a078f6222f917367dc82b1edb0 174615: f197cf7a34f51fa4b15794b82ba0cc8b247fc12d v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/rs600.c | 6 ++++++ trunk/drivers/gpu/drm/radeon/rs690.c | 10 ++-------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 2e2a2eaa7e3a..2159e8ecf4d6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8de21525439e6b5bb8d8c81e49094d867bf82f6d +refs/heads/master: 722f29434e72188b2d20f9b41f4b5952073ed568 diff --git a/trunk/drivers/gpu/drm/radeon/rs600.c b/trunk/drivers/gpu/drm/radeon/rs600.c index c97eb63a21d2..00bc71fe98d1 100644 --- a/trunk/drivers/gpu/drm/radeon/rs600.c +++ b/trunk/drivers/gpu/drm/radeon/rs600.c @@ -320,6 +320,12 @@ void rs600_vram_info(struct radeon_device *rdev) /* FIXME: to do or is these values sane ? */ rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; + + rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); + rdev->mc.mc_vram_size = rdev->mc.real_vram_size; + + rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); + rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); } void rs600_bandwidth_update(struct radeon_device *rdev) diff --git a/trunk/drivers/gpu/drm/radeon/rs690.c b/trunk/drivers/gpu/drm/radeon/rs690.c index e7a5f87c23fe..81b8efcac4e8 100644 --- a/trunk/drivers/gpu/drm/radeon/rs690.c +++ b/trunk/drivers/gpu/drm/radeon/rs690.c @@ -131,19 +131,13 @@ void rs690_pm_info(struct radeon_device *rdev) void rs690_vram_info(struct radeon_device *rdev) { - uint32_t tmp; fixed20_12 a; rs400_gart_adjust_size(rdev); /* DDR for all card after R300 & IGP */ rdev->mc.vram_is_ddr = true; - /* FIXME: is this correct for RS690/RS740 ? */ - tmp = RREG32(RADEON_MEM_CNTL); - if (tmp & R300_MEM_NUM_CHANNELS_MASK) { - rdev->mc.vram_width = 128; - } else { - rdev->mc.vram_width = 64; - } + rdev->mc.vram_width = 128; + rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.mc_vram_size = rdev->mc.real_vram_size;