diff --git a/[refs] b/[refs]
index 323c78eae94d..7732375ee046 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c52c983551ba3fb991f91eff4d924a375b0f9b83
+refs/heads/master: ae4fa7f66e542ef5c7662ceabfaaa33283eb4216
diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile
index 70c424eaf7b0..9260c293405c 100644
--- a/trunk/arch/arm/Makefile
+++ b/trunk/arch/arm/Makefile
@@ -154,9 +154,7 @@ machine-$(CONFIG_ARCH_LPC32XX)		:= lpc32xx
 machine-$(CONFIG_ARCH_MMP)		:= mmp
 machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
-machine-$(CONFIG_ARCH_MX1)		:= imx
-machine-$(CONFIG_ARCH_MX2)		:= imx
-machine-$(CONFIG_ARCH_MX25)		:= imx
+machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
 machine-$(CONFIG_ARCH_MX3)		:= imx
 machine-$(CONFIG_ARCH_MX5)		:= mx5
 machine-$(CONFIG_ARCH_MXS)		:= mxs
diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-imx/Kconfig
index 0519dd7f034b..bdc634567800 100644
--- a/trunk/arch/arm/mach-imx/Kconfig
+++ b/trunk/arch/arm/mach-imx/Kconfig
@@ -5,6 +5,18 @@ config IMX_HAVE_DMA_V1
 # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
 # To easily distinguish good and reviewed from unreviewed usages new (and IMHO
 # more sensible) names are used: SOC_IMX31 and SOC_IMX35
+config ARCH_MX1
+	bool
+
+config MACH_MX21
+	bool
+
+config ARCH_MX25
+	bool
+
+config MACH_MX27
+	bool
+
 config ARCH_MX31
 	bool
 
@@ -13,6 +25,7 @@ config ARCH_MX35
 
 config SOC_IMX1
 	bool
+	select ARCH_MX1
 	select CPU_ARM920T
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
@@ -20,6 +33,7 @@ config SOC_IMX1
 
 config SOC_IMX21
 	bool
+	select MACH_MX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
@@ -28,6 +42,7 @@ config SOC_IMX21
 
 config SOC_IMX25
 	bool
+	select ARCH_MX25
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V2
 	select ARCH_MXC_IOMUX_V3
@@ -35,6 +50,7 @@ config SOC_IMX25
 
 config SOC_IMX27
 	bool
+	select MACH_MX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
@@ -59,7 +75,7 @@ config SOC_IMX35
 	select MXC_AVIC
 
 
-if ARCH_MX1
+if ARCH_IMX_V4_V5
 
 comment "MX1 platforms:"
 config MACH_MXLADS
@@ -87,30 +103,6 @@ config MACH_APF9328
 	help
 	  Say Yes here if you are using the Armadeus APF9328 development board
 
-endif
-
-if ARCH_MX2
-
-choice
-	prompt "CPUs:"
-	default MACH_MX21
-
-config MACH_MX21
-	bool "i.MX21 support"
-	help
-	  This enables support for Freescale's MX2 based i.MX21 processor.
-
-config MACH_MX27
-	bool "i.MX27 support"
-	help
-	  This enables support for Freescale's MX2 based i.MX27 processor.
-
-endchoice
-
-endif
-
-if MACH_MX21
-
 comment "MX21 platforms:"
 
 config MACH_MX21ADS
@@ -124,10 +116,6 @@ config MACH_MX21ADS
 	  Include support for MX21ADS platform. This includes specific
 	  configurations for the board and its peripherals.
 
-endif
-
-if ARCH_MX25
-
 comment "MX25 platforms:"
 
 config MACH_MX25_3DS
@@ -174,10 +162,6 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
 
 endchoice
 
-endif
-
-if MACH_MX27
-
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile
index 0a5332c694bd..e9eb36dad888 100644
--- a/trunk/arch/arm/mach-imx/Makefile
+++ b/trunk/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
diff --git a/trunk/arch/arm/mach-imx/clock-imx25.c b/trunk/arch/arm/mach-imx/clock-imx25.c
index b0fec74c8c91..e63e23504fe5 100644
--- a/trunk/arch/arm/mach-imx/clock-imx25.c
+++ b/trunk/arch/arm/mach-imx/clock-imx25.c
@@ -263,7 +263,6 @@ DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 DEFINE_CLOCK(can1_clk,	 0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(can2_clk,	 1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(iim_clk,    0, CCM_CGCR1, 26, NULL, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)	\
 	{				\
@@ -311,7 +310,6 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
 	/* i.mx25 has the i.mx35 type sdma */
 	_REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-	_REGISTER_CLOCK(NULL, "iim", iim_clk)
 };
 
 int __init mx25_clocks_init(void)
@@ -336,10 +334,6 @@ int __init mx25_clocks_init(void)
 	/* Clock source for gpt is ahb_div */
 	__raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
 
-	clk_enable(&iim_clk);
-	imx_print_silicon_rev("i.MX25", mx25_revision());
-	clk_disable(&iim_clk);
-
 	mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 
 	return 0;
diff --git a/trunk/arch/arm/mach-imx/clock-imx27.c b/trunk/arch/arm/mach-imx/clock-imx27.c
index e6b1beb4282c..6912b821b37b 100644
--- a/trunk/arch/arm/mach-imx/clock-imx27.c
+++ b/trunk/arch/arm/mach-imx/clock-imx27.c
@@ -751,8 +751,6 @@ int __init mx27_clocks_init(unsigned long fref)
 	clk_enable(&gpio_clk);
 	clk_enable(&emi_clk);
 	clk_enable(&iim_clk);
-	imx_print_silicon_rev("i.MX27", mx27_revision());
-	clk_disable(&iim_clk);
 
 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
 	clk_enable(&uart1_clk);
diff --git a/trunk/arch/arm/mach-imx/clock-imx31.c b/trunk/arch/arm/mach-imx/clock-imx31.c
index 85b8885cf345..d973770b1f96 100644
--- a/trunk/arch/arm/mach-imx/clock-imx31.c
+++ b/trunk/arch/arm/mach-imx/clock-imx31.c
@@ -611,11 +611,11 @@ int __init mx31_clocks_init(unsigned long fref)
 	clk_enable(&gpt_clk);
 	clk_enable(&emi_clk);
 	clk_enable(&iim_clk);
-	mx31_revision();
-	clk_disable(&iim_clk);
 
 	clk_enable(&serial_pll_clk);
 
+	mx31_read_cpu_rev();
+
 	if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
 		reg = __raw_readl(MXC_CCM_PMCR1);
 		/* No PLL restart on DVFS switch; enable auto EMI handshake */
diff --git a/trunk/arch/arm/mach-imx/clock-imx35.c b/trunk/arch/arm/mach-imx/clock-imx35.c
index abf30d48161f..88b62a071aea 100644
--- a/trunk/arch/arm/mach-imx/clock-imx35.c
+++ b/trunk/arch/arm/mach-imx/clock-imx35.c
@@ -537,8 +537,7 @@ int __init mx35_clocks_init()
 	__raw_writel(cgr3, CCM_BASE + CCM_CGR3);
 
 	clk_enable(&iim_clk);
-	imx_print_silicon_rev("i.MX35", mx35_revision());
-	clk_disable(&iim_clk);
+	mx35_read_cpu_rev();
 
 #ifdef CONFIG_MXC_USE_EPIT
 	epit_timer_init(&epit1_clk,
diff --git a/trunk/arch/arm/mach-imx/cpu-imx25.c b/trunk/arch/arm/mach-imx/cpu-imx25.c
deleted file mode 100644
index 6914bcbf84e4..000000000000
--- a/trunk/arch/arm/mach-imx/cpu-imx25.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * MX25 CPU type detection
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/iim.h>
-
-static int mx25_cpu_rev = -1;
-
-static int mx25_read_cpu_rev(void)
-{
-	u32 rev;
-
-	rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV));
-	switch (rev) {
-	case 0x00:
-		return IMX_CHIP_REVISION_1_0;
-	case 0x01:
-		return IMX_CHIP_REVISION_1_1;
-	default:
-		return IMX_CHIP_REVISION_UNKNOWN;
-	}
-}
-
-int mx25_revision(void)
-{
-	if (mx25_cpu_rev == -1)
-		mx25_cpu_rev = mx25_read_cpu_rev();
-
-	return mx25_cpu_rev;
-}
-EXPORT_SYMBOL(mx25_revision);
diff --git a/trunk/arch/arm/mach-imx/cpu-imx27.c b/trunk/arch/arm/mach-imx/cpu-imx27.c
index ff38e1505f67..3b117be37bd2 100644
--- a/trunk/arch/arm/mach-imx/cpu-imx27.c
+++ b/trunk/arch/arm/mach-imx/cpu-imx27.c
@@ -26,12 +26,12 @@
 
 #include <mach/hardware.h>
 
-static int mx27_cpu_rev = -1;
-static int mx27_cpu_partnumber;
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
 
 #define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
 
-static int mx27_read_cpu_rev(void)
+static void query_silicon_parameter(void)
 {
 	u32 val;
 	/*
@@ -42,18 +42,20 @@ static int mx27_read_cpu_rev(void)
 	val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
 				+ SYS_CHIP_ID));
 
-	mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
-
 	switch (val >> 28) {
 	case 0:
-		return IMX_CHIP_REVISION_1_0;
+		cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+		break;
 	case 1:
-		return IMX_CHIP_REVISION_2_0;
+		cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+		break;
 	case 2:
-		return IMX_CHIP_REVISION_2_1;
+		cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+		break;
 	default:
-		return IMX_CHIP_REVISION_UNKNOWN;
+		cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
 	}
+	cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }
 
 /*
@@ -63,12 +65,12 @@ static int mx27_read_cpu_rev(void)
  */
 int mx27_revision(void)
 {
-	if (mx27_cpu_rev == -1)
-		mx27_cpu_rev = mx27_read_cpu_rev();
+	if (cpu_silicon_rev == -1)
+		query_silicon_parameter();
 
-	if (mx27_cpu_partnumber != 0x8821)
+	if (cpu_partnumber != 0x8821)
 		return -EINVAL;
 
-	return mx27_cpu_rev;
+	return cpu_silicon_rev;
 }
 EXPORT_SYMBOL(mx27_revision);
diff --git a/trunk/arch/arm/mach-imx/cpu-imx31.c b/trunk/arch/arm/mach-imx/cpu-imx31.c
index 3f2345f0cdaf..a3780700a882 100644
--- a/trunk/arch/arm/mach-imx/cpu-imx31.c
+++ b/trunk/arch/arm/mach-imx/cpu-imx31.c
@@ -13,50 +13,45 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <mach/iim.h>
-#include <mach/common.h>
 
-static int mx31_cpu_rev = -1;
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
 
 static struct {
 	u8 srev;
 	const char *name;
+	const char *v;
 	unsigned int rev;
-} mx31_cpu_type[] = {
-	{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
-	{ .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-	{ .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-	{ .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
-	{ .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
-	{ .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
-	{ .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
-	{ .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
-	{ .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
+} mx31_cpu_type[] __initdata = {
+	{ .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0	},
+	{ .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1	},
+	{ .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
+	{ .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2	},
+	{ .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
+	{ .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0	},
 };
 
-static int mx31_read_cpu_rev(void)
+void __init mx31_read_cpu_rev(void)
 {
 	u32 i, srev;
 
 	/* read SREV register from IIM module */
 	srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
-	srev &= 0xff;
 
 	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
 		if (srev == mx31_cpu_type[i].srev) {
-			imx_print_silicon_rev(mx31_cpu_type[i].name,
-						mx31_cpu_type[i].rev);
-			return mx31_cpu_type[i].rev;
-		}
+			printk(KERN_INFO
+				"CPU identified as %s, silicon rev %s\n",
+				mx31_cpu_type[i].name, mx31_cpu_type[i].v);
 
-	imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
-	return IMX_CHIP_REVISION_UNKNOWN;
-}
+			mx31_cpu_rev = mx31_cpu_type[i].rev;
+			return;
+		}
 
-int mx31_revision(void)
-{
-	if (mx31_cpu_rev == -1)
-		mx31_cpu_rev = mx31_read_cpu_rev();
+	mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
 
-	return mx31_cpu_rev;
+	printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
-EXPORT_SYMBOL(mx31_revision);
diff --git a/trunk/arch/arm/mach-imx/cpu-imx35.c b/trunk/arch/arm/mach-imx/cpu-imx35.c
index 846e46eb8cbf..6637cd819ecb 100644
--- a/trunk/arch/arm/mach-imx/cpu-imx35.c
+++ b/trunk/arch/arm/mach-imx/cpu-imx35.c
@@ -13,30 +13,32 @@
 #include <mach/hardware.h>
 #include <mach/iim.h>
 
-static int mx35_cpu_rev = -1;
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
 
-static int mx35_read_cpu_rev(void)
+void __init mx35_read_cpu_rev(void)
 {
 	u32 rev;
+	char *srev;
 
 	rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
 	switch (rev) {
 	case 0x00:
-		return IMX_CHIP_REVISION_1_0;
+		mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
+		srev = "1.0";
+		break;
 	case 0x10:
-		return IMX_CHIP_REVISION_2_0;
+		mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
+		srev = "2.0";
+		break;
 	case 0x11:
-		return IMX_CHIP_REVISION_2_1;
+		mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
+		srev = "2.1";
+		break;
 	default:
-		return IMX_CHIP_REVISION_UNKNOWN;
+		mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+		srev = "unknown";
 	}
-}
-
-int mx35_revision(void)
-{
-	if (mx35_cpu_rev == -1)
-		mx35_cpu_rev = mx35_read_cpu_rev();
 
-	return mx35_cpu_rev;
+	printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
 }
-EXPORT_SYMBOL(mx35_revision);
diff --git a/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c b/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0e23e1d2af9c..f7bf996f463b 100644
--- a/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1548,8 +1548,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 	clk_enable(&main_bus_clk);
 
 	clk_enable(&iim_clk);
-	imx_print_silicon_rev("i.MX51", mx51_revision());
+	mx51_revision();
 	clk_disable(&iim_clk);
+	mx51_display_revision();
 
 	/* move usb_phy_clk to 24MHz */
 	clk_set_parent(&usb_phy1_clk, &osc_clk);
@@ -1591,8 +1592,9 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
 	clk_enable(&main_bus_clk);
 
 	clk_enable(&iim_clk);
-	imx_print_silicon_rev("i.MX53", mx53_revision());
+	mx53_revision();
 	clk_disable(&iim_clk);
+	mx53_display_revision();
 
 	/* Set SDHC parents to be PLL2 */
 	clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
diff --git a/trunk/arch/arm/mach-mx5/cpu.c b/trunk/arch/arm/mach-mx5/cpu.c
index 5c5328257dca..86f87da59c64 100644
--- a/trunk/arch/arm/mach-mx5/cpu.c
+++ b/trunk/arch/arm/mach-mx5/cpu.c
@@ -18,7 +18,7 @@
 #include <mach/hardware.h>
 #include <asm/io.h>
 
-static int mx5_cpu_rev = -1;
+static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
 #define MX50_HW_ADADIG_DIGPROG	0xB0
@@ -28,14 +28,11 @@ static int get_mx51_srev(void)
 	void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
 	u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-	switch (rev) {
-	case 0x0:
+	if (rev == 0x0)
 		return IMX_CHIP_REVISION_2_0;
-	case 0x10:
+	else if (rev == 0x10)
 		return IMX_CHIP_REVISION_3_0;
-	default:
-		return IMX_CHIP_REVISION_UNKNOWN;
-	}
+	return 0;
 }
 
 /*
@@ -48,13 +45,33 @@ int mx51_revision(void)
 	if (!cpu_is_mx51())
 		return -EINVAL;
 
-	if (mx5_cpu_rev == -1)
-		mx5_cpu_rev = get_mx51_srev();
+	if (cpu_silicon_rev == -1)
+		cpu_silicon_rev = get_mx51_srev();
 
-	return mx5_cpu_rev;
+	return cpu_silicon_rev;
 }
 EXPORT_SYMBOL(mx51_revision);
 
+void mx51_display_revision(void)
+{
+	int rev;
+	char *srev;
+	rev = mx51_revision();
+
+	switch (rev) {
+	case IMX_CHIP_REVISION_2_0:
+		srev = IMX_CHIP_REVISION_2_0_STRING;
+		break;
+	case IMX_CHIP_REVISION_3_0:
+		srev = IMX_CHIP_REVISION_3_0_STRING;
+		break;
+	default:
+		srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+	}
+	printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
 #ifdef CONFIG_NEON
 
 /*
@@ -104,10 +121,10 @@ int mx53_revision(void)
 	if (!cpu_is_mx53())
 		return -EINVAL;
 
-	if (mx5_cpu_rev == -1)
-		mx5_cpu_rev = get_mx53_srev();
+	if (cpu_silicon_rev == -1)
+		cpu_silicon_rev = get_mx53_srev();
 
-	return mx5_cpu_rev;
+	return cpu_silicon_rev;
 }
 EXPORT_SYMBOL(mx53_revision);
 
@@ -117,7 +134,7 @@ static int get_mx50_srev(void)
 	u32 rev;
 
 	if (!anatop) {
-		mx5_cpu_rev = -EINVAL;
+		cpu_silicon_rev = -EINVAL;
 		return 0;
 	}
 
@@ -142,13 +159,36 @@ int mx50_revision(void)
 	if (!cpu_is_mx50())
 		return -EINVAL;
 
-	if (mx5_cpu_rev == -1)
-		mx5_cpu_rev = get_mx50_srev();
+	if (cpu_silicon_rev == -1)
+		cpu_silicon_rev = get_mx50_srev();
 
-	return mx5_cpu_rev;
+	return cpu_silicon_rev;
 }
 EXPORT_SYMBOL(mx50_revision);
 
+void mx53_display_revision(void)
+{
+	int rev;
+	char *srev;
+	rev = mx53_revision();
+
+	switch (rev) {
+	case IMX_CHIP_REVISION_1_0:
+		srev = IMX_CHIP_REVISION_1_0_STRING;
+		break;
+	case IMX_CHIP_REVISION_2_0:
+		srev = IMX_CHIP_REVISION_2_0_STRING;
+		break;
+	case IMX_CHIP_REVISION_2_1:
+		srev = IMX_CHIP_REVISION_2_1_STRING;
+		break;
+	default:
+		srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+	}
+	printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx53_display_revision);
+
 static int __init post_cpu_init(void)
 {
 	unsigned int reg;
diff --git a/trunk/arch/arm/plat-mxc/Kconfig b/trunk/arch/arm/plat-mxc/Kconfig
index a5353fc0793f..0665c1f7e93d 100644
--- a/trunk/arch/arm/plat-mxc/Kconfig
+++ b/trunk/arch/arm/plat-mxc/Kconfig
@@ -14,20 +14,13 @@ choice
 	prompt "Freescale CPU family:"
 	default ARCH_MX3
 
-config ARCH_MX1
-	bool "MX1-based"
+config ARCH_IMX_V4_V5
+	bool "i.MX1, i.MX21, i.MX25, i.MX27"
+	select AUTO_ZRELADDR
+	select ARM_PATCH_PHYS_VIRT
 	help
-	  This enables support for systems based on the Freescale i.MX1 family
-
-config ARCH_MX2
-	bool "MX2-based"
-	help
-	  This enables support for systems based on the Freescale i.MX2 family
-
-config ARCH_MX25
-	bool "MX25-based"
-	help
-	  This enables support for systems based on the Freescale i.MX25 family
+	  This enables support for systems based on the Freescale i.MX ARMv4
+	  and ARMv5 SoCs
 
 config ARCH_MX3
 	bool "MX3-based"
diff --git a/trunk/arch/arm/plat-mxc/cpu.c b/trunk/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237f..386e0d52cf58 100644
--- a/trunk/arch/arm/plat-mxc/cpu.c
+++ b/trunk/arch/arm/plat-mxc/cpu.c
@@ -1,6 +1,5 @@
 
 #include <linux/module.h>
-#include <mach/hardware.h>
 
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
@@ -10,11 +9,3 @@ void mxc_set_cpu_type(unsigned int type)
 	__mxc_cpu_type = type;
 }
 
-void imx_print_silicon_rev(const char *cpu, int srev)
-{
-	if (srev == IMX_CHIP_REVISION_UNKNOWN)
-		pr_info("CPU identified as %s, unknown revision\n", cpu);
-	else
-		pr_info("CPU identified as %s, silicon rev %d.%d\n",
-				cpu, (srev >> 4) & 0xf, srev & 0xf);
-}
diff --git a/trunk/arch/arm/plat-mxc/include/mach/common.h b/trunk/arch/arm/plat-mxc/include/mach/common.h
index 318e0da13a79..4e3d97890d69 100644
--- a/trunk/arch/arm/plat-mxc/include/mach/common.h
+++ b/trunk/arch/arm/plat-mxc/include/mach/common.h
@@ -72,5 +72,4 @@ extern void mxc_arch_reset_init(void __iomem *);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
-extern void imx_print_silicon_rev(const char *cpu, int srev);
 #endif
diff --git a/trunk/arch/arm/plat-mxc/include/mach/memory.h b/trunk/arch/arm/plat-mxc/include/mach/memory.h
index 11be5cdbdd1a..cbe2e3d08067 100644
--- a/trunk/arch/arm/plat-mxc/include/mach/memory.h
+++ b/trunk/arch/arm/plat-mxc/include/mach/memory.h
@@ -21,15 +21,7 @@
 #define MX53_PHYS_OFFSET	UL(0x70000000)
 
 #if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
-# if defined CONFIG_ARCH_MX1
-#  define PLAT_PHYS_OFFSET		MX1_PHYS_OFFSET
-# elif defined CONFIG_MACH_MX21
-#  define PLAT_PHYS_OFFSET		MX21_PHYS_OFFSET
-# elif defined CONFIG_ARCH_MX25
-#  define PLAT_PHYS_OFFSET		MX25_PHYS_OFFSET
-# elif defined CONFIG_MACH_MX27
-#  define PLAT_PHYS_OFFSET		MX27_PHYS_OFFSET
-# elif defined CONFIG_ARCH_MX3
+# if defined CONFIG_ARCH_MX3
 #  define PLAT_PHYS_OFFSET		MX3x_PHYS_OFFSET
 # elif defined CONFIG_ARCH_MX50
 #  define PLAT_PHYS_OFFSET		MX50_PHYS_OFFSET
diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx25.h b/trunk/arch/arm/plat-mxc/include/mach/mx25.h
index 8dcab80acff3..087cd7ac8d52 100644
--- a/trunk/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/trunk/arch/arm/plat-mxc/include/mach/mx25.h
@@ -104,8 +104,4 @@
 #define MX25_DMA_REQ_SSI1_RX0	28
 #define MX25_DMA_REQ_SSI1_TX0	29
 
-#ifndef __ASSEMBLY__
-extern int mx25_revision(void);
-#endif
-
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/trunk/arch/arm/plat-mxc/include/mach/mx3x.h b/trunk/arch/arm/plat-mxc/include/mach/mx3x.h
index 30dbf424583e..388a407d72d6 100644
--- a/trunk/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/trunk/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -187,8 +187,22 @@
 /* Mandatory defines used globally */
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern int mx35_revision(void);
-extern int mx31_revision(void);
+
+extern unsigned int mx31_cpu_rev;
+extern void mx31_read_cpu_rev(void);
+
+static inline int mx31_revision(void)
+{
+	return mx31_cpu_rev;
+}
+
+extern unsigned int mx35_cpu_rev;
+extern void mx35_read_cpu_rev(void);
+
+static inline int mx35_revision(void)
+{
+	return mx35_cpu_rev;
+}
 #endif
 
 #endif /* ifndef __MACH_MX3x_H__ */