diff --git a/[refs] b/[refs] index 075581dd9585..4cc2341cb66e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f6940610c76e9a6dbb23cef51b64fd48877b68df +refs/heads/master: 7c3c1b8c90e0f226610b9932cd66678d99e42176 diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio.txt index d933af370697..a33628759d36 100644 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio.txt @@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; reg = <0x1460 0x18>; gpio-controller; - gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; + gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; } @@ -107,8 +107,8 @@ where, Next values specify the base pin and number of pins for the range handled by 'qe_pio_e' gpio. In the given example from base pin 20 to - pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under - pinctrl2 with gpio offset 10 is handled by this gpio controller. + pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled + by this gpio controller. The pinctrl node must have "#gpio-range-cells" property to show number of arguments to pass with phandle from gpio controllers node. diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index fa1746b639b9..2c81e45f1374 100644 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,9 +1,7 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" or "pinconf-single". - "pinctrl-single" means that pinconf isn't supported. - "pinconf-single" means that generic pinconf is supported. +- compatible : "pinctrl-single" - reg : offset and length of the register set for the mux registers @@ -16,61 +14,9 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored - - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin -- pinctrl-single,drive-strength : array of value that are used to configure - drive strength in the pinmux register. They're value of drive strength - current and drive strength mask. - - /* drive strength current, mask */ - pinctrl-single,power-source = <0x30 0xf0>; - -- pinctrl-single,bias-pullup : array of value that are used to configure the - input bias pullup in the pinmux register. - - /* input, enabled pullup bits, disabled pullup bits, mask */ - pinctrl-single,bias-pullup = <0 1 0 1>; - -- pinctrl-single,bias-pulldown : array of value that are used to configure the - input bias pulldown in the pinmux register. - - /* input, enabled pulldown bits, disabled pulldown bits, mask */ - pinctrl-single,bias-pulldown = <2 2 0 2>; - - * Two bits to control input bias pullup and pulldown: User should use - pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means - pullup, and the other one bit means pulldown. - * Three bits to control input bias enable, pullup and pulldown. User should - use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias - enable bit should be included in pullup or pulldown bits. - * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as - pinctrl-single,bias-disable. Because pinctrl single driver could implement - it by calling pulldown, pullup disabled. - -- pinctrl-single,input-schmitt : array of value that are used to configure - input schmitt in the pinmux register. In some silicons, there're two input - schmitt value (rising-edge & falling-edge) in the pinmux register. - - /* input schmitt value, mask */ - pinctrl-single,input-schmitt = <0x30 0x70>; - -- pinctrl-single,input-schmitt-enable : array of value that are used to - configure input schmitt enable or disable in the pinmux register. - - /* input, enable bits, disable bits, mask */ - pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; - -- pinctrl-single,gpio-range : list of value that are used to configure a GPIO - range. They're value of subnode phandle, pin base in pinctrl device, pin - number in this range, GPIO function value of this GPIO range. - The number of parameters is depend on #pinctrl-single,gpio-range-cells - property. - - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; - This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -96,20 +42,6 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. - -Optional sub-node: In case some pins could be configured as GPIO in the pinmux -register, those pins could be defined as a GPIO range. This sub-node is required -by pinctrl-single,gpio-range property. - -Required properties in sub-node: -- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in - pinctrl-single,gpio-range property. - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - Example: /* SoC common file */ @@ -144,29 +76,6 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; -/* third controller instance for pins in gpio domain */ -pmx_gpio: pinmux@d401e000 { - compatible = "pinconf-single"; - reg = <0xd401e000 0x0330>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - - /* sparse GPIO range could be supported */ - pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 - &range 12 1 0 &range 13 29 1 - &range 43 1 0 &range 44 49 1 - &range 94 1 1 &range 96 2 1>; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - - /* board specific .dts file */ &pmx_core { @@ -187,15 +96,6 @@ pmx_gpio: pinmux@d401e000 { >; }; - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - 0x208 0 /* UART0_RXD (IOCFG138) */ - 0x20c 0 /* UART0_TXD (IOCFG139) */ - >; - pinctrl-single,bias-pulldown = <0 2 2>; - pinctrl-single,bias-pullup = <0 1 1>; - }; - /* map uart2 pins */ uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < @@ -222,11 +122,6 @@ pmx_gpio: pinmux@d401e000 { }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; diff --git a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt deleted file mode 100644 index 993695c659e1..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt +++ /dev/null @@ -1,17 +0,0 @@ -Cadence TTC - Triple Timer Counter - -Required properties: -- compatible : Should be "cdns,ttc". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 3 interrupts; one per timer channel. -- clocks: phandle to the source clock - -Example: - -ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; - reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; -}; diff --git a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt index 4499bd948860..95731a08f257 100644 --- a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt +++ b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt @@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. enable_msi - Enable Message Signaled Interrupt (MSI) (default = off) power_save - Automatic power-saving timeout (in second, 0 = disable) - power_save_controller - Support runtime D3 of HD-audio controller - (-1 = on for supported chip (default), false = off, - true = force to on even for unsupported hardware) + power_save_controller - Reset HD-audio controller in power-saving mode + (default = on) align_buffer_size - Force rounding of buffer/period sizes to multiples of 128 bytes. This is more efficient in terms of memory access but isn't required by the HDA spec and prevents diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 74e58a4d035b..836a6183c37f 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -5065,9 +5065,8 @@ S: Maintained F: drivers/net/ethernet/marvell/sk* MARVELL LIBERTAS WIRELESS DRIVER -M: Dan Williams L: libertas-dev@lists.infradead.org -S: Maintained +S: Orphan F: drivers/net/wireless/libertas/ MARVELL MV643XX ETHERNET DRIVER @@ -5569,6 +5568,7 @@ F: include/uapi/linux/if_* F: include/uapi/linux/netdevice.h NETXEN (1/10) GbE SUPPORT +M: Manish Chopra M: Sony Chacko M: Rajesh Borundia L: netdev@vger.kernel.org diff --git a/trunk/Makefile b/trunk/Makefile index 58a165b02af1..6db672b15bda 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 9 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc6 NAME = Unicycling Gorilla # *DOCUMENTATION* diff --git a/trunk/arch/alpha/Makefile b/trunk/arch/alpha/Makefile index 4759fe751aa1..2cc3cc519c54 100644 --- a/trunk/arch/alpha/Makefile +++ b/trunk/arch/alpha/Makefile @@ -12,7 +12,7 @@ NM := $(NM) -B LDFLAGS_vmlinux := -static -N #-relax CHECKFLAGS += -D__alpha__ -m64 -cflags-y := -pipe -mno-fp-regs -ffixed-8 -msmall-data +cflags-y := -pipe -mno-fp-regs -ffixed-8 cflags-y += $(call cc-option, -fno-jump-tables) cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4 diff --git a/trunk/arch/alpha/include/asm/floppy.h b/trunk/arch/alpha/include/asm/floppy.h index 46cefbd50e73..bae97eb19d26 100644 --- a/trunk/arch/alpha/include/asm/floppy.h +++ b/trunk/arch/alpha/include/asm/floppy.h @@ -26,7 +26,7 @@ #define fd_disable_irq() disable_irq(FLOPPY_IRQ) #define fd_cacheflush(addr,size) /* nothing */ #define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt,\ - IRQF_DISABLED, "floppy", NULL) + 0, "floppy", NULL) #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) #ifdef CONFIG_PCI diff --git a/trunk/arch/alpha/kernel/irq.c b/trunk/arch/alpha/kernel/irq.c index 2872accd2215..7b2be251c30f 100644 --- a/trunk/arch/alpha/kernel/irq.c +++ b/trunk/arch/alpha/kernel/irq.c @@ -117,13 +117,6 @@ handle_irq(int irq) return; } - /* - * From here we must proceed with IPL_MAX. Note that we do not - * explicitly enable interrupts afterwards - some MILO PALcode - * (namely LX164 one) seems to have severe problems with RTI - * at IPL 0. - */ - local_irq_disable(); irq_enter(); generic_handle_irq_desc(irq, desc); irq_exit(); diff --git a/trunk/arch/alpha/kernel/irq_alpha.c b/trunk/arch/alpha/kernel/irq_alpha.c index 772ddfdb71a8..f433fc11877a 100644 --- a/trunk/arch/alpha/kernel/irq_alpha.c +++ b/trunk/arch/alpha/kernel/irq_alpha.c @@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector, unsigned long la_ptr, struct pt_regs *regs) { struct pt_regs *old_regs; + + /* + * Disable interrupts during IRQ handling. + * Note that there is no matching local_irq_enable() due to + * severe problems with RTI at IPL0 and some MILO PALcode + * (namely LX164). + */ + local_irq_disable(); switch (type) { case 0: #ifdef CONFIG_SMP @@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector, { long cpu; - local_irq_disable(); smp_percpu_timer_interrupt(regs); cpu = smp_processor_id(); if (cpu != boot_cpuid) { @@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr, struct irqaction timer_irqaction = { .handler = timer_interrupt, - .flags = IRQF_DISABLED, .name = "timer", }; diff --git a/trunk/arch/alpha/kernel/sys_nautilus.c b/trunk/arch/alpha/kernel/sys_nautilus.c index 4d4c046f708d..1383f8601a93 100644 --- a/trunk/arch/alpha/kernel/sys_nautilus.c +++ b/trunk/arch/alpha/kernel/sys_nautilus.c @@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr) extern void free_reserved_mem(void *, void *); extern void pcibios_claim_one_bus(struct pci_bus *); +static struct resource irongate_io = { + .name = "Irongate PCI IO", + .flags = IORESOURCE_IO, +}; static struct resource irongate_mem = { .name = "Irongate PCI MEM", .flags = IORESOURCE_MEM, @@ -209,6 +213,7 @@ nautilus_init_pci(void) irongate = pci_get_bus_and_slot(0, 0); bus->self = irongate; + bus->resource[0] = &irongate_io; bus->resource[1] = &irongate_mem; pci_bus_size_bridges(bus); diff --git a/trunk/arch/alpha/kernel/sys_titan.c b/trunk/arch/alpha/kernel/sys_titan.c index 5cf4a481b8c5..a53cf03f49d5 100644 --- a/trunk/arch/alpha/kernel/sys_titan.c +++ b/trunk/arch/alpha/kernel/sys_titan.c @@ -280,15 +280,15 @@ titan_late_init(void) * all reported to the kernel as machine checks, so the handler * is a nop so it can be called to count the individual events. */ - titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(63+16, titan_intr_nop, 0, "CChip Error", NULL); - titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(62+16, titan_intr_nop, 0, "PChip 0 H_Error", NULL); - titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(61+16, titan_intr_nop, 0, "PChip 1 H_Error", NULL); - titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(60+16, titan_intr_nop, 0, "PChip 0 C_Error", NULL); - titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(59+16, titan_intr_nop, 0, "PChip 1 C_Error", NULL); /* @@ -348,9 +348,9 @@ privateer_init_pci(void) * Hook a couple of extra err interrupts that the * common titan code won't. */ - titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(53+16, titan_intr_nop, 0, "NMI", NULL); - titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(50+16, titan_intr_nop, 0, "Temperature Warning", NULL); /* diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 11680092e407..1cacda426a0e 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -723,7 +723,7 @@ config ARCH_SHMOBILE select MULTI_IRQ_HANDLER select NEED_MACH_MEMORY_H select NO_IOPORT - select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL select PM_GENERIC_DOMAINS if PM select SPARSE_IRQ help @@ -1183,9 +1183,9 @@ config ARM_NR_BANKS default 8 config IWMMXT - bool "Enable iWMMXt support" + bool "Enable iWMMXt support" if !CPU_PJ4 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 - default y if PXA27x || PXA3xx || ARCH_MMP + default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420 to deadlock. This workaround puts DSB before executing ISB if an abort may occur on cache maintenance. +config ARM_ERRATA_798181 + bool "ARM errata: TLBI/DSB failure on Cortex-A15" + depends on CPU_V7 && SMP + help + On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not + adequately shooting down all use of the old entries. This + option enables the Linux kernel workaround for this erratum + which sends an IPI to the CPUs that are running the same ASID + as the one being invalidated. + endmenu source "arch/arm/common/Kconfig" @@ -1593,7 +1603,6 @@ config HAVE_ARM_ARCH_TIMER config HAVE_ARM_TWD bool depends on SMP - select CLKSRC_OF if OF help This options enables support for the ARM timer and watchdog unit diff --git a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..3234875824dc 100644 --- a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts @@ -54,7 +54,7 @@ }; mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins2>; + pinctrl-0 = <&sdio_pins3>; pinctrl-names = "default"; status = "okay"; /* diff --git a/trunk/arch/arm/boot/dts/armada-370.dtsi b/trunk/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..a195debb67d3 100644 --- a/trunk/arch/arm/boot/dts/armada-370.dtsi +++ b/trunk/arch/arm/boot/dts/armada-370.dtsi @@ -59,6 +59,12 @@ "mpp50", "mpp51", "mpp52"; marvell,function = "sd0"; }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; }; gpio0: gpio@d0018100 { diff --git a/trunk/arch/arm/boot/dts/dbx5x0.dtsi b/trunk/arch/arm/boot/dts/dbx5x0.dtsi index 9de93096601a..aaa63d0a8096 100644 --- a/trunk/arch/arm/boot/dts/dbx5x0.dtsi +++ b/trunk/arch/arm/boot/dts/dbx5x0.dtsi @@ -191,8 +191,8 @@ prcmu: prcmu@80157000 { compatible = "stericsson,db8500-prcmu"; - reg = <0x80157000 0x1000>; - reg-names = "prcmu"; + reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; interrupts = <0 47 0x4>; #address-cells = <1>; #size-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/imx6qdl.dtsi b/trunk/arch/arm/boot/dts/imx6qdl.dtsi index 06ec460b4581..281a223591ff 100644 --- a/trunk/arch/arm/boot/dts/imx6qdl.dtsi +++ b/trunk/arch/arm/boot/dts/imx6qdl.dtsi @@ -91,6 +91,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; interrupts = <1 13 0xf01>; + clocks = <&clks 15>; }; L2: l2-cache@00a02000 { diff --git a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -77,6 +77,7 @@ }; nand@3000000 { + chip-delay = <40>; status = "okay"; partition@0 { diff --git a/trunk/arch/arm/boot/dts/orion5x.dtsi b/trunk/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..f7bec3b1ba32 100644 --- a/trunk/arch/arm/boot/dts/orion5x.dtsi +++ b/trunk/arch/arm/boot/dts/orion5x.dtsi @@ -13,6 +13,9 @@ compatible = "marvell,orion5x"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + }; intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller; @@ -32,7 +35,9 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; interrupts = <6>, <7>, <8>, <9>; }; @@ -91,7 +96,7 @@ reg = <0x90000 0x10000>, <0xf2200000 0x800>; reg-names = "regs", "sram"; - interrupts = <22>; + interrupts = <28>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/r8a73a4.dtsi b/trunk/arch/arm/boot/dts/r8a73a4.dtsi deleted file mode 100644 index fde2a337d1ff..000000000000 --- a/trunk/arch/arm/boot/dts/r8a73a4.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Device Tree Source for the r8a73a4 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - compatible = "renesas,r8a73a4"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; - - gic-cpuif@4 { - compatible = "arm,gic-cpuif"; - cpuif-id = <4>; - cpu = <&cpu0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, - <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, - <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, - <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, - <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, - <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, - <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; - }; - - irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0200 0 0x200>; - interrupt-parent = <&gic>; - interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, - <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, - <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, - <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, - <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, - <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, - <0 56 4>, <0 57 4>; - }; - - thermal@e61f0000 { - compatible = "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, - <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; - interrupt-parent = <&gic>; - interrupts = <0 69 4>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/r8a7778.dtsi b/trunk/arch/arm/boot/dts/r8a7778.dtsi deleted file mode 100644 index 474373559bdc..000000000000 --- a/trunk/arch/arm/boot/dts/r8a7778.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Device Tree Source for Renesas r8a7778 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,r8a7778"; - - cpus { - cpu@0 { - compatible = "arm,cortex-a9"; - }; - }; - - gic: interrupt-controller@fe438000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfe438000 0x1000>, - <0xfe430000 0x100>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/r8a7779.dtsi b/trunk/arch/arm/boot/dts/r8a7779.dtsi deleted file mode 100644 index fe5c6f213271..000000000000 --- a/trunk/arch/arm/boot/dts/r8a7779.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Device Tree Source for Renesas r8a7779 - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Simon Horman - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "renesas,r8a7779"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - }; - }; - - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; - - i2c0: i2c@0xffc70000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc70000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 79 0x4>; - }; - - i2c1: i2c@0xffc71000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc71000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 82 0x4>; - }; - - i2c2: i2c@0xffc72000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc72000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 80 0x4>; - }; - - i2c3: i2c@0xffc73000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0xffc73000 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 81 0x4>; - }; - - thermal@ffc48000 { - compatible = "renesas,rcar-thermal"; - reg = <0xffc48000 0x38>; - }; - - sata: sata@fc600000 { - compatible = "renesas,rcar-sata"; - reg = <0xfc600000 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 100 0x4>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/r8a7790.dtsi b/trunk/arch/arm/boot/dts/r8a7790.dtsi deleted file mode 100644 index 7a1711027e41..000000000000 --- a/trunk/arch/arm/boot/dts/r8a7790.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Device Tree Source for the r8a7790 SoC - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/ { - compatible = "renesas,r8a7790"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; - - gic-cpuif@4 { - compatible = "arm,gic-cpuif"; - cpuif-id = <4>; - cpu = <&cpu0>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/sh73a0.dtsi b/trunk/arch/arm/boot/dts/sh73a0.dtsi index 7e71e3a85767..8a59465d0231 100644 --- a/trunk/arch/arm/boot/dts/sh73a0.dtsi +++ b/trunk/arch/arm/boot/dts/sh73a0.dtsi @@ -38,87 +38,6 @@ <0xf0000100 0x100>; }; - irqpin0: irqpin@e6900000 { - compatible = "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900000 4>, - <0xe6900010 4>, - <0xe6900020 1>, - <0xe6900040 1>, - <0xe6900060 1>; - interrupt-parent = <&gic>; - interrupts = <0 1 0x4 - 0 2 0x4 - 0 3 0x4 - 0 4 0x4 - 0 5 0x4 - 0 6 0x4 - 0 7 0x4 - 0 8 0x4>; - }; - - irqpin1: irqpin@e6900004 { - compatible = "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupt-parent = <&gic>; - interrupts = <0 9 0x4 - 0 10 0x4 - 0 11 0x4 - 0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4 - 0 16 0x4>; - control-parent; - }; - - irqpin2: irqpin@e6900008 { - compatible = "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900008 4>, - <0xe6900018 4>, - <0xe6900028 1>, - <0xe6900048 1>, - <0xe6900068 1>; - interrupt-parent = <&gic>; - interrupts = <0 17 0x4 - 0 18 0x4 - 0 19 0x4 - 0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4 - 0 24 0x4>; - }; - - irqpin3: irqpin@e690000c { - compatible = "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe690000c 4>, - <0xe690001c 4>, - <0xe690002c 1>, - <0xe690004c 1>, - <0xe690006c 1>; - interrupt-parent = <&gic>; - interrupts = <0 25 0x4 - 0 26 0x4 - 0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4 - 0 31 0x4 - 0 32 0x4>; - }; - i2c0: i2c@0xe6820000 { #address-cells = <1>; #size-cells = <0>; diff --git a/trunk/arch/arm/boot/dts/spear1310.dtsi b/trunk/arch/arm/boot/dts/spear1310.dtsi index 122ae94076c8..1513c1927cc8 100644 --- a/trunk/arch/arm/boot/dts/spear1310.dtsi +++ b/trunk/arch/arm/boot/dts/spear1310.dtsi @@ -89,7 +89,7 @@ pinmux: pinmux@e0700000 { compatible = "st,spear1310-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; + #gpio-range-cells = <2>; }; apb { @@ -212,7 +212,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 246>; + gpio-ranges = <&pinmux 0 246>; status = "disabled"; st-plgpio,ngpio = <246>; diff --git a/trunk/arch/arm/boot/dts/spear1340.dtsi b/trunk/arch/arm/boot/dts/spear1340.dtsi index c511c4772efd..34da11aa6795 100644 --- a/trunk/arch/arm/boot/dts/spear1340.dtsi +++ b/trunk/arch/arm/boot/dts/spear1340.dtsi @@ -63,7 +63,7 @@ pinmux: pinmux@e0700000 { compatible = "st,spear1340-pinmux"; reg = <0xe0700000 0x1000>; - #gpio-range-cells = <3>; + #gpio-range-cells = <2>; }; pwm: pwm@e0180000 { @@ -127,7 +127,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 252>; + gpio-ranges = <&pinmux 0 252>; status = "disabled"; st-plgpio,ngpio = <250>; diff --git a/trunk/arch/arm/boot/dts/spear310.dtsi b/trunk/arch/arm/boot/dts/spear310.dtsi index 95372080eea6..ab45b8c81982 100644 --- a/trunk/arch/arm/boot/dts/spear310.dtsi +++ b/trunk/arch/arm/boot/dts/spear310.dtsi @@ -25,7 +25,7 @@ pinmux: pinmux@b4000000 { compatible = "st,spear310-pinmux"; reg = <0xb4000000 0x1000>; - #gpio-range-cells = <3>; + #gpio-range-cells = <2>; }; fsmc: flash@44000000 { @@ -102,7 +102,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; + gpio-ranges = <&pinmux 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/trunk/arch/arm/boot/dts/spear320.dtsi b/trunk/arch/arm/boot/dts/spear320.dtsi index ffea342aeec9..caa5520b1fd4 100644 --- a/trunk/arch/arm/boot/dts/spear320.dtsi +++ b/trunk/arch/arm/boot/dts/spear320.dtsi @@ -24,7 +24,7 @@ pinmux: pinmux@b3000000 { compatible = "st,spear320-pinmux"; reg = <0xb3000000 0x1000>; - #gpio-range-cells = <3>; + #gpio-range-cells = <2>; }; clcd@90000000 { @@ -130,7 +130,7 @@ interrupt-controller; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinmux 0 0 102>; + gpio-ranges = <&pinmux 0 102>; status = "disabled"; st-plgpio,ngpio = <102>; diff --git a/trunk/arch/arm/boot/dts/zynq-7000.dtsi b/trunk/arch/arm/boot/dts/zynq-7000.dtsi index 2a1df1bc4b99..5914b5654591 100644 --- a/trunk/arch/arm/boot/dts/zynq-7000.dtsi +++ b/trunk/arch/arm/boot/dts/zynq-7000.dtsi @@ -111,30 +111,56 @@ }; ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; reg = <0xF8001000 0x1000>; clocks = <&cpu_clk 3>; clock-names = "cpu_1x"; clock-ranges; + + ttc0_0: ttc0.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 10 4>; + }; + ttc0_1: ttc0.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 11 4>; + }; + ttc0_2: ttc0.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 12 4>; + }; }; ttc1: ttc1@f8002000 { - interrupt-parent = <&intc>; - interrupts = < 0 37 4 0 38 4 0 39 4 >; - compatible = "cdns,ttc"; + #interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,ttc"; reg = <0xF8002000 0x1000>; clocks = <&cpu_clk 3>; clock-names = "cpu_1x"; clock-ranges; + + ttc1_0: ttc1.0 { + status = "disabled"; + reg = <0>; + interrupts = <0 37 4>; + }; + ttc1_1: ttc1.1 { + status = "disabled"; + reg = <1>; + interrupts = <0 38 4>; + }; + ttc1_2: ttc1.2 { + status = "disabled"; + reg = <2>; + interrupts = <0 39 4>; + }; }; - scutimer: scutimer@f8f00600 { - interrupt-parent = <&intc>; - interrupts = < 1 13 0x301 >; - compatible = "arm,cortex-a9-twd-timer"; - reg = < 0xf8f00600 0x20 >; - clocks = <&cpu_clk 1>; - } ; }; }; diff --git a/trunk/arch/arm/boot/dts/zynq-zc702.dts b/trunk/arch/arm/boot/dts/zynq-zc702.dts index 86f44d5b0265..c772942a399a 100644 --- a/trunk/arch/arm/boot/dts/zynq-zc702.dts +++ b/trunk/arch/arm/boot/dts/zynq-zc702.dts @@ -32,3 +32,13 @@ &ps_clk { clock-frequency = <33333330>; }; + +&ttc0_0 { + status = "ok"; + compatible = "xlnx,ttc-counter-clocksource"; +}; + +&ttc0_1 { + status = "ok"; + compatible = "xlnx,ttc-counter-clockevent"; +}; diff --git a/trunk/arch/arm/include/asm/delay.h b/trunk/arch/arm/include/asm/delay.h index 720799fd3a81..dff714d886d5 100644 --- a/trunk/arch/arm/include/asm/delay.h +++ b/trunk/arch/arm/include/asm/delay.h @@ -24,7 +24,7 @@ extern struct arm_delay_ops { void (*delay)(unsigned long); void (*const_udelay)(unsigned long); void (*udelay)(unsigned long); - bool const_clock; + unsigned long ticks_per_jiffy; } arm_delay_ops; #define __delay(n) arm_delay_ops.delay(n) diff --git a/trunk/arch/arm/include/asm/highmem.h b/trunk/arch/arm/include/asm/highmem.h index 8c5e828f484d..91b99abe7a95 100644 --- a/trunk/arch/arm/include/asm/highmem.h +++ b/trunk/arch/arm/include/asm/highmem.h @@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page); #endif #endif +/* + * Needed to be able to broadcast the TLB invalidation for kmap. + */ +#ifdef CONFIG_ARM_ERRATA_798181 +#undef ARCH_NEEDS_KMAP_HIGH_GET +#endif + #ifdef ARCH_NEEDS_KMAP_HIGH_GET extern void *kmap_high_get(struct page *page); #else diff --git a/trunk/arch/arm/include/asm/irq.h b/trunk/arch/arm/include/asm/irq.h index 53c15dec7af6..35c21c375d81 100644 --- a/trunk/arch/arm/include/asm/irq.h +++ b/trunk/arch/arm/include/asm/irq.h @@ -30,11 +30,6 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); -#ifdef CONFIG_MULTI_IRQ_HANDLER -extern void (*handle_arch_irq)(struct pt_regs *); -extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); -#endif - #endif #endif diff --git a/trunk/arch/arm/include/asm/mach/irq.h b/trunk/arch/arm/include/asm/mach/irq.h index 2092ee1e1300..18c883023339 100644 --- a/trunk/arch/arm/include/asm/mach/irq.h +++ b/trunk/arch/arm/include/asm/mach/irq.h @@ -20,6 +20,11 @@ struct seq_file; extern void init_FIQ(int); extern int show_fiq_list(struct seq_file *, int); +#ifdef CONFIG_MULTI_IRQ_HANDLER +extern void (*handle_arch_irq)(struct pt_regs *); +extern void set_handle_irq(void (*handle_irq)(struct pt_regs *)); +#endif + /* * This is for easy migration, but should be changed in the source */ @@ -30,4 +35,35 @@ do { \ raw_spin_unlock(&desc->lock); \ } while(0) +#ifndef __ASSEMBLY__ +/* + * Entry/exit functions for chained handlers where the primary IRQ chip + * may implement either fasteoi or level-trigger flow control. + */ +static inline void chained_irq_enter(struct irq_chip *chip, + struct irq_desc *desc) +{ + /* FastEOI controllers require no action on entry. */ + if (chip->irq_eoi) + return; + + if (chip->irq_mask_ack) { + chip->irq_mask_ack(&desc->irq_data); + } else { + chip->irq_mask(&desc->irq_data); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + } +} + +static inline void chained_irq_exit(struct irq_chip *chip, + struct irq_desc *desc) +{ + if (chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + else + chip->irq_unmask(&desc->irq_data); +} +#endif + #endif diff --git a/trunk/arch/arm/include/asm/mmu_context.h b/trunk/arch/arm/include/asm/mmu_context.h index 863a6611323c..a7b85e0d0cc1 100644 --- a/trunk/arch/arm/include/asm/mmu_context.h +++ b/trunk/arch/arm/include/asm/mmu_context.h @@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) +DECLARE_PER_CPU(atomic64_t, active_asids); + #else /* !CONFIG_CPU_HAS_ASID */ #ifdef CONFIG_MMU diff --git a/trunk/arch/arm/include/asm/smp_twd.h b/trunk/arch/arm/include/asm/smp_twd.h index 7b2899c2f7fc..0f01f4677bd2 100644 --- a/trunk/arch/arm/include/asm/smp_twd.h +++ b/trunk/arch/arm/include/asm/smp_twd.h @@ -34,4 +34,12 @@ struct twd_local_timer name __initdata = { \ int twd_local_timer_register(struct twd_local_timer *); +#ifdef CONFIG_HAVE_ARM_TWD +void twd_local_timer_of_register(void); +#else +static inline void twd_local_timer_of_register(void) +{ +} +#endif + #endif diff --git a/trunk/arch/arm/include/asm/tlbflush.h b/trunk/arch/arm/include/asm/tlbflush.h index 4db8c8820f0d..9e9c041358ca 100644 --- a/trunk/arch/arm/include/asm/tlbflush.h +++ b/trunk/arch/arm/include/asm/tlbflush.h @@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void) isb(); } +#ifdef CONFIG_ARM_ERRATA_798181 +static inline void dummy_flush_tlb_a15_erratum(void) +{ + /* + * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. + */ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(); +} +#else +static inline void dummy_flush_tlb_a15_erratum(void) +{ +} +#endif + /* * flush_pmd_entry * diff --git a/trunk/arch/arm/kernel/entry-common.S b/trunk/arch/arm/kernel/entry-common.S index 3248cde504ed..fefd7f971437 100644 --- a/trunk/arch/arm/kernel/entry-common.S +++ b/trunk/arch/arm/kernel/entry-common.S @@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old) */ .macro mcount_enter +/* + * This pad compensates for the push {lr} at the call site. Note that we are + * unable to unwind through a function which does not otherwise save its lr. + */ + UNWIND(.pad #4) stmdb sp!, {r0-r3, lr} + UNWIND(.save {r0-r3, lr}) .endm .macro mcount_get_lr reg @@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old) .endm ENTRY(__gnu_mcount_nc) +UNWIND(.fnstart) #ifdef CONFIG_DYNAMIC_FTRACE mov ip, lr ldmia sp!, {lr} @@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc) #else __mcount #endif +UNWIND(.fnend) ENDPROC(__gnu_mcount_nc) #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(ftrace_caller) +UNWIND(.fnstart) __ftrace_caller +UNWIND(.fnend) ENDPROC(ftrace_caller) #endif #ifdef CONFIG_FUNCTION_GRAPH_TRACER ENTRY(ftrace_graph_caller) +UNWIND(.fnstart) __ftrace_graph_caller +UNWIND(.fnend) ENDPROC(ftrace_graph_caller) #endif diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index e0eb9a1cae77..8bac553fe213 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -267,7 +267,7 @@ __create_page_tables: addne r6, r6, #1 << SECTION_SHIFT strne r6, [r3] -#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) +#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) sub r4, r4, #4 @ Fixup page table pointer @ for 64-bit descriptors #endif diff --git a/trunk/arch/arm/kernel/hw_breakpoint.c b/trunk/arch/arm/kernel/hw_breakpoint.c index 96093b75ab90..5dc1aa6f0f7d 100644 --- a/trunk/arch/arm/kernel/hw_breakpoint.c +++ b/trunk/arch/arm/kernel/hw_breakpoint.c @@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused) } if (err) { - pr_warning("CPU %d debug is powered down!\n", cpu); + pr_warn_once("CPU %d debug is powered down!\n", cpu); cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); return; } @@ -987,7 +987,7 @@ static void reset_ctrl_regs(void *unused) isb(); if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { - pr_warning("CPU %d failed to disable vector catch\n", cpu); + pr_warn_once("CPU %d failed to disable vector catch\n", cpu); return; } @@ -1007,7 +1007,7 @@ static void reset_ctrl_regs(void *unused) } if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { - pr_warning("CPU %d failed to clear debug register pairs\n", cpu); + pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu); return; } diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index 3f6cbb2e3eda..d343a6c3a6d1 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...) printk("%s", buf); } +static void __init cpuid_init_hwcaps(void) +{ + unsigned int divide_instrs; + + if (cpu_architecture() < CPU_ARCH_ARMv7) + return; + + divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; + + switch (divide_instrs) { + case 2: + elf_hwcap |= HWCAP_IDIVA; + case 1: + elf_hwcap |= HWCAP_IDIVT; + } +} + static void __init feat_v6_fixup(void) { int id = read_cpuid_id(); @@ -483,8 +500,11 @@ static void __init setup_processor(void) snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", list->elf_name, ENDIANNESS); elf_hwcap = list->elf_hwcap; + + cpuid_init_hwcaps(); + #ifndef CONFIG_ARM_THUMB - elf_hwcap &= ~HWCAP_THUMB; + elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); #endif feat_v6_fixup(); @@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size) size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); -#ifndef CONFIG_LPAE +#ifndef CONFIG_ARM_LPAE if (bank->start + size < bank->start) { printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " "32-bit physical address space\n", (long long)start); diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 79078edbb9bc..1f2ccccaf009 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb, if (freq->flags & CPUFREQ_CONST_LOOPS) return NOTIFY_OK; - if (arm_delay_ops.const_clock) - return NOTIFY_OK; - if (!per_cpu(l_p_j_ref, cpu)) { per_cpu(l_p_j_ref, cpu) = per_cpu(cpu_data, cpu).loops_per_jiffy; diff --git a/trunk/arch/arm/kernel/smp_tlb.c b/trunk/arch/arm/kernel/smp_tlb.c index bd0300531399..e82e1d248772 100644 --- a/trunk/arch/arm/kernel/smp_tlb.c +++ b/trunk/arch/arm/kernel/smp_tlb.c @@ -12,6 +12,7 @@ #include #include +#include /**********************************************************************/ @@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored) local_flush_bp_all(); } +#ifdef CONFIG_ARM_ERRATA_798181 +static int erratum_a15_798181(void) +{ + unsigned int midr = read_cpuid_id(); + + /* Cortex-A15 r0p0..r3p2 affected */ + if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) + return 0; + return 1; +} +#else +static int erratum_a15_798181(void) +{ + return 0; +} +#endif + +static void ipi_flush_tlb_a15_erratum(void *arg) +{ + dmb(); +} + +static void broadcast_tlb_a15_erratum(void) +{ + if (!erratum_a15_798181()) + return; + + dummy_flush_tlb_a15_erratum(); + smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum, + NULL, 1); +} + +static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm) +{ + int cpu; + cpumask_t mask = { CPU_BITS_NONE }; + + if (!erratum_a15_798181()) + return; + + dummy_flush_tlb_a15_erratum(); + for_each_online_cpu(cpu) { + if (cpu == smp_processor_id()) + continue; + /* + * We only need to send an IPI if the other CPUs are running + * the same ASID as the one being invalidated. There is no + * need for locking around the active_asids check since the + * switch_mm() function has at least one dmb() (as required by + * this workaround) in case a context switch happens on + * another CPU after the condition below. + */ + if (atomic64_read(&mm->context.id) == + atomic64_read(&per_cpu(active_asids, cpu))) + cpumask_set_cpu(cpu, &mask); + } + smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1); +} + void flush_tlb_all(void) { if (tlb_ops_need_broadcast()) on_each_cpu(ipi_flush_tlb_all, NULL, 1); else local_flush_tlb_all(); + broadcast_tlb_a15_erratum(); } void flush_tlb_mm(struct mm_struct *mm) @@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm) on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); else local_flush_tlb_mm(mm); + broadcast_tlb_mm_a15_erratum(mm); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) @@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) &ta, 1); } else local_flush_tlb_page(vma, uaddr); + broadcast_tlb_mm_a15_erratum(vma->vm_mm); } void flush_tlb_kernel_page(unsigned long kaddr) @@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); } else local_flush_tlb_kernel_page(kaddr); + broadcast_tlb_a15_erratum(); } void flush_tlb_range(struct vm_area_struct *vma, @@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma, &ta, 1); } else local_flush_tlb_range(vma, start, end); + broadcast_tlb_mm_a15_erratum(vma->vm_mm); } void flush_tlb_kernel_range(unsigned long start, unsigned long end) @@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); } else local_flush_tlb_kernel_range(start, end); + broadcast_tlb_a15_erratum(); } void flush_bp_all(void) diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index 90525d9d290b..3f2565037480 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -362,13 +362,25 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) } #ifdef CONFIG_OF -static void __init twd_local_timer_of_register(struct device_node *np) +const static struct of_device_id twd_of_match[] __initconst = { + { .compatible = "arm,cortex-a9-twd-timer", }, + { .compatible = "arm,cortex-a5-twd-timer", }, + { .compatible = "arm,arm11mp-twd-timer", }, + { }, +}; + +void __init twd_local_timer_of_register(void) { + struct device_node *np; int err; if (!is_smp() || !setup_max_cpus) return; + np = of_find_matching_node(NULL, twd_of_match); + if (!np) + return; + twd_ppi = irq_of_parse_and_map(np, 0); if (!twd_ppi) { err = -EINVAL; @@ -386,7 +398,4 @@ static void __init twd_local_timer_of_register(struct device_node *np) out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); } -CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); #endif diff --git a/trunk/arch/arm/kvm/vgic.c b/trunk/arch/arm/kvm/vgic.c index c9a17316e9fe..0e4cfe123b38 100644 --- a/trunk/arch/arm/kvm/vgic.c +++ b/trunk/arch/arm/kvm/vgic.c @@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) lr, irq, vgic_cpu->vgic_lr[lr]); BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; - - goto out; + return true; } /* Try to use another LR for this interrupt */ @@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) vgic_cpu->vgic_irq_lr_map[irq] = lr; set_bit(lr, vgic_cpu->lr_used); -out: if (!vgic_irq_is_edge(vcpu, irq)) vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; @@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); - /* - * We do not need to take the distributor lock here, since the only - * action we perform is clearing the irq_active_bit for an EOIed - * level interrupt. There is a potential race with - * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we - * check if the interrupt is already active. Two possibilities: - * - * - The queuing is occurring on the same vcpu: cannot happen, - * as we're already in the context of this vcpu, and - * executing the handler - * - The interrupt has been migrated to another vcpu, and we - * ignore this interrupt for this run. Big deal. It is still - * pending though, and will get considered when this vcpu - * exits. - */ if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { /* * Some level interrupts have been EOIed. Clear their @@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) } else { vgic_cpu_irq_clear(vcpu, irq); } + + /* + * Despite being EOIed, the LR may not have + * been marked as empty. + */ + set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); + vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT; } } @@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) } /* - * Sync back the VGIC state after a guest run. We do not really touch - * the distributor here (the irq_pending_on_cpu bit is safe to set), - * so there is no need for taking its lock. + * Sync back the VGIC state after a guest run. The distributor lock is + * needed so we don't get preempted in the middle of the state processing. */ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) { @@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) { + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + if (!irqchip_in_kernel(vcpu->kvm)) return; + spin_lock(&dist->lock); __kvm_vgic_sync_hwstate(vcpu); + spin_unlock(&dist->lock); } int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) diff --git a/trunk/arch/arm/lib/delay.c b/trunk/arch/arm/lib/delay.c index 6b93f6a1a3c7..64dbfa57204a 100644 --- a/trunk/arch/arm/lib/delay.c +++ b/trunk/arch/arm/lib/delay.c @@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles) static void __timer_const_udelay(unsigned long xloops) { unsigned long long loops = xloops; - loops *= loops_per_jiffy; + loops *= arm_delay_ops.ticks_per_jiffy; __timer_delay(loops >> UDELAY_SHIFT); } @@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer) pr_info("Switching to timer-based delay loop\n"); delay_timer = timer; lpj_fine = timer->freq / HZ; - loops_per_jiffy = lpj_fine; + + /* cpufreq may scale loops_per_jiffy, so keep a private copy */ + arm_delay_ops.ticks_per_jiffy = lpj_fine; arm_delay_ops.delay = __timer_delay; arm_delay_ops.const_udelay = __timer_const_udelay; arm_delay_ops.udelay = __timer_udelay; - arm_delay_ops.const_clock = true; + delay_calibrated = true; } else { pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); diff --git a/trunk/arch/arm/mach-at91/gpio.c b/trunk/arch/arm/mach-at91/gpio.c index a5afcf76550e..c5d7e1e9d757 100644 --- a/trunk/arch/arm/mach-at91/gpio.c +++ b/trunk/arch/arm/mach-at91/gpio.c @@ -22,9 +22,10 @@ #include #include #include -#include #include +#include + #include #include diff --git a/trunk/arch/arm/mach-cns3xxx/core.c b/trunk/arch/arm/mach-cns3xxx/core.c index e698f26cc0cb..52e4bb5cf12d 100644 --- a/trunk/arch/arm/mach-cns3xxx/core.c +++ b/trunk/arch/arm/mach-cns3xxx/core.c @@ -22,19 +22,9 @@ static struct map_desc cns3xxx_io_desc[] __initdata = { { - .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE), - .length = SZ_4K, + .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), + .length = SZ_8K, .type = MT_DEVICE, }, { .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 191c8e57f289..b1021aafa481 100644 --- a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -94,10 +94,10 @@ #define RTC_INTR_STS_OFFSET 0x34 #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ +#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 +#define CNS3XXX_PM_BASE_VIRT 0xFB001000 #define PM_CLK_GATE_OFFSET 0x00 #define PM_SOFT_RST_OFFSET 0x04 @@ -109,7 +109,7 @@ #define PM_PLL_HM_PD_OFFSET 0x1C #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 +#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ #define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 @@ -130,7 +130,7 @@ #define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 +#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 #define TIMER1_COUNTER_OFFSET 0x00 #define TIMER1_AUTO_RELOAD_OFFSET 0x04 @@ -227,16 +227,16 @@ * Testchip peripheral and fpga gic regions */ #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 +#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) #define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ #define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h b/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h index d2afb4dd82ab..b5cc77d2380b 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr) static inline void putc(int c) { - /* Transmit fifo not full? */ - while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) - ; + int i; + + for (i = 0; i < 10000; i++) { + /* Transmit fifo not full? */ + if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) + break; + } __raw_writeb(c, PHYS_UART_DATA); } diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c index 7bc0f9aa8b33..d63d399c7bae 100644 --- a/trunk/arch/arm/mach-exynos/common.c +++ b/trunk/arch/arm/mach-exynos/common.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-exynos/platsmp.c b/trunk/arch/arm/mach-exynos/platsmp.c index 95e04bd5813f..60f7c5be057d 100644 --- a/trunk/arch/arm/mach-exynos/platsmp.c +++ b/trunk/arch/arm/mach-exynos/platsmp.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,13 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit exynos_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/arm/mach-highbank/highbank.c b/trunk/arch/arm/mach-highbank/highbank.c index 76c1170b3528..a4f9f50247d4 100644 --- a/trunk/arch/arm/mach-highbank/highbank.c +++ b/trunk/arch/arm/mach-highbank/highbank.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -118,10 +119,10 @@ static void __init highbank_timer_init(void) sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); sp804_clockevents_init(timer_base, irq, "timer0"); + twd_local_timer_of_register(); + arch_timer_of_register(); arch_timer_sched_clock_init(); - - clocksource_of_init(); } static void highbank_power_off(void) diff --git a/trunk/arch/arm/mach-highbank/platsmp.c b/trunk/arch/arm/mach-highbank/platsmp.c index a984573e0d02..8797a7001720 100644 --- a/trunk/arch/arm/mach-highbank/platsmp.c +++ b/trunk/arch/arm/mach-highbank/platsmp.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -24,6 +25,11 @@ extern void secondary_startup(void); +static void __cpuinit highbank_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) { highbank_set_cpu_jump(cpu, secondary_startup); @@ -61,6 +67,7 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) struct smp_operations highbank_smp_ops __initdata = { .smp_init_cpus = highbank_smp_init_cpus, .smp_prepare_cpus = highbank_smp_prepare_cpus, + .smp_secondary_init = highbank_secondary_init, .smp_boot_secondary = highbank_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = highbank_cpu_die, diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index e13a8fa5e62c..2193c834f55c 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -257,6 +257,7 @@ int __init mx35_clocks_init(void) clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); + clk_register_clkdev(clk[admux_gate], "audmux", NULL); clk_prepare_enable(clk[spba_gate]); clk_prepare_enable(clk[gpio1_gate]); @@ -265,6 +266,7 @@ int __init mx35_clocks_init(void) clk_prepare_enable(clk[iim_gate]); clk_prepare_enable(clk[emi_gate]); clk_prepare_enable(clk[max_gate]); + clk_prepare_enable(clk[iomuxc_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 2f9ff93a4e61..d38e54f5b6d7 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -115,7 +115,7 @@ static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m" static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; -static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", }; +static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; @@ -443,7 +443,6 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - clk_register_clkdev(clk[twd], NULL, "smp_twd"); clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); clk_register_clkdev(clk[ahb], "ahb", NULL); clk_register_clkdev(clk[cko1], "cko1", NULL); diff --git a/trunk/arch/arm/mach-imx/common.h b/trunk/arch/arm/mach-imx/common.h index 5a800bfcec5b..5bf4a97ab241 100644 --- a/trunk/arch/arm/mach-imx/common.h +++ b/trunk/arch/arm/mach-imx/common.h @@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *); extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); +extern u32 imx_get_cpu_arg(int cpu); +extern void imx_set_cpu_arg(int cpu, u32 arg); extern void v7_cpu_resume(void); extern u32 *pl310_get_save_ptr(void); #ifdef CONFIG_SMP diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c index 7bc5fe15dda2..361a253e2b63 100644 --- a/trunk/arch/arm/mach-imx/hotplug.c +++ b/trunk/arch/arm/mach-imx/hotplug.c @@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void) void imx_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); + /* + * We use the cpu jumping argument register to sync with + * imx_cpu_kill() which is running on cpu0 and waiting for + * the register being cleared to kill the cpu. + */ + imx_set_cpu_arg(cpu, ~0); cpu_do_idle(); } int imx_cpu_kill(unsigned int cpu) { + unsigned long timeout = jiffies + msecs_to_jiffies(50); + + while (imx_get_cpu_arg(cpu) == 0) + if (time_after(jiffies, timeout)) + return 0; imx_enable_cpu(cpu, false); + imx_set_cpu_arg(cpu, 0); return 1; } diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index b59ddcb57c78..9ffd103b27e4 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -12,7 +12,6 @@ #include #include -#include #include #include #include @@ -29,9 +28,11 @@ #include #include #include +#include #include #include #include +#include #include #include "common.h" @@ -291,7 +292,7 @@ static void __init imx6q_init_irq(void) static void __init imx6q_timer_init(void) { mx6q_clocks_init(); - clocksource_of_init(); + twd_local_timer_of_register(); imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } diff --git a/trunk/arch/arm/mach-imx/platsmp.c b/trunk/arch/arm/mach-imx/platsmp.c index 77e9a25ed0f6..7c0b03f67b05 100644 --- a/trunk/arch/arm/mach-imx/platsmp.c +++ b/trunk/arch/arm/mach-imx/platsmp.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -51,6 +52,16 @@ void imx_scu_standby_enable(void) writel_relaxed(val, scu_base); } +static void __cpuinit imx_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); +} + static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) { imx_set_cpu_jump(cpu, v7_secondary_startup); @@ -85,6 +96,7 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) struct smp_operations imx_smp_ops __initdata = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, + .smp_secondary_init = imx_secondary_init, .smp_boot_secondary = imx_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = imx_cpu_die, diff --git a/trunk/arch/arm/mach-imx/src.c b/trunk/arch/arm/mach-imx/src.c index e15f1555c59b..09a742f8c7ab 100644 --- a/trunk/arch/arm/mach-imx/src.c +++ b/trunk/arch/arm/mach-imx/src.c @@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) src_base + SRC_GPR1 + cpu * 8); } +u32 imx_get_cpu_arg(int cpu) +{ + cpu = cpu_logical_map(cpu); + return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); +} + +void imx_set_cpu_arg(int cpu, u32 arg) +{ + cpu = cpu_logical_map(cpu); + writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); +} + void imx_src_prepare_restart(void) { u32 val; diff --git a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { static struct mvsdio_platform_data guruplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ + .gpio_card_detect = -1, + .gpio_write_protect = -1, }; static struct gpio_led guruplug_led_pins[] = { diff --git a/trunk/arch/arm/mach-kirkwood/openrd-setup.c b/trunk/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/trunk/arch/arm/mach-kirkwood/openrd-setup.c +++ b/trunk/arch/arm/mach-kirkwood/openrd-setup.c @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { static struct mvsdio_platform_data openrd_mvsdio_data = { .gpio_card_detect = 29, /* MPP29 used as SD card detect */ + .gpio_write_protect = -1, }; static unsigned int openrd_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { static struct mvsdio_platform_data rd88f6281_mvsdio_data = { .gpio_card_detect = 28, + .gpio_write_protect = -1, }; static unsigned int rd88f6281_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-msm/platsmp.c b/trunk/arch/arm/mach-msm/platsmp.c index 00cdb0a5dac8..42932865416a 100644 --- a/trunk/arch/arm/mach-msm/platsmp.c +++ b/trunk/arch/arm/mach-msm/platsmp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,13 @@ static inline int get_core_count(void) static void __cpuinit msm_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/arm/mach-msm/timer.c b/trunk/arch/arm/mach-msm/timer.c index 2969027f02fa..f9fd77e8f1f5 100644 --- a/trunk/arch/arm/mach-msm/timer.c +++ b/trunk/arch/arm/mach-msm/timer.c @@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles, { u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); - writel_relaxed(0, event_base + TIMER_CLEAR); + ctrl &= ~TIMER_ENABLE_EN; + writel_relaxed(ctrl, event_base + TIMER_ENABLE); + + writel_relaxed(ctrl, event_base + TIMER_CLEAR); writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); return 0; diff --git a/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c b/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c index 274ff58271de..6a9195e10579 100644 --- a/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -44,6 +44,8 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) + #define ACTIVE_DOORBELLS (8) static DEFINE_RAW_SPINLOCK(irq_controller_lock); @@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d) #ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); else @@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) #ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); else @@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); irq_set_status_flags(virq, IRQ_LEVEL); - if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { + if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_percpu_devid_irq); diff --git a/trunk/arch/arm/mach-omap1/clock_data.c b/trunk/arch/arm/mach-omap1/clock_data.c index cb7c6ae2e3fc..6c4f766365a2 100644 --- a/trunk/arch/arm/mach-omap1/clock_data.c +++ b/trunk/arch/arm/mach-omap1/clock_data.c @@ -538,15 +538,6 @@ static struct clk usb_hhc_ck16xx = { }; static struct clk usb_dc_ck = { - .name = "usb_dc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = USB_REQ_EN_SHIFT, -}; - -static struct clk usb_dc_ck7xx = { .name = "usb_dc_ck", .ops = &clkops_generic, /* Direct from ULPD, no parent */ @@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = { CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), CLK(NULL, "mclk", &mclk_16xx, CK_16XX), CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), diff --git a/trunk/arch/arm/mach-omap2/cclock44xx_data.c b/trunk/arch/arm/mach-omap2/cclock44xx_data.c index 3d58f335f173..0c6834ae1fc4 100644 --- a/trunk/arch/arm/mach-omap2/cclock44xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock44xx_data.c @@ -52,6 +52,13 @@ */ #define OMAP4_DPLL_ABE_DEFFREQ 98304000 +/* + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred + * locked frequency for the USB DPLL is 960MHz. + */ +#define OMAP4_DPLL_USB_DEFFREQ 960000000 + /* Root clocks */ DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); @@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); +DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, + OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); + DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); @@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X), CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X), CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), @@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + return 0; } diff --git a/trunk/arch/arm/mach-omap2/common.h b/trunk/arch/arm/mach-omap2/common.h index 40f4a03d728f..d6ba13e1c540 100644 --- a/trunk/arch/arm/mach-omap2/common.h +++ b/trunk/arch/arm/mach-omap2/common.h @@ -293,5 +293,8 @@ extern void omap_reserve(void); struct omap_hwmod; extern int omap_dss_reset(struct omap_hwmod *); +/* SoC specific clock initializer */ +extern int (*omap_clk_init)(void); + #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 2c3fdd65387b..5c445ca1e271 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -54,6 +54,12 @@ #include "prm3xxx.h" #include "prm44xx.h" +/* + * omap_clk_init: points to a function that does the SoC-specific + * clock initializations + */ +int (*omap_clk_init)(void); + /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. @@ -397,7 +403,7 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap2420_clk_init(); + omap_clk_init = omap2420_clk_init; } void __init omap2420_init_late(void) @@ -427,7 +433,7 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap2430_clk_init(); + omap_clk_init = omap2430_clk_init; } void __init omap2430_init_late(void) @@ -462,7 +468,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap3xxx_clk_init(); + omap_clk_init = omap3xxx_clk_init; } void __init omap3430_init_early(void) @@ -500,7 +506,7 @@ void __init ti81xx_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap3xxx_clk_init(); + omap_clk_init = omap3xxx_clk_init; } void __init omap3_init_late(void) @@ -568,7 +574,7 @@ void __init am33xx_init_early(void) am33xx_clockdomains_init(); am33xx_hwmod_init(); omap_hwmod_init_postsetup(); - am33xx_clk_init(); + omap_clk_init = am33xx_clk_init; } #endif @@ -593,7 +599,7 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap4xxx_clk_init(); + omap_clk_init = omap4xxx_clk_init; } void __init omap4430_init_late(void) diff --git a/trunk/arch/arm/mach-omap2/omap-smp.c b/trunk/arch/arm/mach-omap2/omap-smp.c index e7a449758ab5..d9727218dd0a 100644 --- a/trunk/arch/arm/mach-omap2/omap-smp.c +++ b/trunk/arch/arm/mach-omap2/omap-smp.c @@ -66,6 +66,13 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 4, 0, 0, 0, 0, 0); + /* + * If any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * Synchronise with the boot thread. */ diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index c2c798c08c2b..a202a4785104 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh) } if (sf & SYSC_HAS_MIDLEMODE) { - if (oh->flags & HWMOD_SWSUP_MSTANDBY) { + if (oh->flags & HWMOD_FORCE_MSTANDBY) { + idlemode = HWMOD_IDLEMODE_FORCE; + } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { idlemode = HWMOD_IDLEMODE_NO; } else { if (sf & SYSC_HAS_ENAWAKEUP) @@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh) } if (sf & SYSC_HAS_MIDLEMODE) { - if (oh->flags & HWMOD_SWSUP_MSTANDBY) { + if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || + (oh->flags & HWMOD_FORCE_MSTANDBY)) { idlemode = HWMOD_IDLEMODE_FORCE; } else { if (sf & SYSC_HAS_ENAWAKEUP) diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.h b/trunk/arch/arm/mach-omap2/omap_hwmod.h index d43d9b608eda..d5dc935f6060 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.h +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.h @@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm { * * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out * of idle, rather than relying on module smart-idle - * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out - * of standby, rather than relying on module smart-standby + * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and + * out of standby, rather than relying on module smart-standby * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for * SDRAM controller, etc. XXX probably belongs outside the main hwmod file * XXX Should be HWMOD_SETUP_NO_RESET @@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm { * correctly, or this is being abused to deal with some PM latency * issues -- but we're currently suffering from a shortage of * folks who are able to track these issues down properly. + * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device + * is kept in force-standby mode. Failing to do so causes PM problems + * with musb on OMAP3630 at least. Note that musb has a dedicated register + * to control MSTANDBY signal when MIDLEMODE is set to force-standby. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_16BIT_REG (1 << 8) #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) #define HWMOD_BLOCK_WFI (1 << 10) +#define HWMOD_FORCE_MSTANDBY (1 << 11) /* * omap_hwmod._int_flags definitions diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index ac7e03ec952f..5112d04e7b79 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { * Erratum ID: i479 idle_req / idle_ack mechanism potentially * broken when autoidle is enabled * workaround is to disable the autoidle bit at module level. + * + * Enabling the device in any other MIDLEMODE setting but force-idle + * causes core_pwrdm not enter idle states at least on OMAP3630. + * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY + * signal when MIDLEMODE is set to force-idle. */ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE - | HWMOD_SWSUP_MSTANDBY, + | HWMOD_FORCE_MSTANDBY, }; /* usb_otg_hs */ diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0e47d2e1687c..9e0576569e07 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { { } }; +static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { + { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" }, +}; + /* ocp2scp_usb_phy */ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { .name = "ocp2scp_usb_phy", @@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { }, }, .dev_attr = ocp2scp_dev_attr, + .opt_clks = ocp2scp_usb_phy_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), }; /* diff --git a/trunk/arch/arm/mach-omap2/timer.c b/trunk/arch/arm/mach-omap2/timer.c index 4fd80257c73e..f62b509ed08d 100644 --- a/trunk/arch/arm/mach-omap2/timer.c +++ b/trunk/arch/arm/mach-omap2/timer.c @@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void) clksrc_nr, clksrc_src) \ void __init omap##name##_gptimer_timer_init(void) \ { \ + if (omap_clk_init) \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ @@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void) \ clksrc_nr, clksrc_src) \ void __init omap##name##_sync32k_timer_init(void) \ { \ + if (omap_clk_init) \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ /* Enable the use of clocksource="gp_timer" kernel parameter */ \ @@ -597,7 +601,7 @@ void __init omap4_local_timer_init(void) int err; if (of_have_populated_dt()) { - clocksource_of_init(); + twd_local_timer_of_register(); return; } diff --git a/trunk/arch/arm/mach-prima2/platsmp.c b/trunk/arch/arm/mach-prima2/platsmp.c index c7c92e78f0cf..4b788310f6a6 100644 --- a/trunk/arch/arm/mach-prima2/platsmp.c +++ b/trunk/arch/arm/mach-prima2/platsmp.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -47,6 +48,13 @@ void __init sirfsoc_map_scu(void) static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/arm/mach-s3c24xx/irq.c b/trunk/arch/arm/mach-s3c24xx/irq.c index b6fac28a0034..cb9f5e011e73 100644 --- a/trunk/arch/arm/mach-s3c24xx/irq.c +++ b/trunk/arch/arm/mach-s3c24xx/irq.c @@ -25,7 +25,6 @@ #include #include #include -#include #include diff --git a/trunk/arch/arm/mach-shmobile/Kconfig b/trunk/arch/arm/mach-shmobile/Kconfig index ff674c5f2d03..9255546e7bf6 100644 --- a/trunk/arch/arm/mach-shmobile/Kconfig +++ b/trunk/arch/arm/mach-shmobile/Kconfig @@ -16,30 +16,12 @@ config ARCH_SH73A0 select CPU_V7 select I2C select SH_CLK_CPG - select RENESAS_INTC_IRQPIN - -config ARCH_R8A73A4 - bool "R-Mobile APE6 (R8A73A40)" - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select CPU_V7 - select ARM_ARCH_TIMER - select SH_CLK_CPG - select RENESAS_IRQC config ARCH_R8A7740 bool "R-Mobile A1 (R8A77400)" select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC select CPU_V7 select SH_CLK_CPG - select RENESAS_INTC_IRQPIN - -config ARCH_R8A7778 - bool "R-Car M1 (R8A77780)" - select CPU_V7 - select SH_CLK_CPG - select ARM_GIC config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" @@ -49,16 +31,6 @@ config ARCH_R8A7779 select SH_CLK_CPG select USB_ARCH_HAS_EHCI select USB_ARCH_HAS_OHCI - select RENESAS_INTC_IRQPIN - -config ARCH_R8A7790 - bool "R-Car H2 (R8A77900)" - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select CPU_V7 - select ARM_ARCH_TIMER - select SH_CLK_CPG - select RENESAS_IRQC config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/trunk/arch/arm/mach-shmobile/Makefile b/trunk/arch/arm/mach-shmobile/Makefile index 709b9b421f93..e1fac57514b9 100644 --- a/trunk/arch/arm/mach-shmobile/Makefile +++ b/trunk/arch/arm/mach-shmobile/Makefile @@ -8,18 +8,16 @@ obj-y := timer.o console.o clock.o # CPU objects obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o -obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o -obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o -obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o # SMP objects smp-y := platsmp.o headsmp.o -smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o -smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o -smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o +smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o +smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o +smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o +smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o # IRQ objects obj-$(CONFIG_ARCH_SH7372) += entry-intc.o diff --git a/trunk/arch/arm/mach-shmobile/board-ag5evm.c b/trunk/arch/arm/mach-shmobile/board-ag5evm.c index c7540710906f..8ff53a19c48c 100644 --- a/trunk/arch/arm/mach-shmobile/board-ag5evm.c +++ b/trunk/arch/arm/mach-shmobile/board-ag5evm.c @@ -23,8 +23,6 @@ #include #include #include -#include -#include #include #include #include @@ -306,9 +304,9 @@ static int lcd_backlight_set_brightness(int brightness) if (brightness == 0) { /* Reset the chip */ - gpio_set_value(235, 0); + gpio_set_value(GPIO_PORT235, 0); mdelay(24); - gpio_set_value(235, 1); + gpio_set_value(GPIO_PORT235, 1); return 0; } @@ -408,7 +406,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, - .cd_gpio = 251, + .cd_gpio = GPIO_PORT251, }; static struct resource sdhi0_resources[] = { @@ -463,7 +461,7 @@ static struct regulator_init_data cn4_power_init_data = { static struct fixed_voltage_config cn4_power_info = { .supply_name = "CN4 SD/MMC Vdd", .microvolts = 3300000, - .gpio = 114, + .gpio = GPIO_PORT114, .enable_high = 1, .init_data = &cn4_power_init_data, }; @@ -481,10 +479,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) static int power_gpio = -EINVAL; if (power_gpio < 0) { - int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW, + int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW, "sdhi1_power"); if (!ret) - power_gpio = 114; + power_gpio = GPIO_PORT114; } /* @@ -495,7 +493,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state) * regulator driver. We have to live with the race in case the driver * gets unloaded and the GPIO freed between these two steps. */ - gpio_set_value(114, state); + gpio_set_value(GPIO_PORT114, state); } static struct sh_mobile_sdhi_info sh_sdhi1_info = { @@ -552,77 +550,6 @@ static struct platform_device *ag5evm_devices[] __initdata = { &sdhi1_device, }; -static unsigned long pin_pullup_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), -}; - -static const struct pinctrl_map ag5evm_pinctrl_map[] = { - /* FSIA */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_mclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_data_out", "fsia"), - /* I2C2 & I2C3 */ - PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0", - "i2c2_0", "i2c2"), - PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", - "i2c3_0", "i2c3"), - /* IrDA */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0", - "irda_0", "irda"), - /* KEYSC */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_in8", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out04", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out5", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out6_0", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out7_0", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out8_0", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out9_2", "keysc"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_in8", pin_pullup_conf), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", pin_pullup_conf), - /* SCIFA2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", - "scifa2_data_0", "scifa2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", - "scifa2_ctrl_0", "scifa2"), - /* SDHI0 (CN15 [SD I/F]) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_wp", "sdhi0"), - /* SDHI1 (CN4 [WLAN I/F]) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_ctrl", "sdhi1"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_data4", pin_pullup_conf), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "PORT263", pin_pullup_conf), -}; - static void __init ag5evm_init(void) { regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, @@ -631,27 +558,96 @@ static void __init ag5evm_init(void) ARRAY_SIZE(fixed2v8_power_consumers), 3300000); regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - pinctrl_register_mappings(ag5evm_pinctrl_map, - ARRAY_SIZE(ag5evm_pinctrl_map)); sh73a0_pinmux_init(); + /* enable SCIFA2 */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); + gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); + + /* enable KEYSC */ + gpio_request(GPIO_FN_KEYIN0_PU, NULL); + gpio_request(GPIO_FN_KEYIN1_PU, NULL); + gpio_request(GPIO_FN_KEYIN2_PU, NULL); + gpio_request(GPIO_FN_KEYIN3_PU, NULL); + gpio_request(GPIO_FN_KEYIN4_PU, NULL); + gpio_request(GPIO_FN_KEYIN5_PU, NULL); + gpio_request(GPIO_FN_KEYIN6_PU, NULL); + gpio_request(GPIO_FN_KEYIN7_PU, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4, NULL); + gpio_request(GPIO_FN_KEYOUT5, NULL); + gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); + gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); + gpio_request(GPIO_FN_KEYOUT8, NULL); + gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); + + /* enable I2C channel 2 and 3 */ + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL); + gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL); + /* enable MMCIF */ - gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCCMD0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_1_PU, NULL); + gpio_request(GPIO_FN_MMCD0_2_PU, NULL); + gpio_request(GPIO_FN_MMCD0_3_PU, NULL); + gpio_request(GPIO_FN_MMCD0_4_PU, NULL); + gpio_request(GPIO_FN_MMCD0_5_PU, NULL); + gpio_request(GPIO_FN_MMCD0_6_PU, NULL); + gpio_request(GPIO_FN_MMCD0_7_PU, NULL); + gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ /* enable SMSC911X */ - gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ - gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ + gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + + /* FSI A */ + gpio_request(GPIO_FN_FSIACK, NULL); + gpio_request(GPIO_FN_FSIAILR, NULL); + gpio_request(GPIO_FN_FSIAIBT, NULL); + gpio_request(GPIO_FN_FSIAISLD, NULL); + gpio_request(GPIO_FN_FSIAOSLD, NULL); + + /* IrDA */ + gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL); + gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL); + gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL); /* LCD panel */ - gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ + gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ mdelay(1); - gpio_set_value(217, 1); + gpio_set_value(GPIO_PORT217, 1); mdelay(100); /* LCD backlight controller */ - gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ + gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ lcd_backlight_set_brightness(0); + /* enable SDHI0 on CN15 [SD I/F] */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + + /* enable SDHI1 on CN4 [WLAN I/F] */ + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHICMD1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_3_PU, NULL); + gpio_request(GPIO_FN_SDHID1_2_PU, NULL); + gpio_request(GPIO_FN_SDHID1_1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_0_PU, NULL); + #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); diff --git a/trunk/arch/arm/mach-shmobile/board-ap4evb.c b/trunk/arch/arm/mach-shmobile/board-ap4evb.c index 45f78cadec1d..38f1259a0daf 100644 --- a/trunk/arch/arm/mach-shmobile/board-ap4evb.c +++ b/trunk/arch/arm/mach-shmobile/board-ap4evb.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -274,11 +273,11 @@ static struct platform_device smc911x_device = { /* * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO 41). + * connected to GPIO A22 of SH7372 (GPIO_PORT41). */ static int slot_cn7_get_cd(struct platform_device *pdev) { - return !gpio_get_value(41); + return !gpio_get_value(GPIO_PORT41); } /* MERAM */ static struct sh_mobile_meram_info meram_info = { @@ -839,22 +838,22 @@ static struct platform_device fsi_hdmi_device = { static struct gpio_led ap4evb_leds[] = { { .name = "led4", - .gpio = 185, + .gpio = GPIO_PORT185, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led2", - .gpio = 186, + .gpio = GPIO_PORT186, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = 187, + .gpio = GPIO_PORT187, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led1", - .gpio = 188, + .gpio = GPIO_PORT188, .default_state = LEDS_GPIO_DEFSTATE_ON, } }; @@ -1027,10 +1026,10 @@ static void __init hdmi_init_pm_clock(void) /* TouchScreen */ #ifdef CONFIG_AP4EVB_QHD # define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 -# define GPIO_TSC_PORT 123 +# define GPIO_TSC_PORT GPIO_PORT123 #else /* WVGA */ # define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 -# define GPIO_TSC_PORT 40 +# define GPIO_TSC_PORT GPIO_PORT40 #endif #define IRQ28 evt2irq(0x3380) /* IRQ28A */ @@ -1085,28 +1084,6 @@ static struct i2c_board_info i2c1_devices[] = { }; -static const struct pinctrl_map ap4evb_pinctrl_map[] = { - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_ctrl_0", "mmc0"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_wp", "sdhi0"), - /* SDHI1 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_ctrl", "sdhi1"), -}; - #define GPIO_PORT9CR IOMEM(0xE6051009) #define GPIO_PORT10CR IOMEM(0xE605100A) #define USCCR1 IOMEM(0xE6058144) @@ -1133,8 +1110,6 @@ static void __init ap4evb_init(void) /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); - pinctrl_register_mappings(ap4evb_pinctrl_map, - ARRAY_SIZE(ap4evb_pinctrl_map)); sh7372_pinmux_init(); /* enable SCIFA0 */ @@ -1146,10 +1121,40 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_IRQ6_39, NULL); /* enable Debug switch (S6) */ - gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL); - gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL); + gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL); + + /* SDHI0 */ + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + + /* SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); /* USB enable */ gpio_request(GPIO_FN_VBUS0_1, NULL); @@ -1167,15 +1172,15 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - gpio_request(9, NULL); - gpio_request(10, NULL); + gpio_request(GPIO_PORT9, NULL); + gpio_request(GPIO_PORT10, NULL); gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ /* card detect pin for MMC slot (CN7) */ - gpio_request_one(41, GPIOF_IN, NULL); + gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); /* setup FSI2 port B (HDMI) */ gpio_request(GPIO_FN_FSIBCK, NULL); @@ -1263,8 +1268,8 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); - gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ - gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ + gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ lcdc_info.clock_source = LCDC_CLK_BUS; lcdc_info.ch[0].interface_type = RGB18; diff --git a/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c b/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c index 9415cb4e6199..f2ec0777cfbe 100644 --- a/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/trunk/arch/arm/mach-shmobile/board-armadillo800eva.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -146,7 +145,7 @@ * see * usbhsf_power_ctrl() */ -#define IRQ7 irq_pin(7) +#define IRQ7 evt2irq(0x02e0) #define USBCR1 IOMEM(0xe605810a) #define USBH 0xC6700000 #define USBH_USBCTR 0x10834 @@ -228,7 +227,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev, static int usbhsf_get_vbus(struct platform_device *pdev) { - return gpio_get_value(209); + return gpio_get_value(GPIO_PORT209); } static irqreturn_t usbhsf_interrupt(int irq, void *data) @@ -331,7 +330,7 @@ static struct resource usbhsf_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gic_spi(51), + .start = evt2irq(0x0A20), .flags = IORESOURCE_IRQ, }, }; @@ -364,7 +363,7 @@ static struct resource sh_eth_resources[] = { .end = 0xe9a02000 - 1, .flags = IORESOURCE_MEM, }, { - .start = gic_spi(110), + .start = evt2irq(0x0500), .flags = IORESOURCE_IRQ, }, }; @@ -418,7 +417,7 @@ static struct resource lcdc0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(177), + .start = intcs_evt2irq(0x580), .flags = IORESOURCE_IRQ, }, }; @@ -453,7 +452,7 @@ static struct resource hdmi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(131), + .start = evt2irq(0x1700), .flags = IORESOURCE_IRQ, }, [2] = { @@ -515,7 +514,7 @@ static struct resource hdmi_lcdc_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(178), + .start = intcs_evt2irq(0x1780), .flags = IORESOURCE_IRQ, }, }; @@ -536,10 +535,10 @@ static struct platform_device hdmi_lcdc_device = { { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1), - GPIO_KEY(KEY_BACK, 100, "SW4"), - GPIO_KEY(KEY_MENU, 97, "SW5"), - GPIO_KEY(KEY_HOME, 98, "SW6"), + GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), + GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), + GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), + GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), }; static struct gpio_keys_platform_data gpio_key_info = { @@ -575,7 +574,7 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] = * We can use IRQ31 as card detect irq, * but it needs chattering removal operation */ -#define IRQ31 irq_pin(31) +#define IRQ31 evt2irq(0x33E0) static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, @@ -597,12 +596,12 @@ static struct resource sdhi0_resources[] = { */ { .name = SH_MOBILE_SDHI_IRQ_SDCARD, - .start = gic_spi(118), + .start = evt2irq(0x0E20), .flags = IORESOURCE_IRQ, }, { .name = SH_MOBILE_SDHI_IRQ_SDIO, - .start = gic_spi(119), + .start = evt2irq(0x0E40), .flags = IORESOURCE_IRQ, }, }; @@ -634,15 +633,15 @@ static struct resource sdhi1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(121), + .start = evt2irq(0x0E80), .flags = IORESOURCE_IRQ, }, [2] = { - .start = gic_spi(122), + .start = evt2irq(0x0EA0), .flags = IORESOURCE_IRQ, }, [3] = { - .start = gic_spi(123), + .start = evt2irq(0x0EC0), .flags = IORESOURCE_IRQ, }, }; @@ -657,17 +656,6 @@ static struct platform_device sdhi1_device = { .resource = sdhi1_resources, }; -static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = { - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_ctrl", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_cd", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740", - "sdhi1_wp", "sdhi1"), -}; - /* MMCIF */ static struct sh_mmcif_plat_data sh_mmcif_plat = { .sup_pclk = 0, @@ -686,12 +674,12 @@ static struct resource sh_mmcif_resources[] = { }, [1] = { /* MMC ERR */ - .start = gic_spi(56), + .start = evt2irq(0x1AC0), .flags = IORESOURCE_IRQ, }, [2] = { /* MMC NOR */ - .start = gic_spi(57), + .start = evt2irq(0x1AE0), .flags = IORESOURCE_IRQ, }, }; @@ -720,9 +708,9 @@ static int mt9t111_power(struct device *dev, int mode) /* video1 (= CON1 camera) expect 24MHz */ clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); clk_enable(mclk); - gpio_set_value(158, 1); + gpio_set_value(GPIO_PORT158, 1); } else { - gpio_set_value(158, 0); + gpio_set_value(GPIO_PORT158, 0); clk_disable(mclk); } @@ -768,7 +756,7 @@ static struct resource ceu0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(160), + .start = intcs_evt2irq(0x0500), .flags = IORESOURCE_IRQ, }, [2] = { @@ -810,7 +798,7 @@ static struct resource fsi_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(9), + .start = evt2irq(0x1840), .flags = IORESOURCE_IRQ, }, }; @@ -876,8 +864,8 @@ static struct platform_device fsi_hdmi_device = { /* RTC: RTC connects i2c-gpio. */ static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 208, - .scl_pin = 91, + .sda_pin = GPIO_PORT208, + .scl_pin = GPIO_PORT91, .udelay = 5, /* 100 kHz */ }; @@ -893,7 +881,7 @@ static struct platform_device i2c_gpio_device = { static struct i2c_board_info i2c0_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = irq_pin(10), + .irq = evt2irq(0x0340), }, { I2C_BOARD_INFO("wm8978", 0x1a), @@ -926,28 +914,6 @@ static struct platform_device *eva_devices[] __initdata = { &i2c_gpio_device, }; -static const struct pinctrl_map eva_pinctrl_map[] = { - /* LCD0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_data24_0", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_lclk_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_sync", "lcd0"), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", - "mmc0_data8_1", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740", - "mmc0_ctrl_1", "mmc0"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740", - "sdhi0_wp", "sdhi0"), -}; - static void __init eva_clock_init(void) { struct clk *system = clk_get(NULL, "system_clk"); @@ -995,8 +961,6 @@ static void __init eva_init(void) regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, ARRAY_SIZE(fixed3v3_power_consumers), 3300000); - pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); - r8a7740_pinmux_init(); r8a7740_meram_workaround(); @@ -1006,13 +970,42 @@ static void __init eva_init(void) /* LCDC0 */ gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ - gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ + gpio_request(GPIO_FN_LCD0_D0, NULL); + gpio_request(GPIO_FN_LCD0_D1, NULL); + gpio_request(GPIO_FN_LCD0_D2, NULL); + gpio_request(GPIO_FN_LCD0_D3, NULL); + gpio_request(GPIO_FN_LCD0_D4, NULL); + gpio_request(GPIO_FN_LCD0_D5, NULL); + gpio_request(GPIO_FN_LCD0_D6, NULL); + gpio_request(GPIO_FN_LCD0_D7, NULL); + gpio_request(GPIO_FN_LCD0_D8, NULL); + gpio_request(GPIO_FN_LCD0_D9, NULL); + gpio_request(GPIO_FN_LCD0_D10, NULL); + gpio_request(GPIO_FN_LCD0_D11, NULL); + gpio_request(GPIO_FN_LCD0_D12, NULL); + gpio_request(GPIO_FN_LCD0_D13, NULL); + gpio_request(GPIO_FN_LCD0_D14, NULL); + gpio_request(GPIO_FN_LCD0_D15, NULL); + gpio_request(GPIO_FN_LCD0_D16, NULL); + gpio_request(GPIO_FN_LCD0_D17, NULL); + gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL); + gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL); + gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL); + gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL); + gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL); + gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL); + gpio_request(GPIO_FN_LCD0_DCK, NULL); + gpio_request(GPIO_FN_LCD0_VSYN, NULL); + gpio_request(GPIO_FN_LCD0_HSYN, NULL); + gpio_request(GPIO_FN_LCD0_DISP, NULL); + gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); + + gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */ /* Touchscreen */ gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ - gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ + gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ /* GETHER */ gpio_request(GPIO_FN_ET_CRS, NULL); @@ -1035,12 +1028,12 @@ static void __init eva_init(void) gpio_request(GPIO_FN_ET_RX_DV, NULL); gpio_request(GPIO_FN_ET_RX_CLK, NULL); - gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ + gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ /* USB */ - gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ + gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ - if (gpio_get_value(159)) { + if (gpio_get_value(GPIO_PORT159)) { /* USB Host */ } else { /* USB Func */ @@ -1049,22 +1042,47 @@ static void __init eva_init(void) * OTOH, usbhs interrupt needs its value (HI/LOW) to decide * USB connection/disconnection (usbhsf_get_vbus()). * This means we needs to select GPIO_FN_IRQ7_PORT209 first, - * and select GPIO 209 here + * and select GPIO_PORT209 here */ gpio_request(GPIO_FN_IRQ7_PORT209, NULL); - gpio_request_one(209, GPIOF_IN, NULL); + gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL); platform_device_register(&usbhsf_device); usb = &usbhsf_device; } /* SDHI0 */ - gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ - gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ - gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ + gpio_request(GPIO_FN_SDHI0_CMD, NULL); + gpio_request(GPIO_FN_SDHI0_CLK, NULL); + gpio_request(GPIO_FN_SDHI0_D0, NULL); + gpio_request(GPIO_FN_SDHI0_D1, NULL); + gpio_request(GPIO_FN_SDHI0_D2, NULL); + gpio_request(GPIO_FN_SDHI0_D3, NULL); + gpio_request(GPIO_FN_SDHI0_WP, NULL); + + gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */ + gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */ + gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */ /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ + /* + * MMCIF + * + * Here doesn't care SW1.4 status, + * since CON2 is not mounted. + */ + gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL); + gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL); + gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL); + gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL); + gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL); + gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL); + gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL); + gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL); + gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL); + gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL); + /* CEU0 */ gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); @@ -1081,10 +1099,10 @@ static void __init eva_init(void) gpio_request(GPIO_FN_VIO_CKO, NULL); /* CON1/CON15 Camera */ - gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ - gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ + gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ + gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ /* see mt9t111_power() */ - gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ + gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ /* FSI-WM8978 */ gpio_request(GPIO_FN_FSIAIBT, NULL); @@ -1093,8 +1111,8 @@ static void __init eva_init(void) gpio_request(GPIO_FN_FSIAOSLD, NULL); gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); - gpio_request(7, NULL); - gpio_request(8, NULL); + gpio_request(GPIO_PORT7, NULL); + gpio_request(GPIO_PORT8, NULL); gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ @@ -1111,22 +1129,28 @@ static void __init eva_init(void) * DBGMD/LCDC0/FSIA MUX * DBGMD_SELECT_B should be set after setting PFC Function. */ - gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL); + gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL); /* * We can switch CON8/CON14 by SW1.5, * but it needs after DBGMD_SELECT_B */ - gpio_request_one(6, GPIOF_IN, NULL); - if (gpio_get_value(6)) { + gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL); + if (gpio_get_value(GPIO_PORT6)) { /* CON14 enable */ } else { /* CON8 (SDHI1) enable */ - pinctrl_register_mappings(eva_sdhi1_pinctrl_map, - ARRAY_SIZE(eva_sdhi1_pinctrl_map)); + gpio_request(GPIO_FN_SDHI1_CLK, NULL); + gpio_request(GPIO_FN_SDHI1_CMD, NULL); + gpio_request(GPIO_FN_SDHI1_D0, NULL); + gpio_request(GPIO_FN_SDHI1_D1, NULL); + gpio_request(GPIO_FN_SDHI1_D2, NULL); + gpio_request(GPIO_FN_SDHI1_D3, NULL); + gpio_request(GPIO_FN_SDHI1_CD, NULL); + gpio_request(GPIO_FN_SDHI1_WP, NULL); /* SDSLOT2_PON */ - gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL); + gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL); platform_device_register(&sdhi1_device); } @@ -1183,6 +1207,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") .map_io = r8a7740_map_io, .init_early = eva_add_early_devices, .init_irq = r8a7740_init_irq, + .handle_irq = shmobile_handle_irq_intc, .init_machine = eva_init, .init_late = shmobile_init_late, .init_time = eva_earlytimer_init, diff --git a/trunk/arch/arm/mach-shmobile/board-bonito.c b/trunk/arch/arm/mach-shmobile/board-bonito.c index 70d992c540ae..e50f86691539 100644 --- a/trunk/arch/arm/mach-shmobile/board-bonito.c +++ b/trunk/arch/arm/mach-shmobile/board-bonito.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -289,16 +288,6 @@ static struct platform_device lcdc0_device = { }, }; -static const struct pinctrl_map lcdc0_pinctrl_map[] = { - /* LCD0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_data24_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_lclk_1", "lcd0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740", - "lcd0_sync", "lcd0"), -}; - /* * SMSC 9221 */ @@ -403,8 +392,8 @@ static void __init bonito_init(void) /* * base board settings */ - gpio_request_one(176, GPIOF_IN, NULL); - if (!gpio_get_value(176)) { + gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL); + if (!gpio_get_value(GPIO_PORT176)) { u16 bsw2; u16 bsw3; u16 bsw4; @@ -441,11 +430,38 @@ static void __init bonito_init(void) */ if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ - pinctrl_register_mappings(lcdc0_pinctrl_map, - ARRAY_SIZE(lcdc0_pinctrl_map)); - gpio_request(GPIO_FN_LCDC0_SELECT, NULL); - - gpio_request_one(61, GPIOF_OUT_INIT_HIGH, + gpio_request(GPIO_FN_LCDC0_SELECT, NULL); + gpio_request(GPIO_FN_LCD0_D0, NULL); + gpio_request(GPIO_FN_LCD0_D1, NULL); + gpio_request(GPIO_FN_LCD0_D2, NULL); + gpio_request(GPIO_FN_LCD0_D3, NULL); + gpio_request(GPIO_FN_LCD0_D4, NULL); + gpio_request(GPIO_FN_LCD0_D5, NULL); + gpio_request(GPIO_FN_LCD0_D6, NULL); + gpio_request(GPIO_FN_LCD0_D7, NULL); + gpio_request(GPIO_FN_LCD0_D8, NULL); + gpio_request(GPIO_FN_LCD0_D9, NULL); + gpio_request(GPIO_FN_LCD0_D10, NULL); + gpio_request(GPIO_FN_LCD0_D11, NULL); + gpio_request(GPIO_FN_LCD0_D12, NULL); + gpio_request(GPIO_FN_LCD0_D13, NULL); + gpio_request(GPIO_FN_LCD0_D14, NULL); + gpio_request(GPIO_FN_LCD0_D15, NULL); + gpio_request(GPIO_FN_LCD0_D16, NULL); + gpio_request(GPIO_FN_LCD0_D17, NULL); + gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL); + gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL); + gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL); + gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL); + gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL); + gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL); + gpio_request(GPIO_FN_LCD0_DCK, NULL); + gpio_request(GPIO_FN_LCD0_VSYN, NULL); + gpio_request(GPIO_FN_LCD0_HSYN, NULL); + gpio_request(GPIO_FN_LCD0_DISP, NULL); + gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL); + + gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* backlight on */ diff --git a/trunk/arch/arm/mach-shmobile/board-kota2.c b/trunk/arch/arm/mach-shmobile/board-kota2.c index ef5ca0ef0cb5..2ccc860403ef 100644 --- a/trunk/arch/arm/mach-shmobile/board-kota2.c +++ b/trunk/arch/arm/mach-shmobile/board-kota2.c @@ -24,8 +24,6 @@ #include #include #include -#include -#include #include #include #include @@ -137,17 +135,17 @@ static struct platform_device keysc_device = { #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } static struct gpio_keys_button gpio_buttons[] = { - GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */ - GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */ - GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */ - GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */ - GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */ - GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */ - GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */ - GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */ - /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */ - GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */ - /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */ + GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */ + GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */ + GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */ + GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */ + GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */ + GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */ + GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */ + GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */ + /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */ + GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */ + /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */ }; static struct gpio_keys_platform_data gpio_key_info = { @@ -167,9 +165,9 @@ static struct platform_device gpio_keys_device = { #define GPIO_LED(n, g) { .name = n, .gpio = g } static struct gpio_led gpio_leds[] = { - GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */ - GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */ - GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */ + GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */ + GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */ + GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */ }; static struct gpio_led_platform_data gpio_leds_info = { @@ -189,7 +187,7 @@ static struct platform_device gpio_leds_device = { static struct led_renesas_tpu_config led_renesas_tpu12_pdata = { .name = "V2513", .pin_gpio_fn = GPIO_FN_TPU1TO2, - .pin_gpio = 153, + .pin_gpio = GPIO_PORT153, .channel_offset = 0x90, .timer_bit = 2, .max_brightness = 1000, @@ -217,7 +215,7 @@ static struct platform_device leds_tpu12_device = { static struct led_renesas_tpu_config led_renesas_tpu41_pdata = { .name = "V2514", .pin_gpio_fn = GPIO_FN_TPU4TO1, - .pin_gpio = 199, + .pin_gpio = GPIO_PORT199, .channel_offset = 0x50, .timer_bit = 1, .max_brightness = 1000, @@ -245,7 +243,7 @@ static struct platform_device leds_tpu41_device = { static struct led_renesas_tpu_config led_renesas_tpu21_pdata = { .name = "V2515", .pin_gpio_fn = GPIO_FN_TPU2TO1, - .pin_gpio = 197, + .pin_gpio = GPIO_PORT197, .channel_offset = 0x50, .timer_bit = 1, .max_brightness = 1000, @@ -273,7 +271,7 @@ static struct platform_device leds_tpu21_device = { static struct led_renesas_tpu_config led_renesas_tpu30_pdata = { .name = "KEYLED", .pin_gpio_fn = GPIO_FN_TPU3TO0, - .pin_gpio = 163, + .pin_gpio = GPIO_PORT163, .channel_offset = 0x10, .timer_bit = 0, .max_brightness = 1000, @@ -435,85 +433,6 @@ static struct platform_device *kota2_devices[] __initdata = { &sdhi1_device, }; -static unsigned long pin_pullup_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), -}; - -static const struct pinctrl_map kota2_pinctrl_map[] = { - /* KEYSC */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_in8", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out04", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out5", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out6_0", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out7_0", "keysc"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_out8_0", "keysc"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0", - "keysc_in8", pin_pullup_conf), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", pin_pullup_conf), - /* SCIFA2 (UART2) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", - "scifa2_data_0", "scifa2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0", - "scifa2_ctrl_0", "scifa2"), - /* SCIFA4 (UART1) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_data", "scifa4"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_ctrl", "scifa4"), - /* SCIFB (BT) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", - "scifb_data_0", "scifb"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", - "scifb_clk_0", "scifb"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0", - "scifb_ctrl_0", "scifb"), - /* SDHI0 (microSD) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_cd", "sdhi0"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_data4", pin_pullup_conf), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "PORT256", pin_pullup_conf), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "PORT251", pin_pullup_conf), - /* SDHI1 (BCM4330) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_ctrl", "sdhi1"), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "sdhi1_data4", pin_pullup_conf), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0", - "PORT263", pin_pullup_conf), - /* SMSC911X */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_data_0_7", "bsc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_data_8_15", "bsc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_cs5_a", "bsc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_we0", "bsc"), -}; - static void __init kota2_init(void) { regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, @@ -522,16 +441,97 @@ static void __init kota2_init(void) ARRAY_SIZE(fixed3v3_power_consumers), 3300000); regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - pinctrl_register_mappings(kota2_pinctrl_map, - ARRAY_SIZE(kota2_pinctrl_map)); sh73a0_pinmux_init(); + /* SCIFA2 (UART2) */ + gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); + gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); + gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); + + /* SCIFA4 (UART1) */ + gpio_request(GPIO_FN_SCIFA4_TXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); + gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); + /* SMSC911X */ - gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */ - gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + gpio_request(GPIO_FN_D0_NAF0, NULL); + gpio_request(GPIO_FN_D1_NAF1, NULL); + gpio_request(GPIO_FN_D2_NAF2, NULL); + gpio_request(GPIO_FN_D3_NAF3, NULL); + gpio_request(GPIO_FN_D4_NAF4, NULL); + gpio_request(GPIO_FN_D5_NAF5, NULL); + gpio_request(GPIO_FN_D6_NAF6, NULL); + gpio_request(GPIO_FN_D7_NAF7, NULL); + gpio_request(GPIO_FN_D8_NAF8, NULL); + gpio_request(GPIO_FN_D9_NAF9, NULL); + gpio_request(GPIO_FN_D10_NAF10, NULL); + gpio_request(GPIO_FN_D11_NAF11, NULL); + gpio_request(GPIO_FN_D12_NAF12, NULL); + gpio_request(GPIO_FN_D13_NAF13, NULL); + gpio_request(GPIO_FN_D14_NAF14, NULL); + gpio_request(GPIO_FN_D15_NAF15, NULL); + gpio_request(GPIO_FN_CS5A_, NULL); + gpio_request(GPIO_FN_WE0__FWE, NULL); + gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ + gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ + + /* KEYSC */ + gpio_request(GPIO_FN_KEYIN0_PU, NULL); + gpio_request(GPIO_FN_KEYIN1_PU, NULL); + gpio_request(GPIO_FN_KEYIN2_PU, NULL); + gpio_request(GPIO_FN_KEYIN3_PU, NULL); + gpio_request(GPIO_FN_KEYIN4_PU, NULL); + gpio_request(GPIO_FN_KEYIN5_PU, NULL); + gpio_request(GPIO_FN_KEYIN6_PU, NULL); + gpio_request(GPIO_FN_KEYIN7_PU, NULL); + gpio_request(GPIO_FN_KEYOUT0, NULL); + gpio_request(GPIO_FN_KEYOUT1, NULL); + gpio_request(GPIO_FN_KEYOUT2, NULL); + gpio_request(GPIO_FN_KEYOUT3, NULL); + gpio_request(GPIO_FN_KEYOUT4, NULL); + gpio_request(GPIO_FN_KEYOUT5, NULL); + gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); + gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); + gpio_request(GPIO_FN_KEYOUT8, NULL); /* MMCIF */ - gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */ + + /* SDHI0 (microSD) */ + gpio_request(GPIO_FN_SDHICD0_PU, NULL); + gpio_request(GPIO_FN_SDHICMD0_PU, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3_PU, NULL); + gpio_request(GPIO_FN_SDHID0_2_PU, NULL); + gpio_request(GPIO_FN_SDHID0_1_PU, NULL); + gpio_request(GPIO_FN_SDHID0_0_PU, NULL); + + /* SCIFB (BT) */ + gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL); + gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL); + gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL); + gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL); + gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL); + + /* SDHI1 (BCM4330) */ + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHICMD1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_3_PU, NULL); + gpio_request(GPIO_FN_SDHID1_2_PU, NULL); + gpio_request(GPIO_FN_SDHID1_1_PU, NULL); + gpio_request(GPIO_FN_SDHID1_0_PU, NULL); #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ diff --git a/trunk/arch/arm/mach-shmobile/board-kzm9g.c b/trunk/arch/arm/mach-shmobile/board-kzm9g.c index 446d04db404f..7f3a6b7e7b7c 100644 --- a/trunk/arch/arm/mach-shmobile/board-kzm9g.c +++ b/trunk/arch/arm/mach-shmobile/board-kzm9g.c @@ -30,8 +30,6 @@ #include #include #include -#include -#include #include #include #include @@ -83,7 +81,7 @@ static struct resource smsc9221_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = irq_pin(3), /* IRQ3 */ + .start = intcs_evt2irq(0x260), /* IRQ3 */ .flags = IORESOURCE_IRQ, }, }; @@ -117,7 +115,7 @@ static struct resource usb_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = irq_pin(1), /* IRQ1 */ + .start = intcs_evt2irq(0x220), /* IRQ1 */ .flags = IORESOURCE_IRQ, }, }; @@ -140,7 +138,7 @@ struct usbhs_private { struct renesas_usbhs_platform_info info; }; -#define IRQ15 irq_pin(15) +#define IRQ15 intcs_evt2irq(0x03e0) #define USB_PHY_MODE (1 << 4) #define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) #define USB_PHY_ON (1 << 1) @@ -435,7 +433,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = { TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED, .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, - .cd_gpio = 13, + .cd_gpio = GPIO_PORT13, }; static struct resource sdhi2_resources[] = { @@ -565,25 +563,25 @@ static struct i2c_board_info i2c0_devices[] = { }, { I2C_BOARD_INFO("ak8975", 0x0c), - .irq = irq_pin(28), /* IRQ28 */ + .irq = intcs_evt2irq(0x3380), /* IRQ28 */ }, { I2C_BOARD_INFO("adxl34x", 0x1d), - .irq = irq_pin(26), /* IRQ26 */ + .irq = intcs_evt2irq(0x3340), /* IRQ26 */ }, }; static struct i2c_board_info i2c1_devices[] = { { I2C_BOARD_INFO("st1232-ts", 0x55), - .irq = irq_pin(8), /* IRQ8 */ + .irq = intcs_evt2irq(0x300), /* IRQ8 */ }, }; static struct i2c_board_info i2c3_devices[] = { { I2C_BOARD_INFO("pcf8575", 0x20), - .irq = irq_pin(19), /* IRQ19 */ + .irq = intcs_evt2irq(0x3260), /* IRQ19 */ .platform_data = &pcf8575_pdata, }, }; @@ -601,64 +599,6 @@ static struct platform_device *kzm_devices[] __initdata = { &fsi_ak4648_device, }; -static unsigned long pin_pullup_conf[] = { - PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0), -}; - -static const struct pinctrl_map kzm_pinctrl_map[] = { - /* FSIA (AK4648) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_mclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_sclk_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_data_in", "fsia"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0", - "fsia_data_out", "fsia"), - /* I2C3 */ - PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0", - "i2c3_1", "i2c3"), - /* LCD */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", - "lcd_data24", "lcd"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0", - "lcd_sync", "lcd"), - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_ctrl_0", "mmc0"), - PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "PORT279", pin_pullup_conf), - PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0", - "mmc0_data8_0", pin_pullup_conf), - /* SCIFA4 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_data", "scifa4"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0", - "scifa4_ctrl", "scifa4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0", - "sdhi0_wp", "sdhi0"), - /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", - "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0", - "sdhi2_ctrl", "sdhi2"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0", - "bsc_cs4", "bsc"), - /* USB */ - PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0", - "usb_vbus", "usb"), -}; - /* * FIXME * @@ -720,26 +660,100 @@ static void __init kzm_init(void) ARRAY_SIZE(fixed2v8_power_consumers), 2800000); regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map)); - sh73a0_pinmux_init(); + /* enable SCIFA4 */ + gpio_request(GPIO_FN_SCIFA4_TXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RXD, NULL); + gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); + gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); + + /* CS4 for SMSC/USB */ + gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */ + /* SMSC */ - gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */ + gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */ /* LCDC */ - gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ - gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ + gpio_request(GPIO_FN_LCDD23, NULL); + gpio_request(GPIO_FN_LCDD22, NULL); + gpio_request(GPIO_FN_LCDD21, NULL); + gpio_request(GPIO_FN_LCDD20, NULL); + gpio_request(GPIO_FN_LCDD19, NULL); + gpio_request(GPIO_FN_LCDD18, NULL); + gpio_request(GPIO_FN_LCDD17, NULL); + gpio_request(GPIO_FN_LCDD16, NULL); + gpio_request(GPIO_FN_LCDD15, NULL); + gpio_request(GPIO_FN_LCDD14, NULL); + gpio_request(GPIO_FN_LCDD13, NULL); + gpio_request(GPIO_FN_LCDD12, NULL); + gpio_request(GPIO_FN_LCDD11, NULL); + gpio_request(GPIO_FN_LCDD10, NULL); + gpio_request(GPIO_FN_LCDD9, NULL); + gpio_request(GPIO_FN_LCDD8, NULL); + gpio_request(GPIO_FN_LCDD7, NULL); + gpio_request(GPIO_FN_LCDD6, NULL); + gpio_request(GPIO_FN_LCDD5, NULL); + gpio_request(GPIO_FN_LCDD4, NULL); + gpio_request(GPIO_FN_LCDD3, NULL); + gpio_request(GPIO_FN_LCDD2, NULL); + gpio_request(GPIO_FN_LCDD1, NULL); + gpio_request(GPIO_FN_LCDD0, NULL); + gpio_request(GPIO_FN_LCDDISP, NULL); + gpio_request(GPIO_FN_LCDDCK, NULL); + + gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */ + gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */ /* Touchscreen */ - gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */ + gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */ + + /* enable MMCIF */ + gpio_request(GPIO_FN_MMCCLK0, NULL); + gpio_request(GPIO_FN_MMCCMD0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_0_PU, NULL); + gpio_request(GPIO_FN_MMCD0_1_PU, NULL); + gpio_request(GPIO_FN_MMCD0_2_PU, NULL); + gpio_request(GPIO_FN_MMCD0_3_PU, NULL); + gpio_request(GPIO_FN_MMCD0_4_PU, NULL); + gpio_request(GPIO_FN_MMCD0_5_PU, NULL); + gpio_request(GPIO_FN_MMCD0_6_PU, NULL); + gpio_request(GPIO_FN_MMCD0_7_PU, NULL); /* enable SD */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICD0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ /* enable Micro SD */ - gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + gpio_request(GPIO_FN_SDHID2_0, NULL); + gpio_request(GPIO_FN_SDHID2_1, NULL); + gpio_request(GPIO_FN_SDHID2_2, NULL); + gpio_request(GPIO_FN_SDHID2_3, NULL); + gpio_request(GPIO_FN_SDHICMD2, NULL); + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */ + + /* I2C 3 */ + gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); + gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); + + /* enable FSI2 port A (ak4648) */ + gpio_request(GPIO_FN_FSIACK, NULL); + gpio_request(GPIO_FN_FSIAILR, NULL); + gpio_request(GPIO_FN_FSIAIBT, NULL); + gpio_request(GPIO_FN_FSIAISLD, NULL); + gpio_request(GPIO_FN_FSIAOSLD, NULL); + + /* enable USB */ + gpio_request(GPIO_FN_VBUS_0, NULL); #ifdef CONFIG_CACHE_L2X0 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ diff --git a/trunk/arch/arm/mach-shmobile/board-mackerel.c b/trunk/arch/arm/mach-shmobile/board-mackerel.c index 336ccb4a0f2a..db968a585ff0 100644 --- a/trunk/arch/arm/mach-shmobile/board-mackerel.c +++ b/trunk/arch/arm/mach-shmobile/board-mackerel.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include #include @@ -364,7 +363,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = { static int mackerel_set_brightness(int brightness) { - gpio_set_value(31, brightness); + gpio_set_value(GPIO_PORT31, brightness); return 0; } @@ -820,22 +819,22 @@ static struct platform_device usbhs1_device = { static struct gpio_led mackerel_leds[] = { { .name = "led0", - .gpio = 0, + .gpio = GPIO_PORT0, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led1", - .gpio = 1, + .gpio = GPIO_PORT1, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led2", - .gpio = 2, + .gpio = GPIO_PORT2, .default_state = LEDS_GPIO_DEFSTATE_ON, }, { .name = "led3", - .gpio = 159, + .gpio = GPIO_PORT159, .default_state = LEDS_GPIO_DEFSTATE_ON, } }; @@ -965,11 +964,11 @@ static struct platform_device nand_flash_device = { /* * The card detect pin of the top SD/MMC slot (CN7) is active low and is - * connected to GPIO A22 of SH7372 (GPIO 41). + * connected to GPIO A22 of SH7372 (GPIO_PORT41). */ static int slot_cn7_get_cd(struct platform_device *pdev) { - return !gpio_get_value(41); + return !gpio_get_value(GPIO_PORT41); } /* SDHI0 */ @@ -978,7 +977,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = { .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_USE_GPIO_CD, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, - .cd_gpio = 172, + .cd_gpio = GPIO_PORT172, }; static struct resource sdhi0_resources[] = { @@ -1061,11 +1060,11 @@ static struct platform_device sdhi1_device = { /* * The card detect pin of the top SD/MMC slot (CN23) is active low and is - * connected to GPIO SCIFB_SCK of SH7372 (162). + * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). */ static int slot_cn23_get_cd(struct platform_device *pdev) { - return !gpio_get_value(162); + return !gpio_get_value(GPIO_PORT162); } /* SDHI2 */ @@ -1329,33 +1328,6 @@ static struct i2c_board_info i2c1_devices[] = { }, }; -static const struct pinctrl_map mackerel_pinctrl_map[] = { - /* MMCIF */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_data8_0", "mmc0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372", - "mmc0_ctrl_0", "mmc0"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", - "sdhi0_wp", "sdhi0"), - /* SDHI1 */ -#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_data4", "sdhi1"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", - "sdhi1_ctrl", "sdhi1"), -#endif - /* SDHI2 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", - "sdhi2_data4", "sdhi2"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", - "sdhi2_ctrl", "sdhi2"), -}; - #define GPIO_PORT9CR IOMEM(0xE6051009) #define GPIO_PORT10CR IOMEM(0xE605100A) #define GPIO_PORT167CR IOMEM(0xE60520A7) @@ -1392,8 +1364,6 @@ static void __init mackerel_init(void) /* External clock source */ clk_set_rate(&sh7372_dv_clki_clk, 27000000); - pinctrl_register_mappings(mackerel_pinctrl_map, - ARRAY_SIZE(mackerel_pinctrl_map)); sh7372_pinmux_init(); /* enable SCIFA0 */ @@ -1433,9 +1403,9 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_LCDDCK, NULL); /* backlight, off by default */ - gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL); + gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL); - gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ + gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ /* USBHS0 */ gpio_request(GPIO_FN_VBUS0_0, NULL); @@ -1451,10 +1421,10 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_FSIAILR, NULL); gpio_request(GPIO_FN_FSIAISLD, NULL); gpio_request(GPIO_FN_FSIAOSLD, NULL); - gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ + gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ - gpio_request(9, NULL); - gpio_request(10, NULL); + gpio_request(GPIO_PORT9, NULL); + gpio_request(GPIO_PORT10, NULL); gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ @@ -1483,14 +1453,52 @@ static void __init mackerel_init(void) gpio_request(GPIO_FN_IRQ21, NULL); irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); + /* enable SDHI0 */ + gpio_request(GPIO_FN_SDHIWP0, NULL); + gpio_request(GPIO_FN_SDHICMD0, NULL); + gpio_request(GPIO_FN_SDHICLK0, NULL); + gpio_request(GPIO_FN_SDHID0_3, NULL); + gpio_request(GPIO_FN_SDHID0_2, NULL); + gpio_request(GPIO_FN_SDHID0_1, NULL); + gpio_request(GPIO_FN_SDHID0_0, NULL); + /* SDHI0 PORT172 card-detect IRQ26 */ gpio_request(GPIO_FN_IRQ26_172, NULL); +#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) + /* enable SDHI1 */ + gpio_request(GPIO_FN_SDHICMD1, NULL); + gpio_request(GPIO_FN_SDHICLK1, NULL); + gpio_request(GPIO_FN_SDHID1_3, NULL); + gpio_request(GPIO_FN_SDHID1_2, NULL); + gpio_request(GPIO_FN_SDHID1_1, NULL); + gpio_request(GPIO_FN_SDHID1_0, NULL); +#endif /* card detect pin for MMC slot (CN7) */ - gpio_request_one(41, GPIOF_IN, NULL); + gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); + + /* enable SDHI2 */ + gpio_request(GPIO_FN_SDHICMD2, NULL); + gpio_request(GPIO_FN_SDHICLK2, NULL); + gpio_request(GPIO_FN_SDHID2_3, NULL); + gpio_request(GPIO_FN_SDHID2_2, NULL); + gpio_request(GPIO_FN_SDHID2_1, NULL); + gpio_request(GPIO_FN_SDHID2_0, NULL); /* card detect pin for microSD slot (CN23) */ - gpio_request_one(162, GPIOF_IN, NULL); + gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL); + + /* MMCIF */ + gpio_request(GPIO_FN_MMCD0_0, NULL); + gpio_request(GPIO_FN_MMCD0_1, NULL); + gpio_request(GPIO_FN_MMCD0_2, NULL); + gpio_request(GPIO_FN_MMCD0_3, NULL); + gpio_request(GPIO_FN_MMCD0_4, NULL); + gpio_request(GPIO_FN_MMCD0_5, NULL); + gpio_request(GPIO_FN_MMCD0_6, NULL); + gpio_request(GPIO_FN_MMCD0_7, NULL); + gpio_request(GPIO_FN_MMCCMD0, NULL); + gpio_request(GPIO_FN_MMCCLK0, NULL); /* FLCTL */ gpio_request(GPIO_FN_D0_NAF0, NULL); diff --git a/trunk/arch/arm/mach-shmobile/board-marzen.c b/trunk/arch/arm/mach-shmobile/board-marzen.c index a88f7f3594c7..fec49ebc359a 100644 --- a/trunk/arch/arm/mach-shmobile/board-marzen.c +++ b/trunk/arch/arm/mach-shmobile/board-marzen.c @@ -25,9 +25,8 @@ #include #include #include -#include +#include #include -#include #include #include #include @@ -169,43 +168,12 @@ static struct platform_device usb_phy_device = { .num_resources = ARRAY_SIZE(usb_phy_resources), }; -/* LEDS */ -static struct gpio_led marzen_leds[] = { - { - .name = "led2", - .gpio = 157, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "led3", - .gpio = 158, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, { - .name = "led4", - .gpio = 159, - .default_state = LEDS_GPIO_DEFSTATE_ON, - }, -}; - -static struct gpio_led_platform_data marzen_leds_pdata = { - .leds = marzen_leds, - .num_leds = ARRAY_SIZE(marzen_leds), -}; - -static struct platform_device leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &marzen_leds_pdata, - }, -}; - static struct platform_device *marzen_devices[] __initdata = { ð_device, &sdhi0_device, &thermal_device, &hspi_device, &usb_phy_device, - &leds_device, }; /* USB */ @@ -359,41 +327,6 @@ void __init marzen_init_late(void) ARRAY_SIZE(marzen_late_devices)); } -static const struct pinctrl_map marzen_pinctrl_map[] = { - /* HSPI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779", - "hspi0", "hspi0"), - /* SCIF2 (CN18: DEBUG0) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779", - "scif2_data_c", "scif2"), - /* SCIF4 (CN19: DEBUG1) */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779", - "scif4_data", "scif4"), - /* SDHI0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_data4", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_ctrl", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_wp", "sdhi0"), - /* SMSC */ - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "intc_irq1_b", "intc"), - PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", - "lbsc_ex_cs0", "lbsc"), - /* USB0 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", - "usb0", "usb0"), - /* USB1 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779", - "usb1", "usb1"), - /* USB2 */ - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779", - "usb2", "usb2"), -}; - static void __init marzen_init(void) { regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, @@ -401,10 +334,44 @@ static void __init marzen_init(void) regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - pinctrl_register_mappings(marzen_pinctrl_map, - ARRAY_SIZE(marzen_pinctrl_map)); r8a7779_pinmux_init(); + /* SCIF2 (CN18: DEBUG0) */ + gpio_request(GPIO_FN_TX2_C, NULL); + gpio_request(GPIO_FN_RX2_C, NULL); + + /* SCIF4 (CN19: DEBUG1) */ + gpio_request(GPIO_FN_TX4, NULL); + gpio_request(GPIO_FN_RX4, NULL); + + /* LAN89218 */ + gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */ + gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */ + + /* SD0 (CN20) */ + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_DAT0, NULL); + gpio_request(GPIO_FN_SD0_DAT1, NULL); + gpio_request(GPIO_FN_SD0_DAT2, NULL); + gpio_request(GPIO_FN_SD0_DAT3, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD0_WP, NULL); + + /* HSPI 0 */ + gpio_request(GPIO_FN_HSPI_CLK0, NULL); + gpio_request(GPIO_FN_HSPI_CS0, NULL); + gpio_request(GPIO_FN_HSPI_TX0, NULL); + gpio_request(GPIO_FN_HSPI_RX0, NULL); + + /* USB (CN21) */ + gpio_request(GPIO_FN_USB_OVC0, NULL); + gpio_request(GPIO_FN_USB_OVC1, NULL); + gpio_request(GPIO_FN_USB_OVC2, NULL); + + /* USB (CN22) */ + gpio_request(GPIO_FN_USB_PENC2, NULL); + r8a7779_add_standard_devices(); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a73a4.c b/trunk/arch/arm/mach-shmobile/clock-r8a73a4.c deleted file mode 100644 index e710c00c3822..000000000000 --- a/trunk/arch/arm/mach-shmobile/clock-r8a73a4.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * r8a73a4 clock framework support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include -#include - -#define CPG_BASE 0xe6150000 -#define CPG_LEN 0x270 - -#define MPCKCR 0xe6150080 -#define SMSTPCR2 0xe6150138 -#define SMSTPCR5 0xe6150144 - -static struct clk_mapping cpg_mapping = { - .phys = CPG_BASE, - .len = CPG_LEN, -}; - -static struct clk extalr_clk = { - .rate = 32768, - .mapping = &cpg_mapping, -}; - -static struct clk extal1_clk = { - .rate = 26000000, - .mapping = &cpg_mapping, -}; - -static struct clk extal2_clk = { - .rate = 48000000, - .mapping = &cpg_mapping, -}; - -static struct clk *main_clks[] = { - &extalr_clk, - &extal1_clk, - &extal2_clk, -}; - -enum { - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, - MSTP522, - MSTP_NR -}; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ - [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ -}; - -static struct clk_lookup lookups[] = { - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), - CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), - - /* for DT */ - CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), -}; - -void __init r8a73a4_clock_init(void) -{ - void __iomem *cpg_base, *reg; - int k, ret = 0; - - /* fix MPCLK to EXTAL2 for now. - * this is needed until more detailed clock topology is supported - */ - cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); - BUG_ON(!cpg_base); - reg = cpg_base + (MPCKCR - CPG_BASE); - iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ - iounmap(cpg_base); - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a73a4 clocks\n"); -} diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a7740.c b/trunk/arch/arm/mach-shmobile/clock-r8a7740.c index c0d39aa6de50..19ce885a3b43 100644 --- a/trunk/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/trunk/arch/arm/mach-shmobile/clock-r8a7740.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -98,13 +97,42 @@ static struct clk dv_clk = { .rate = 27000000, }; -SH_CLK_RATIO(div2, 1, 2); -SH_CLK_RATIO(div1k, 1, 1024); +static unsigned long div_recalc(struct clk *clk) +{ + return clk->parent->rate / (int)(clk->priv); +} + +static struct sh_clk_ops div_clk_ops = { + .recalc = div_recalc, +}; + +/* extal1 / 2 */ +static struct clk extal1_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &extal1_clk, +}; + +/* extal1 / 1024 */ +static struct clk extal1_div1024_clk = { + .ops = &div_clk_ops, + .priv = (void *)1024, + .parent = &extal1_clk, +}; + +/* extal1 / 2 / 1024 */ +static struct clk extal1_div2048_clk = { + .ops = &div_clk_ops, + .priv = (void *)1024, + .parent = &extal1_div2_clk, +}; -SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k); -SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k); -SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); +/* extal2 / 2 */ +static struct clk extal2_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &extal2_clk, +}; static struct sh_clk_ops followparent_clk_ops = { .recalc = followparent_recalc, @@ -115,7 +143,11 @@ static struct clk system_clk = { .ops = &followparent_clk_ops, }; -SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2); +static struct clk system_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &system_clk, +}; /* r_clk */ static struct clk r_clk = { @@ -152,7 +184,11 @@ static struct clk pllc1_clk = { }; /* PLLC1 / 2 */ -SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); +static struct clk pllc1_div2_clk = { + .ops = &div_clk_ops, + .priv = (void *)2, + .parent = &pllc1_clk, +}; /* USB clock */ /* @@ -287,7 +323,6 @@ struct clk *main_clks[] = { &fsibck_clk, }; -/* DIV4 clocks */ static void div4_kick(struct clk *clk) { unsigned long value; @@ -311,26 +346,6 @@ static struct clk_div4_table div4_table = { .kick = div4_kick, }; -enum { - DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, - DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, - DIV4_NR -}; - -struct clk div4_clks[DIV4_NR] = { - [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), - [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), - [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), - [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), - [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), - [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), - [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), - [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), -}; - /* DIV6 reparent */ enum { DIV6_HDMI, @@ -376,16 +391,6 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), }; -/* DIV6 clocks */ -enum { - DIV6_SUB, - DIV6_NR -}; - -static struct clk div6_clks[DIV6_NR] = { - [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), -}; - /* HDMI1/2 clock */ static unsigned long hdmi12_recalc(struct clk *clk) { @@ -450,6 +455,35 @@ static struct clk fsidivs[] = { }; /* MSTP */ +enum { + DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, + DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP, + DIV4_NR +}; + +struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), + [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0), + [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0), + [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0), + [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0), + [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0), + [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0), + [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0), +}; + +enum { + DIV6_SUB, + DIV6_NR +}; + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0), +}; + enum { MSTP128, MSTP127, MSTP125, MSTP116, MSTP111, MSTP100, MSTP117, @@ -559,42 +593,29 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), - CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]), CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), - CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), - CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), - CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]), CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), - CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]), CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), - CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* ICK */ CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a7778.c b/trunk/arch/arm/mach-shmobile/clock-r8a7778.c deleted file mode 100644 index cd6855290b1f..000000000000 --- a/trunk/arch/arm/mach-shmobile/clock-r8a7778.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * r8a7778 clock framework support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * based on r8a7779 - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define MSTPCR0 IOMEM(0xffc80030) -#define MSTPCR1 IOMEM(0xffc80034) -#define MSTPCR3 IOMEM(0xffc8003c) -#define MSTPSR1 IOMEM(0xffc80044) -#define MSTPSR4 IOMEM(0xffc80048) -#define MSTPSR6 IOMEM(0xffc8004c) -#define MSTPCR4 IOMEM(0xffc80050) -#define MSTPCR5 IOMEM(0xffc80054) -#define MSTPCR6 IOMEM(0xffc80058) - -/* ioremap() through clock mapping mandatory to avoid - * collision with ARM coherent DMA virtual memory range. - */ - -static struct clk_mapping cpg_mapping = { - .phys = 0xffc80000, - .len = 0x80, -}; - -static struct clk clkp = { - .rate = 62500000, /* FIXME: shortcut */ - .flags = CLK_ENABLE_ON_INIT, - .mapping = &cpg_mapping, -}; - -static struct clk *main_clks[] = { - &clkp, -}; - -enum { - MSTP114, - MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, - MSTP016, MSTP015, - MSTP_NR }; - -static struct clk mstp_clks[MSTP_NR] = { - [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */ - [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */ -}; - -static struct clk_lookup lookups[] = { - /* MSTP32 clocks */ - CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ - CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ - CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ -}; - -void __init r8a7778_clock_init(void) -{ - int k, ret = 0; - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a7778 clocks\n"); -} diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a7779.c b/trunk/arch/arm/mach-shmobile/clock-r8a7779.c index 31d5cd4d9787..1db36537255c 100644 --- a/trunk/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/trunk/arch/arm/mach-shmobile/clock-r8a7779.c @@ -17,36 +17,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include #include #include #include #include #include -#include #include -/* - * MD1 = 1 MD1 = 0 - * (PLLA = 1500) (PLLA = 1600) - * (MHz) (MHz) - *------------------------------------------------+-------------------- - * clkz 1000 (2/3) 800 (1/2) - * clkzs 250 (1/6) 200 (1/8) - * clki 750 (1/2) 800 (1/2) - * clks 250 (1/6) 200 (1/8) - * clks1 125 (1/12) 100 (1/16) - * clks3 187.5 (1/8) 200 (1/8) - * clks4 93.7 (1/16) 100 (1/16) - * clkp 62.5 (1/24) 50 (1/32) - * clkg 62.5 (1/24) 66.6 (1/24) - * clkb, CLKOUT - * (MD2 = 0) 62.5 (1/24) 66.6 (1/24) - * (MD2 = 1) 41.6 (1/36) 50 (1/32) -*/ - -#define MD(nr) BIT(nr) - #define FRQMR IOMEM(0xffc80014) #define MSTPCR0 IOMEM(0xffc80030) #define MSTPCR1 IOMEM(0xffc80034) @@ -59,9 +36,6 @@ #define MSTPCR6 IOMEM(0xffc80058) #define MSTPCR7 IOMEM(0xffc80040) -#define MODEMR 0xffcc0020 - - /* ioremap() through clock mapping mandatory to avoid * collision with ARM coherent DMA virtual memory range. */ @@ -76,44 +50,44 @@ static struct clk_mapping cpg_mapping = { * from the platform code. */ static struct clk plla_clk = { - /* .rate will be updated on r8a7779_clock_init() */ + .rate = 1500000000, .mapping = &cpg_mapping, }; -/* - * clock ratio of these clock will be updated - * on r8a7779_clock_init() - */ -SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1); -SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1); - static struct clk *main_clks[] = { &plla_clk, - &clkz_clk, - &clkzs_clk, - &clki_clk, - &clks_clk, - &clks1_clk, - &clks3_clk, - &clks4_clk, - &clkb_clk, - &clkout_clk, - &clkp_clk, - &clkg_clk, +}; + +static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, +}; + +enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR }; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20, + 0x0018, CLK_ENABLE_ON_INIT), + [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16, + 0x0700, CLK_ENABLE_ON_INIT), + [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12, + 0x0040, CLK_ENABLE_ON_INIT), + [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8, + 0x0010, CLK_ENABLE_ON_INIT), + [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4, + 0x0060, CLK_ENABLE_ON_INIT), + [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0, + 0x0300, CLK_ENABLE_ON_INIT), }; enum { MSTP323, MSTP322, MSTP321, MSTP320, - MSTP115, MSTP114, - MSTP103, MSTP101, MSTP100, + MSTP101, MSTP100, MSTP030, MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, MSTP016, MSTP015, MSTP014, @@ -121,29 +95,50 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320, MSTP_NR }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */ - [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ - [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ - [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ - [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ - [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ - [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ - [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ - [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ - [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ - [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ - [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ - [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */ - [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */ - [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */ - [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */ - [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */ - [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */ - [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */ - [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */ - [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */ - [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */ - [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */ + [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ + [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ + [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ + [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ + [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ + [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ + [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ + [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ + [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ + [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ + [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ + [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ + [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ + [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ + [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ + [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ + [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ +}; + +static unsigned long mul4_recalc(struct clk *clk) +{ + return clk->parent->rate * 4; +} + +static struct sh_clk_ops mul4_clk_ops = { + .recalc = mul4_recalc, +}; + +struct clk clkz_clk = { + .ops = &mul4_clk_ops, + .parent = &div4_clks[DIV4_S], +}; + +struct clk clkzs_clk = { + /* clks x 4 / 4 = clks */ + .parent = &div4_clks[DIV4_S], +}; + +static struct clk *late_main_clks[] = { + &clkz_clk, + &clkzs_clk, }; static struct clk_lookup lookups[] = { @@ -153,17 +148,14 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), /* DIV4 clocks */ - CLKDEV_CON_ID("shyway_clk", &clks_clk), - CLKDEV_CON_ID("bus_clk", &clkout_clk), - CLKDEV_CON_ID("shyway4_clk", &clks4_clk), - CLKDEV_CON_ID("shyway3_clk", &clks3_clk), - CLKDEV_CON_ID("shyway1_clk", &clks1_clk), - CLKDEV_CON_ID("peripheral_clk", &clkp_clk), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), + CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), + CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), + CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), /* MSTP32 clocks */ - CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ - CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */ - CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */ CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */ CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */ CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ @@ -188,65 +180,24 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ - CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */ }; void __init r8a7779_clock_init(void) { - void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); - u32 mode; int k, ret = 0; - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - - if (mode & MD(1)) { - plla_clk.rate = 1500000000; - - SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); - if (mode & MD(2)) { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36); - } else { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); - } - } else { - plla_clk.rate = 1600000000; - - SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); - SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); - SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); - SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32); - SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); - if (mode & MD(2)) { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32); - } else { - SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24); - SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24); - } - } - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); + if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); + for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) + ret = clk_register(late_main_clks[k]); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); if (!ret) diff --git a/trunk/arch/arm/mach-shmobile/clock-r8a7790.c b/trunk/arch/arm/mach-shmobile/clock-r8a7790.c deleted file mode 100644 index bad9bf2e34d6..000000000000 --- a/trunk/arch/arm/mach-shmobile/clock-r8a7790.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * r8a7790 clock framework support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include -#include - -#define CPG_BASE 0xe6150000 -#define CPG_LEN 0x1000 - -#define SMSTPCR2 0xe6150138 -#define SMSTPCR7 0xe615014c - -static struct clk_mapping cpg_mapping = { - .phys = CPG_BASE, - .len = CPG_LEN, -}; - -static struct clk p_clk = { - .rate = 65000000, /* shortcut for now */ - .mapping = &cpg_mapping, -}; - -static struct clk mp_clk = { - .rate = 52000000, /* shortcut for now */ - .mapping = &cpg_mapping, -}; - -static struct clk *main_clks[] = { - &p_clk, - &mp_clk, -}; - -enum { MSTP721, MSTP720, - MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; -static struct clk mstp_clks[MSTP_NR] = { - [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ - [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ - [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ -}; - -static struct clk_lookup lookups[] = { - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), - CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), - CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), -}; - -void __init r8a7790_clock_init(void) -{ - int k, ret = 0; - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup r8a7790 clocks\n"); -} diff --git a/trunk/arch/arm/mach-shmobile/clock-sh7372.c b/trunk/arch/arm/mach-shmobile/clock-sh7372.c index 7e105932c09d..45d21fe317f4 100644 --- a/trunk/arch/arm/mach-shmobile/clock-sh7372.c +++ b/trunk/arch/arm/mach-shmobile/clock-sh7372.c @@ -21,7 +21,6 @@ #include #include #include -#include #include /* SH7372 registers */ @@ -84,12 +83,39 @@ struct clk sh7372_extal2_clk = { .rate = 48000000, }; -SH_CLK_RATIO(div2, 1, 2); +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) +{ + return clk->parent->rate / 2; +} + +static struct sh_clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; -SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2); -SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2); +/* Divide dv_clki by two */ +struct clk sh7372_dv_clki_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7372_dv_clki_clk, +}; + +/* Divide extal1 by two */ +static struct clk extal1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7372_extal1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh7372_extal2_clk, +}; + +/* Divide extal2 by four */ +static struct clk extal2_div4_clk = { + .ops = &div2_clk_ops, + .parent = &extal2_div2_clk, +}; /* PLLC0 and PLLC1 */ static unsigned long pllc01_recalc(struct clk *clk) @@ -121,7 +147,10 @@ static struct clk pllc1_clk = { }; /* Divide PLLC1 by two */ -SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2); +static struct clk pllc1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pllc1_clk, +}; /* PLLC2 */ @@ -313,7 +342,7 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, - DIV4_ZX, DIV4_HP, + DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_DDRP, DIV4_NR }; @@ -326,6 +355,8 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), + [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0), + [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), @@ -485,6 +516,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), + CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]), + CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]), CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), @@ -621,4 +654,5 @@ void __init sh7372_clock_init(void) shmobile_clk_init(); else panic("failed to setup sh7372 clocks\n"); + } diff --git a/trunk/arch/arm/mach-shmobile/clock-sh73a0.c b/trunk/arch/arm/mach-shmobile/clock-sh73a0.c index 784fbaa4cc55..afa5423a0f93 100644 --- a/trunk/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/trunk/arch/arm/mach-shmobile/clock-sh73a0.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #define FRQCRA IOMEM(0xe6150000) @@ -84,16 +82,61 @@ struct clk sh73a0_extal2_clk = { .rate = 48000000, }; +/* A fixed divide-by-2 block */ +static unsigned long div2_recalc(struct clk *clk) +{ + return clk->parent->rate / 2; +} + +static struct sh_clk_ops div2_clk_ops = { + .recalc = div2_recalc, +}; + +static unsigned long div7_recalc(struct clk *clk) +{ + return clk->parent->rate / 7; +} + +static struct sh_clk_ops div7_clk_ops = { + .recalc = div7_recalc, +}; + +static unsigned long div13_recalc(struct clk *clk) +{ + return clk->parent->rate / 13; +} + +static struct sh_clk_ops div13_clk_ops = { + .recalc = div13_recalc, +}; + +/* Divide extal1 by two */ +static struct clk extal1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh73a0_extal1_clk, +}; + +/* Divide extal2 by two */ +static struct clk extal2_div2_clk = { + .ops = &div2_clk_ops, + .parent = &sh73a0_extal2_clk, +}; + static struct sh_clk_ops main_clk_ops = { .recalc = followparent_recalc, }; /* Main clock */ static struct clk main_clk = { - /* .parent wll be set on sh73a0_clock_init() */ .ops = &main_clk_ops, }; +/* Divide Main clock by two */ +static struct clk main_div2_clk = { + .ops = &div2_clk_ops, + .parent = &main_clk, +}; + /* PLL0, PLL1, PLL2, PLL3 */ static unsigned long pll_recalc(struct clk *clk) { @@ -149,17 +192,21 @@ static struct clk pll3_clk = { .enable_bit = 3, }; -/* A fixed divide block */ -SH_CLK_RATIO(div2, 1, 2); -SH_CLK_RATIO(div7, 1, 7); -SH_CLK_RATIO(div13, 1, 13); +/* Divide PLL */ +static struct clk pll1_div2_clk = { + .ops = &div2_clk_ops, + .parent = &pll1_clk, +}; + +static struct clk pll1_div7_clk = { + .ops = &div7_clk_ops, + .parent = &pll1_clk, +}; -SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2); -SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2); -SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); -SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); -SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7); -SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13); +static struct clk pll1_div13_clk = { + .ops = &div13_clk_ops, + .parent = &pll1_clk, +}; /* External input clock */ struct clk sh73a0_extcki_clk = { @@ -187,24 +234,14 @@ static struct clk *main_clks[] = { &sh73a0_extalr_clk, }; -static int frqcr_kick(void) -{ - int i; - - /* set KICK bit in FRQCRB to update hardware setting, check success */ - __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); - for (i = 1000; i; i--) - if (__raw_readl(FRQCRB) & (1 << 31)) - cpu_relax(); - else - return i; - - return -ETIMEDOUT; -} - static void div4_kick(struct clk *clk) { - frqcr_kick(); + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = __raw_readl(FRQCRB); + value |= (1 << 31); + __raw_writel(value, FRQCRB); } static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, @@ -221,37 +258,25 @@ static struct clk_div4_table div4_table = { }; enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, - DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; + DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; #define DIV4(_reg, _bit, _mask, _flags) \ SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) static struct clk div4_clks[DIV4_NR] = { [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT), - [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), + [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT), [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT), [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), - [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), + [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0), + [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), + [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), }; -static unsigned long twd_recalc(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 4; -} - -static struct sh_clk_ops twd_clk_ops = { - .recalc = twd_recalc, -}; - -static struct clk twd_clk = { - .parent = &div4_clks[DIV4_Z], - .ops = &twd_clk_ops, -}; - enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, DIV6_FSIA, DIV6_FSIB, DIV6_SUB, @@ -446,7 +471,6 @@ static struct clk dsi1phy_clk = { static struct clk *late_main_clks[] = { &dsi0phy_clk, &dsi1phy_clk, - &twd_clk, }; enum { MSTP001, @@ -511,7 +535,6 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main clocks */ CLKDEV_CON_ID("r_clk", &r_clk), - CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ /* DIV6 clocks */ CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), @@ -558,13 +581,10 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ diff --git a/trunk/arch/arm/mach-shmobile/clock.c b/trunk/arch/arm/mach-shmobile/clock.c index ad7df629d995..e816ca9bd213 100644 --- a/trunk/arch/arm/mach-shmobile/clock.c +++ b/trunk/arch/arm/mach-shmobile/clock.c @@ -23,19 +23,6 @@ #include #include #include -#include -#include - -unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) -{ - struct clk_ratio *p = clk->priv; - - return clk->parent->rate / p->div * p->mul; -}; - -struct sh_clk_ops shmobile_fixed_ratio_clk_ops = { - .recalc = shmobile_fixed_ratio_clk_recalc, -}; int __init shmobile_clk_init(void) { diff --git a/trunk/arch/arm/mach-shmobile/headsmp-scu.S b/trunk/arch/arm/mach-shmobile/headsmp-sh73a0.S similarity index 85% rename from trunk/arch/arm/mach-shmobile/headsmp-scu.S rename to trunk/arch/arm/mach-shmobile/headsmp-sh73a0.S index 7d113f898e7f..bec4c0d9b713 100644 --- a/trunk/arch/arm/mach-shmobile/headsmp-scu.S +++ b/trunk/arch/arm/mach-shmobile/headsmp-sh73a0.S @@ -1,5 +1,5 @@ /* - * Shared SCU setup for mach-shmobile + * SMP support for SoC sh73a0 * * Copyright (C) 2012 Bastian Hecht * @@ -35,12 +35,11 @@ * the physical address as the MMU is still turned off. */ .align 12 -ENTRY(shmobile_secondary_vector_scu) +ENTRY(sh73a0_secondary_vector) mrc p15, 0, r0, c0, c0, 5 @ read MIPDR and r0, r0, #3 @ mask out cpu ID lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits - ldr r1, 2f - ldr r1, [r1] @ SCU base address + mov r1, #0xf0000000 @ SCU base address ldr r2, [r1, #8] @ SCU Power Status Register mov r3, #3 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) @@ -48,10 +47,4 @@ ENTRY(shmobile_secondary_vector_scu) ldr pc, 1f 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET -2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET -ENDPROC(shmobile_secondary_vector_scu) - - .text - .globl shmobile_scu_base -shmobile_scu_base: - .space 4 +ENDPROC(sh73a0_secondary_vector) diff --git a/trunk/arch/arm/mach-shmobile/hotplug.c b/trunk/arch/arm/mach-shmobile/hotplug.c new file mode 100644 index 000000000000..a1524e3367b0 --- /dev/null +++ b/trunk/arch/arm/mach-shmobile/hotplug.c @@ -0,0 +1,68 @@ +/* + * SMP support for R-Mobile / SH-Mobile + * + * Copyright (C) 2010 Magnus Damm + * + * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static cpumask_t dead_cpus; + +void shmobile_cpu_die(unsigned int cpu) +{ + /* hardware shutdown code running on the CPU that is being offlined */ + flush_cache_all(); + dsb(); + + /* notify platform_cpu_kill() that hardware shutdown is finished */ + cpumask_set_cpu(cpu, &dead_cpus); + + /* wait for SoC code in platform_cpu_kill() to shut off CPU core + * power. CPU bring up starts from the reset vector. + */ + while (1) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + } +} + +int shmobile_cpu_disable(unsigned int cpu) +{ + cpumask_clear_cpu(cpu, &dead_cpus); + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} + +int shmobile_cpu_disable_any(unsigned int cpu) +{ + cpumask_clear_cpu(cpu, &dead_cpus); + return 0; +} + +int shmobile_cpu_is_dead(unsigned int cpu) +{ + return cpumask_test_cpu(cpu, &dead_cpus); +} diff --git a/trunk/arch/arm/mach-shmobile/include/mach/clock.h b/trunk/arch/arm/mach-shmobile/include/mach/clock.h deleted file mode 100644 index 76ac61292e48..000000000000 --- a/trunk/arch/arm/mach-shmobile/include/mach/clock.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef CLOCK_H -#define CLOCK_H - -unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); -extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; - -/* clock ratio */ -struct clk_ratio { - int mul; - int div; -}; - -#define SH_CLK_RATIO(name, m, d) \ -static struct clk_ratio name ##_ratio = { \ - .mul = m, \ - .div = d, \ -} - -#define SH_FIXED_RATIO_CLKg(name, p, r) \ -struct clk name = { \ - .parent = &p, \ - .ops = &shmobile_fixed_ratio_clk_ops,\ - .priv = &r ## _ratio, \ -} - -#define SH_FIXED_RATIO_CLK(name, p, r) \ -static SH_FIXED_RATIO_CLKg(name, p, r); - -#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ - SH_CLK_RATIO(name, m, d); \ - SH_FIXED_RATIO_CLK(name, p, name); - -#define SH_CLK_SET_RATIO(p, m, d) \ -{ \ - (p)->mul = m; \ - (p)->div = d; \ -} - -#endif diff --git a/trunk/arch/arm/mach-shmobile/include/mach/common.h b/trunk/arch/arm/mach-shmobile/include/mach/common.h index e002cfd9d2df..e48606d8a2be 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/common.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/common.h @@ -8,7 +8,6 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, struct twd_local_timer; extern void shmobile_setup_console(void); extern void shmobile_secondary_vector(void); -extern void shmobile_secondary_vector_scu(void); struct clk; extern int shmobile_clk_init(void); extern void shmobile_handle_irq_intc(struct pt_regs *); @@ -19,6 +18,58 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); +extern void sh7372_init_irq(void); +extern void sh7372_map_io(void); +extern void sh7372_earlytimer_init(void); +extern void sh7372_add_early_devices(void); +extern void sh7372_add_standard_devices(void); +extern void sh7372_add_early_devices_dt(void); +extern void sh7372_add_standard_devices_dt(void); +extern void sh7372_clock_init(void); +extern void sh7372_pinmux_init(void); +extern void sh7372_pm_init(void); +extern void sh7372_resume_core_standby_sysc(void); +extern int sh7372_do_idle_sysc(unsigned long sleep_mode); +extern struct clk sh7372_extal1_clk; +extern struct clk sh7372_extal2_clk; + +extern void sh73a0_init_irq(void); +extern void sh73a0_init_irq_dt(void); +extern void sh73a0_map_io(void); +extern void sh73a0_earlytimer_init(void); +extern void sh73a0_add_early_devices(void); +extern void sh73a0_add_early_devices_dt(void); +extern void sh73a0_add_standard_devices(void); +extern void sh73a0_add_standard_devices_dt(void); +extern void sh73a0_clock_init(void); +extern void sh73a0_pinmux_init(void); +extern void sh73a0_pm_init(void); +extern void sh73a0_secondary_vector(void); +extern struct clk sh73a0_extal1_clk; +extern struct clk sh73a0_extal2_clk; +extern struct clk sh73a0_extcki_clk; +extern struct clk sh73a0_extalr_clk; + +extern void r8a7740_init_irq(void); +extern void r8a7740_map_io(void); +extern void r8a7740_add_early_devices(void); +extern void r8a7740_add_standard_devices(void); +extern void r8a7740_clock_init(u8 md_ck); +extern void r8a7740_pinmux_init(void); +extern void r8a7740_pm_init(void); + +extern void r8a7779_init_irq(void); +extern void r8a7779_map_io(void); +extern void r8a7779_earlytimer_init(void); +extern void r8a7779_add_early_devices(void); +extern void r8a7779_add_standard_devices(void); +extern void r8a7779_clock_init(void); +extern void r8a7779_pinmux_init(void); +extern void r8a7779_pm_init(void); +extern void r8a7740_meram_workaround(void); + +extern void r8a7779_register_twd(void); + #ifdef CONFIG_SUSPEND int shmobile_suspend_init(void); #else @@ -31,7 +82,16 @@ int shmobile_cpuidle_init(void); static inline int shmobile_cpuidle_init(void) { return 0; } #endif -extern void __iomem *shmobile_scu_base; +extern void shmobile_cpu_die(unsigned int cpu); +extern int shmobile_cpu_disable(unsigned int cpu); +extern int shmobile_cpu_disable_any(unsigned int cpu); + +#ifdef CONFIG_HOTPLUG_CPU +extern int shmobile_cpu_is_dead(unsigned int cpu); +#else +static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } +#endif + extern void shmobile_smp_init_cpus(unsigned int ncores); static inline void __init shmobile_init_late(void) diff --git a/trunk/arch/arm/mach-shmobile/include/mach/irqs.h b/trunk/arch/arm/mach-shmobile/include/mach/irqs.h index b2074e2acb15..06a5da3c3050 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/irqs.h @@ -5,15 +5,10 @@ /* GIC */ #define gic_spi(nr) ((nr) + 32) -#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ /* INTCS */ #define INTCS_VECT_BASE 0x3400 #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) -/* External IRQ pins */ -#define IRQPIN_BASE 2000 -#define irq_pin(nr) ((nr) + IRQPIN_BASE) - #endif /* __ASM_MACH_IRQS_H */ diff --git a/trunk/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/trunk/arch/arm/mach-shmobile/include/mach/r8a73a4.h deleted file mode 100644 index f043103e32c9..000000000000 --- a/trunk/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_R8A73A4_H__ -#define __ASM_R8A73A4_H__ - -void r8a73a4_add_standard_devices(void); -void r8a73a4_clock_init(void); -void r8a73a4_pinmux_init(void); - -#endif /* __ASM_R8A73A4_H__ */ diff --git a/trunk/arch/arm/mach-shmobile/include/mach/r8a7740.h b/trunk/arch/arm/mach-shmobile/include/mach/r8a7740.h index abdc4d4efa28..59d252f4cf97 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/r8a7740.h @@ -241,9 +241,48 @@ enum { /* LCD0 */ GPIO_FN_LCDC0_SELECT, + GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, + GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, + GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, + GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, + GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, + GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, + GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, + + GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ + GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ + + GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ + GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ + + GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, + GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, + GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, + GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ + + GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, + GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, + GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, + GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ /* LCD1 */ GPIO_FN_LCDC1_SELECT, + GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, + GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, + GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, + GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, + GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, + GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, + GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, + GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, + GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, + GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, + + GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ + GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ + + GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ + GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ /* RSPI */ GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, @@ -307,6 +346,26 @@ enum { GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ GPIO_FN_SIM_D_PORT199, + /* SDHI0 */ + GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, + GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, + GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, + + /* SDHI1 */ + GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, + GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, + GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, + + /* SDHI2 */ + GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, + GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, + + GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ + GPIO_FN_SDHI2_WP_PORT25, + + GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ + GPIO_FN_SDHI2_CD_PORT202, + /* MSIOF2 */ GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, @@ -358,6 +417,21 @@ enum { GPIO_FN_MEMC_DREQ1, GPIO_FN_MEMC_A0, + /* MMC */ + GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, + GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, + GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, + GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, + GPIO_FN_MMC0_CLK_PORT66, + GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ + + GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, + GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, + GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, + GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, + GPIO_FN_MMC1_CLK_PORT103, + GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ + /* MSIOF0 */ GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, @@ -532,15 +606,6 @@ enum { SHDMA_SLAVE_USBHS_RX, }; -extern void r8a7740_meram_workaround(void); -extern void r8a7740_init_irq(void); -extern void r8a7740_map_io(void); -extern void r8a7740_add_early_devices(void); -extern void r8a7740_add_standard_devices(void); -extern void r8a7740_clock_init(u8 md_ck); -extern void r8a7740_pinmux_init(void); -extern void r8a7740_pm_init(void); - #ifdef CONFIG_PM extern void __init r8a7740_init_pm_domains(void); #else diff --git a/trunk/arch/arm/mach-shmobile/include/mach/r8a7778.h b/trunk/arch/arm/mach-shmobile/include/mach/r8a7778.h deleted file mode 100644 index 951149e6bcca..000000000000 --- a/trunk/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef __ASM_R8A7778_H__ -#define __ASM_R8A7778_H__ - -#include - -extern void r8a7778_add_standard_devices(void); -extern void r8a7778_add_standard_devices_dt(void); -extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); -extern void r8a7778_init_delay(void); -extern void r8a7778_init_irq(void); -extern void r8a7778_init_irq_dt(void); -extern void r8a7778_clock_init(void); -extern void r8a7778_init_irq_extpin(int irlm); - -#endif /* __ASM_R8A7778_H__ */ diff --git a/trunk/arch/arm/mach-shmobile/include/mach/r8a7779.h b/trunk/arch/arm/mach-shmobile/include/mach/r8a7779.h index 188b295938a5..8ab0cd6ad6b0 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -3,7 +3,327 @@ #include #include -#include + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, + + GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18, + GPIO_FN_A19, + + /* IPSR0 */ + GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, + GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2, + GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, + GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3, + GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D, + GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B, + GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0, + GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1, + GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4, + GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25, + GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2, + GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B, + GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0, + GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2, + GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0, + GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C, + + /* IPSR1 */ + GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6, + GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7, + GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE, + GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD, + GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B, + GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B, + GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0, + GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B, + GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9, + GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1, + GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E, + GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2, + GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4, + GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0, + GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK, + GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18, + GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34, + + /* IPSR2 */ + GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C, + GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11, + GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35, + GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5, + GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO, + GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16, + GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1, + GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C, + GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0, + GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS, + GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17, + GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0, + GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0, + GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0, + GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C, + GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3, + GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5, + GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7, + GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2, + GPIO_FN_AUDATA2, + + /* IPSR3 */ + GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2, + GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3, + GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5, + GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7, + GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1, + GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1, + GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B, + GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18, + GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20, + GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22, + GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN, + GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B, + GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1, + GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B, + GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B, + GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS, + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, + GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON, + + /* IPSR4 */ + GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C, + GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C, + GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0, + GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK, + GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B, + GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0, + GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC, + GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3, + GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5, + GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7, + GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2, + GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6, + GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3, + GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7, + GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3, + GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5, + GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7, + GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4, + GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D, + + /* IPSR5 */ + GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B, + GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D, + GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5, + GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7, + GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D, + GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1, + GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD, + GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC, + GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC, + GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD, + GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB, + GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN, + GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6, + GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1, + GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D, + GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B, + GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD, + GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C, + GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK, + GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0, + GPIO_FN_MOUT0, + + /* IPSR6 */ + GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1, + GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2, + GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5, + GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6, + GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34, + GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX, + GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7, + GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C, + GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8, + GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B, + GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C, + GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10, + GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP, + GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5, + GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX, + GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B, + + /* IPSR7 */ + GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B, + GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B, + GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B, + GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B, + GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15, + GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C, + GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C, + GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD, + GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0, + GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1, + GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2, + GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3, + GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD, + GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2, + GPIO_FN_CTS1_B, + + /* IPSR8 */ + GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK, + GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20, + GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0, + GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI, + GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21, + GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0, + GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO, + GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22, + GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0, + GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7, + GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31, + GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE, + GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA, + GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C, + GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C, + GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B, + GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B, + GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B, + GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C, + + /* IPSR9 */ + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO, + GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM, + GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3, + GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2, + GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6, + GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0, + GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2, + GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1, + GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1, + GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0, + GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7, + GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4, + GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6, + GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B, + GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0, + GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7, + GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9, + + /* IPSR10 */ + GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B, + GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1, + GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11, + GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK, + GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12, + GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3, + GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK, + GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14, + GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0, + GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15, + GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC, + GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK, + GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO, + GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D, + GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D, + GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4, + GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC, + GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK, + GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3, + + /* IPSR11 */ + GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST, + GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1, + GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS, + GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2, + GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B, + GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN, + GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4, + GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST, + GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5, + GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK, + GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6, + GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D, + GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM, + GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0, + GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2, + GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1, + GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2, + GPIO_FN_HRTS0_B, + + /* IPSR12 */ + GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1, + GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3, + GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B, + GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C, + GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5, + GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B, + GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB, + GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7, + GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B, +}; struct platform_device; @@ -23,20 +343,6 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; } -extern void r8a7779_init_delay(void); -extern void r8a7779_init_irq(void); -extern void r8a7779_init_irq_extpin(int irlm); -extern void r8a7779_init_irq_dt(void); -extern void r8a7779_map_io(void); -extern void r8a7779_earlytimer_init(void); -extern void r8a7779_add_early_devices(void); -extern void r8a7779_add_standard_devices(void); -extern void r8a7779_add_standard_devices_dt(void); -extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); -extern void r8a7779_clock_init(void); -extern void r8a7779_pinmux_init(void); -extern void r8a7779_pm_init(void); -extern void r8a7779_register_twd(void); extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); diff --git a/trunk/arch/arm/mach-shmobile/include/mach/r8a7790.h b/trunk/arch/arm/mach-shmobile/include/mach/r8a7790.h deleted file mode 100644 index 2e919e61fa0d..000000000000 --- a/trunk/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_R8A7790_H__ -#define __ASM_R8A7790_H__ - -void r8a7790_add_standard_devices(void); -void r8a7790_clock_init(void); -void r8a7790_pinmux_init(void); -void r8a7790_timer_init(void); - -#endif /* __ASM_R8A7790_H__ */ diff --git a/trunk/arch/arm/mach-shmobile/include/mach/sh7372.h b/trunk/arch/arm/mach-shmobile/include/mach/sh7372.h index fd7cba024c39..b582facc1cf6 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -294,6 +294,21 @@ enum { GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, + /* + * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89, + * 90, 91, 92, 99) + */ + GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5, + GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7, + GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0, + + /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */ + GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2, + GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5, + GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7, + GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1, + /* SPU2 (PORT 65) */ GPIO_FN_VINT_I, @@ -401,6 +416,20 @@ enum { /* HDMI (PORT 169, 170) */ GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, + /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */ + GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, + GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0, + GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3, + + /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */ + GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0, + GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3, + + /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */ + GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0, + GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3, + /* SDENC see MSEL4CR 19 */ GPIO_FN_SDENC_CPG, GPIO_FN_SDENC_DV_CLKI, @@ -449,18 +478,6 @@ extern struct clk sh7372_dv_clki_clk; extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; -extern void sh7372_init_irq(void); -extern void sh7372_map_io(void); -extern void sh7372_earlytimer_init(void); -extern void sh7372_add_early_devices(void); -extern void sh7372_add_standard_devices(void); -extern void sh7372_add_early_devices_dt(void); -extern void sh7372_add_standard_devices_dt(void); -extern void sh7372_clock_init(void); -extern void sh7372_pinmux_init(void); -extern void sh7372_pm_init(void); -extern void sh7372_resume_core_standby_sysc(void); -extern int sh7372_do_idle_sysc(unsigned long sleep_mode); extern void sh7372_intcs_suspend(void); extern void sh7372_intcs_resume(void); extern void sh7372_intca_suspend(void); diff --git a/trunk/arch/arm/mach-shmobile/include/mach/sh73a0.h b/trunk/arch/arm/mach-shmobile/include/mach/sh73a0.h index eb7a4320d487..606d31d02a4e 100644 --- a/trunk/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/trunk/arch/arm/mach-shmobile/include/mach/sh73a0.h @@ -94,7 +94,8 @@ enum { GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, /* Table 25-1 (Function 0-7) */ - GPIO_FN_GPI0 = 310, + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPI2, GPIO_FN_GPI3, @@ -102,11 +103,15 @@ enum { GPIO_FN_GPI5, GPIO_FN_GPI6, GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, - GPIO_FN_GPO5, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ GPIO_FN_PORT16_VIO_CKOR, - GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, GPIO_FN_GPO0, GPIO_FN_GPO1, GPIO_FN_GPO2, GPIO_FN_STATUS0, @@ -114,44 +119,83 @@ enum { GPIO_FN_GPO4, GPIO_FN_STATUS2, GPIO_FN_VINT, GPIO_FN_TCKON, - GPIO_FN_XDVFS1, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, - GPIO_FN_XDVFS2, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ GPIO_FN_PORT28_TPU1TO1, GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, - GPIO_FN_XWUP, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, GPIO_FN_VACK, GPIO_FN_XTAL1L, - GPIO_FN_PORT49_IROUT, - GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, - - GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, - GPIO_FN_BBIF2_TXD2, - GPIO_FN_TPU3TO3, - GPIO_FN_TPU3TO2, - GPIO_FN_TPU0TO0, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, GPIO_FN_A0, GPIO_FN_BS_, - GPIO_FN_A12, GPIO_FN_TPU4TO2, - GPIO_FN_A13, GPIO_FN_TPU0TO1, - GPIO_FN_A14, - GPIO_FN_A15, - GPIO_FN_A16, GPIO_FN_MSIOF0_SS1, - GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC, - GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_A19, GPIO_FN_MSIOF0_TXD, - GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC, - GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_A24, GPIO_FN_MSIOF0_RXD, - GPIO_FN_A25, GPIO_FN_MSIOF0_SS2, - GPIO_FN_A26, - GPIO_FN_FCE1_, - GPIO_FN_DACK0, - GPIO_FN_FCE0_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, GPIO_FN_FRB, GPIO_FN_CKO, GPIO_FN_NBRSTOUT_, @@ -160,118 +204,145 @@ enum { GPIO_FN_BBIF2_RXD, GPIO_FN_BBIF2_SYNC, GPIO_FN_BBIF2_SCK, - GPIO_FN_MFG3_IN2, - GPIO_FN_MFG3_IN1, - GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, - GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, - GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, GPIO_FN_HSI_TX_FLAG, - GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD, - - GPIO_FN_VIO_HD, - GPIO_FN_VIO2_HD, - GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, - GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1, - GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2, - GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, - GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, - GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_VIO_D6, - GPIO_FN_VIO_D7, - GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0, - GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1, - GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, - GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, - GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4, - GPIO_FN_VIO_D13, - GPIO_FN_VIO2_D5, - GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6, - GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, - GPIO_FN_VIO2_D7, - GPIO_FN_VIO_CLK, - GPIO_FN_VIO2_CLK, - GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, GPIO_FN_VIO_CKO, - GPIO_FN_A27, GPIO_FN_MFG0_IN1, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, GPIO_FN_MFG0_IN2, GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, - GPIO_FN_MSIOF2_MCK0, - GPIO_FN_MSIOF2_MCK1, - GPIO_FN_PORT156_MSIOF2_SS2, - GPIO_FN_PORT157_MSIOF2_RXD, - GPIO_FN_DINT_, GPIO_FN_TS_SCK3, - GPIO_FN_NMI, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ GPIO_FN_TPU3TO0, - GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_BBIF2_TSCK1, - GPIO_FN_BBIF2_TXD1, - GPIO_FN_MFG2_OUT2, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ GPIO_FN_TPU2TO1, - GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, - GPIO_FN_D16, - GPIO_FN_D17, - GPIO_FN_D18, - GPIO_FN_D19, - GPIO_FN_D20, - GPIO_FN_D21, - GPIO_FN_D22, - GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, - GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, - GPIO_FN_D25, - GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, - GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, - GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, - GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, - GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, - GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, - GPIO_FN_DACK2, - GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, - GPIO_FN_DACK3, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ - GPIO_FN_DREQ1, + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ - GPIO_FN_DACK1, GPIO_FN_OVCN, - GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, - - GPIO_FN_OVCN2, - GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2, - GPIO_FN_IDIN, - GPIO_FN_MFG1_IN1, - GPIO_FN_MSIOF1_TXD, - GPIO_FN_MSIOF1_TSYNC, - GPIO_FN_MSIOF1_TSCK, - GPIO_FN_MSIOF1_RXD, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2, + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ - GPIO_FN_MSIOF1_MCK0, - GPIO_FN_MSIOF1_MCK1, - GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, - GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, - GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ GPIO_FN_TPU4TO0, - GPIO_FN_MFG4_IN2, - GPIO_FN_PORT243_VIO_CKO2, - GPIO_FN_MFG2_IN1, - GPIO_FN_MSIOF2R_RXD, - GPIO_FN_MFG2_IN2, - GPIO_FN_MSIOF2R_TXD, - GPIO_FN_MFG1_OUT1, - GPIO_FN_TPU1TO0, - GPIO_FN_MFG3_OUT2, - GPIO_FN_TPU3TO1, - GPIO_FN_MFG2_OUT1, - GPIO_FN_TPU2TO0, - GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ - GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0, GPIO_FN_SDHID0_0, @@ -364,12 +435,54 @@ enum { GPIO_FN_IRQ9_MEM_INT, GPIO_FN_IRQ9_MCP_INT, GPIO_FN_A11, + GPIO_FN_KEYOUT8, GPIO_FN_TPU4TO3, GPIO_FN_RESETA_N_PU_ON, GPIO_FN_RESETA_N_PU_OFF, GPIO_FN_EDBGREQ_PD, GPIO_FN_EDBGREQ_PU, + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_MMCD0_0_PU, + GPIO_FN_MMCD0_1_PU, + GPIO_FN_MMCD0_2_PU, + GPIO_FN_MMCD0_3_PU, + GPIO_FN_MMCD0_4_PU, + GPIO_FN_MMCD0_5_PU, + GPIO_FN_MMCD0_6_PU, + GPIO_FN_MMCD0_7_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, + /* end of GPIO */ GPIO_NR, }; @@ -444,21 +557,6 @@ enum { #define SH73A0_PINT0_IRQ(irq) ((irq) + 700) #define SH73A0_PINT1_IRQ(irq) ((irq) + 732) -extern void sh73a0_init_delay(void); -extern void sh73a0_init_irq(void); -extern void sh73a0_init_irq_dt(void); -extern void sh73a0_map_io(void); -extern void sh73a0_earlytimer_init(void); -extern void sh73a0_add_early_devices(void); -extern void sh73a0_add_standard_devices(void); -extern void sh73a0_add_standard_devices_dt(void); -extern void sh73a0_clock_init(void); -extern void sh73a0_pinmux_init(void); -extern void sh73a0_pm_init(void); -extern struct clk sh73a0_extal1_clk; -extern struct clk sh73a0_extal2_clk; -extern struct clk sh73a0_extcki_clk; -extern struct clk sh73a0_extalr_clk; extern struct smp_operations sh73a0_smp_ops; #endif /* __ASM_SH73A0_H__ */ diff --git a/trunk/arch/arm/mach-shmobile/intc-r8a7740.c b/trunk/arch/arm/mach-shmobile/intc-r8a7740.c index b741c8409a5a..9a69a31918ba 100644 --- a/trunk/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/trunk/arch/arm/mach-shmobile/intc-r8a7740.c @@ -18,39 +18,620 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include +#include #include -#include +#include +#include +#include +#include +#include + +/* + * INTCA + */ +enum { + UNUSED_INTCA = 0, + + /* interrupt sources INTCA */ + DIRC, + ATAPI, + IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI, + AP_ARM_COMMTX, AP_ARM_COMMRX, + MFI, MFIS, + BBIF1, BBIF2, + USBHSDMAC, + USBF_OUL_SOF, USBF_IXL_INT, + SGX540, + CMT1_0, CMT1_1, CMT1_2, CMT1_3, + CMT2, + CMT3, + KEYSC, + SCIFA0, SCIFA1, SCIFA2, SCIFA3, + MSIOF2, MSIOF1, + SCIFA4, SCIFA5, SCIFB, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3, + SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3, + AP_ARM_L2CINT, + IRDA, + TPU0, + SCIFA6, SCIFA7, + GbEther, + ICBS0, + DDM, + SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3, + RWDT0, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, + HDMI, + USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, + SPU2_0, SPU2_1, + FSI, FMSI, + HDMI_SSS, HDMI_KEY, + IPMMU, + AP_ARM_CTIIRQ, AP_ARM_PMURQ, + MFIS2, + CPORTR2S, + CMT14, CMT15, + MMCIF_0, MMCIF_1, MMCIF_2, + SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, + STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4, + + /* interrupt groups INTCA */ + DMAC1_1, DMAC1_2, + DMAC2_1, DMAC2_2, + DMAC3_1, DMAC3_2, + AP_ARM1, AP_ARM2, + SDHI0, SDHI1, SDHI2, + SHWYSTAT, + USBF, USBH1, USBH2, + RSPI, SPU2, FLCTL, IIC1, +}; + +static struct intc_vect intca_vectors[] __initdata = { + INTC_VECT(DIRC, 0x0560), + INTC_VECT(ATAPI, 0x05E0), + INTC_VECT(IIC1_ALI, 0x0780), + INTC_VECT(IIC1_TACKI, 0x07A0), + INTC_VECT(IIC1_WAITI, 0x07C0), + INTC_VECT(IIC1_DTEI, 0x07E0), + INTC_VECT(AP_ARM_COMMTX, 0x0840), + INTC_VECT(AP_ARM_COMMRX, 0x0860), + INTC_VECT(MFI, 0x0900), + INTC_VECT(MFIS, 0x0920), + INTC_VECT(BBIF1, 0x0940), + INTC_VECT(BBIF2, 0x0960), + INTC_VECT(USBHSDMAC, 0x0A00), + INTC_VECT(USBF_OUL_SOF, 0x0A20), + INTC_VECT(USBF_IXL_INT, 0x0A40), + INTC_VECT(SGX540, 0x0A60), + INTC_VECT(CMT1_0, 0x0B00), + INTC_VECT(CMT1_1, 0x0B20), + INTC_VECT(CMT1_2, 0x0B40), + INTC_VECT(CMT1_3, 0x0B60), + INTC_VECT(CMT2, 0x0B80), + INTC_VECT(CMT3, 0x0BA0), + INTC_VECT(KEYSC, 0x0BE0), + INTC_VECT(SCIFA0, 0x0C00), + INTC_VECT(SCIFA1, 0x0C20), + INTC_VECT(SCIFA2, 0x0C40), + INTC_VECT(SCIFA3, 0x0C60), + INTC_VECT(MSIOF2, 0x0C80), + INTC_VECT(MSIOF1, 0x0D00), + INTC_VECT(SCIFA4, 0x0D20), + INTC_VECT(SCIFA5, 0x0D40), + INTC_VECT(SCIFB, 0x0D60), + INTC_VECT(FLCTL_FLSTEI, 0x0D80), + INTC_VECT(FLCTL_FLTENDI, 0x0DA0), + INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0), + INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0), + INTC_VECT(SDHI0_0, 0x0E00), + INTC_VECT(SDHI0_1, 0x0E20), + INTC_VECT(SDHI0_2, 0x0E40), + INTC_VECT(SDHI0_3, 0x0E60), + INTC_VECT(SDHI1_0, 0x0E80), + INTC_VECT(SDHI1_1, 0x0EA0), + INTC_VECT(SDHI1_2, 0x0EC0), + INTC_VECT(SDHI1_3, 0x0EE0), + INTC_VECT(AP_ARM_L2CINT, 0x0FA0), + INTC_VECT(IRDA, 0x0480), + INTC_VECT(TPU0, 0x04A0), + INTC_VECT(SCIFA6, 0x04C0), + INTC_VECT(SCIFA7, 0x04E0), + INTC_VECT(GbEther, 0x0500), + INTC_VECT(ICBS0, 0x0540), + INTC_VECT(DDM, 0x1140), + INTC_VECT(SDHI2_0, 0x1200), + INTC_VECT(SDHI2_1, 0x1220), + INTC_VECT(SDHI2_2, 0x1240), + INTC_VECT(SDHI2_3, 0x1260), + INTC_VECT(RWDT0, 0x1280), + INTC_VECT(DMAC1_1_DEI0, 0x2000), + INTC_VECT(DMAC1_1_DEI1, 0x2020), + INTC_VECT(DMAC1_1_DEI2, 0x2040), + INTC_VECT(DMAC1_1_DEI3, 0x2060), + INTC_VECT(DMAC1_2_DEI4, 0x2080), + INTC_VECT(DMAC1_2_DEI5, 0x20A0), + INTC_VECT(DMAC1_2_DADERR, 0x20C0), + INTC_VECT(DMAC2_1_DEI0, 0x2100), + INTC_VECT(DMAC2_1_DEI1, 0x2120), + INTC_VECT(DMAC2_1_DEI2, 0x2140), + INTC_VECT(DMAC2_1_DEI3, 0x2160), + INTC_VECT(DMAC2_2_DEI4, 0x2180), + INTC_VECT(DMAC2_2_DEI5, 0x21A0), + INTC_VECT(DMAC2_2_DADERR, 0x21C0), + INTC_VECT(DMAC3_1_DEI0, 0x2200), + INTC_VECT(DMAC3_1_DEI1, 0x2220), + INTC_VECT(DMAC3_1_DEI2, 0x2240), + INTC_VECT(DMAC3_1_DEI3, 0x2260), + INTC_VECT(DMAC3_2_DEI4, 0x2280), + INTC_VECT(DMAC3_2_DEI5, 0x22A0), + INTC_VECT(DMAC3_2_DADERR, 0x22C0), + INTC_VECT(SHWYSTAT_RT, 0x1300), + INTC_VECT(SHWYSTAT_HS, 0x1320), + INTC_VECT(SHWYSTAT_COM, 0x1340), + INTC_VECT(USBH_INT, 0x1540), + INTC_VECT(USBH_OHCI, 0x1560), + INTC_VECT(USBH_EHCI, 0x1580), + INTC_VECT(USBH_PME, 0x15A0), + INTC_VECT(USBH_BIND, 0x15C0), + INTC_VECT(HDMI, 0x1700), + INTC_VECT(RSPI_OVRF, 0x1780), + INTC_VECT(RSPI_SPTEF, 0x17A0), + INTC_VECT(RSPI_SPRF, 0x17C0), + INTC_VECT(SPU2_0, 0x1800), + INTC_VECT(SPU2_1, 0x1820), + INTC_VECT(FSI, 0x1840), + INTC_VECT(FMSI, 0x1860), + INTC_VECT(HDMI_SSS, 0x18A0), + INTC_VECT(HDMI_KEY, 0x18C0), + INTC_VECT(IPMMU, 0x1920), + INTC_VECT(AP_ARM_CTIIRQ, 0x1980), + INTC_VECT(AP_ARM_PMURQ, 0x19A0), + INTC_VECT(MFIS2, 0x1A00), + INTC_VECT(CPORTR2S, 0x1A20), + INTC_VECT(CMT14, 0x1A40), + INTC_VECT(CMT15, 0x1A60), + INTC_VECT(MMCIF_0, 0x1AA0), + INTC_VECT(MMCIF_1, 0x1AC0), + INTC_VECT(MMCIF_2, 0x1AE0), + INTC_VECT(SIM_ERI, 0x1C00), + INTC_VECT(SIM_RXI, 0x1C20), + INTC_VECT(SIM_TXI, 0x1C40), + INTC_VECT(SIM_TEI, 0x1C60), + INTC_VECT(STPRO_0, 0x1C80), + INTC_VECT(STPRO_1, 0x1CA0), + INTC_VECT(STPRO_2, 0x1CC0), + INTC_VECT(STPRO_3, 0x1CE0), + INTC_VECT(STPRO_4, 0x1D00), +}; + +static struct intc_group intca_groups[] __initdata = { + INTC_GROUP(DMAC1_1, + DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3), + INTC_GROUP(DMAC1_2, + DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR), + INTC_GROUP(DMAC2_1, + DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3), + INTC_GROUP(DMAC2_2, + DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR), + INTC_GROUP(DMAC3_1, + DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3), + INTC_GROUP(DMAC3_2, + DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR), + INTC_GROUP(AP_ARM1, + AP_ARM_COMMTX, AP_ARM_COMMRX), + INTC_GROUP(AP_ARM2, + AP_ARM_CTIIRQ, AP_ARM_PMURQ), + INTC_GROUP(USBF, + USBF_OUL_SOF, USBF_IXL_INT), + INTC_GROUP(SDHI0, + SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3), + INTC_GROUP(SDHI1, + SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3), + INTC_GROUP(SDHI2, + SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3), + INTC_GROUP(SHWYSTAT, + SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM), + INTC_GROUP(USBH1, /* FIXME */ + USBH_INT, USBH_OHCI), + INTC_GROUP(USBH2, /* FIXME */ + USBH_EHCI, + USBH_PME, USBH_BIND), + INTC_GROUP(RSPI, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF), + INTC_GROUP(SPU2, + SPU2_0, SPU2_1), + INTC_GROUP(FLCTL, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), + INTC_GROUP(IIC1, + IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI), +}; + +static struct intc_mask_reg intca_mask_registers[] __initdata = { + { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8, + { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, + 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, + { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8, + { ATAPI, 0, DIRC, 0, + DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } }, + { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8, + { 0, 0, 0, 0, + BBIF1, BBIF2, MFIS, MFI } }, + { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8, + { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0, + DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } }, + { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8, + { DDM, 0, 0, 0, + 0, 0, 0, 0 } }, + { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8, + { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4, + SCIFA3, SCIFA2, SCIFA1, SCIFA0 } }, + { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8, + { SCIFB, SCIFA5, SCIFA4, MSIOF1, + 0, 0, MSIOF2, 0 } }, + { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8, + { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0, + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, + { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8, + { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0, + 0, USBHSDMAC, 0, AP_ARM_L2CINT } }, + { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8, + { CMT1_3, CMT1_2, CMT1_1, CMT1_0, + CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } }, + { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8, + { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4, + 0, 0, 0, 0 } }, + { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8, + { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI, + ICBS0, 0, 0, 0 } }, + { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8, + { 0, 0, TPU0, SCIFA6, + SCIFA7, GbEther, 0, 0 } }, + { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8, + { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0, + 0, CMT3, 0, RWDT0 } }, + { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8, + { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0, + 0, 0, 0, 0 } }, + /* IMR1A3 / IMCR1A3 */ + { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8, + { 0, 0, USBH_INT, USBH_OHCI, + USBH_EHCI, USBH_PME, USBH_BIND, 0 } }, + /* IMR3A3 / IMCR3A3 */ + { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8, + { HDMI, 0, 0, 0, + RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } }, + { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8, + { SPU2_0, SPU2_1, FSI, FMSI, + 0, HDMI_SSS, HDMI_KEY, 0 } }, + { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8, + { 0, IPMMU, 0, 0, + AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } }, + { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8, + { MFIS2, CPORTR2S, CMT14, CMT15, + 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, + /* IMR8A3 / IMCR8A3 */ + { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8, + { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, + STPRO_0, STPRO_1, STPRO_2, STPRO_3 } }, + { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8, + { STPRO_4, 0, 0, 0, + 0, 0, 0, 0 } }, +}; + +static struct intc_prio_reg intca_prio_registers[] __initdata = { + { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } }, + { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, + { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } }, + { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } }, + { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } }, + { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2, + SGX540, CMT1_0 } }, + { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1, + SCIFA2, SCIFA3 } }, + { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC, + FLCTL, SDHI0 } }, + { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } }, + { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, + AP_ARM_L2CINT, 0 } }, + { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } }, + { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6, + SCIFA7, GbEther } }, + { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } }, + { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } }, + { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, + { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } }, + /* IPRBA3 */ + /* IPRCA3 */ + /* IPRDA3 */ + { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } }, + { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } }, + /* IPRGA3 */ + /* IPRHA3 */ + { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } }, + { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } }, + { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } }, + { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } }, + { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } }, + { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } }, + { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S, + CMT14, CMT15 } }, + { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } }, + /* IPRQA3 */ + /* IPRRA3 */ + { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI, + SIM_TXI, SIM_TEI } }, + { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1, + STPRO_2, STPRO_3 } }, + { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } }, +}; + +static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca", + intca_vectors, intca_groups, + intca_mask_registers, intca_prio_registers, + NULL); + +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTC_VECT, "r8a7740-intca-irq-pins"); + + +/* + * INTCS + */ +enum { + UNUSED_INTCS = 0, + + INTCS, + + /* interrupt sources INTCS */ + + /* HUDI */ + /* STPRO */ + /* RTDMAC(1) */ + VPU5HA2, + _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT, + /* MFI */ + /* BBIF2 */ + VPU5F, + _2DG_BRK_INT, + /* SGX540 */ + /* 2DDMAC */ + /* IPMMU */ + /* RTDMAC 2 */ + /* KEYSC */ + /* MSIOF */ + IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI, + TMU0_0, TMU0_1, TMU0_2, + CMT0, + /* CMT2 */ + LMB, + CTI, + VOU, + /* RWDT0 */ + ICB, + VIO6C, + CEU20, CEU21, + JPU, + LCDC0, + LCRC, + /* RTDMAC2(1) */ + /* RTDMAC2(2) */ + LCDC1, + /* SPU2 */ + /* FSI */ + /* FMSI */ + TMU1_0, TMU1_1, TMU1_2, + CMT4, + DISP, + DSRV, + /* MFIS2 */ + CPORTS2R, + + /* interrupt groups INTCS */ + _2DG1, + IIC0, TMU1, +}; + +static struct intc_vect intcs_vectors[] = { + /* HUDI */ + /* STPRO */ + /* RTDMAC(1) */ + INTCS_VECT(VPU5HA2, 0x0880), + INTCS_VECT(_2DG_TRAP, 0x08A0), + INTCS_VECT(_2DG_GPM_INT, 0x08C0), + INTCS_VECT(_2DG_CER_INT, 0x08E0), + /* MFI */ + /* BBIF2 */ + INTCS_VECT(VPU5F, 0x0980), + INTCS_VECT(_2DG_BRK_INT, 0x09A0), + /* SGX540 */ + /* 2DDMAC */ + /* IPMMU */ + /* RTDMAC(2) */ + /* KEYSC */ + /* MSIOF */ + INTCS_VECT(IIC0_ALI, 0x0E00), + INTCS_VECT(IIC0_TACKI, 0x0E20), + INTCS_VECT(IIC0_WAITI, 0x0E40), + INTCS_VECT(IIC0_DTEI, 0x0E60), + INTCS_VECT(TMU0_0, 0x0E80), + INTCS_VECT(TMU0_1, 0x0EA0), + INTCS_VECT(TMU0_2, 0x0EC0), + INTCS_VECT(CMT0, 0x0F00), + /* CMT2 */ + INTCS_VECT(LMB, 0x0F60), + INTCS_VECT(CTI, 0x0400), + INTCS_VECT(VOU, 0x0420), + /* RWDT0 */ + INTCS_VECT(ICB, 0x0480), + INTCS_VECT(VIO6C, 0x04E0), + INTCS_VECT(CEU20, 0x0500), + INTCS_VECT(CEU21, 0x0520), + INTCS_VECT(JPU, 0x0560), + INTCS_VECT(LCDC0, 0x0580), + INTCS_VECT(LCRC, 0x05A0), + /* RTDMAC2(1) */ + /* RTDMAC2(2) */ + INTCS_VECT(LCDC1, 0x1780), + /* SPU2 */ + /* FSI */ + /* FMSI */ + INTCS_VECT(TMU1_0, 0x1900), + INTCS_VECT(TMU1_1, 0x1920), + INTCS_VECT(TMU1_2, 0x1940), + INTCS_VECT(CMT4, 0x1980), + INTCS_VECT(DISP, 0x19A0), + INTCS_VECT(DSRV, 0x19C0), + /* MFIS2 */ + INTCS_VECT(CPORTS2R, 0x1A20), + + INTC_VECT(INTCS, 0xf80), +}; + +static struct intc_group intcs_groups[] __initdata = { + INTC_GROUP(_2DG1, /*FIXME*/ + _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP), + INTC_GROUP(IIC0, + IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI), + INTC_GROUP(TMU1, + TMU1_0, TMU1_1, TMU1_2), +}; + +static struct intc_mask_reg intcs_mask_registers[] = { + /* IMR0SA / IMCR0SA */ /* all 0 */ + { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8, + { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2, + 0, 0, 0, 0 /*STPRO*/ } }, + { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8, + { 0/*STPRO*/, 0, CEU21, VPU5F, + 0/*BBIF2*/, 0, 0, 0/*MFI*/ } }, + { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8, + { 0, 0, 0, 0, /*2DDMAC*/ + VIO6C, 0, 0, ICB } }, + { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8, + { 0, 0, VOU, CTI, + JPU, 0, LCRC, LCDC0 } }, + /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/ + /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/ + { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8, + { 0, TMU0_2, TMU0_1, TMU0_0, + 0, 0, 0, 0 } }, + { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8, + { 0, 0, 0, 0, + CEU20, 0, 0, 0 } }, + { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8, + { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0, + 0, 0, 0, 0 } }, + /* IMR10SA / IMCR10SA */ /*IPMMU*/ + { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8, + { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI, + 0, _2DG_BRK_INT, LMB, 0 } }, + /* IMR12SA / IMCR12SA */ + /* IMR13SA / IMCR13SA */ + /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/ + /* IMR1SA3 / IMCR1SA3 */ + /* IMR2SA3 / IMCR2SA3 */ + /* IMR3SA3 / IMCR3SA3 */ + { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8, + { 0, 0, 0, 0, + LCDC1, 0, 0, 0 } }, + /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */ + { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8, + { TMU1_0, TMU1_1, TMU1_2, 0, + CMT4, DISP, DSRV, 0 } }, + { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8, + { 0/*MFIS2*/, CPORTS2R, 0, 0, + 0, 0, 0, 0 } }, + { /* INTAMASK */ 0xffd20104, 0, 16, + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, INTCS } }, +}; + +/* Priority is needed for INTCA to receive the INTCS interrupt */ +static struct intc_prio_reg intcs_prio_registers[] = { + { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } }, + { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } }, + /* IPRCS */ /*BBIF2*/ + /* IPRDS */ + { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2, + 0/*MFI*/, VPU5F } }, + { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/, + 0/*CMT2*/, CMT0 } }, + { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1, + TMU0_2, _2DG1 } }, + { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/, + _2DG_BRK_INT/*FIXME*/ } }, + { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } }, + { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } }, + { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } }, + { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } }, + /* IPRMS */ /*RWDT0*/ + /* IPRAS3 */ /*RTDMAC2(1)*/ + /* IPRBS3 */ /*RTDMAC2(2)*/ + /* IPRCS3 */ + /* IPRDS3 */ + /* IPRES3 */ + /* IPRFS3 */ + /* IPRGS3 */ + /* IPRHS3 */ + /* IPRIS3 */ + { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } }, + /* IPRKS3 */ /*SPU2/FSI/FMSi*/ + /* IPRLS3 */ + { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } }, + { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } }, + { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } }, + /* IPRPS3 */ +}; + +static struct resource intcs_resources[] __initdata = { + [0] = { + .start = 0xffd20000, + .end = 0xffd201ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0xffd50000, + .end = 0xffd501ff, + .flags = IORESOURCE_MEM, + } +}; + +static struct intc_desc intcs_desc __initdata = { + .name = "r8a7740-intcs", + .resource = intcs_resources, + .num_resources = ARRAY_SIZE(intcs_resources), + .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, + intcs_prio_registers, NULL, NULL), +}; + +static void intcs_demux(unsigned int irq, struct irq_desc *desc) +{ + void __iomem *reg = (void *)irq_get_handler_data(irq); + unsigned int evtcodeas = ioread32(reg); + + generic_handle_irq(intcs_evt2irq(evtcodeas)); +} void __init r8a7740_init_irq(void) { - void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); - void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); - void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); - void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); - void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); - - /* initialize the Generic Interrupt Controller PL390 r0p0 */ - gic_init(0, 29, gic_dist_base, gic_cpu_base); - - /* route signals to GIC */ - iowrite32(0x0, pfc_inta_ctrl); - - /* - * To mask the shared interrupt to SPI 149 we must ensure to set - * PRIO *and* MASK. Else we run into IRQ floods when registering - * the intc_irqpin devices - */ - iowrite32(0x0, intc_prio_base + 0x0); - iowrite32(0x0, intc_prio_base + 0x4); - iowrite32(0x0, intc_prio_base + 0x8); - iowrite32(0x0, intc_prio_base + 0xc); - iowrite8(0xff, intc_msk_base + 0x0); - iowrite8(0xff, intc_msk_base + 0x4); - iowrite8(0xff, intc_msk_base + 0x8); - iowrite8(0xff, intc_msk_base + 0xc); - - iounmap(intc_prio_base); - iounmap(intc_msk_base); - iounmap(pfc_inta_ctrl); + void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + + register_intc_controller(&intca_desc); + register_intc_controller(&intca_irq_pins_desc); + register_intc_controller(&intcs_desc); + + /* demux using INTEVTSA */ + irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); + irq_set_chained_handler(evt2irq(0xf80), intcs_demux); } diff --git a/trunk/arch/arm/mach-shmobile/intc-r8a7779.c b/trunk/arch/arm/mach-shmobile/intc-r8a7779.c index b86dc8908724..8807c27f71f9 100644 --- a/trunk/arch/arm/mach-shmobile/intc-r8a7779.c +++ b/trunk/arch/arm/mach-shmobile/intc-r8a7779.c @@ -19,16 +19,12 @@ */ #include #include -#include #include #include #include #include -#include -#include #include #include -#include #include #include #include @@ -42,61 +38,18 @@ #define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) -static struct renesas_intc_irqpin_config irqpin0_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ - .sense_bitfield_width = 2, -}; - -static struct resource irqpin0_resources[] = { - DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ - DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ - DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ - DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ - DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ -}; - -static struct platform_device irqpin0_device = { - .name = "renesas_intc_irqpin", - .id = 0, - .resource = irqpin0_resources, - .num_resources = ARRAY_SIZE(irqpin0_resources), - .dev = { - .platform_data = &irqpin0_platform_data, - }, -}; - -void __init r8a7779_init_irq_extpin(int irlm) -{ - void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); - unsigned long tmp; - - if (icr0) { - tmp = ioread32(icr0); - if (irlm) - tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ - else - tmp &= ~(1 << 23); /* IRL mode - not supported */ - tmp |= (1 << 21); /* LVLMODE = 1 */ - iowrite32(tmp, icr0); - iounmap(icr0); - - if (irlm) - platform_device_register(&irqpin0_device); - } else - pr_warn("r8a7779: unable to setup external irq pin mode\n"); -} - static int r8a7779_set_wake(struct irq_data *data, unsigned int on) { return 0; /* always allow wakeup */ } -static void __init r8a7779_init_irq_common(void) +void __init r8a7779_init_irq(void) { + void __iomem *gic_dist_base = IOMEM(0xf0001000); + void __iomem *gic_cpu_base = IOMEM(0xf0000100); + + /* use GIC to handle interrupts */ + gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = r8a7779_set_wake; /* route all interrupts to ARM */ @@ -110,22 +63,3 @@ static void __init r8a7779_init_irq_common(void) __raw_writel(0xbffffffc, INT2SMSKCR3); __raw_writel(0x003fee3f, INT2SMSKCR4); } - -void __init r8a7779_init_irq(void) -{ - void __iomem *gic_dist_base = IOMEM(0xf0001000); - void __iomem *gic_cpu_base = IOMEM(0xf0000100); - - /* use GIC to handle interrupts */ - gic_init(0, 29, gic_dist_base, gic_cpu_base); - - r8a7779_init_irq_common(); -} - -#ifdef CONFIG_OF -void __init r8a7779_init_irq_dt(void) -{ - irqchip_init(); - r8a7779_init_irq_common(); -} -#endif diff --git a/trunk/arch/arm/mach-shmobile/intc-sh73a0.c b/trunk/arch/arm/mach-shmobile/intc-sh73a0.c index 19a26f4579b3..91faba666d46 100644 --- a/trunk/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/trunk/arch/arm/mach-shmobile/intc-sh73a0.c @@ -260,6 +260,108 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } +#define RELOC_BASE 0x1200 + +/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */ +#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) + +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); + +static int to_gic_irq(struct irq_data *data) +{ + unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; + + if (vect >= 0x3200) + vect -= 0x3000; + else + vect -= 0x0200; + + return gic_spi((vect >> 5) + 1); +} + +static int to_intca_reloc_irq(struct irq_data *data) +{ + return data->irq + (RELOC_BASE >> 5); +} + +#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) +#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) + +static void intca_gic_enable(struct irq_data *data) +{ + irq_cb(irq_unmask, to_intca_reloc_irq(data)); + irq_cb(irq_unmask, to_gic_irq(data)); +} + +static void intca_gic_disable(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask, to_intca_reloc_irq(data)); +} + +static void intca_gic_mask_ack(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); +} + +static void intca_gic_eoi(struct irq_data *data) +{ + irq_cb(irq_eoi, to_gic_irq(data)); +} + +static int intca_gic_set_type(struct irq_data *data, unsigned int type) +{ + return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); +} + +#ifdef CONFIG_SMP +static int intca_gic_set_affinity(struct irq_data *data, + const struct cpumask *cpumask, + bool force) +{ + return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); +} +#endif + +struct irq_chip intca_gic_irq_chip = { + .name = "INTCA-GIC", + .irq_mask = intca_gic_disable, + .irq_unmask = intca_gic_enable, + .irq_mask_ack = intca_gic_mask_ack, + .irq_eoi = intca_gic_eoi, + .irq_enable = intca_gic_enable, + .irq_disable = intca_gic_disable, + .irq_shutdown = intca_gic_disable, + .irq_set_type = intca_gic_set_type, + .irq_set_wake = sh73a0_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = intca_gic_set_affinity, +#endif +}; + +static int to_intc_vect(int irq) +{ + unsigned int irq_pin = irq - gic_spi(1); + unsigned int offs; + + if (irq_pin < 16) + offs = 0x0200; + else + offs = 0x3000; + + return offs + (irq_pin << 5); +} + +static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) +{ + generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); + return IRQ_HANDLED; +} + +static struct irqaction sh73a0_irq_pin_cascade[32]; + #define PINTER0_PHYS 0xe69000a0 #define PINTER1_PHYS 0xe69000a4 #define PINTER0_VIRT IOMEM(0xe69000a0) @@ -320,11 +422,13 @@ void __init sh73a0_init_irq(void) void __iomem *gic_dist_base = IOMEM(0xf0001000); void __iomem *gic_cpu_base = IOMEM(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + int k, n; gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); + register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intc_pint0_desc); register_intc_controller(&intc_pint1_desc); @@ -334,6 +438,19 @@ void __init sh73a0_init_irq(void) sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); + /* IRQ pins require special handling through INTCA and GIC */ + for (k = 0; k < 32; k++) { + sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; + sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; + setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); + + n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); + WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n); + irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, + handle_level_irq, "level"); + set_irq_flags(n, IRQF_VALID); /* yuck */ + } + /* PINT pins are sanely tied to the GIC as SPI */ sh73a0_pint0_cascade.name = "PINT0 cascade"; sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; @@ -343,3 +460,11 @@ void __init sh73a0_init_irq(void) sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; setup_irq(gic_spi(34), &sh73a0_pint1_cascade); } + +#ifdef CONFIG_OF +void __init sh73a0_init_irq_dt(void) +{ + irqchip_init(); + gic_arch_extn.irq_set_wake = sh73a0_set_wake; +} +#endif diff --git a/trunk/arch/arm/mach-shmobile/setup-emev2.c b/trunk/arch/arm/mach-shmobile/setup-emev2.c index e4545c152722..47662a581c0a 100644 --- a/trunk/arch/arm/mach-shmobile/setup-emev2.c +++ b/trunk/arch/arm/mach-shmobile/setup-emev2.c @@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void) ARRAY_SIZE(emev2_late_devices)); } -static void __init emev2_init_delay(void) +void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } @@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = { { } }; -static void __init emev2_add_standard_devices_dt(void) +void __init emev2_add_standard_devices_dt(void) { of_platform_populate(NULL, of_default_bus_match_table, emev2_auxdata_lookup, NULL); diff --git a/trunk/arch/arm/mach-shmobile/setup-r8a73a4.c b/trunk/arch/arm/mach-shmobile/setup-r8a73a4.c deleted file mode 100644 index c5a75a7a508f..000000000000 --- a/trunk/arch/arm/mach-shmobile/setup-r8a73a4.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * r8a73a4 processor support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const struct resource pfc_resources[] = { - DEFINE_RES_MEM(0xe6050000, 0x9000), -}; - -void __init r8a73a4_pinmux_init(void) -{ - platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); -} - -#define SCIF_COMMON(scif_type, baseaddr, irq) \ - .type = scif_type, \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ -} - -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; - -static const struct plat_sci_port scif[] = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ -}; - -static inline void r8a73a4_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} - -static const struct renesas_irqc_config irqc0_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ -}; - -static const struct resource irqc0_resources[] = { - DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ - DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ - DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ - DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ -}; - -static const struct renesas_irqc_config irqc1_data = { - .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ -}; - -static const struct resource irqc1_resources[] = { - DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ - DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ - DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ - DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ - DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ - DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ - DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ - DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ - DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ - DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ - DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ - DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ - DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ - DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ - DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ - DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ - DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ - DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ - DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ - DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ - DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ - DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ - DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ - DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ - DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ - DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ - DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ -}; - -#define r8a73a4_register_irqc(idx) \ - platform_device_register_resndata(&platform_bus, "renesas_irqc", \ - idx, irqc##idx##_resources, \ - ARRAY_SIZE(irqc##idx##_resources), \ - &irqc##idx##_data, \ - sizeof(struct renesas_irqc_config)) - -/* Thermal0 -> Thermal2 */ -static const struct resource thermal0_resources[] = { - DEFINE_RES_MEM(0xe61f0000, 0x14), - DEFINE_RES_MEM(0xe61f0100, 0x38), - DEFINE_RES_MEM(0xe61f0200, 0x38), - DEFINE_RES_MEM(0xe61f0300, 0x38), - DEFINE_RES_IRQ(gic_spi(69)), -}; - -#define r8a73a4_register_thermal() \ - platform_device_register_simple("rcar_thermal", -1, \ - thermal0_resources, \ - ARRAY_SIZE(thermal0_resources)) - -void __init r8a73a4_add_standard_devices(void) -{ - r8a73a4_register_scif(SCIFA0); - r8a73a4_register_scif(SCIFA1); - r8a73a4_register_scif(SCIFB0); - r8a73a4_register_scif(SCIFB1); - r8a73a4_register_scif(SCIFB2); - r8a73a4_register_scif(SCIFB3); - r8a73a4_register_irqc(0); - r8a73a4_register_irqc(1); - r8a73a4_register_thermal(); -} - -#ifdef CONFIG_USE_OF -void __init r8a73a4_add_standard_devices_dt(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char *r8a73a4_boards_compat_dt[] __initdata = { - "renesas,r8a73a4", - NULL, -}; - -DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") - .init_irq = irqchip_init, - .init_machine = r8a73a4_add_standard_devices_dt, - .init_time = shmobile_timer_init, - .dt_compat = r8a73a4_boards_compat_dt, -MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/trunk/arch/arm/mach-shmobile/setup-r8a7740.c b/trunk/arch/arm/mach-shmobile/setup-r8a7740.c index 228d7aba4a7c..8b85d4d8fab6 100644 --- a/trunk/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/trunk/arch/arm/mach-shmobile/setup-r8a7740.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -95,126 +94,6 @@ void __init r8a7740_pinmux_init(void) platform_device_register(&r8a7740_pfc_device); } -static struct renesas_intc_irqpin_config irqpin0_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ -}; - -static struct resource irqpin0_resources[] = { - DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ - DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ - DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ - DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ - DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ -}; - -static struct platform_device irqpin0_device = { - .name = "renesas_intc_irqpin", - .id = 0, - .resource = irqpin0_resources, - .num_resources = ARRAY_SIZE(irqpin0_resources), - .dev = { - .platform_data = &irqpin0_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin1_platform_data = { - .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ -}; - -static struct resource irqpin1_resources[] = { - DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ - DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ - DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ - DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ - DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */ -}; - -static struct platform_device irqpin1_device = { - .name = "renesas_intc_irqpin", - .id = 1, - .resource = irqpin1_resources, - .num_resources = ARRAY_SIZE(irqpin1_resources), - .dev = { - .platform_data = &irqpin1_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin2_platform_data = { - .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ -}; - -static struct resource irqpin2_resources[] = { - DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */ -}; - -static struct platform_device irqpin2_device = { - .name = "renesas_intc_irqpin", - .id = 2, - .resource = irqpin2_resources, - .num_resources = ARRAY_SIZE(irqpin2_resources), - .dev = { - .platform_data = &irqpin2_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin3_platform_data = { - .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ -}; - -static struct resource irqpin3_resources[] = { - DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */ -}; - -static struct platform_device irqpin3_device = { - .name = "renesas_intc_irqpin", - .id = 3, - .resource = irqpin3_resources, - .num_resources = ARRAY_SIZE(irqpin3_resources), - .dev = { - .platform_data = &irqpin3_platform_data, - }, -}; - /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, @@ -222,7 +101,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(100)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), }; static struct platform_device scif0_device = { @@ -240,7 +119,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(101)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), }; static struct platform_device scif1_device = { @@ -258,7 +137,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(102)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), }; static struct platform_device scif2_device = { @@ -276,7 +155,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(103)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), }; static struct platform_device scif3_device = { @@ -294,7 +173,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(104)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), }; static struct platform_device scif4_device = { @@ -312,7 +191,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(105)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), }; static struct platform_device scif5_device = { @@ -330,7 +209,7 @@ static struct plat_sci_port scif6_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(106)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), }; static struct platform_device scif6_device = { @@ -348,7 +227,7 @@ static struct plat_sci_port scif7_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFA, - .irqs = SCIx_IRQ_MUXED(gic_spi(107)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), }; static struct platform_device scif7_device = { @@ -366,7 +245,7 @@ static struct plat_sci_port scifb_platform_data = { .scscr = SCSCR_RE | SCSCR_TE, .scbrr_algo_id = SCBRR_ALGO_4, .type = PORT_SCIFB, - .irqs = SCIx_IRQ_MUXED(gic_spi(108)), + .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), }; static struct platform_device scifb_device = { @@ -394,7 +273,7 @@ static struct resource cmt10_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(58), + .start = evt2irq(0x0b00), .flags = IORESOURCE_IRQ, }, }; @@ -425,7 +304,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(198), + .start = intcs_evt2irq(0xe80), .flags = IORESOURCE_IRQ, }, }; @@ -455,7 +334,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(199), + .start = intcs_evt2irq(0xea0), .flags = IORESOURCE_IRQ, }, }; @@ -485,7 +364,7 @@ static struct resource tmu02_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(200), + .start = intcs_evt2irq(0xec0), .flags = IORESOURCE_IRQ, }, }; @@ -532,10 +411,6 @@ static struct platform_device ipmmu_device = { }; static struct platform_device *r8a7740_early_devices[] __initdata = { - &irqpin0_device, - &irqpin1_device, - &irqpin2_device, - &irqpin3_device, &scif0_device, &scif1_device, &scif2_device, @@ -650,14 +525,14 @@ static struct resource r8a7740_dmae0_resources[] = { }, { .name = "error_irq", - .start = gic_spi(34), - .end = gic_spi(34), + .start = evt2irq(0x20c0), + .end = evt2irq(0x20c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = gic_spi(28), - .end = gic_spi(33), + .start = evt2irq(0x2000), + .end = evt2irq(0x20a0), .flags = IORESOURCE_IRQ, }, }; @@ -678,14 +553,14 @@ static struct resource r8a7740_dmae1_resources[] = { }, { .name = "error_irq", - .start = gic_spi(41), - .end = gic_spi(41), + .start = evt2irq(0x21c0), + .end = evt2irq(0x21c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = gic_spi(35), - .end = gic_spi(40), + .start = evt2irq(0x2100), + .end = evt2irq(0x21a0), .flags = IORESOURCE_IRQ, }, }; @@ -706,14 +581,14 @@ static struct resource r8a7740_dmae2_resources[] = { }, { .name = "error_irq", - .start = gic_spi(48), - .end = gic_spi(48), + .start = evt2irq(0x22c0), + .end = evt2irq(0x22c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = gic_spi(42), - .end = gic_spi(47), + .start = evt2irq(0x2200), + .end = evt2irq(0x22a0), .flags = IORESOURCE_IRQ, }, }; @@ -802,8 +677,8 @@ static struct resource r8a7740_usb_dma_resources[] = { }, { /* IRQ for channels */ - .start = gic_spi(49), - .end = gic_spi(49), + .start = evt2irq(0x0a00), + .end = evt2irq(0x0a00), .flags = IORESOURCE_IRQ, }, }; @@ -827,8 +702,8 @@ static struct resource i2c0_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(201), - .end = gic_spi(204), + .start = intcs_evt2irq(0xe00), + .end = intcs_evt2irq(0xe60), .flags = IORESOURCE_IRQ, }, }; @@ -841,8 +716,8 @@ static struct resource i2c1_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_spi(70), /* IIC1_ALI1 */ - .end = gic_spi(73), /* IIC1_DTEI1 */ + .start = evt2irq(0x780), /* IIC1_ALI1 */ + .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ .flags = IORESOURCE_IRQ, }, }; @@ -863,8 +738,8 @@ static struct platform_device i2c1_device = { static struct resource pmu_resources[] = { [0] = { - .start = gic_spi(83), - .end = gic_spi(83), + .start = evt2irq(0x19a0), + .end = evt2irq(0x19a0), .flags = IORESOURCE_IRQ, }, }; @@ -1029,6 +904,7 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") .map_io = r8a7740_map_io, .init_early = r8a7740_add_early_devices_dt, .init_irq = r8a7740_init_irq, + .handle_irq = shmobile_handle_irq_intc, .init_machine = r8a7740_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a7740_boards_compat_dt, diff --git a/trunk/arch/arm/mach-shmobile/setup-r8a7778.c b/trunk/arch/arm/mach-shmobile/setup-r8a7778.c deleted file mode 100644 index 30b4a336308f..000000000000 --- a/trunk/arch/arm/mach-shmobile/setup-r8a7778.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * r8a7778 processor support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Kuninori Morimoto - * Copyright (C) 2013 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* SCIF */ -#define SCIF_INFO(baseaddr, irq) \ -{ \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .type = PORT_SCIF, \ - .irqs = SCIx_IRQ_MUXED(irq), \ -} - -static struct plat_sci_port scif_platform_data[] = { - SCIF_INFO(0xffe40000, gic_iid(0x66)), - SCIF_INFO(0xffe41000, gic_iid(0x67)), - SCIF_INFO(0xffe42000, gic_iid(0x68)), - SCIF_INFO(0xffe43000, gic_iid(0x69)), - SCIF_INFO(0xffe44000, gic_iid(0x6a)), - SCIF_INFO(0xffe45000, gic_iid(0x6b)), -}; - -/* TMU */ -static struct resource sh_tmu0_resources[] = { - DEFINE_RES_MEM(0xffd80008, 12), - DEFINE_RES_IRQ(gic_iid(0x40)), -}; - -static struct sh_timer_config sh_tmu0_platform_data = { - .name = "TMU00", - .channel_offset = 0x4, - .timer_bit = 0, - .clockevent_rating = 200, -}; - -static struct resource sh_tmu1_resources[] = { - DEFINE_RES_MEM(0xffd80014, 12), - DEFINE_RES_IRQ(gic_iid(0x41)), -}; - -static struct sh_timer_config sh_tmu1_platform_data = { - .name = "TMU01", - .channel_offset = 0x10, - .timer_bit = 1, - .clocksource_rating = 200, -}; - -/* Ether */ -static struct resource ether_resources[] = { - DEFINE_RES_MEM(0xfde00000, 0x400), - DEFINE_RES_IRQ(gic_iid(0x89)), -}; - -#define r8a7778_register_tmu(idx) \ - platform_device_register_resndata( \ - &platform_bus, "sh_tmu", idx, \ - sh_tmu##idx##_resources, \ - ARRAY_SIZE(sh_tmu##idx##_resources), \ - &sh_tmu##idx##_platform_data, \ - sizeof(sh_tmu##idx##_platform_data)) - -void __init r8a7778_add_standard_devices(void) -{ - int i; - -#ifdef CONFIG_CACHE_L2X0 - void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); - if (base) { - /* - * Early BRESP enable, Shared attribute override enable, 64K*16way - * don't call iounmap(base) - */ - l2x0_init(base, 0x40470000, 0x82000fff); - } -#endif - - for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) - platform_device_register_data(&platform_bus, "sh-sci", i, - &scif_platform_data[i], - sizeof(struct plat_sci_port)); - - r8a7778_register_tmu(0); - r8a7778_register_tmu(1); -} - -void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) -{ - platform_device_register_resndata(&platform_bus, "sh_eth", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); -} - -static struct renesas_intc_irqpin_config irqpin_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ - .sense_bitfield_width = 2, -}; - -static struct resource irqpin_resources[] = { - DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ - DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ - DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ - DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ - DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ - DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ -}; - -void __init r8a7778_init_irq_extpin(int irlm) -{ - void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); - unsigned long tmp; - - if (!icr0) { - pr_warn("r8a7778: unable to setup external irq pin mode\n"); - return; - } - - tmp = ioread32(icr0); - if (irlm) - tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ - else - tmp &= ~(1 << 23); /* IRL mode - not supported */ - tmp |= (1 << 21); /* LVLMODE = 1 */ - iowrite32(tmp, icr0); - iounmap(icr0); - - if (irlm) - platform_device_register_resndata( - &platform_bus, "renesas_intc_irqpin", -1, - irqpin_resources, ARRAY_SIZE(irqpin_resources), - &irqpin_platform_data, sizeof(irqpin_platform_data)); -} - -#define INT2SMSKCR0 0x82288 /* 0xfe782288 */ -#define INT2SMSKCR1 0x8228c /* 0xfe78228c */ - -#define INT2NTSR0 0x00018 /* 0xfe700018 */ -#define INT2NTSR1 0x0002c /* 0xfe70002c */ -static void __init r8a7778_init_irq_common(void) -{ - void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); - - BUG_ON(!base); - - /* route all interrupts to ARM */ - __raw_writel(0x73ffffff, base + INT2NTSR0); - __raw_writel(0xffffffff, base + INT2NTSR1); - - /* unmask all known interrupts in INTCS2 */ - __raw_writel(0x08330773, base + INT2SMSKCR0); - __raw_writel(0x00311110, base + INT2SMSKCR1); - - iounmap(base); -} - -void __init r8a7778_init_irq(void) -{ - void __iomem *gic_dist_base; - void __iomem *gic_cpu_base; - - gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE); - gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE); - BUG_ON(!gic_dist_base || !gic_cpu_base); - - /* use GIC to handle interrupts */ - gic_init(0, 29, gic_dist_base, gic_cpu_base); - - r8a7778_init_irq_common(); -} - -void __init r8a7778_init_delay(void) -{ - shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ -} - -#ifdef CONFIG_USE_OF -void __init r8a7778_init_irq_dt(void) -{ - irqchip_init(); - r8a7778_init_irq_common(); -} - -static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = { - {}, -}; - -void __init r8a7778_add_standard_devices_dt(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, - r8a7778_auxdata_lookup, NULL); -} - -static const char *r8a7778_compat_dt[] __initdata = { - "renesas,r8a7778", - NULL, -}; - -DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") - .init_early = r8a7778_init_delay, - .init_irq = r8a7778_init_irq_dt, - .init_machine = r8a7778_add_standard_devices_dt, - .init_time = shmobile_timer_init, - .dt_compat = r8a7778_compat_dt, -MACHINE_END - -#endif /* CONFIG_USE_OF */ diff --git a/trunk/arch/arm/mach-shmobile/setup-r8a7779.c b/trunk/arch/arm/mach-shmobile/setup-r8a7779.c index b0b394842ea5..c54ff9b29fe5 100644 --- a/trunk/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/trunk/arch/arm/mach-shmobile/setup-r8a7779.c @@ -1,9 +1,8 @@ /* * r8a7779 processor support * - * Copyright (C) 2011, 2013 Renesas Solutions Corp. + * Copyright (C) 2011 Renesas Solutions Corp. * Copyright (C) 2011 Magnus Damm - * Copyright (C) 2013 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,8 +21,6 @@ #include #include #include -#include -#include #include #include #include @@ -31,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -70,6 +66,11 @@ static struct resource r8a7779_pfc_resources[] = { .end = 0xfffc023b, .flags = IORESOURCE_MEM, }, + [1] = { + .start = 0xffc40000, + .end = 0xffc46fff, + .flags = IORESOURCE_MEM, + } }; static struct platform_device r8a7779_pfc_device = { @@ -79,59 +80,9 @@ static struct platform_device r8a7779_pfc_device = { .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), }; -#define R8A7779_GPIO(idx, npins) \ -static struct resource r8a7779_gpio##idx##_resources[] = { \ - [0] = { \ - .start = 0xffc40000 + 0x1000 * (idx), \ - .end = 0xffc4002b + 0x1000 * (idx), \ - .flags = IORESOURCE_MEM, \ - }, \ - [1] = { \ - .start = gic_iid(0xad + (idx)), \ - .flags = IORESOURCE_IRQ, \ - } \ -}; \ - \ -static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ - .gpio_base = 32 * (idx), \ - .irq_base = 0, \ - .number_of_pins = npins, \ - .pctl_name = "pfc-r8a7779", \ -}; \ - \ -static struct platform_device r8a7779_gpio##idx##_device = { \ - .name = "gpio_rcar", \ - .id = idx, \ - .resource = r8a7779_gpio##idx##_resources, \ - .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ - .dev = { \ - .platform_data = &r8a7779_gpio##idx##_platform_data, \ - }, \ -} - -R8A7779_GPIO(0, 32); -R8A7779_GPIO(1, 32); -R8A7779_GPIO(2, 32); -R8A7779_GPIO(3, 32); -R8A7779_GPIO(4, 32); -R8A7779_GPIO(5, 32); -R8A7779_GPIO(6, 9); - -static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { - &r8a7779_pfc_device, - &r8a7779_gpio0_device, - &r8a7779_gpio1_device, - &r8a7779_gpio2_device, - &r8a7779_gpio3_device, - &r8a7779_gpio4_device, - &r8a7779_gpio5_device, - &r8a7779_gpio6_device, -}; - void __init r8a7779_pinmux_init(void) { - platform_add_devices(r8a7779_pinctrl_devices, - ARRAY_SIZE(r8a7779_pinctrl_devices)); + platform_device_register(&r8a7779_pfc_device); } static struct plat_sci_port scif0_platform_data = { @@ -140,7 +91,7 @@ static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), + .irqs = SCIx_IRQ_MUXED(gic_spi(88)), }; static struct platform_device scif0_device = { @@ -157,7 +108,7 @@ static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), + .irqs = SCIx_IRQ_MUXED(gic_spi(89)), }; static struct platform_device scif1_device = { @@ -174,7 +125,7 @@ static struct plat_sci_port scif2_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), + .irqs = SCIx_IRQ_MUXED(gic_spi(90)), }; static struct platform_device scif2_device = { @@ -191,7 +142,7 @@ static struct plat_sci_port scif3_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), + .irqs = SCIx_IRQ_MUXED(gic_spi(91)), }; static struct platform_device scif3_device = { @@ -208,7 +159,7 @@ static struct plat_sci_port scif4_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), + .irqs = SCIx_IRQ_MUXED(gic_spi(92)), }; static struct platform_device scif4_device = { @@ -225,7 +176,7 @@ static struct plat_sci_port scif5_platform_data = { .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, .scbrr_algo_id = SCBRR_ALGO_2, .type = PORT_SCIF, - .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), + .irqs = SCIx_IRQ_MUXED(gic_spi(93)), }; static struct platform_device scif5_device = { @@ -252,7 +203,7 @@ static struct resource tmu00_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_iid(0x40), + .start = gic_spi(32), .flags = IORESOURCE_IRQ, }, }; @@ -282,7 +233,7 @@ static struct resource tmu01_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gic_iid(0x41), + .start = gic_spi(33), .flags = IORESOURCE_IRQ, }, }; @@ -304,7 +255,7 @@ static struct resource rcar_i2c0_res[] = { .end = 0xffc70fff, .flags = IORESOURCE_MEM, }, { - .start = gic_iid(0x6f), + .start = gic_spi(79), .flags = IORESOURCE_IRQ, }, }; @@ -322,7 +273,7 @@ static struct resource rcar_i2c1_res[] = { .end = 0xffc71fff, .flags = IORESOURCE_MEM, }, { - .start = gic_iid(0x72), + .start = gic_spi(82), .flags = IORESOURCE_IRQ, }, }; @@ -340,7 +291,7 @@ static struct resource rcar_i2c2_res[] = { .end = 0xffc72fff, .flags = IORESOURCE_MEM, }, { - .start = gic_iid(0x70), + .start = gic_spi(80), .flags = IORESOURCE_IRQ, }, }; @@ -358,7 +309,7 @@ static struct resource rcar_i2c3_res[] = { .end = 0xffc73fff, .flags = IORESOURCE_MEM, }, { - .start = gic_iid(0x71), + .start = gic_spi(81), .flags = IORESOURCE_IRQ, }, }; @@ -370,43 +321,7 @@ static struct platform_device i2c3_device = { .num_resources = ARRAY_SIZE(rcar_i2c3_res), }; -static struct resource sata_resources[] = { - [0] = { - .name = "rcar-sata", - .start = 0xfc600000, - .end = 0xfc601fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = gic_iid(0x84), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device sata_device = { - .name = "sata_rcar", - .id = -1, - .resource = sata_resources, - .num_resources = ARRAY_SIZE(sata_resources), - .dev = { - .dma_mask = &sata_device.dev.coherent_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -/* Ether */ -static struct resource ether_resources[] = { - { - .start = 0xfde00000, - .end = 0xfde003ff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0xb4), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device *r8a7779_devices_dt[] __initdata = { +static struct platform_device *r8a7779_early_devices[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -415,14 +330,13 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif5_device, &tmu00_device, &tmu01_device, -}; - -static struct platform_device *r8a7779_late_devices[] __initdata = { &i2c0_device, &i2c1_device, &i2c2_device, &i2c3_device, - &sata_device, +}; + +static struct platform_device *r8a7779_late_devices[] __initdata = { }; void __init r8a7779_add_standard_devices(void) @@ -435,20 +349,12 @@ void __init r8a7779_add_standard_devices(void) r8a7779_init_pm_domains(); - platform_add_devices(r8a7779_devices_dt, - ARRAY_SIZE(r8a7779_devices_dt)); + platform_add_devices(r8a7779_early_devices, + ARRAY_SIZE(r8a7779_early_devices)); platform_add_devices(r8a7779_late_devices, ARRAY_SIZE(r8a7779_late_devices)); } -void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) -{ - platform_device_register_resndata(&platform_bus, "sh_eth", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); -} - /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } @@ -461,8 +367,8 @@ void __init r8a7779_earlytimer_init(void) void __init r8a7779_add_early_devices(void) { - early_platform_add_devices(r8a7779_devices_dt, - ARRAY_SIZE(r8a7779_devices_dt)); + early_platform_add_devices(r8a7779_early_devices, + ARRAY_SIZE(r8a7779_early_devices)); /* Early serial console setup is not included here due to * memory map collisions. The SCIF serial ports in r8a7779 @@ -480,40 +386,3 @@ void __init r8a7779_add_early_devices(void) * command line in case of the marzen board. */ } - -#ifdef CONFIG_USE_OF -void __init r8a7779_init_delay(void) -{ - shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ -} - -static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = { - {}, -}; - -void __init r8a7779_add_standard_devices_dt(void) -{ - /* clocks are setup late during boot in the case of DT */ - r8a7779_clock_init(); - - platform_add_devices(r8a7779_devices_dt, - ARRAY_SIZE(r8a7779_devices_dt)); - of_platform_populate(NULL, of_default_bus_match_table, - r8a7779_auxdata_lookup, NULL); -} - -static const char *r8a7779_compat_dt[] __initdata = { - "renesas,r8a7779", - NULL, -}; - -DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") - .map_io = r8a7779_map_io, - .init_early = r8a7779_init_delay, - .nr_irqs = NR_IRQS_LEGACY, - .init_irq = r8a7779_init_irq_dt, - .init_machine = r8a7779_add_standard_devices_dt, - .init_time = shmobile_timer_init, - .dt_compat = r8a7779_compat_dt, -MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/trunk/arch/arm/mach-shmobile/setup-r8a7790.c b/trunk/arch/arm/mach-shmobile/setup-r8a7790.c deleted file mode 100644 index 49de2d56f86d..000000000000 --- a/trunk/arch/arm/mach-shmobile/setup-r8a7790.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * r8a7790 processor support - * - * Copyright (C) 2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const struct resource pfc_resources[] = { - DEFINE_RES_MEM(0xe6060000, 0x250), - DEFINE_RES_MEM(0xe6050000, 0x5050), -}; - -void __init r8a7790_pinmux_init(void) -{ - platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); -} - -#define SCIF_COMMON(scif_type, baseaddr, irq) \ - .type = scif_type, \ - .mapbase = baseaddr, \ - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ - .irqs = SCIx_IRQ_MUXED(irq) - -#define SCIFA_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ -} - -#define SCIFB_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_4, \ - .scscr = SCSCR_RE | SCSCR_TE, \ -} - -#define SCIF_DATA(index, baseaddr, irq) \ -[index] = { \ - SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ - .scbrr_algo_id = SCBRR_ALGO_2, \ - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ -} - -enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 }; - -static const struct plat_sci_port scif[] = { - SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ - SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ - SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ - SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ - SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ - SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ - SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ - SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ -}; - -static inline void r8a7790_register_scif(int idx) -{ - platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], - sizeof(struct plat_sci_port)); -} - -static struct renesas_irqc_config irqc0_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ -}; - -static struct resource irqc0_resources[] = { - DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ - DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ -}; - -#define r8a7790_register_irqc(idx) \ - platform_device_register_resndata(&platform_bus, "renesas_irqc", \ - idx, irqc##idx##_resources, \ - ARRAY_SIZE(irqc##idx##_resources), \ - &irqc##idx##_data, \ - sizeof(struct renesas_irqc_config)) - -void __init r8a7790_add_standard_devices(void) -{ - r8a7790_register_scif(SCIFA0); - r8a7790_register_scif(SCIFA1); - r8a7790_register_scif(SCIFB0); - r8a7790_register_scif(SCIFB1); - r8a7790_register_scif(SCIFB2); - r8a7790_register_scif(SCIFA2); - r8a7790_register_scif(SCIF0); - r8a7790_register_scif(SCIF1); - r8a7790_register_irqc(0); -} - -void __init r8a7790_timer_init(void) -{ - void __iomem *cntcr; - - /* make sure arch timer is started by setting bit 0 of CNTCT */ - cntcr = ioremap(0xe6080000, PAGE_SIZE); - iowrite32(1, cntcr); - iounmap(cntcr); - - shmobile_timer_init(); -} - -#ifdef CONFIG_USE_OF -void __init r8a7790_add_standard_devices_dt(void) -{ - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char *r8a7790_boards_compat_dt[] __initdata = { - "renesas,r8a7790", - NULL, -}; - -DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") - .init_irq = irqchip_init, - .init_machine = r8a7790_add_standard_devices_dt, - .init_time = r8a7790_timer_init, - .dt_compat = r8a7790_boards_compat_dt, -MACHINE_END -#endif /* CONFIG_USE_OF */ diff --git a/trunk/arch/arm/mach-shmobile/setup-sh73a0.c b/trunk/arch/arm/mach-shmobile/setup-sh73a0.c index e8cd93a5c550..bdab575f88bc 100644 --- a/trunk/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/trunk/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -33,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -812,128 +810,7 @@ static struct platform_device ipmmu_device = { .num_resources = ARRAY_SIZE(ipmmu_resources), }; -static struct renesas_intc_irqpin_config irqpin0_platform_data = { - .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ -}; - -static struct resource irqpin0_resources[] = { - DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ - DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ - DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ - DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ - DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ - DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ - DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ - DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ - DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ - DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ - DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ - DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ - DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ -}; - -static struct platform_device irqpin0_device = { - .name = "renesas_intc_irqpin", - .id = 0, - .resource = irqpin0_resources, - .num_resources = ARRAY_SIZE(irqpin0_resources), - .dev = { - .platform_data = &irqpin0_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin1_platform_data = { - .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ - .control_parent = true, /* Disable spurious IRQ10 */ -}; - -static struct resource irqpin1_resources[] = { - DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ - DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ - DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ - DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ - DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ - DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ - DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ - DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ - DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ - DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ - DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ - DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ - DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ -}; - -static struct platform_device irqpin1_device = { - .name = "renesas_intc_irqpin", - .id = 1, - .resource = irqpin1_resources, - .num_resources = ARRAY_SIZE(irqpin1_resources), - .dev = { - .platform_data = &irqpin1_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin2_platform_data = { - .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ -}; - -static struct resource irqpin2_resources[] = { - DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ - DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ - DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ - DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ - DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ - DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ - DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ - DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ - DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ - DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ - DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ - DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ - DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ -}; - -static struct platform_device irqpin2_device = { - .name = "renesas_intc_irqpin", - .id = 2, - .resource = irqpin2_resources, - .num_resources = ARRAY_SIZE(irqpin2_resources), - .dev = { - .platform_data = &irqpin2_platform_data, - }, -}; - -static struct renesas_intc_irqpin_config irqpin3_platform_data = { - .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ -}; - -static struct resource irqpin3_resources[] = { - DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ - DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ - DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ - DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ - DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ - DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ - DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ - DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ - DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ - DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ - DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ - DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ - DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ -}; - -static struct platform_device irqpin3_device = { - .name = "renesas_intc_irqpin", - .id = 3, - .resource = irqpin3_resources, - .num_resources = ARRAY_SIZE(irqpin3_resources), - .dev = { - .platform_data = &irqpin3_platform_data, - }, -}; - -static struct platform_device *sh73a0_devices_dt[] __initdata = { +static struct platform_device *sh73a0_early_devices_dt[] __initdata = { &scif0_device, &scif1_device, &scif2_device, @@ -961,10 +838,6 @@ static struct platform_device *sh73a0_late_devices[] __initdata = { &dma0_device, &mpdma0_device, &pmu_device, - &irqpin0_device, - &irqpin1_device, - &irqpin2_device, - &irqpin3_device, }; #define SRCR2 IOMEM(0xe61580b0) @@ -974,8 +847,8 @@ void __init sh73a0_add_standard_devices(void) /* Clear software reset bit on SY-DMAC module */ __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); - platform_add_devices(sh73a0_devices_dt, - ARRAY_SIZE(sh73a0_devices_dt)); + platform_add_devices(sh73a0_early_devices_dt, + ARRAY_SIZE(sh73a0_early_devices_dt)); platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); platform_add_devices(sh73a0_late_devices, @@ -994,8 +867,8 @@ void __init sh73a0_earlytimer_init(void) void __init sh73a0_add_early_devices(void) { - early_platform_add_devices(sh73a0_devices_dt, - ARRAY_SIZE(sh73a0_devices_dt)); + early_platform_add_devices(sh73a0_early_devices_dt, + ARRAY_SIZE(sh73a0_early_devices_dt)); early_platform_add_devices(sh73a0_early_devices, ARRAY_SIZE(sh73a0_early_devices)); @@ -1005,9 +878,23 @@ void __init sh73a0_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init sh73a0_init_delay(void) +/* Please note that the clock initialisation shcheme used in + * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() + * does not work with SMP as there is a yet to be resolved lock-up in + * workqueue initialisation. + * + * CONFIG_SMP should be disabled when using this code. + */ + +void __init sh73a0_add_early_devices_dt(void) { shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ + + early_platform_add_devices(sh73a0_early_devices_dt, + ARRAY_SIZE(sh73a0_early_devices_dt)); + + /* setup early console here as well */ + shmobile_setup_console(); } static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { @@ -1019,8 +906,8 @@ void __init sh73a0_add_standard_devices_dt(void) /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); - platform_add_devices(sh73a0_devices_dt, - ARRAY_SIZE(sh73a0_devices_dt)); + platform_add_devices(sh73a0_early_devices_dt, + ARRAY_SIZE(sh73a0_early_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, sh73a0_auxdata_lookup, NULL); } @@ -1031,11 +918,10 @@ static const char *sh73a0_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") - .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, - .init_early = sh73a0_init_delay, + .init_early = sh73a0_add_early_devices_dt, .nr_irqs = NR_IRQS_LEGACY, - .init_irq = irqchip_init, + .init_irq = sh73a0_init_irq_dt, .init_machine = sh73a0_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = sh73a0_boards_compat_dt, diff --git a/trunk/arch/arm/mach-shmobile/smp-emev2.c b/trunk/arch/arm/mach-shmobile/smp-emev2.c index e38691b4d0dd..953eb1f9388d 100644 --- a/trunk/arch/arm/mach-shmobile/smp-emev2.c +++ b/trunk/arch/arm/mach-shmobile/smp-emev2.c @@ -23,39 +23,100 @@ #include #include #include +#include #include #include #include #include +#include #define EMEV2_SCU_BASE 0x1e000000 +static DEFINE_SPINLOCK(scu_lock); +static void __iomem *scu_base; + +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + unsigned long tmp; + + /* we assume this code is running on a different cpu + * than the one that is changing coherency setting */ + spin_lock(&scu_lock); + tmp = readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + writel(tmp, scu_base + 8); + spin_unlock(&scu_lock); + +} + +static unsigned int __init emev2_get_core_count(void) +{ + if (!scu_base) { + scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); + emev2_clock_init(); /* need ioremapped SMU */ + } + + WARN_ON_ONCE(!scu_base); + + return scu_base ? scu_get_core_count(scu_base) : 1; +} + +static int emev2_platform_cpu_kill(unsigned int cpu) +{ + return 0; /* not supported yet */ +} + +static int __maybe_unused emev2_cpu_kill(unsigned int cpu) +{ + int k; + + /* this function is running on another CPU than the offline target, + * here we need wait for shutdown code in platform_cpu_die() to + * finish before asking SoC-specific code to power off the CPU core. + */ + for (k = 0; k < 1000; k++) { + if (shmobile_cpu_is_dead(cpu)) + return emev2_platform_cpu_kill(cpu); + mdelay(1); + } + + return 0; +} + + +static void __cpuinit emev2_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { - arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); + cpu = cpu_logical_map(cpu); + + /* enable cache coherency */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); + + /* Tell ROM loader about our vector (in headsmp.S) */ + emev2_set_boot_vector(__pa(shmobile_secondary_vector)); + + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); return 0; } static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) { - scu_enable(shmobile_scu_base); + int cpu = cpu_logical_map(0); - /* Tell ROM loader about our vector (in headsmp-scu.S) */ - emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); + scu_enable(scu_base); - /* enable cache coherency on booting CPU */ - scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); + /* enable cache coherency on CPU0 */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); } static void __init emev2_smp_init_cpus(void) { - unsigned int ncores; - - /* setup EMEV2 specific SCU base */ - shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); - emev2_clock_init(); /* need ioremapped SMU */ - - ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1; + unsigned int ncores = emev2_get_core_count(); shmobile_smp_init_cpus(ncores); } @@ -63,5 +124,11 @@ static void __init emev2_smp_init_cpus(void) struct smp_operations emev2_smp_ops __initdata = { .smp_init_cpus = emev2_smp_init_cpus, .smp_prepare_cpus = emev2_smp_prepare_cpus, + .smp_secondary_init = emev2_secondary_init, .smp_boot_secondary = emev2_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = emev2_cpu_kill, + .cpu_die = shmobile_cpu_die, + .cpu_disable = shmobile_cpu_disable, +#endif }; diff --git a/trunk/arch/arm/mach-shmobile/smp-r8a7779.c b/trunk/arch/arm/mach-shmobile/smp-r8a7779.c index a853bf182ed5..3a4acf23edcf 100644 --- a/trunk/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/trunk/arch/arm/mach-shmobile/smp-r8a7779.c @@ -23,15 +23,14 @@ #include #include #include +#include #include #include -#include #include #include #include #define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE 0xf0000000 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ @@ -57,14 +56,44 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { [3] = &r8a7779_ch_cpu3, }; +static void __iomem *scu_base_addr(void) +{ + return (void __iomem *)0xf0000000; +} + +static DEFINE_SPINLOCK(scu_lock); +static unsigned long tmp; + #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29); +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); + void __init r8a7779_register_twd(void) { twd_local_timer_register(&twd_local_timer); } #endif +static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) +{ + void __iomem *scu_base = scu_base_addr(); + + spin_lock(&scu_lock); + tmp = __raw_readl(scu_base + 8); + tmp &= ~clr; + tmp |= set; + spin_unlock(&scu_lock); + + /* disable cache coherency after releasing the lock */ + __raw_writel(tmp, scu_base + 8); +} + +static unsigned int __init r8a7779_get_core_count(void) +{ + void __iomem *scu_base = scu_base_addr(); + + return scu_get_core_count(scu_base); +} + static int r8a7779_platform_cpu_kill(unsigned int cpu) { struct r8a7779_pm_ch *ch = NULL; @@ -72,6 +101,9 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) cpu = cpu_logical_map(cpu); + /* disable cache coherency */ + modify_scu_cpu_psr(3 << (cpu * 8), 0); + if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -81,6 +113,30 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) return ret ? ret : 1; } +static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) +{ + int k; + + /* this function is running on another CPU than the offline target, + * here we need wait for shutdown code in platform_cpu_die() to + * finish before asking SoC-specific code to power off the CPU core. + */ + for (k = 0; k < 1000; k++) { + if (shmobile_cpu_is_dead(cpu)) + return r8a7779_platform_cpu_kill(cpu); + + mdelay(1); + } + + return 0; +} + + +static void __cpuinit r8a7779_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { struct r8a7779_pm_ch *ch = NULL; @@ -88,6 +144,9 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct cpu = cpu_logical_map(cpu); + /* enable cache coherency */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); + if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) ch = r8a7779_ch_cpu[cpu]; @@ -99,13 +158,15 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { - scu_enable(shmobile_scu_base); + int cpu = cpu_logical_map(0); + + scu_enable(scu_base_addr()); - /* Map the reset vector (in headsmp-scu.S) */ - __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); + /* Map the reset vector (in headsmp.S) */ + __raw_writel(__pa(shmobile_secondary_vector), AVECR); - /* enable cache coherency on booting CPU */ - scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); + /* enable cache coherency on CPU0 */ + modify_scu_cpu_psr(0, 3 << (cpu * 8)); r8a7779_pm_init(); @@ -117,68 +178,19 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) static void __init r8a7779_smp_init_cpus(void) { - /* setup r8a7779 specific SCU base */ - shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); - - shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); -} - -#ifdef CONFIG_HOTPLUG_CPU -static int r8a7779_scu_psr_core_disabled(int cpu) -{ - unsigned long mask = 3 << (cpu * 8); - - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) - return 1; - - return 0; -} - -static int r8a7779_cpu_kill(unsigned int cpu) -{ - int k; + unsigned int ncores = r8a7779_get_core_count(); - /* this function is running on another CPU than the offline target, - * here we need wait for shutdown code in platform_cpu_die() to - * finish before asking SoC-specific code to power off the CPU core. - */ - for (k = 0; k < 1000; k++) { - if (r8a7779_scu_psr_core_disabled(cpu)) - return r8a7779_platform_cpu_kill(cpu); - - mdelay(1); - } - - return 0; -} - -static void r8a7779_cpu_die(unsigned int cpu) -{ - dsb(); - flush_cache_all(); - - /* disable cache coherency */ - scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); - - /* Endless loop until power off from r8a7779_cpu_kill() */ - while (1) - cpu_do_idle(); -} - -static int r8a7779_cpu_disable(unsigned int cpu) -{ - /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ - return cpu == 0 ? -EPERM : 0; + shmobile_smp_init_cpus(ncores); } -#endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations r8a7779_smp_ops __initdata = { .smp_init_cpus = r8a7779_smp_init_cpus, .smp_prepare_cpus = r8a7779_smp_prepare_cpus, + .smp_secondary_init = r8a7779_secondary_init, .smp_boot_secondary = r8a7779_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = r8a7779_cpu_kill, - .cpu_die = r8a7779_cpu_die, - .cpu_disable = r8a7779_cpu_disable, + .cpu_die = shmobile_cpu_die, + .cpu_disable = shmobile_cpu_disable, #endif }; diff --git a/trunk/arch/arm/mach-shmobile/smp-sh73a0.c b/trunk/arch/arm/mach-shmobile/smp-sh73a0.c index bf79626ee5a4..acb46a94ccdf 100644 --- a/trunk/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/trunk/arch/arm/mach-shmobile/smp-sh73a0.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -38,16 +39,31 @@ #define PSTR_SHUTDOWN_MODE 3 -#define SH73A0_SCU_BASE 0xf0000000 +static void __iomem *scu_base_addr(void) +{ + return (void __iomem *)0xf0000000; +} #ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); void __init sh73a0_register_twd(void) { twd_local_timer_register(&twd_local_timer); } #endif +static unsigned int __init sh73a0_get_core_count(void) +{ + void __iomem *scu_base = scu_base_addr(); + + return scu_get_core_count(scu_base); +} + +static void __cpuinit sh73a0_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { cpu = cpu_logical_map(cpu); @@ -62,22 +78,21 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { - scu_enable(shmobile_scu_base); + scu_enable(scu_base_addr()); - /* Map the reset vector (in headsmp-scu.S) */ + /* Map the reset vector (in headsmp-sh73a0.S) */ __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); + __raw_writel(__pa(sh73a0_secondary_vector), SBAR); /* enable cache coherency on booting CPU */ - scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); + scu_power_mode(scu_base_addr(), SCU_PM_NORMAL); } static void __init sh73a0_smp_init_cpus(void) { - /* setup sh73a0 specific SCU base */ - shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); + unsigned int ncores = sh73a0_get_core_count(); - shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base)); + shmobile_smp_init_cpus(ncores); } #ifdef CONFIG_HOTPLUG_CPU @@ -113,25 +128,21 @@ static void sh73a0_cpu_die(unsigned int cpu) flush_cache_all(); /* Set power off mode. This takes the CPU out of the MP cluster */ - scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF); + scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF); /* Enter shutdown mode */ cpu_do_idle(); } - -static int sh73a0_cpu_disable(unsigned int cpu) -{ - return 0; /* CPU0 and CPU1 supported */ -} #endif /* CONFIG_HOTPLUG_CPU */ struct smp_operations sh73a0_smp_ops __initdata = { .smp_init_cpus = sh73a0_smp_init_cpus, .smp_prepare_cpus = sh73a0_smp_prepare_cpus, + .smp_secondary_init = sh73a0_secondary_init, .smp_boot_secondary = sh73a0_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_kill = sh73a0_cpu_kill, .cpu_die = sh73a0_cpu_die, - .cpu_disable = sh73a0_cpu_disable, + .cpu_disable = shmobile_cpu_disable_any, #endif }; diff --git a/trunk/arch/arm/mach-socfpga/platsmp.c b/trunk/arch/arm/mach-socfpga/platsmp.c index ca14d1d5ac7f..84c60fa8daa0 100644 --- a/trunk/arch/arm/mach-socfpga/platsmp.c +++ b/trunk/arch/arm/mach-socfpga/platsmp.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,16 @@ extern void __iomem *sys_manager_base_addr; extern void __iomem *rst_manager_base_addr; +static void __cpuinit socfpga_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); +} + static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) { int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; @@ -98,6 +109,7 @@ static void socfpga_cpu_die(unsigned int cpu) struct smp_operations socfpga_smp_ops __initdata = { .smp_init_cpus = socfpga_smp_init_cpus, .smp_prepare_cpus = socfpga_smp_prepare_cpus, + .smp_secondary_init = socfpga_secondary_init, .smp_boot_secondary = socfpga_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = socfpga_cpu_die, diff --git a/trunk/arch/arm/mach-spear13xx/platsmp.c b/trunk/arch/arm/mach-spear13xx/platsmp.c index 551c69c9a228..af4ade61cd95 100644 --- a/trunk/arch/arm/mach-spear13xx/platsmp.c +++ b/trunk/arch/arm/mach-spear13xx/platsmp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,13 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE); static void __cpuinit spear13xx_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/arm/mach-spear13xx/spear13xx.c b/trunk/arch/arm/mach-spear13xx/spear13xx.c index 25a10191b021..c7d2b4a8d8cc 100644 --- a/trunk/arch/arm/mach-spear13xx/spear13xx.c +++ b/trunk/arch/arm/mach-spear13xx/spear13xx.c @@ -15,12 +15,12 @@ #include #include -#include #include #include #include #include #include +#include #include #include #include @@ -179,5 +179,5 @@ void __init spear13xx_timer_init(void) clk_put(pclk); spear_setup_of_timer(); - clocksource_of_init(); + twd_local_timer_of_register(); } diff --git a/trunk/arch/arm/mach-tegra/platsmp.c b/trunk/arch/arm/mach-tegra/platsmp.c index 9348d3c496a9..2c6b3d55213b 100644 --- a/trunk/arch/arm/mach-tegra/platsmp.c +++ b/trunk/arch/arm/mach-tegra/platsmp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -43,6 +44,13 @@ static cpumask_t tegra_cpu_init_mask; static void __cpuinit tegra_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + cpumask_set_cpu(cpu, &tegra_cpu_init_mask); } diff --git a/trunk/arch/arm/mach-ux500/board-mop500-sdi.c b/trunk/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c27102..7f2cb6c5e2c1 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/trunk/arch/arm/mach-ux500/board-mop500-sdi.c @@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { #endif struct mmci_platform_data mop500_sdi0_data = { - .ios_handler = mop500_sdi0_ios_handler, .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | diff --git a/trunk/arch/arm/mach-ux500/board-mop500.c b/trunk/arch/arm/mach-ux500/board-mop500.c index b03457881c4b..87d2d7b38ce9 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.c +++ b/trunk/arch/arm/mach-ux500/board-mop500.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev) regulator_put(prox_regulator); } +void mop500_snowball_ethernet_clock_enable(void) +{ + struct clk *clk; + + clk = clk_get_sys("fsmc", NULL); + if (!IS_ERR(clk)) + clk_prepare_enable(clk); +} + static struct cryp_platform_data u8500_cryp1_platform_data = { .mem_to_engine = { .dir = STEDMA40_MEM_TO_PERIPH, @@ -683,6 +693,8 @@ static void __init snowball_init_machine(void) mop500_audio_init(parent); mop500_uart_init(parent); + mop500_snowball_ethernet_clock_enable(); + /* This board has full regulator constraints */ regulator_has_full_constraints(); } diff --git a/trunk/arch/arm/mach-ux500/board-mop500.h b/trunk/arch/arm/mach-ux500/board-mop500.h index eaa605f5d90d..d38951be70df 100644 --- a/trunk/arch/arm/mach-ux500/board-mop500.h +++ b/trunk/arch/arm/mach-ux500/board-mop500.h @@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); void __init hrefv60_pinmaps_init(void); void mop500_audio_init(struct device *parent); +void mop500_snowball_ethernet_clock_enable(void); int __init mop500_uib_init(void); void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, diff --git a/trunk/arch/arm/mach-ux500/cpu-db8500.c b/trunk/arch/arm/mach-ux500/cpu-db8500.c index 19235cf7bbe3..f1a581844372 100644 --- a/trunk/arch/arm/mach-ux500/cpu-db8500.c +++ b/trunk/arch/arm/mach-ux500/cpu-db8500.c @@ -312,9 +312,10 @@ static void __init u8500_init_machine(void) /* Pinmaps must be in place before devices register */ if (of_machine_is_compatible("st-ericsson,mop500")) mop500_pinmaps_init(); - else if (of_machine_is_compatible("calaosystems,snowball-a9500")) + else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { snowball_pinmaps_init(); - else if (of_machine_is_compatible("st-ericsson,hrefv60+")) + mop500_snowball_ethernet_clock_enable(); + } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) hrefv60_pinmaps_init(); else if (of_machine_is_compatible("st-ericsson,ccu9540")) {} /* TODO: Add pinmaps for ccu9540 board. */ diff --git a/trunk/arch/arm/mach-ux500/platsmp.c b/trunk/arch/arm/mach-ux500/platsmp.c index 152b1309b9af..18f7af339dc9 100644 --- a/trunk/arch/arm/mach-ux500/platsmp.c +++ b/trunk/arch/arm/mach-ux500/platsmp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -56,6 +57,13 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit ux500_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/arm/mach-ux500/timer.c b/trunk/arch/arm/mach-ux500/timer.c index d07bbe7f04a6..a6af0b8732ba 100644 --- a/trunk/arch/arm/mach-ux500/timer.c +++ b/trunk/arch/arm/mach-ux500/timer.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -33,7 +32,7 @@ static void __init ux500_twd_init(void) twd_local_timer = &u8500_twd_local_timer; if (of_have_populated_dt()) - clocksource_of_init(); + twd_local_timer_of_register(); else { err = twd_local_timer_register(twd_local_timer); if (err) diff --git a/trunk/arch/arm/mach-vexpress/v2m.c b/trunk/arch/arm/mach-vexpress/v2m.c index d0ad78998cb6..915683cb67d6 100644 --- a/trunk/arch/arm/mach-vexpress/v2m.c +++ b/trunk/arch/arm/mach-vexpress/v2m.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -26,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -435,7 +435,6 @@ static void __init v2m_dt_timer_init(void) vexpress_clk_of_init(); - clocksource_of_init(); do { node = of_find_compatible_node(node, NULL, "arm,sp804"); } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); @@ -446,7 +445,8 @@ static void __init v2m_dt_timer_init(void) irq_of_parse_and_map(node, 0)); } - arch_timer_of_register(); + if (arch_timer_of_register() != 0) + twd_local_timer_of_register(); if (arch_timer_sched_clock_init() != 0) versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), diff --git a/trunk/arch/arm/mach-virt/platsmp.c b/trunk/arch/arm/mach-virt/platsmp.c index f4143f5bfa5b..8badaabe70a1 100644 --- a/trunk/arch/arm/mach-virt/platsmp.c +++ b/trunk/arch/arm/mach-virt/platsmp.c @@ -21,6 +21,8 @@ #include #include +#include + #include #include @@ -43,8 +45,14 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu, return -ENODEV; } +static void __cpuinit virt_secondary_init(unsigned int cpu) +{ + gic_secondary_init(0); +} + struct smp_operations __initdata virt_smp_ops = { .smp_init_cpus = virt_smp_init_cpus, .smp_prepare_cpus = virt_smp_prepare_cpus, + .smp_secondary_init = virt_secondary_init, .smp_boot_secondary = virt_boot_secondary, }; diff --git a/trunk/arch/arm/mach-zynq/Kconfig b/trunk/arch/arm/mach-zynq/Kconfig index f4a7e630bde0..adb6c0ea0e53 100644 --- a/trunk/arch/arm/mach-zynq/Kconfig +++ b/trunk/arch/arm/mach-zynq/Kconfig @@ -8,8 +8,6 @@ config ARCH_ZYNQ select ICST select MIGHT_HAVE_CACHE_L2X0 select USE_OF - select HAVE_SMP select SPARSE_IRQ - select CADENCE_TTC_TIMER help Support for Xilinx Zynq ARM Cortex A9 Platform diff --git a/trunk/arch/arm/mach-zynq/Makefile b/trunk/arch/arm/mach-zynq/Makefile index 1b25d92ebf22..397268c1b250 100644 --- a/trunk/arch/arm/mach-zynq/Makefile +++ b/trunk/arch/arm/mach-zynq/Makefile @@ -3,8 +3,4 @@ # # Common support -obj-y := common.o slcr.o -CFLAGS_REMOVE_hotplug.o =-march=armv6k -CFLAGS_hotplug.o =-Wa,-march=armv7-a -mcpu=cortex-a9 -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-y := common.o timer.o diff --git a/trunk/arch/arm/mach-zynq/common.c b/trunk/arch/arm/mach-zynq/common.c index 5bfe7035b73d..5c8983218183 100644 --- a/trunk/arch/arm/mach-zynq/common.c +++ b/trunk/arch/arm/mach-zynq/common.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -33,23 +32,20 @@ #include #include #include -#include #include #include "common.h" -void __iomem *zynq_scu_base; - static struct of_device_id zynq_of_bus_ids[] __initdata = { { .compatible = "simple-bus", }, {} }; /** - * zynq_init_machine - System specific initialization, intended to be - * called from board specific initialization. + * xilinx_init_machine() - System specific initialization, intended to be + * called from board specific initialization. */ -static void __init zynq_init_machine(void) +static void __init xilinx_init_machine(void) { /* * 64KB way size, 8-way associativity, parity disabled @@ -59,56 +55,50 @@ static void __init zynq_init_machine(void) of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); } -static void __init zynq_timer_init(void) -{ - zynq_slcr_init(); - clocksource_of_init(); -} +#define SCU_PERIPH_PHYS 0xF8F00000 +#define SCU_PERIPH_SIZE SZ_8K +#define SCU_PERIPH_VIRT (VMALLOC_END - SCU_PERIPH_SIZE) -static struct map_desc zynq_cortex_a9_scu_map __initdata = { - .length = SZ_256, - .type = MT_DEVICE, +static struct map_desc scu_desc __initdata = { + .virtual = SCU_PERIPH_VIRT, + .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), + .length = SCU_PERIPH_SIZE, + .type = MT_DEVICE, }; -static void __init zynq_scu_map_io(void) +static void __init xilinx_zynq_timer_init(void) { - unsigned long base; + struct device_node *np; + void __iomem *slcr; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + slcr = of_iomap(np, 0); + WARN_ON(!slcr); - base = scu_a9_get_base(); - zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base); - /* Expected address is in vmalloc area that's why simple assign here */ - zynq_cortex_a9_scu_map.virtual = base; - iotable_init(&zynq_cortex_a9_scu_map, 1); - zynq_scu_base = (void __iomem *)base; - BUG_ON(!zynq_scu_base); + xilinx_zynq_clocks_init(slcr); + + xttcps_timer_init(); } /** - * zynq_map_io - Create memory mappings needed for early I/O. + * xilinx_map_io() - Create memory mappings needed for early I/O. */ -static void __init zynq_map_io(void) +static void __init xilinx_map_io(void) { debug_ll_io_init(); - zynq_scu_map_io(); -} - -static void zynq_system_reset(char mode, const char *cmd) -{ - zynq_slcr_system_reset(); + iotable_init(&scu_desc, 1); } -static const char * const zynq_dt_match[] = { +static const char *xilinx_dt_match[] = { "xlnx,zynq-zc702", "xlnx,zynq-7000", NULL }; MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") - .smp = smp_ops(zynq_smp_ops), - .map_io = zynq_map_io, + .map_io = xilinx_map_io, .init_irq = irqchip_init, - .init_machine = zynq_init_machine, - .init_time = zynq_timer_init, - .dt_compat = zynq_dt_match, - .restart = zynq_system_reset, + .init_machine = xilinx_init_machine, + .init_time = xilinx_zynq_timer_init, + .dt_compat = xilinx_dt_match, MACHINE_END diff --git a/trunk/arch/arm/mach-zynq/common.h b/trunk/arch/arm/mach-zynq/common.h index fbbd0e21c404..8b4dbbaa01cf 100644 --- a/trunk/arch/arm/mach-zynq/common.h +++ b/trunk/arch/arm/mach-zynq/common.h @@ -17,24 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -extern int zynq_slcr_init(void); -extern void zynq_slcr_system_reset(void); -extern void zynq_slcr_cpu_stop(int cpu); -extern void zynq_slcr_cpu_start(int cpu); - -#ifdef CONFIG_SMP -extern void secondary_startup(void); -extern char zynq_secondary_trampoline; -extern char zynq_secondary_trampoline_jump; -extern char zynq_secondary_trampoline_end; -extern int __cpuinit zynq_cpun_start(u32 address, int cpu); -extern struct smp_operations zynq_smp_ops __initdata; -#endif - -extern void __iomem *zynq_slcr_base; -extern void __iomem *zynq_scu_base; - -/* Hotplug */ -extern void zynq_platform_cpu_die(unsigned int cpu); +void __init xttcps_timer_init(void); #endif diff --git a/trunk/arch/arm/mach-zynq/headsmp.S b/trunk/arch/arm/mach-zynq/headsmp.S deleted file mode 100644 index d183cd234a9b..000000000000 --- a/trunk/arch/arm/mach-zynq/headsmp.S +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2013 Steffen Trumtrar - * Copyright (c) 2012-2013 Xilinx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - - __CPUINIT - -ENTRY(zynq_secondary_trampoline) - ldr r0, [pc] - bx r0 -.globl zynq_secondary_trampoline_jump -zynq_secondary_trampoline_jump: - /* Space for jumping address */ - .word /* cpu 1 */ -.globl zynq_secondary_trampoline_end -zynq_secondary_trampoline_end: - -ENDPROC(zynq_secondary_trampoline) diff --git a/trunk/arch/arm/mach-zynq/hotplug.c b/trunk/arch/arm/mach-zynq/hotplug.c deleted file mode 100644 index c89672bd1de2..000000000000 --- a/trunk/arch/arm/mach-zynq/hotplug.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (C) 2012-2013 Xilinx - * - * based on linux/arch/arm/mach-realview/hotplug.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#include -#include -#include "common.h" - -static inline void zynq_cpu_enter_lowpower(void) -{ - unsigned int v; - - flush_cache_all(); - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " dsb\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, #0x40\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C) - : "cc"); -} - -static inline void zynq_cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x40\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - dsb(); - wfi(); - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void zynq_platform_cpu_die(unsigned int cpu) -{ - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ - zynq_cpu_enter_lowpower(); - zynq_platform_do_lowpower(cpu, &spurious); - - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - zynq_cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} diff --git a/trunk/arch/arm/mach-zynq/platsmp.c b/trunk/arch/arm/mach-zynq/platsmp.c deleted file mode 100644 index 5fc167e07619..000000000000 --- a/trunk/arch/arm/mach-zynq/platsmp.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * This file contains Xilinx specific SMP code, used to start up - * the second processor. - * - * Copyright (C) 2011-2013 Xilinx - * - * based on linux/arch/arm/mach-realview/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -/* - * Store number of cores in the system - * Because of scu_get_core_count() must be in __init section and can't - * be called from zynq_cpun_start() because it is in __cpuinit section. - */ -static int ncores; - -int __cpuinit zynq_cpun_start(u32 address, int cpu) -{ - u32 trampoline_code_size = &zynq_secondary_trampoline_end - - &zynq_secondary_trampoline; - - if (cpu > ncores) { - pr_warn("CPU No. is not available in the system\n"); - return -1; - } - - /* MS: Expectation that SLCR are directly map and accessible */ - /* Not possible to jump to non aligned address */ - if (!(address & 3) && (!address || (address >= trampoline_code_size))) { - /* Store pointer to ioremap area which points to address 0x0 */ - static u8 __iomem *zero; - u32 trampoline_size = &zynq_secondary_trampoline_jump - - &zynq_secondary_trampoline; - - zynq_slcr_cpu_stop(cpu); - - if (__pa(PAGE_OFFSET)) { - zero = ioremap(0, trampoline_code_size); - if (!zero) { - pr_warn("BOOTUP jump vectors not accessible\n"); - return -1; - } - } else { - zero = (__force u8 __iomem *)PAGE_OFFSET; - } - - /* - * This is elegant way how to jump to any address - * 0x0: Load address at 0x8 to r0 - * 0x4: Jump by mov instruction - * 0x8: Jumping address - */ - memcpy((__force void *)zero, &zynq_secondary_trampoline, - trampoline_size); - writel(address, zero + trampoline_size); - - flush_cache_all(); - outer_flush_range(0, trampoline_code_size); - smp_wmb(); - - if (__pa(PAGE_OFFSET)) - iounmap(zero); - - zynq_slcr_cpu_start(cpu); - - return 0; - } - - pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu, address); - - return -1; -} -EXPORT_SYMBOL(zynq_cpun_start); - -static int __cpuinit zynq_boot_secondary(unsigned int cpu, - struct task_struct *idle) -{ - return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init zynq_smp_init_cpus(void) -{ - int i; - - ncores = scu_get_core_count(zynq_scu_base); - - for (i = 0; i < ncores && i < CONFIG_NR_CPUS; i++) - set_cpu_possible(i, true); -} - -static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) -{ - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - - scu_enable(zynq_scu_base); -} - -struct smp_operations zynq_smp_ops __initdata = { - .smp_init_cpus = zynq_smp_init_cpus, - .smp_prepare_cpus = zynq_smp_prepare_cpus, - .smp_boot_secondary = zynq_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = zynq_platform_cpu_die, -#endif -}; diff --git a/trunk/arch/arm/mach-zynq/slcr.c b/trunk/arch/arm/mach-zynq/slcr.c deleted file mode 100644 index c70969b9c258..000000000000 --- a/trunk/arch/arm/mach-zynq/slcr.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Xilinx SLCR driver - * - * Copyright (c) 2011-2013 Xilinx Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the Free - * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA - * 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" - -#define SLCR_UNLOCK_MAGIC 0xDF0D -#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ - -#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ - -#define SLCR_A9_CPU_CLKSTOP 0x10 -#define SLCR_A9_CPU_RST 0x1 - -#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ -#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ - -void __iomem *zynq_slcr_base; - -/** - * zynq_slcr_system_reset - Reset the entire system. - */ -void zynq_slcr_system_reset(void) -{ - u32 reboot; - - /* - * Unlock the SLCR then reset the system. - * Note that this seems to require raw i/o - * functions or there's a lockup? - */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); - - /* - * Clear 0x0F000000 bits of reboot status register to workaround - * the FSBL not loading the bitstream after soft-reboot - * This is a temporary solution until we know more. - */ - reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); - writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); - writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); -} - -/** - * zynq_slcr_cpu_start - Start cpu - * @cpu: cpu number - */ -void zynq_slcr_cpu_start(int cpu) -{ - /* enable CPUn */ - writel(SLCR_A9_CPU_CLKSTOP << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); - /* enable CLK for CPUn */ - writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); -} - -/** - * zynq_slcr_cpu_stop - Stop cpu - * @cpu: cpu number - */ -void zynq_slcr_cpu_stop(int cpu) -{ - /* stop CLK and reset CPUn */ - writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, - zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); -} - -/** - * zynq_slcr_init - * Returns 0 on success, negative errno otherwise. - * - * Called early during boot from platform code to remap SLCR area. - */ -int __init zynq_slcr_init(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); - if (!np) { - pr_err("%s: no slcr node found\n", __func__); - BUG(); - } - - zynq_slcr_base = of_iomap(np, 0); - if (!zynq_slcr_base) { - pr_err("%s: Unable to map I/O memory\n", __func__); - BUG(); - } - - /* unlock the SLCR so that registers can be changed */ - writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); - - pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); - - xilinx_zynq_clocks_init(zynq_slcr_base); - - of_node_put(np); - - return 0; -} diff --git a/trunk/arch/arm/mach-zynq/timer.c b/trunk/arch/arm/mach-zynq/timer.c new file mode 100644 index 000000000000..f9fbc9c1e7a6 --- /dev/null +++ b/trunk/arch/arm/mach-zynq/timer.c @@ -0,0 +1,324 @@ +/* + * This file contains driver for the Xilinx PS Timer Counter IP. + * + * Copyright (C) 2011 Xilinx + * + * based on arch/mips/kernel/time.c timer driver + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Timer Register Offset Definitions of Timer 1, Increment base address by 4 + * and use same offsets for Timer 2 + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ +#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ +#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ + +#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1 + +/* + * Setup the timers to use pre-scaling, using a fixed value for now that will + * work across most input frequency, but it may need to be more dynamic + */ +#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ +#define PRESCALE 2048 /* The exponent must match this */ +#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) +#define CLK_CNTRL_PRESCALE_EN 1 +#define CNT_CNTRL_RESET (1<<4) + +/** + * struct xttcps_timer - This definition defines local timer structure + * + * @base_addr: Base address of timer + **/ +struct xttcps_timer { + void __iomem *base_addr; +}; + +struct xttcps_timer_clocksource { + struct xttcps_timer xttc; + struct clocksource cs; +}; + +#define to_xttcps_timer_clksrc(x) \ + container_of(x, struct xttcps_timer_clocksource, cs) + +struct xttcps_timer_clockevent { + struct xttcps_timer xttc; + struct clock_event_device ce; + struct clk *clk; +}; + +#define to_xttcps_timer_clkevent(x) \ + container_of(x, struct xttcps_timer_clockevent, ce) + +/** + * xttcps_set_interval - Set the timer interval value + * + * @timer: Pointer to the timer instance + * @cycles: Timer interval ticks + **/ +static void xttcps_set_interval(struct xttcps_timer *timer, + unsigned long cycles) +{ + u32 ctrl_reg; + + /* Disable the counter, set the counter value and re-enable counter */ + ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + + __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET); + + /* + * Reset the counter (0x10) so that it starts from 0, one-shot + * mode makes this needed for timing to be right. + */ + ctrl_reg |= CNT_CNTRL_RESET; + ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); +} + +/** + * xttcps_clock_event_interrupt - Clock event timer interrupt handler + * + * @irq: IRQ number of the Timer + * @dev_id: void pointer to the xttcps_timer instance + * + * returns: Always IRQ_HANDLED - success + **/ +static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id) +{ + struct xttcps_timer_clockevent *xttce = dev_id; + struct xttcps_timer *timer = &xttce->xttc; + + /* Acknowledge the interrupt and call event handler */ + __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET); + + xttce->ce.event_handler(&xttce->ce); + + return IRQ_HANDLED; +} + +/** + * __xttc_clocksource_read - Reads the timer counter register + * + * returns: Current timer counter register value + **/ +static cycle_t __xttc_clocksource_read(struct clocksource *cs) +{ + struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc; + + return (cycle_t)__raw_readl(timer->base_addr + + XTTCPS_COUNT_VAL_OFFSET); +} + +/** + * xttcps_set_next_event - Sets the time interval for next event + * + * @cycles: Timer interval ticks + * @evt: Address of clock event instance + * + * returns: Always 0 - success + **/ +static int xttcps_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); + struct xttcps_timer *timer = &xttce->xttc; + + xttcps_set_interval(timer, cycles); + return 0; +} + +/** + * xttcps_set_mode - Sets the mode of timer + * + * @mode: Mode to be set + * @evt: Address of clock event instance + **/ +static void xttcps_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt); + struct xttcps_timer *timer = &xttce->xttc; + u32 ctrl_reg; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + xttcps_set_interval(timer, + DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk), + PRESCALE * HZ)); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + break; + case CLOCK_EVT_MODE_RESUME: + ctrl_reg = __raw_readl(timer->base_addr + + XTTCPS_CNT_CNTRL_OFFSET); + ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK; + __raw_writel(ctrl_reg, + timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET); + break; + } +} + +static void __init zynq_ttc_setup_clocksource(struct device_node *np, + void __iomem *base) +{ + struct xttcps_timer_clocksource *ttccs; + struct clk *clk; + int err; + u32 reg; + + ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); + if (WARN_ON(!ttccs)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(clk))) + return; + + err = clk_prepare_enable(clk); + if (WARN_ON(err)) + return; + + ttccs->xttc.base_addr = base + reg * 4; + + ttccs->cs.name = np->name; + ttccs->cs.rating = 200; + ttccs->cs.read = __xttc_clocksource_read; + ttccs->cs.mask = CLOCKSOURCE_MASK(16); + ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + __raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); + __raw_writel(CNT_CNTRL_RESET, + ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); + + err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE); + if (WARN_ON(err)) + return; +} + +static void __init zynq_ttc_setup_clockevent(struct device_node *np, + void __iomem *base) +{ + struct xttcps_timer_clockevent *ttcce; + int err, irq; + u32 reg; + + ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); + if (WARN_ON(!ttcce)) + return; + + err = of_property_read_u32(np, "reg", ®); + if (WARN_ON(err)) + return; + + ttcce->xttc.base_addr = base + reg * 4; + + ttcce->clk = of_clk_get_by_name(np, "cpu_1x"); + if (WARN_ON(IS_ERR(ttcce->clk))) + return; + + err = clk_prepare_enable(ttcce->clk); + if (WARN_ON(err)) + return; + + irq = irq_of_parse_and_map(np, 0); + if (WARN_ON(!irq)) + return; + + ttcce->ce.name = np->name; + ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ttcce->ce.set_next_event = xttcps_set_next_event; + ttcce->ce.set_mode = xttcps_set_mode; + ttcce->ce.rating = 200; + ttcce->ce.irq = irq; + ttcce->ce.cpumask = cpu_possible_mask; + + __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET); + __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, + ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET); + __raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET); + + err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER, + np->name, ttcce); + if (WARN_ON(err)) + return; + + clockevents_config_and_register(&ttcce->ce, + clk_get_rate(ttcce->clk) / PRESCALE, + 1, 0xfffe); +} + +static const __initconst struct of_device_id zynq_ttc_match[] = { + { .compatible = "xlnx,ttc-counter-clocksource", + .data = zynq_ttc_setup_clocksource, }, + { .compatible = "xlnx,ttc-counter-clockevent", + .data = zynq_ttc_setup_clockevent, }, + {} +}; + +/** + * xttcps_timer_init - Initialize the timer + * + * Initializes the timer hardware and register the clock source and clock event + * timers with Linux kernal timer framework + **/ +void __init xttcps_timer_init(void) +{ + struct device_node *np; + + for_each_compatible_node(np, NULL, "xlnx,ttc") { + struct device_node *np_chld; + void __iomem *base; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + for_each_available_child_of_node(np, np_chld) { + int (*cb)(struct device_node *np, void __iomem *base); + const struct of_device_id *match; + + match = of_match_node(zynq_ttc_match, np_chld); + if (match) { + cb = match->data; + cb(np_chld, base); + } + } + } +} diff --git a/trunk/arch/arm/mm/cache-l2x0.c b/trunk/arch/arm/mm/cache-l2x0.c index c2f37390308a..c465faca51b0 100644 --- a/trunk/arch/arm/mm/cache-l2x0.c +++ b/trunk/arch/arm/mm/cache-l2x0.c @@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id) int lockregs; int i; - switch (cache_id) { + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: lockregs = 8; break; @@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) if (cache_id_part_number_from_dt) cache_id = cache_id_part_number_from_dt; else - cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID) - & L2X0_CACHE_ID_PART_MASK; + cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); aux &= aux_mask; aux |= aux_val; /* Determine the number of ways */ - switch (cache_id) { + switch (cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: if (aux & (1 << 16)) ways = 16; @@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = { .flush_all = l2x0_flush_all, .inv_all = l2x0_inv_all, .disable = l2x0_disable, - .set_debug = pl310_set_debug, }, }; @@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) data->save(); of_init = true; - l2x0_init(l2x0_base, aux_val, aux_mask); - memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache)); + l2x0_init(l2x0_base, aux_val, aux_mask); return 0; } diff --git a/trunk/arch/arm/mm/context.c b/trunk/arch/arm/mm/context.c index a5a4b2bc42ba..2ac37372ef52 100644 --- a/trunk/arch/arm/mm/context.c +++ b/trunk/arch/arm/mm/context.c @@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock); static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION); static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS); -static DEFINE_PER_CPU(atomic64_t, active_asids); +DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; @@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { local_flush_bp_all(); local_flush_tlb_all(); + dummy_flush_tlb_a15_erratum(); } atomic64_set(&per_cpu(active_asids, cpu), asid); diff --git a/trunk/arch/arm/mm/mmu.c b/trunk/arch/arm/mm/mmu.c index e95a996ab78f..78978945492a 100644 --- a/trunk/arch/arm/mm/mmu.c +++ b/trunk/arch/arm/mm/mmu.c @@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, } while (pte++, addr += PAGE_SIZE, addr != end); } -static void __init alloc_init_section(pud_t *pud, unsigned long addr, - unsigned long end, phys_addr_t phys, - const struct mem_type *type) +static void __init map_init_section(pmd_t *pmd, unsigned long addr, + unsigned long end, phys_addr_t phys, + const struct mem_type *type) { - pmd_t *pmd = pmd_offset(pud, addr); - +#ifndef CONFIG_ARM_LPAE /* - * Try a section mapping - end, addr and phys must all be aligned - * to a section boundary. Note that PMDs refer to the individual - * L1 entries, whereas PGDs refer to a group of L1 entries making - * up one logical pointer to an L2 table. + * In classic MMU format, puds and pmds are folded in to + * the pgds. pmd_offset gives the PGD entry. PGDs refer to a + * group of L1 entries making up one logical pointer to + * an L2 table (2MB), where as PMDs refer to the individual + * L1 entries (1MB). Hence increment to get the correct + * offset for odd 1MB sections. + * (See arch/arm/include/asm/pgtable-2level.h) */ - if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { - pmd_t *p = pmd; - -#ifndef CONFIG_ARM_LPAE - if (addr & SECTION_SIZE) - pmd++; + if (addr & SECTION_SIZE) + pmd++; #endif + do { + *pmd = __pmd(phys | type->prot_sect); + phys += SECTION_SIZE; + } while (pmd++, addr += SECTION_SIZE, addr != end); - do { - *pmd = __pmd(phys | type->prot_sect); - phys += SECTION_SIZE; - } while (pmd++, addr += SECTION_SIZE, addr != end); + flush_pmd_entry(pmd); +} - flush_pmd_entry(p); - } else { +static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, + unsigned long end, phys_addr_t phys, + const struct mem_type *type) +{ + pmd_t *pmd = pmd_offset(pud, addr); + unsigned long next; + + do { /* - * No need to loop; pte's aren't interested in the - * individual L1 entries. + * With LPAE, we must loop over to map + * all the pmds for the given range. */ - alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); - } + next = pmd_addr_end(addr, end); + + /* + * Try a section mapping - addr, next and phys must all be + * aligned to a section boundary. + */ + if (type->prot_sect && + ((addr | next | phys) & ~SECTION_MASK) == 0) { + map_init_section(pmd, addr, next, phys, type); + } else { + alloc_init_pte(pmd, addr, next, + __phys_to_pfn(phys), type); + } + + phys += next - addr; + + } while (pmd++, addr = next, addr != end); } static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, @@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, do { next = pud_addr_end(addr, end); - alloc_init_section(pud, addr, next, phys, type); + alloc_init_pmd(pud, addr, next, phys, type); phys += next - addr; } while (pud++, addr = next, addr != end); } diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index 3a3c015f8d5c..f584d3f5b37c 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -420,7 +420,7 @@ __v7_pj4b_proc_info: __v7_ca7mp_proc_info: .long 0x410fc070 .long 0xff0ffff0 - __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV + __v7_proc __v7_ca7mp_setup .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info /* @@ -430,9 +430,24 @@ __v7_ca7mp_proc_info: __v7_ca15mp_proc_info: .long 0x410fc0f0 .long 0xff0ffff0 - __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV + __v7_proc __v7_ca15mp_setup .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info + /* + * Qualcomm Inc. Krait processors. + */ + .type __krait_proc_info, #object +__krait_proc_info: + .long 0x510f0400 @ Required ID value + .long 0xff0ffc00 @ Mask for ID + /* + * Some Krait processors don't indicate support for SDIV and UDIV + * instructions in the ARM instruction set, even though they actually + * do support them. + */ + __v7_proc __v7_setup, hwcaps = HWCAP_IDIV + .size __krait_proc_info, . - __krait_proc_info + /* * Match any ARMv7 processor core. */ diff --git a/trunk/arch/arm/plat-samsung/irq-vic-timer.c b/trunk/arch/arm/plat-samsung/irq-vic-timer.c index 5d205e74e495..f980cf3d2baa 100644 --- a/trunk/arch/arm/plat-samsung/irq-vic-timer.c +++ b/trunk/arch/arm/plat-samsung/irq-vic-timer.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -24,6 +23,8 @@ #include #include +#include + static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); diff --git a/trunk/arch/arm/plat-samsung/s5p-irq-gpioint.c b/trunk/arch/arm/plat-samsung/s5p-irq-gpioint.c index fafdb059043a..bae56131a50a 100644 --- a/trunk/arch/arm/plat-samsung/s5p-irq-gpioint.c +++ b/trunk/arch/arm/plat-samsung/s5p-irq-gpioint.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -23,6 +22,8 @@ #include #include +#include + #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u)) #define CON_OFFSET 0x700 diff --git a/trunk/arch/arm/plat-versatile/platsmp.c b/trunk/arch/arm/plat-versatile/platsmp.c index 1e1b2d769748..f2ac15561778 100644 --- a/trunk/arch/arm/plat-versatile/platsmp.c +++ b/trunk/arch/arm/plat-versatile/platsmp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,13 @@ static DEFINE_SPINLOCK(boot_lock); void __cpuinit versatile_secondary_init(unsigned int cpu) { + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + /* * let the primary processor know we're out of the * pen, then head off into the C entry point diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index cd2e21ff562a..51244bf97271 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -18,7 +18,7 @@ config MIPS select HAVE_KRETPROBES select HAVE_DEBUG_KMEMLEAK select ARCH_BINFMT_ELF_RANDOMIZE_PIE - select HAVE_ARCH_TRANSPARENT_HUGEPAGE + select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT select RTC_LIB if !MACH_LOONGSON select GENERIC_ATOMIC64 if !64BIT select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE @@ -657,7 +657,7 @@ config SNI_RM bool "SNI RM200/300/400" select FW_ARC if CPU_LITTLE_ENDIAN select FW_ARC32 if CPU_LITTLE_ENDIAN - select SNIPROM if CPU_BIG_ENDIAN + select FW_SNIPROM if CPU_BIG_ENDIAN select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select CEVT_R4K @@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION config FW_ARC32 bool -config SNIPROM +config FW_SNIPROM bool config BOOT_ELF32 @@ -1493,7 +1493,6 @@ config CPU_XLP select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM - select CPU_HAS_LLSC select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select CPU_HAS_PREFETCH diff --git a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c index ed1949c29508..9aa7d44898ed 100644 --- a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -745,10 +745,7 @@ void __init board_prom_init(void) strcpy(cfe_version, "unknown"); printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); - if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) { - printk(KERN_ERR PFX "invalid nvram checksum\n"); - return; - } + bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); board_name = bcm63xx_nvram_get_name(); /* find board by name */ diff --git a/trunk/arch/mips/bcm63xx/nvram.c b/trunk/arch/mips/bcm63xx/nvram.c index 620611680839..a4b8864f9307 100644 --- a/trunk/arch/mips/bcm63xx/nvram.c +++ b/trunk/arch/mips/bcm63xx/nvram.c @@ -38,7 +38,7 @@ struct bcm963xx_nvram { static struct bcm963xx_nvram nvram; static int mac_addr_used; -int __init bcm63xx_nvram_init(void *addr) +void __init bcm63xx_nvram_init(void *addr) { unsigned int check_len; u32 crc, expected_crc; @@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr) crc = crc32_le(~0, (u8 *)&nvram, check_len); if (crc != expected_crc) - return -EINVAL; - - return 0; + pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n", + expected_crc, crc); } u8 *bcm63xx_nvram_get_name(void) diff --git a/trunk/arch/mips/bcm63xx/setup.c b/trunk/arch/mips/bcm63xx/setup.c index 314231be788c..35e18e98beb9 100644 --- a/trunk/arch/mips/bcm63xx/setup.c +++ b/trunk/arch/mips/bcm63xx/setup.c @@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void) return board_register_devices(); } -device_initcall(bcm63xx_register_devices); +arch_initcall(bcm63xx_register_devices); diff --git a/trunk/arch/mips/cavium-octeon/setup.c b/trunk/arch/mips/cavium-octeon/setup.c index c594a3d4f743..b0baa299f899 100644 --- a/trunk/arch/mips/cavium-octeon/setup.c +++ b/trunk/arch/mips/cavium-octeon/setup.c @@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image) static void octeon_generic_shutdown(void) { - int cpu, i; + int i; +#ifdef CONFIG_SMP + int cpu; +#endif struct cvmx_bootmem_desc *bootmem_desc; void *named_block_array_ptr; diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h index 62d6a3b4d3b7..4e0b6bc1165e 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h @@ -9,10 +9,8 @@ * * Initialized the local nvram copy from the target address and checks * its checksum. - * - * Returns 0 on success. */ -int __init bcm63xx_nvram_init(void *nvram); +void bcm63xx_nvram_init(void *nvram); /** * bcm63xx_nvram_get_name() - returns the board name according to nvram diff --git a/trunk/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h index d9c828419037..193c0912d38e 100644 --- a/trunk/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h +++ b/trunk/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h @@ -28,11 +28,7 @@ /* #define cpu_has_prefetch ? */ #define cpu_has_mcheck 1 /* #define cpu_has_ejtag ? */ -#ifdef CONFIG_CPU_HAS_LLSC #define cpu_has_llsc 1 -#else -#define cpu_has_llsc 0 -#endif /* #define cpu_has_vtag_icache ? */ /* #define cpu_has_dc_aliases ? */ /* #define cpu_has_ic_fills_f_dc ? */ diff --git a/trunk/arch/mips/include/asm/mipsregs.h b/trunk/arch/mips/include/asm/mipsregs.h index 12b70c25906a..0da44d422f5b 100644 --- a/trunk/arch/mips/include/asm/mipsregs.h +++ b/trunk/arch/mips/include/asm/mipsregs.h @@ -1166,7 +1166,10 @@ do { \ unsigned int __dspctl; \ \ __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ " rddsp %0, %x1 \n" \ + " .set pop \n" \ : "=r" (__dspctl) \ : "i" (mask)); \ __dspctl; \ @@ -1175,30 +1178,198 @@ do { \ #define wrdsp(val, mask) \ do { \ __asm__ __volatile__( \ + " .set push \n" \ + " .set dsp \n" \ " wrdsp %0, %x1 \n" \ + " .set pop \n" \ : \ : "r" (val), "i" (mask)); \ } while (0) -#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) -#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) -#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) -#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) - -#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) -#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) -#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) -#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) - -#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) -#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) -#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) -#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) - -#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) -#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) -#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) -#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) +#define mflo0() \ +({ \ + long mflo0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mflo0)); \ + mflo0; \ +}) + +#define mflo1() \ +({ \ + long mflo1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mflo1)); \ + mflo1; \ +}) + +#define mflo2() \ +({ \ + long mflo2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mflo2)); \ + mflo2; \ +}) + +#define mflo3() \ +({ \ + long mflo3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mflo %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mflo3)); \ + mflo3; \ +}) + +#define mfhi0() \ +({ \ + long mfhi0; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac0 \n" \ + " .set pop \n" \ + : "=r" (mfhi0)); \ + mfhi0; \ +}) + +#define mfhi1() \ +({ \ + long mfhi1; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac1 \n" \ + " .set pop \n" \ + : "=r" (mfhi1)); \ + mfhi1; \ +}) + +#define mfhi2() \ +({ \ + long mfhi2; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac2 \n" \ + " .set pop \n" \ + : "=r" (mfhi2)); \ + mfhi2; \ +}) + +#define mfhi3() \ +({ \ + long mfhi3; \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mfhi %0, $ac3 \n" \ + " .set pop \n" \ + : "=r" (mfhi3)); \ + mfhi3; \ +}) + + +#define mtlo0(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac0 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mtlo1(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mtlo2(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mtlo3(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mtlo %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi0(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac0 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi1(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac1 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi2(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac2 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) + +#define mthi3(x) \ +({ \ + __asm__( \ + " .set push \n" \ + " .set dsp \n" \ + " mthi %0, $ac3 \n" \ + " .set pop \n" \ + : \ + : "r" (x)); \ +}) #else diff --git a/trunk/arch/mips/include/asm/signal.h b/trunk/arch/mips/include/asm/signal.h index 197f6367c201..8efe5a9e2c3e 100644 --- a/trunk/arch/mips/include/asm/signal.h +++ b/trunk/arch/mips/include/asm/signal.h @@ -21,6 +21,6 @@ #include #include -#define __ARCH_HAS_ODD_SIGACTION +#define __ARCH_HAS_IRIX_SIGACTION #endif /* _ASM_SIGNAL_H */ diff --git a/trunk/arch/mips/include/uapi/asm/signal.h b/trunk/arch/mips/include/uapi/asm/signal.h index d6b18b4d0f3a..addb9f556b71 100644 --- a/trunk/arch/mips/include/uapi/asm/signal.h +++ b/trunk/arch/mips/include/uapi/asm/signal.h @@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ * * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single * Unix names RESETHAND and NODEFER respectively. + * + * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever + * supported its use and no libc was using it, so the entire sa-restorer + * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48 + * retaining only the SA_RESTORER definition as a reminder to avoid + * accidental reuse of the mask bit. */ #define SA_ONSTACK 0x08000000 #define SA_RESETHAND 0x80000000 @@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SA_NOMASK SA_NODEFER #define SA_ONESHOT SA_RESETHAND -#define SA_RESTORER 0x04000000 /* Only for o32 */ - #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile index f81d98f6184c..de75fb50562b 100644 --- a/trunk/arch/mips/kernel/Makefile +++ b/trunk/arch/mips/kernel/Makefile @@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o # -# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe -# to enable DSP assembler support here even if the MIPS Release 2 CPU we -# are targetting does not support DSP because all code-paths making use of -# it properly check that the running CPU *actually does* support these -# instructions. +# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not +# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches +# here because the compiler may use DSP ASE instructions (such as lwx) in +# code paths where we cannot check that the CPU we are running on supports it. +# Proper abstraction using HAVE_AS_DSP and macros is done in +# arch/mips/include/asm/mipsregs.h. # ifeq ($(CONFIG_CPU_MIPSR2), y) CFLAGS_DSP = -DHAVE_AS_DSP -# -# Check if assembler supports DSP ASE -# -ifeq ($(call cc-option-yn,-mdsp), y) -CFLAGS_DSP += -mdsp -endif - -# -# Check if assembler supports DSP ASE Rev2 -# -ifeq ($(call cc-option-yn,-mdspr2), y) -CFLAGS_DSP += -mdspr2 -endif - CFLAGS_signal.o = $(CFLAGS_DSP) CFLAGS_signal32.o = $(CFLAGS_DSP) CFLAGS_process.o = $(CFLAGS_DSP) diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index 6bfccc227a95..5fe66a0c3224 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->tlbsize = 48; break; case PRID_IMP_VR41XX: + set_isa(c, MIPS_CPU_ISA_III); + c->options = R4K_OPTS; + c->tlbsize = 32; switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; @@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "NEC VR4131"; } else { c->cputype = CPU_VR4133; + c->options |= MIPS_CPU_LLSC; __cpu_name[cpu] = "NEC VR4133"; } break; @@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "NEC Vr41xx"; break; } - set_isa(c, MIPS_CPU_ISA_III); - c->options = R4K_OPTS; - c->tlbsize = 32; break; case PRID_IMP_R4300: c->cputype = CPU_R4300; @@ -1226,10 +1227,8 @@ __cpuinit void cpu_probe(void) if (c->options & MIPS_CPU_FPU) { c->fpu_id = cpu_get_fpu_id(); - if (c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M32R2 || - c->isa_level == MIPS_CPU_ISA_M64R1 || - c->isa_level == MIPS_CPU_ISA_M64R2) { + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { if (c->fpu_id & MIPS_FPIR_3D) c->ases |= MIPS_ASE_MIPS3D; } diff --git a/trunk/arch/mips/kernel/linux32.c b/trunk/arch/mips/kernel/linux32.c index 8eeee1c860c0..db9655f08892 100644 --- a/trunk/arch/mips/kernel/linux32.c +++ b/trunk/arch/mips/kernel/linux32.c @@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third, err = compat_sys_shmctl(first, second, compat_ptr(ptr)); break; default: - err = -EINVAL; + err = -ENOSYS; break; } diff --git a/trunk/arch/mips/kernel/mcount.S b/trunk/arch/mips/kernel/mcount.S index 165867673357..33d067148e61 100644 --- a/trunk/arch/mips/kernel/mcount.S +++ b/trunk/arch/mips/kernel/mcount.S @@ -46,10 +46,9 @@ PTR_L a5, PT_R9(sp) PTR_L a6, PT_R10(sp) PTR_L a7, PT_R11(sp) -#else - PTR_ADDIU sp, PT_SIZE #endif -.endm + PTR_ADDIU sp, PT_SIZE + .endm .macro RETURN_BACK jr ra @@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra) .globl _mcount _mcount: b ftrace_stub - addiu sp,sp,8 +#ifdef CONFIG_32BIT + addiu sp,sp,8 +#else + nop +#endif /* When tracing is activated, it calls ftrace_caller+8 (aka here) */ lw t1, function_trace_stop diff --git a/trunk/arch/mips/kernel/proc.c b/trunk/arch/mips/kernel/proc.c index 135c4aadccbe..7a54f74b7818 100644 --- a/trunk/arch/mips/kernel/proc.c +++ b/trunk/arch/mips/kernel/proc.c @@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_mips_r) { seq_printf(m, "isa\t\t\t:"); if (cpu_has_mips_1) - seq_printf(m, "%s", "mips1"); + seq_printf(m, "%s", " mips1"); if (cpu_has_mips_2) seq_printf(m, "%s", " mips2"); if (cpu_has_mips_3) diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index a200b5bdbb87..c3abb88170fc 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) #ifdef CONFIG_64BIT status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; #endif - if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) + if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) status_set |= ST0_XX; if (cpu_has_dsp) status_set |= ST0_MX; diff --git a/trunk/arch/mips/lib/bitops.c b/trunk/arch/mips/lib/bitops.c index 81f1dcfdcab8..a64daee740ee 100644 --- a/trunk/arch/mips/lib/bitops.c +++ b/trunk/arch/mips/lib/bitops.c @@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr, unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a |= mask; raw_local_irq_restore(flags); return res; @@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr, unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a |= mask; raw_local_irq_restore(flags); return res; @@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a &= ~mask; raw_local_irq_restore(flags); return res; @@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr) unsigned bit = nr & SZLONG_MASK; unsigned long mask; unsigned long flags; - unsigned long res; + int res; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); - res = (mask & *a); + res = (mask & *a) != 0; *a ^= mask; raw_local_irq_restore(flags); return res; diff --git a/trunk/arch/mips/lib/csum_partial.S b/trunk/arch/mips/lib/csum_partial.S index 507147aebd41..a6adffbb4e5f 100644 --- a/trunk/arch/mips/lib/csum_partial.S +++ b/trunk/arch/mips/lib/csum_partial.S @@ -270,7 +270,7 @@ LEAF(csum_partial) #endif /* odd buffer alignment? */ -#ifdef CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2 wsbh v1, sum movn sum, v1, t7 #else @@ -670,7 +670,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc) addu sum, v1 #endif -#ifdef CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2 wsbh v1, sum movn sum, v1, odd #else diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index ecca559b8d7b..2078915eacb9 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void) return; default: - if (c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M32R2 || - c->isa_level == MIPS_CPU_ISA_M64R1 || - c->isa_level == MIPS_CPU_ISA_M64R2) { + if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { #ifdef CONFIG_MIPS_CPU_SCACHE if (mips_sc_init ()) { scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; diff --git a/trunk/arch/mips/mm/sc-mips.c b/trunk/arch/mips/mm/sc-mips.c index 93d937b4b1ba..df96da7e939b 100644 --- a/trunk/arch/mips/mm/sc-mips.c +++ b/trunk/arch/mips/mm/sc-mips.c @@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void) c->scache.flags |= MIPS_CACHE_NOT_PRESENT; /* Ignore anything but MIPSxx processors */ - if (c->isa_level != MIPS_CPU_ISA_M32R1 && - c->isa_level != MIPS_CPU_ISA_M32R2 && - c->isa_level != MIPS_CPU_ISA_M64R1 && - c->isa_level != MIPS_CPU_ISA_M64R2) + if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2))) return 0; /* Does this MIPS32/MIPS64 CPU have a config2 register? */ diff --git a/trunk/arch/mips/pci/pci-alchemy.c b/trunk/arch/mips/pci/pci-alchemy.c index 38a80c83fd67..d1faece21b6a 100644 --- a/trunk/arch/mips/pci/pci-alchemy.c +++ b/trunk/arch/mips/pci/pci-alchemy.c @@ -19,7 +19,7 @@ #include #include -#ifdef CONFIG_DEBUG_PCI +#ifdef CONFIG_PCI_DEBUG #define DBG(x...) printk(KERN_DEBUG x) #else #define DBG(x...) do {} while (0) @@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, if (status & (1 << 29)) { *data = 0xffffffff; error = -1; - DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", + DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n", access_type, bus->number, device); } else if ((status >> 28) & 0xf) { DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", diff --git a/trunk/arch/s390/include/asm/pgtable.h b/trunk/arch/s390/include/asm/pgtable.h index 4a2930844d43..4a5443118cfb 100644 --- a/trunk/arch/s390/include/asm/pgtable.h +++ b/trunk/arch/s390/include/asm/pgtable.h @@ -344,6 +344,7 @@ extern unsigned long MODULES_END; #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ /* Bits in the segment table entry */ +#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ @@ -1531,7 +1532,8 @@ extern int s390_enable_sie(void); /* * No page table caches to initialise */ -#define pgtable_cache_init() do { } while (0) +static inline void pgtable_cache_init(void) { } +static inline void check_pgt_cache(void) { } #include diff --git a/trunk/arch/s390/lib/uaccess_pt.c b/trunk/arch/s390/lib/uaccess_pt.c index dff631d34b45..466fb3383960 100644 --- a/trunk/arch/s390/lib/uaccess_pt.c +++ b/trunk/arch/s390/lib/uaccess_pt.c @@ -77,42 +77,69 @@ static size_t copy_in_kernel(size_t count, void __user *to, * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address * contains the (negative) exception code. */ -static __always_inline unsigned long follow_table(struct mm_struct *mm, - unsigned long addr, int write) +#ifdef CONFIG_64BIT +static unsigned long follow_table(struct mm_struct *mm, + unsigned long address, int write) { - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ptep; + unsigned long *table = (unsigned long *)__pa(mm->pgd); + + switch (mm->context.asce_bits & _ASCE_TYPE_MASK) { + case _ASCE_TYPE_REGION1: + table = table + ((address >> 53) & 0x7ff); + if (unlikely(*table & _REGION_ENTRY_INV)) + return -0x39UL; + table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + case _ASCE_TYPE_REGION2: + table = table + ((address >> 42) & 0x7ff); + if (unlikely(*table & _REGION_ENTRY_INV)) + return -0x3aUL; + table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + case _ASCE_TYPE_REGION3: + table = table + ((address >> 31) & 0x7ff); + if (unlikely(*table & _REGION_ENTRY_INV)) + return -0x3bUL; + table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN); + case _ASCE_TYPE_SEGMENT: + table = table + ((address >> 20) & 0x7ff); + if (unlikely(*table & _SEGMENT_ENTRY_INV)) + return -0x10UL; + if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) { + if (write && (*table & _SEGMENT_ENTRY_RO)) + return -0x04UL; + return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) + + (address & ~_SEGMENT_ENTRY_ORIGIN_LARGE); + } + table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN); + } + table = table + ((address >> 12) & 0xff); + if (unlikely(*table & _PAGE_INVALID)) + return -0x11UL; + if (write && (*table & _PAGE_RO)) + return -0x04UL; + return (*table & PAGE_MASK) + (address & ~PAGE_MASK); +} - pgd = pgd_offset(mm, addr); - if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd))) - return -0x3aUL; +#else /* CONFIG_64BIT */ - pud = pud_offset(pgd, addr); - if (pud_none(*pud) || unlikely(pud_bad(*pud))) - return -0x3bUL; +static unsigned long follow_table(struct mm_struct *mm, + unsigned long address, int write) +{ + unsigned long *table = (unsigned long *)__pa(mm->pgd); - pmd = pmd_offset(pud, addr); - if (pmd_none(*pmd)) + table = table + ((address >> 20) & 0x7ff); + if (unlikely(*table & _SEGMENT_ENTRY_INV)) return -0x10UL; - if (pmd_large(*pmd)) { - if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO)) - return -0x04UL; - return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK); - } - if (unlikely(pmd_bad(*pmd))) - return -0x10UL; - - ptep = pte_offset_map(pmd, addr); - if (!pte_present(*ptep)) + table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN); + table = table + ((address >> 12) & 0xff); + if (unlikely(*table & _PAGE_INVALID)) return -0x11UL; - if (write && (!pte_write(*ptep) || !pte_dirty(*ptep))) + if (write && (*table & _PAGE_RO)) return -0x04UL; - - return (pte_val(*ptep) & PAGE_MASK) + (addr & ~PAGE_MASK); + return (*table & PAGE_MASK) + (address & ~PAGE_MASK); } +#endif /* CONFIG_64BIT */ + static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr, size_t n, int write_user) { @@ -197,7 +224,7 @@ size_t copy_to_user_pt(size_t n, void __user *to, const void *from) static size_t clear_user_pt(size_t n, void __user *to) { - void *zpage = &empty_zero_page; + void *zpage = (void *) empty_zero_page; long done, size, ret; done = 0; diff --git a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c index eef17dcc3a41..96c6c2634cb4 100644 --- a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c +++ b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c @@ -8,23 +8,12 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7203_pfc_resources[] = { - [0] = { - .start = 0xfffe3800, - .end = 0xfffe3a9f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources, - ARRAY_SIZE(sh7203_pfc_resources)); + return sh_pfc_register("pfc-sh7203", NULL, 0); } arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c index 569decbd6d93..b1b7c1bae127 100644 --- a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c +++ b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c @@ -8,23 +8,12 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7264_pfc_resources[] = { - [0] = { - .start = 0xfffe3800, - .end = 0xfffe393f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources, - ARRAY_SIZE(sh7264_pfc_resources)); + return sh_pfc_register("pfc-sh7264", NULL, 0); } arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c index 4c17fb6970b1..dc2a86830456 100644 --- a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c +++ b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -9,23 +9,12 @@ * for more details. */ -#include #include -#include #include #include -static struct resource sh7269_pfc_resources[] = { - [0] = { - .start = 0xfffe3800, - .end = 0xfffe391f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources, - ARRAY_SIZE(sh7269_pfc_resources)); + return sh_pfc_register("pfc-sh7269", NULL, 0); } arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/trunk/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c index 26e90a66ebb7..7d3744ac7b08 100644 --- a/trunk/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c +++ b/trunk/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c @@ -8,23 +8,13 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7720_pfc_resources[] = { - [0] = { - .start = 0xa4050100, - .end = 0xa405016f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources, - ARRAY_SIZE(sh7720_pfc_resources)); + return sh_pfc_register("pfc-sh7720", NULL, 0); } + arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c index 271bbc864929..d9bcc4290997 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c @@ -1,20 +1,10 @@ -#include #include #include -#include #include -static struct resource sh7722_pfc_resources[] = { - [0] = { - .start = 0xa4050100, - .end = 0xa405018f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources, - ARRAY_SIZE(sh7722_pfc_resources)); + return sh_pfc_register("pfc-sh7722", NULL, 0); } + arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c index 99c637d5bf7a..bcec7ad7f783 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c @@ -8,23 +8,13 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7723_pfc_resources[] = { - [0] = { - .start = 0xa4050100, - .end = 0xa405016f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources, - ARRAY_SIZE(sh7723_pfc_resources)); + return sh_pfc_register("pfc-sh7723", NULL, 0); } + arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c index 63be4749e341..5c3541d6aed8 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c @@ -13,23 +13,12 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7724_pfc_resources[] = { - [0] = { - .start = 0xa4050100, - .end = 0xa405016f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources, - ARRAY_SIZE(sh7724_pfc_resources)); + return sh_pfc_register("pfc-sh7724", NULL, 0); } arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c index 567745d44221..cda6bd177b8c 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -13,23 +13,12 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7757_pfc_resources[] = { - [0] = { - .start = 0xffec0000, - .end = 0xffec008f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources, - ARRAY_SIZE(sh7757_pfc_resources)); + return sh_pfc_register("pfc-sh7757", NULL, 0); } arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c index e336ab8b5125..01055b809f64 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c @@ -8,23 +8,13 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7785_pfc_resources[] = { - [0] = { - .start = 0xffe70000, - .end = 0xffe7008f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources, - ARRAY_SIZE(sh7785_pfc_resources)); + return sh_pfc_register("pfc-sh7785", NULL, 0); } + arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c index 9a459556a2f7..3061778d55da 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c @@ -13,23 +13,13 @@ * for more details. */ -#include #include #include -#include #include -static struct resource sh7786_pfc_resources[] = { - [0] = { - .start = 0xffcc0000, - .end = 0xffcc008f, - .flags = IORESOURCE_MEM, - }, -}; - static int __init plat_pinmux_setup(void) { - return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources, - ARRAY_SIZE(sh7786_pfc_resources)); + return sh_pfc_register("pfc-sh7786", NULL, 0); } + arch_initcall(plat_pinmux_setup); diff --git a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c index 444bf25c60fa..ace84acc55ea 100644 --- a/trunk/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c +++ b/trunk/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c @@ -7,23 +7,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include #include #include -#include #include -static struct resource shx3_pfc_resources[] = { - [0] = { - .start = 0xffc70000, - .end = 0xffc7001f, - .flags = IORESOURCE_MEM, - }, -}; - -static int __init plat_pinmux_setup(void) +static int __init shx3_pinmux_setup(void) { - return sh_pfc_register("pfc-shx3", shx3_pfc_resources, - ARRAY_SIZE(shx3_pfc_resources)); + return sh_pfc_register("pfc-shx3", NULL, 0); } -arch_initcall(plat_pinmux_setup); +arch_initcall(shx3_pinmux_setup); diff --git a/trunk/arch/tile/kernel/setup.c b/trunk/arch/tile/kernel/setup.c index d1e15f7b59c6..7a5aa1a7864e 100644 --- a/trunk/arch/tile/kernel/setup.c +++ b/trunk/arch/tile/kernel/setup.c @@ -1004,15 +1004,8 @@ void __cpuinit setup_cpu(int boot) #ifdef CONFIG_BLK_DEV_INITRD -/* - * Note that the kernel can potentially support other compression - * techniques than gz, though we don't do so by default. If we ever - * decide to do so we can either look for other filename extensions, - * or just allow a file with this name to be compressed with an - * arbitrary compressor (somewhat counterintuitively). - */ static int __initdata set_initramfs_file; -static char __initdata initramfs_file[128] = "initramfs.cpio.gz"; +static char __initdata initramfs_file[128] = "initramfs"; static int __init setup_initramfs_file(char *str) { @@ -1026,9 +1019,9 @@ static int __init setup_initramfs_file(char *str) early_param("initramfs_file", setup_initramfs_file); /* - * We look for an "initramfs.cpio.gz" file in the hvfs. - * If there is one, we allocate some memory for it and it will be - * unpacked to the initramfs. + * We look for a file called "initramfs" in the hvfs. If there is one, we + * allocate some memory for it and it will be unpacked to the initramfs. + * If it's compressed, the initd code will uncompress it first. */ static void __init load_hv_initrd(void) { @@ -1038,10 +1031,16 @@ static void __init load_hv_initrd(void) fd = hv_fs_findfile((HV_VirtAddr) initramfs_file); if (fd == HV_ENOENT) { - if (set_initramfs_file) + if (set_initramfs_file) { pr_warning("No such hvfs initramfs file '%s'\n", initramfs_file); - return; + return; + } else { + /* Try old backwards-compatible name. */ + fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz"); + if (fd == HV_ENOENT) + return; + } } BUG_ON(fd < 0); stat = hv_fs_fstat(fd); diff --git a/trunk/arch/x86/boot/compressed/Makefile b/trunk/arch/x86/boot/compressed/Makefile index 8a84501acb1b..5ef205c5f37b 100644 --- a/trunk/arch/x86/boot/compressed/Makefile +++ b/trunk/arch/x86/boot/compressed/Makefile @@ -4,7 +4,7 @@ # create a compressed vmlinux image from the original vmlinux # -targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o +targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2 KBUILD_CFLAGS += -fno-strict-aliasing -fPIC @@ -29,7 +29,6 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \ $(obj)/piggy.o $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone -$(obj)/efi_stub_$(BITS).o: KBUILD_CLFAGS += -fshort-wchar -mno-red-zone ifeq ($(CONFIG_EFI_STUB), y) VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o @@ -43,7 +42,7 @@ OBJCOPYFLAGS_vmlinux.bin := -R .comment -S $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) -targets += vmlinux.bin.all vmlinux.relocs +targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs CMD_RELOCS = arch/x86/tools/relocs quiet_cmd_relocs = RELOCS $@ diff --git a/trunk/arch/x86/include/asm/syscall.h b/trunk/arch/x86/include/asm/syscall.h index 1ace47b62592..2e188d68397c 100644 --- a/trunk/arch/x86/include/asm/syscall.h +++ b/trunk/arch/x86/include/asm/syscall.h @@ -29,13 +29,13 @@ extern const unsigned long sys_call_table[]; */ static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { - return regs->orig_ax & __SYSCALL_MASK; + return regs->orig_ax; } static inline void syscall_rollback(struct task_struct *task, struct pt_regs *regs) { - regs->ax = regs->orig_ax & __SYSCALL_MASK; + regs->ax = regs->orig_ax; } static inline long syscall_get_error(struct task_struct *task, diff --git a/trunk/arch/x86/kvm/lapic.c b/trunk/arch/x86/kvm/lapic.c index 02b51dd4e4ad..f77df1c5de6e 100644 --- a/trunk/arch/x86/kvm/lapic.c +++ b/trunk/arch/x86/kvm/lapic.c @@ -1857,7 +1857,7 @@ int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) if (!pv_eoi_enabled(vcpu)) return 0; return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, - addr); + addr, sizeof(u8)); } void kvm_lapic_init(void) diff --git a/trunk/arch/x86/kvm/x86.c b/trunk/arch/x86/kvm/x86.c index f19ac0aca60d..e1721324c271 100644 --- a/trunk/arch/x86/kvm/x86.c +++ b/trunk/arch/x86/kvm/x86.c @@ -1823,7 +1823,8 @@ static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) return 0; } - if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa)) + if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, + sizeof(u32))) return 1; vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); @@ -1952,12 +1953,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) gpa_offset = data & ~(PAGE_MASK | 1); - /* Check that the address is 32-byte aligned. */ - if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1)) - break; - if (kvm_gfn_to_hva_cache_init(vcpu->kvm, - &vcpu->arch.pv_time, data & ~1ULL)) + &vcpu->arch.pv_time, data & ~1ULL, + sizeof(struct pvclock_vcpu_time_info))) vcpu->arch.pv_time_enabled = false; else vcpu->arch.pv_time_enabled = true; @@ -1977,7 +1975,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, - data & KVM_STEAL_VALID_BITS)) + data & KVM_STEAL_VALID_BITS, + sizeof(struct kvm_steal_time))) return 1; vcpu->arch.st.msr_val = data; diff --git a/trunk/drivers/acpi/Kconfig b/trunk/drivers/acpi/Kconfig index 92ed9692c47e..4bf68c8d4797 100644 --- a/trunk/drivers/acpi/Kconfig +++ b/trunk/drivers/acpi/Kconfig @@ -396,7 +396,7 @@ config ACPI_CUSTOM_METHOD config ACPI_BGRT bool "Boottime Graphics Resource Table support" - depends on EFI + depends on EFI && X86 help This driver adds support for exposing the ACPI Boottime Graphics Resource Table, which allows the operating system to obtain diff --git a/trunk/drivers/acpi/acpi_i2c.c b/trunk/drivers/acpi/acpi_i2c.c index 82045e3f5cac..a82c7626aa9b 100644 --- a/trunk/drivers/acpi/acpi_i2c.c +++ b/trunk/drivers/acpi/acpi_i2c.c @@ -90,7 +90,7 @@ void acpi_i2c_register_devices(struct i2c_adapter *adapter) acpi_handle handle; acpi_status status; - handle = ACPI_HANDLE(&adapter->dev); + handle = ACPI_HANDLE(adapter->dev.parent); if (!handle) return; diff --git a/trunk/drivers/acpi/pci_root.c b/trunk/drivers/acpi/pci_root.c index 5ff173066127..6ae5e440436e 100644 --- a/trunk/drivers/acpi/pci_root.c +++ b/trunk/drivers/acpi/pci_root.c @@ -415,7 +415,6 @@ static int acpi_pci_root_add(struct acpi_device *device, struct acpi_pci_root *root; struct acpi_pci_driver *driver; u32 flags, base_flags; - bool is_osc_granted = false; root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL); if (!root) @@ -476,6 +475,30 @@ static int acpi_pci_root_add(struct acpi_device *device, flags = base_flags = OSC_PCI_SEGMENT_GROUPS_SUPPORT; acpi_pci_osc_support(root, flags); + /* + * TBD: Need PCI interface for enumeration/configuration of roots. + */ + + mutex_lock(&acpi_pci_root_lock); + list_add_tail(&root->node, &acpi_pci_roots); + mutex_unlock(&acpi_pci_root_lock); + + /* + * Scan the Root Bridge + * -------------------- + * Must do this prior to any attempt to bind the root device, as the + * PCI namespace does not get created until this call is made (and + * thus the root bridge's pci_dev does not exist). + */ + root->bus = pci_acpi_scan_root(root); + if (!root->bus) { + printk(KERN_ERR PREFIX + "Bus %04x:%02x not present in PCI namespace\n", + root->segment, (unsigned int)root->secondary.start); + result = -ENODEV; + goto out_del_root; + } + /* Indicate support for various _OSC capabilities. */ if (pci_ext_cfg_avail()) flags |= OSC_EXT_PCI_CONFIG_SUPPORT; @@ -494,6 +517,7 @@ static int acpi_pci_root_add(struct acpi_device *device, flags = base_flags; } } + if (!pcie_ports_disabled && (flags & ACPI_PCIE_REQ_SUPPORT) == ACPI_PCIE_REQ_SUPPORT) { flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL @@ -514,54 +538,28 @@ static int acpi_pci_root_add(struct acpi_device *device, status = acpi_pci_osc_control_set(device->handle, &flags, OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); if (ACPI_SUCCESS(status)) { - is_osc_granted = true; dev_info(&device->dev, "ACPI _OSC control (0x%02x) granted\n", flags); + if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) { + /* + * We have ASPM control, but the FADT indicates + * that it's unsupported. Clear it. + */ + pcie_clear_aspm(root->bus); + } } else { - is_osc_granted = false; dev_info(&device->dev, "ACPI _OSC request failed (%s), " "returned control mask: 0x%02x\n", acpi_format_exception(status), flags); + pr_info("ACPI _OSC control for PCIe not granted, " + "disabling ASPM\n"); + pcie_no_aspm(); } } else { dev_info(&device->dev, - "Unable to request _OSC control " - "(_OSC support mask: 0x%02x)\n", flags); - } - - /* - * TBD: Need PCI interface for enumeration/configuration of roots. - */ - - mutex_lock(&acpi_pci_root_lock); - list_add_tail(&root->node, &acpi_pci_roots); - mutex_unlock(&acpi_pci_root_lock); - - /* - * Scan the Root Bridge - * -------------------- - * Must do this prior to any attempt to bind the root device, as the - * PCI namespace does not get created until this call is made (and - * thus the root bridge's pci_dev does not exist). - */ - root->bus = pci_acpi_scan_root(root); - if (!root->bus) { - printk(KERN_ERR PREFIX - "Bus %04x:%02x not present in PCI namespace\n", - root->segment, (unsigned int)root->secondary.start); - result = -ENODEV; - goto out_del_root; - } - - /* ASPM setting */ - if (is_osc_granted) { - if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) - pcie_clear_aspm(root->bus); - } else { - pr_info("ACPI _OSC control for PCIe not granted, " - "disabling ASPM\n"); - pcie_no_aspm(); + "Unable to request _OSC control " + "(_OSC support mask: 0x%02x)\n", flags); } pci_acpi_add_bus_pm_notifier(device, root->bus); diff --git a/trunk/drivers/acpi/processor_idle.c b/trunk/drivers/acpi/processor_idle.c index fc95308e9a11..ee255c60bdac 100644 --- a/trunk/drivers/acpi/processor_idle.c +++ b/trunk/drivers/acpi/processor_idle.c @@ -66,7 +66,8 @@ module_param(latency_factor, uint, 0644); static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); -static struct acpi_processor_cx *acpi_cstate[CPUIDLE_STATE_MAX]; +static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX], + acpi_cstate); static int disabled_by_idle_boot_param(void) { @@ -722,7 +723,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { struct acpi_processor *pr; - struct acpi_processor_cx *cx = acpi_cstate[index]; + struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); pr = __this_cpu_read(processors); @@ -745,7 +746,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev, */ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) { - struct acpi_processor_cx *cx = acpi_cstate[index]; + struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); ACPI_FLUSH_CPU_CACHE(); @@ -775,7 +776,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { struct acpi_processor *pr; - struct acpi_processor_cx *cx = acpi_cstate[index]; + struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); pr = __this_cpu_read(processors); @@ -833,7 +834,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { struct acpi_processor *pr; - struct acpi_processor_cx *cx = acpi_cstate[index]; + struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu); pr = __this_cpu_read(processors); @@ -960,7 +961,7 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr, !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) continue; #endif - acpi_cstate[count] = cx; + per_cpu(acpi_cstate[count], dev->cpu) = cx; count++; if (count == CPUIDLE_STATE_MAX) diff --git a/trunk/drivers/base/power/qos.c b/trunk/drivers/base/power/qos.c index 5f74587ef258..71671c42ef45 100644 --- a/trunk/drivers/base/power/qos.c +++ b/trunk/drivers/base/power/qos.c @@ -46,6 +46,7 @@ #include "power.h" static DEFINE_MUTEX(dev_pm_qos_mtx); +static DEFINE_MUTEX(dev_pm_qos_sysfs_mtx); static BLOCKING_NOTIFIER_HEAD(dev_pm_notifiers); @@ -216,12 +217,17 @@ void dev_pm_qos_constraints_destroy(struct device *dev) struct pm_qos_constraints *c; struct pm_qos_flags *f; - mutex_lock(&dev_pm_qos_mtx); + mutex_lock(&dev_pm_qos_sysfs_mtx); /* * If the device's PM QoS resume latency limit or PM QoS flags have been * exposed to user space, they have to be hidden at this point. */ + pm_qos_sysfs_remove_latency(dev); + pm_qos_sysfs_remove_flags(dev); + + mutex_lock(&dev_pm_qos_mtx); + __dev_pm_qos_hide_latency_limit(dev); __dev_pm_qos_hide_flags(dev); @@ -254,6 +260,8 @@ void dev_pm_qos_constraints_destroy(struct device *dev) out: mutex_unlock(&dev_pm_qos_mtx); + + mutex_unlock(&dev_pm_qos_sysfs_mtx); } /** @@ -558,6 +566,14 @@ static void __dev_pm_qos_drop_user_request(struct device *dev, kfree(req); } +static void dev_pm_qos_drop_user_request(struct device *dev, + enum dev_pm_qos_req_type type) +{ + mutex_lock(&dev_pm_qos_mtx); + __dev_pm_qos_drop_user_request(dev, type); + mutex_unlock(&dev_pm_qos_mtx); +} + /** * dev_pm_qos_expose_latency_limit - Expose PM QoS latency limit to user space. * @dev: Device whose PM QoS latency limit is to be exposed to user space. @@ -581,6 +597,8 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value) return ret; } + mutex_lock(&dev_pm_qos_sysfs_mtx); + mutex_lock(&dev_pm_qos_mtx); if (IS_ERR_OR_NULL(dev->power.qos)) @@ -591,26 +609,27 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value) if (ret < 0) { __dev_pm_qos_remove_request(req); kfree(req); + mutex_unlock(&dev_pm_qos_mtx); goto out; } - dev->power.qos->latency_req = req; + + mutex_unlock(&dev_pm_qos_mtx); + ret = pm_qos_sysfs_add_latency(dev); if (ret) - __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY); + dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY); out: - mutex_unlock(&dev_pm_qos_mtx); + mutex_unlock(&dev_pm_qos_sysfs_mtx); return ret; } EXPORT_SYMBOL_GPL(dev_pm_qos_expose_latency_limit); static void __dev_pm_qos_hide_latency_limit(struct device *dev) { - if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req) { - pm_qos_sysfs_remove_latency(dev); + if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req) __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY); - } } /** @@ -619,9 +638,15 @@ static void __dev_pm_qos_hide_latency_limit(struct device *dev) */ void dev_pm_qos_hide_latency_limit(struct device *dev) { + mutex_lock(&dev_pm_qos_sysfs_mtx); + + pm_qos_sysfs_remove_latency(dev); + mutex_lock(&dev_pm_qos_mtx); __dev_pm_qos_hide_latency_limit(dev); mutex_unlock(&dev_pm_qos_mtx); + + mutex_unlock(&dev_pm_qos_sysfs_mtx); } EXPORT_SYMBOL_GPL(dev_pm_qos_hide_latency_limit); @@ -649,6 +674,8 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val) } pm_runtime_get_sync(dev); + mutex_lock(&dev_pm_qos_sysfs_mtx); + mutex_lock(&dev_pm_qos_mtx); if (IS_ERR_OR_NULL(dev->power.qos)) @@ -659,16 +686,19 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val) if (ret < 0) { __dev_pm_qos_remove_request(req); kfree(req); + mutex_unlock(&dev_pm_qos_mtx); goto out; } - dev->power.qos->flags_req = req; + + mutex_unlock(&dev_pm_qos_mtx); + ret = pm_qos_sysfs_add_flags(dev); if (ret) - __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS); + dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS); out: - mutex_unlock(&dev_pm_qos_mtx); + mutex_unlock(&dev_pm_qos_sysfs_mtx); pm_runtime_put(dev); return ret; } @@ -676,10 +706,8 @@ EXPORT_SYMBOL_GPL(dev_pm_qos_expose_flags); static void __dev_pm_qos_hide_flags(struct device *dev) { - if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req) { - pm_qos_sysfs_remove_flags(dev); + if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req) __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS); - } } /** @@ -689,9 +717,15 @@ static void __dev_pm_qos_hide_flags(struct device *dev) void dev_pm_qos_hide_flags(struct device *dev) { pm_runtime_get_sync(dev); + mutex_lock(&dev_pm_qos_sysfs_mtx); + + pm_qos_sysfs_remove_flags(dev); + mutex_lock(&dev_pm_qos_mtx); __dev_pm_qos_hide_flags(dev); mutex_unlock(&dev_pm_qos_mtx); + + mutex_unlock(&dev_pm_qos_sysfs_mtx); pm_runtime_put(dev); } EXPORT_SYMBOL_GPL(dev_pm_qos_hide_flags); diff --git a/trunk/drivers/base/regmap/regcache-rbtree.c b/trunk/drivers/base/regmap/regcache-rbtree.c index e6732cf7c06e..79f4fca9877a 100644 --- a/trunk/drivers/base/regmap/regcache-rbtree.c +++ b/trunk/drivers/base/regmap/regcache-rbtree.c @@ -398,7 +398,7 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min, base = 0; if (max < rbnode->base_reg + rbnode->blklen) - end = rbnode->base_reg + rbnode->blklen - max; + end = max - rbnode->base_reg + 1; else end = rbnode->blklen; diff --git a/trunk/drivers/base/regmap/regmap.c b/trunk/drivers/base/regmap/regmap.c index 3d2367501fd0..d34adef1e63e 100644 --- a/trunk/drivers/base/regmap/regmap.c +++ b/trunk/drivers/base/regmap/regmap.c @@ -710,12 +710,12 @@ struct regmap *regmap_init(struct device *dev, } } + regmap_debugfs_init(map, config->name); + ret = regcache_init(map, config); if (ret != 0) goto err_range; - regmap_debugfs_init(map, config->name); - /* Add a devres resource for dev_get_regmap() */ m = devres_alloc(dev_get_regmap_release, sizeof(*m), GFP_KERNEL); if (!m) { @@ -943,8 +943,7 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg, unsigned int ival; int val_bytes = map->format.val_bytes; for (i = 0; i < val_len / val_bytes; i++) { - memcpy(map->work_buf, val + (i * val_bytes), val_bytes); - ival = map->format.parse_val(map->work_buf); + ival = map->format.parse_val(val + (i * val_bytes)); ret = regcache_write(map, reg + (i * map->reg_stride), ival); if (ret) { @@ -1036,6 +1035,8 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg, kfree(async->work_buf); kfree(async); } + + return ret; } trace_regmap_hw_write_start(map->dev, reg, diff --git a/trunk/drivers/block/aoe/aoecmd.c b/trunk/drivers/block/aoe/aoecmd.c index 25ef5c014fca..92b6d7c51e39 100644 --- a/trunk/drivers/block/aoe/aoecmd.c +++ b/trunk/drivers/block/aoe/aoecmd.c @@ -51,8 +51,9 @@ new_skb(ulong len) { struct sk_buff *skb; - skb = alloc_skb(len, GFP_ATOMIC); + skb = alloc_skb(len + MAX_HEADER, GFP_ATOMIC); if (skb) { + skb_reserve(skb, MAX_HEADER); skb_reset_mac_header(skb); skb_reset_network_header(skb); skb->protocol = __constant_htons(ETH_P_AOE); diff --git a/trunk/drivers/block/loop.c b/trunk/drivers/block/loop.c index fe5f6403417f..2c127f9c3f3b 100644 --- a/trunk/drivers/block/loop.c +++ b/trunk/drivers/block/loop.c @@ -922,6 +922,11 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, lo->lo_flags |= LO_FLAGS_PARTSCAN; if (lo->lo_flags & LO_FLAGS_PARTSCAN) ioctl_by_bdev(bdev, BLKRRPART, 0); + + /* Grab the block_device to prevent its destruction after we + * put /dev/loopXX inode. Later in loop_clr_fd() we bdput(bdev). + */ + bdgrab(bdev); return 0; out_clr: @@ -1031,8 +1036,10 @@ static int loop_clr_fd(struct loop_device *lo) memset(lo->lo_encrypt_key, 0, LO_KEY_SIZE); memset(lo->lo_crypt_name, 0, LO_NAME_SIZE); memset(lo->lo_file_name, 0, LO_NAME_SIZE); - if (bdev) + if (bdev) { + bdput(bdev); invalidate_bdev(bdev); + } set_capacity(lo->lo_disk, 0); loop_sysfs_exit(lo); if (bdev) { diff --git a/trunk/drivers/char/hw_random/core.c b/trunk/drivers/char/hw_random/core.c index 69ae5972713c..a0f7724852eb 100644 --- a/trunk/drivers/char/hw_random/core.c +++ b/trunk/drivers/char/hw_random/core.c @@ -380,6 +380,15 @@ void hwrng_unregister(struct hwrng *rng) } EXPORT_SYMBOL_GPL(hwrng_unregister); +static void __exit hwrng_exit(void) +{ + mutex_lock(&rng_mutex); + BUG_ON(current_rng); + kfree(rng_buffer); + mutex_unlock(&rng_mutex); +} + +module_exit(hwrng_exit); MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver"); MODULE_LICENSE("GPL"); diff --git a/trunk/drivers/char/virtio_console.c b/trunk/drivers/char/virtio_console.c index e905d5f53051..ce5f3fc25d6d 100644 --- a/trunk/drivers/char/virtio_console.c +++ b/trunk/drivers/char/virtio_console.c @@ -149,7 +149,8 @@ struct ports_device { spinlock_t ports_lock; /* To protect the vq operations for the control channel */ - spinlock_t cvq_lock; + spinlock_t c_ivq_lock; + spinlock_t c_ovq_lock; /* The current config space is stored here */ struct virtio_console_config config; @@ -569,11 +570,14 @@ static ssize_t __send_control_msg(struct ports_device *portdev, u32 port_id, vq = portdev->c_ovq; sg_init_one(sg, &cpkt, sizeof(cpkt)); + + spin_lock(&portdev->c_ovq_lock); if (virtqueue_add_buf(vq, sg, 1, 0, &cpkt, GFP_ATOMIC) == 0) { virtqueue_kick(vq); while (!virtqueue_get_buf(vq, &len)) cpu_relax(); } + spin_unlock(&portdev->c_ovq_lock); return 0; } @@ -1436,7 +1440,7 @@ static int add_port(struct ports_device *portdev, u32 id) * rproc_serial does not want the console port, only * the generic port implementation. */ - port->host_connected = port->guest_connected = true; + port->host_connected = true; else if (!use_multiport(port->portdev)) { /* * If we're not using multiport support, @@ -1709,23 +1713,23 @@ static void control_work_handler(struct work_struct *work) portdev = container_of(work, struct ports_device, control_work); vq = portdev->c_ivq; - spin_lock(&portdev->cvq_lock); + spin_lock(&portdev->c_ivq_lock); while ((buf = virtqueue_get_buf(vq, &len))) { - spin_unlock(&portdev->cvq_lock); + spin_unlock(&portdev->c_ivq_lock); buf->len = len; buf->offset = 0; handle_control_message(portdev, buf); - spin_lock(&portdev->cvq_lock); + spin_lock(&portdev->c_ivq_lock); if (add_inbuf(portdev->c_ivq, buf) < 0) { dev_warn(&portdev->vdev->dev, "Error adding buffer to queue\n"); free_buf(buf, false); } } - spin_unlock(&portdev->cvq_lock); + spin_unlock(&portdev->c_ivq_lock); } static void out_intr(struct virtqueue *vq) @@ -1752,13 +1756,23 @@ static void in_intr(struct virtqueue *vq) port->inbuf = get_inbuf(port); /* - * Don't queue up data when port is closed. This condition + * Normally the port should not accept data when the port is + * closed. For generic serial ports, the host won't (shouldn't) + * send data till the guest is connected. But this condition * can be reached when a console port is not yet connected (no - * tty is spawned) and the host sends out data to console - * ports. For generic serial ports, the host won't - * (shouldn't) send data till the guest is connected. + * tty is spawned) and the other side sends out data over the + * vring, or when a remote devices start sending data before + * the ports are opened. + * + * A generic serial port will discard data if not connected, + * while console ports and rproc-serial ports accepts data at + * any time. rproc-serial is initiated with guest_connected to + * false because port_fops_open expects this. Console ports are + * hooked up with an HVC console and is initialized with + * guest_connected to true. */ - if (!port->guest_connected) + + if (!port->guest_connected && !is_rproc_serial(port->portdev->vdev)) discard_port_data(port); spin_unlock_irqrestore(&port->inbuf_lock, flags); @@ -1986,10 +2000,12 @@ static int virtcons_probe(struct virtio_device *vdev) if (multiport) { unsigned int nr_added_bufs; - spin_lock_init(&portdev->cvq_lock); + spin_lock_init(&portdev->c_ivq_lock); + spin_lock_init(&portdev->c_ovq_lock); INIT_WORK(&portdev->control_work, &control_work_handler); - nr_added_bufs = fill_queue(portdev->c_ivq, &portdev->cvq_lock); + nr_added_bufs = fill_queue(portdev->c_ivq, + &portdev->c_ivq_lock); if (!nr_added_bufs) { dev_err(&vdev->dev, "Error allocating buffers for control queue\n"); @@ -2140,7 +2156,7 @@ static int virtcons_restore(struct virtio_device *vdev) return ret; if (use_multiport(portdev)) - fill_queue(portdev->c_ivq, &portdev->cvq_lock); + fill_queue(portdev->c_ivq, &portdev->c_ivq_lock); list_for_each_entry(port, &portdev->ports, list) { port->in_vq = portdev->in_vqs[port->id]; diff --git a/trunk/drivers/clk/tegra/clk-tegra20.c b/trunk/drivers/clk/tegra/clk-tegra20.c index 1e2de7305362..f873dcefe0de 100644 --- a/trunk/drivers/clk/tegra/clk-tegra20.c +++ b/trunk/drivers/clk/tegra/clk-tegra20.c @@ -703,7 +703,7 @@ static void tegra20_pll_init(void) clks[pll_a_out0] = clk; /* PLLE */ - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 0, 100000000, &pll_e_params, 0, pll_e_freq_table, NULL); clk_register_clkdev(clk, "pll_e", NULL); diff --git a/trunk/drivers/clocksource/Kconfig b/trunk/drivers/clocksource/Kconfig index 3167fda9bbb3..e507ab7df60b 100644 --- a/trunk/drivers/clocksource/Kconfig +++ b/trunk/drivers/clocksource/Kconfig @@ -31,9 +31,6 @@ config SUNXI_TIMER config VT8500_TIMER bool -config CADENCE_TTC_TIMER - bool - config CLKSRC_NOMADIK_MTU bool depends on (ARCH_NOMADIK || ARCH_U8500) diff --git a/trunk/drivers/clocksource/Makefile b/trunk/drivers/clocksource/Makefile index e74c8ce26bf0..4d8283aec5b5 100644 --- a/trunk/drivers/clocksource/Makefile +++ b/trunk/drivers/clocksource/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o -obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o diff --git a/trunk/drivers/clocksource/bcm2835_timer.c b/trunk/drivers/clocksource/bcm2835_timer.c index 766611d29945..50c68fef944b 100644 --- a/trunk/drivers/clocksource/bcm2835_timer.c +++ b/trunk/drivers/clocksource/bcm2835_timer.c @@ -95,13 +95,23 @@ static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id) } } -static void __init bcm2835_timer_init(struct device_node *node) +static struct of_device_id bcm2835_time_match[] __initconst = { + { .compatible = "brcm,bcm2835-system-timer" }, + {} +}; + +static void __init bcm2835_timer_init(void) { + struct device_node *node; void __iomem *base; u32 freq; int irq; struct bcm2835_timer *timer; + node = of_find_matching_node(NULL, bcm2835_time_match); + if (!node) + panic("No bcm2835 timer node"); + base = of_iomap(node, 0); if (!base) panic("Can't remap registers"); diff --git a/trunk/drivers/clocksource/cadence_ttc_timer.c b/trunk/drivers/clocksource/cadence_ttc_timer.c deleted file mode 100644 index 685bc60e210a..000000000000 --- a/trunk/drivers/clocksource/cadence_ttc_timer.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * This file contains driver for the Cadence Triple Timer Counter Rev 06 - * - * Copyright (C) 2011-2013 Xilinx - * - * based on arch/mips/kernel/time.c timer driver - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - - * The input frequency to the timer module in silicon is configurable and - * obtained from device tree. The pre-scaler of 32 is used. - */ - -/* - * Timer Register Offset Definitions of Timer 1, Increment base address by 4 - * and use same offsets for Timer 2 - */ -#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ - -#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 - -/* - * Setup the timers to use pre-scaling, using a fixed value for now that will - * work across most input frequency, but it may need to be more dynamic - */ -#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ -#define PRESCALE 2048 /* The exponent must match this */ -#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) -#define CLK_CNTRL_PRESCALE_EN 1 -#define CNT_CNTRL_RESET (1 << 4) - -/** - * struct ttc_timer - This definition defines local timer structure - * - * @base_addr: Base address of timer - * @clk: Associated clock source - * @clk_rate_change_nb Notifier block for clock rate changes - */ -struct ttc_timer { - void __iomem *base_addr; - struct clk *clk; - struct notifier_block clk_rate_change_nb; -}; - -#define to_ttc_timer(x) \ - container_of(x, struct ttc_timer, clk_rate_change_nb) - -struct ttc_timer_clocksource { - struct ttc_timer ttc; - struct clocksource cs; -}; - -#define to_ttc_timer_clksrc(x) \ - container_of(x, struct ttc_timer_clocksource, cs) - -struct ttc_timer_clockevent { - struct ttc_timer ttc; - struct clock_event_device ce; -}; - -#define to_ttc_timer_clkevent(x) \ - container_of(x, struct ttc_timer_clockevent, ce) - -/** - * ttc_set_interval - Set the timer interval value - * - * @timer: Pointer to the timer instance - * @cycles: Timer interval ticks - **/ -static void ttc_set_interval(struct ttc_timer *timer, - unsigned long cycles) -{ - u32 ctrl_reg; - - /* Disable the counter, set the counter value and re-enable counter */ - ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); - ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); - - __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); - - /* - * Reset the counter (0x10) so that it starts from 0, one-shot - * mode makes this needed for timing to be right. - */ - ctrl_reg |= CNT_CNTRL_RESET; - ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); -} - -/** - * ttc_clock_event_interrupt - Clock event timer interrupt handler - * - * @irq: IRQ number of the Timer - * @dev_id: void pointer to the ttc_timer instance - * - * returns: Always IRQ_HANDLED - success - **/ -static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) -{ - struct ttc_timer_clockevent *ttce = dev_id; - struct ttc_timer *timer = &ttce->ttc; - - /* Acknowledge the interrupt and call event handler */ - __raw_readl(timer->base_addr + TTC_ISR_OFFSET); - - ttce->ce.event_handler(&ttce->ce); - - return IRQ_HANDLED; -} - -/** - * __ttc_clocksource_read - Reads the timer counter register - * - * returns: Current timer counter register value - **/ -static cycle_t __ttc_clocksource_read(struct clocksource *cs) -{ - struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; - - return (cycle_t)__raw_readl(timer->base_addr + - TTC_COUNT_VAL_OFFSET); -} - -/** - * ttc_set_next_event - Sets the time interval for next event - * - * @cycles: Timer interval ticks - * @evt: Address of clock event instance - * - * returns: Always 0 - success - **/ -static int ttc_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); - struct ttc_timer *timer = &ttce->ttc; - - ttc_set_interval(timer, cycles); - return 0; -} - -/** - * ttc_set_mode - Sets the mode of timer - * - * @mode: Mode to be set - * @evt: Address of clock event instance - **/ -static void ttc_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); - struct ttc_timer *timer = &ttce->ttc; - u32 ctrl_reg; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - ttc_set_interval(timer, - DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), - PRESCALE * HZ)); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - ctrl_reg = __raw_readl(timer->base_addr + - TTC_CNT_CNTRL_OFFSET); - ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + TTC_CNT_CNTRL_OFFSET); - break; - case CLOCK_EVT_MODE_RESUME: - ctrl_reg = __raw_readl(timer->base_addr + - TTC_CNT_CNTRL_OFFSET); - ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + TTC_CNT_CNTRL_OFFSET); - break; - } -} - -static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct ttc_timer *ttc = to_ttc_timer(nb); - struct ttc_timer_clocksource *ttccs = container_of(ttc, - struct ttc_timer_clocksource, ttc); - - switch (event) { - case POST_RATE_CHANGE: - /* - * Do whatever is necessary to maintain a proper time base - * - * I cannot find a way to adjust the currently used clocksource - * to the new frequency. __clocksource_updatefreq_hz() sounds - * good, but does not work. Not sure what's that missing. - * - * This approach works, but triggers two clocksource switches. - * The first after unregister to clocksource jiffies. And - * another one after the register to the newly registered timer. - * - * Alternatively we could 'waste' another HW timer to ping pong - * between clock sources. That would also use one register and - * one unregister call, but only trigger one clocksource switch - * for the cost of another HW timer used by the OS. - */ - clocksource_unregister(&ttccs->cs); - clocksource_register_hz(&ttccs->cs, - ndata->new_rate / PRESCALE); - /* fall through */ - case PRE_RATE_CHANGE: - case ABORT_RATE_CHANGE: - default: - return NOTIFY_DONE; - } -} - -static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) -{ - struct ttc_timer_clocksource *ttccs; - int err; - - ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); - if (WARN_ON(!ttccs)) - return; - - ttccs->ttc.clk = clk; - - err = clk_prepare_enable(ttccs->ttc.clk); - if (WARN_ON(err)) { - kfree(ttccs); - return; - } - - ttccs->ttc.clk_rate_change_nb.notifier_call = - ttc_rate_change_clocksource_cb; - ttccs->ttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttccs->ttc.clk, - &ttccs->ttc.clk_rate_change_nb)) - pr_warn("Unable to register clock notifier.\n"); - - ttccs->ttc.base_addr = base; - ttccs->cs.name = "ttc_clocksource"; - ttccs->cs.rating = 200; - ttccs->cs.read = __ttc_clocksource_read; - ttccs->cs.mask = CLOCKSOURCE_MASK(16); - ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; - - /* - * Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - * it by 32 also. Let it start running now. - */ - __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); - __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); - __raw_writel(CNT_CNTRL_RESET, - ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); - - err = clocksource_register_hz(&ttccs->cs, - clk_get_rate(ttccs->ttc.clk) / PRESCALE); - if (WARN_ON(err)) { - kfree(ttccs); - return; - } -} - -static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct ttc_timer *ttc = to_ttc_timer(nb); - struct ttc_timer_clockevent *ttcce = container_of(ttc, - struct ttc_timer_clockevent, ttc); - - switch (event) { - case POST_RATE_CHANGE: - { - unsigned long flags; - - /* - * clockevents_update_freq should be called with IRQ disabled on - * the CPU the timer provides events for. The timer we use is - * common to both CPUs, not sure if we need to run on both - * cores. - */ - local_irq_save(flags); - clockevents_update_freq(&ttcce->ce, - ndata->new_rate / PRESCALE); - local_irq_restore(flags); - - /* fall through */ - } - case PRE_RATE_CHANGE: - case ABORT_RATE_CHANGE: - default: - return NOTIFY_DONE; - } -} - -static void __init ttc_setup_clockevent(struct clk *clk, - void __iomem *base, u32 irq) -{ - struct ttc_timer_clockevent *ttcce; - int err; - - ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); - if (WARN_ON(!ttcce)) - return; - - ttcce->ttc.clk = clk; - - err = clk_prepare_enable(ttcce->ttc.clk); - if (WARN_ON(err)) { - kfree(ttcce); - return; - } - - ttcce->ttc.clk_rate_change_nb.notifier_call = - ttc_rate_change_clockevent_cb; - ttcce->ttc.clk_rate_change_nb.next = NULL; - if (clk_notifier_register(ttcce->ttc.clk, - &ttcce->ttc.clk_rate_change_nb)) - pr_warn("Unable to register clock notifier.\n"); - - ttcce->ttc.base_addr = base; - ttcce->ce.name = "ttc_clockevent"; - ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - ttcce->ce.set_next_event = ttc_set_next_event; - ttcce->ce.set_mode = ttc_set_mode; - ttcce->ce.rating = 200; - ttcce->ce.irq = irq; - ttcce->ce.cpumask = cpu_possible_mask; - - /* - * Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); - __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, - ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); - __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); - - err = request_irq(irq, ttc_clock_event_interrupt, - IRQF_DISABLED | IRQF_TIMER, - ttcce->ce.name, ttcce); - if (WARN_ON(err)) { - kfree(ttcce); - return; - } - - clockevents_config_and_register(&ttcce->ce, - clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); -} - -/** - * ttc_timer_init - Initialize the timer - * - * Initializes the timer hardware and register the clock source and clock event - * timers with Linux kernal timer framework - */ -static void __init ttc_timer_init(struct device_node *timer) -{ - unsigned int irq; - void __iomem *timer_baseaddr; - struct clk *clk; - static int initialized; - - if (initialized) - return; - - initialized = 1; - - /* - * Get the 1st Triple Timer Counter (TTC) block from the device tree - * and use it. Note that the event timer uses the interrupt and it's the - * 2nd TTC hence the irq_of_parse_and_map(,1) - */ - timer_baseaddr = of_iomap(timer, 0); - if (!timer_baseaddr) { - pr_err("ERROR: invalid timer base address\n"); - BUG(); - } - - irq = irq_of_parse_and_map(timer, 1); - if (irq <= 0) { - pr_err("ERROR: invalid interrupt number\n"); - BUG(); - } - - clk = of_clk_get_by_name(timer, "cpu_1x"); - if (IS_ERR(clk)) { - pr_err("ERROR: timer input clock not found\n"); - BUG(); - } - - ttc_setup_clocksource(clk, timer_baseaddr); - ttc_setup_clockevent(clk, timer_baseaddr + 4, irq); - - pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); -} - -CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); diff --git a/trunk/drivers/clocksource/clksrc-of.c b/trunk/drivers/clocksource/clksrc-of.c index 37f5325bec95..bdabdaa8d00f 100644 --- a/trunk/drivers/clocksource/clksrc-of.c +++ b/trunk/drivers/clocksource/clksrc-of.c @@ -16,7 +16,6 @@ #include #include -#include extern struct of_device_id __clksrc_of_table[]; @@ -27,10 +26,10 @@ void __init clocksource_of_init(void) { struct device_node *np; const struct of_device_id *match; - clocksource_of_init_fn init_func; + void (*init_func)(void); for_each_matching_node_and_match(np, __clksrc_of_table, &match) { init_func = match->data; - init_func(np); + init_func(); } } diff --git a/trunk/drivers/clocksource/tegra20_timer.c b/trunk/drivers/clocksource/tegra20_timer.c index 2e4d8a666c36..0bde03feb095 100644 --- a/trunk/drivers/clocksource/tegra20_timer.c +++ b/trunk/drivers/clocksource/tegra20_timer.c @@ -154,12 +154,29 @@ static struct irqaction tegra_timer_irq = { .dev_id = &tegra_clockevent, }; -static void __init tegra20_init_timer(struct device_node *np) +static const struct of_device_id timer_match[] __initconst = { + { .compatible = "nvidia,tegra20-timer" }, + {} +}; + +static const struct of_device_id rtc_match[] __initconst = { + { .compatible = "nvidia,tegra20-rtc" }, + {} +}; + +static void __init tegra20_init_timer(void) { + struct device_node *np; struct clk *clk; unsigned long rate; int ret; + np = of_find_matching_node(NULL, timer_match); + if (!np) { + pr_err("Failed to find timer DT node\n"); + BUG(); + } + timer_reg_base = of_iomap(np, 0); if (!timer_reg_base) { pr_err("Can't map timer registers\n"); @@ -183,6 +200,30 @@ static void __init tegra20_init_timer(struct device_node *np) of_node_put(np); + np = of_find_matching_node(NULL, rtc_match); + if (!np) { + pr_err("Failed to find RTC DT node\n"); + BUG(); + } + + rtc_base = of_iomap(np, 0); + if (!rtc_base) { + pr_err("Can't map RTC registers"); + BUG(); + } + + /* + * rtc registers are used by read_persistent_clock, keep the rtc clock + * enabled + */ + clk = clk_get_sys("rtc-tegra", NULL); + if (IS_ERR(clk)) + pr_warn("Unable to get rtc-tegra clock\n"); + else + clk_prepare_enable(clk); + + of_node_put(np); + switch (rate) { case 12000000: timer_writel(0x000b, TIMERUS_USEC_CFG); @@ -218,34 +259,12 @@ static void __init tegra20_init_timer(struct device_node *np) tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_config_and_register(&tegra_clockevent, 1000000, 0x1, 0x1fffffff); -} -CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); - -static void __init tegra20_init_rtc(struct device_node *np) -{ - struct clk *clk; - - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers"); - BUG(); - } - - /* - * rtc registers are used by read_persistent_clock, keep the rtc clock - * enabled - */ - clk = clk_get_sys("rtc-tegra", NULL); - if (IS_ERR(clk)) - pr_warn("Unable to get rtc-tegra clock\n"); - else - clk_prepare_enable(clk); - - of_node_put(np); - +#ifdef CONFIG_HAVE_ARM_TWD + twd_local_timer_of_register(); +#endif register_persistent_clock(NULL, tegra_read_persistent_clock); } -CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer); #ifdef CONFIG_PM static u32 usec_config; diff --git a/trunk/drivers/clocksource/vt8500_timer.c b/trunk/drivers/clocksource/vt8500_timer.c index 64f553f04fa4..8efc86b5b5dd 100644 --- a/trunk/drivers/clocksource/vt8500_timer.c +++ b/trunk/drivers/clocksource/vt8500_timer.c @@ -129,10 +129,22 @@ static struct irqaction irq = { .dev_id = &clockevent, }; -static void __init vt8500_timer_init(struct device_node *np) +static struct of_device_id vt8500_timer_ids[] = { + { .compatible = "via,vt8500-timer" }, + { } +}; + +static void __init vt8500_timer_init(void) { + struct device_node *np; int timer_irq; + np = of_find_matching_node(NULL, vt8500_timer_ids); + if (!np) { + pr_err("%s: Timer description missing from Device Tree\n", + __func__); + return; + } regbase = of_iomap(np, 0); if (!regbase) { pr_err("%s: Missing iobase description in Device Tree\n", @@ -165,4 +177,4 @@ static void __init vt8500_timer_init(struct device_node *np) 4, 0xf0000000); } -CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init); +CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init) diff --git a/trunk/drivers/cpufreq/cpufreq-cpu0.c b/trunk/drivers/cpufreq/cpufreq-cpu0.c index 4e5b7fb8927c..37d23a0f8c56 100644 --- a/trunk/drivers/cpufreq/cpufreq-cpu0.c +++ b/trunk/drivers/cpufreq/cpufreq-cpu0.c @@ -178,10 +178,16 @@ static struct cpufreq_driver cpu0_cpufreq_driver = { static int cpu0_cpufreq_probe(struct platform_device *pdev) { - struct device_node *np; + struct device_node *np, *parent; int ret; - for_each_child_of_node(of_find_node_by_path("/cpus"), np) { + parent = of_find_node_by_path("/cpus"); + if (!parent) { + pr_err("failed to find OF /cpus\n"); + return -ENOENT; + } + + for_each_child_of_node(parent, np) { if (of_get_property(np, "operating-points", NULL)) break; } diff --git a/trunk/drivers/cpufreq/cpufreq_governor.h b/trunk/drivers/cpufreq/cpufreq_governor.h index 46bde01eee62..cc4bd2f6838a 100644 --- a/trunk/drivers/cpufreq/cpufreq_governor.h +++ b/trunk/drivers/cpufreq/cpufreq_governor.h @@ -14,8 +14,8 @@ * published by the Free Software Foundation. */ -#ifndef _CPUFREQ_GOVERNER_H -#define _CPUFREQ_GOVERNER_H +#ifndef _CPUFREQ_GOVERNOR_H +#define _CPUFREQ_GOVERNOR_H #include #include @@ -175,4 +175,4 @@ bool need_load_eval(struct cpu_dbs_common_info *cdbs, unsigned int sampling_rate); int cpufreq_governor_dbs(struct dbs_data *dbs_data, struct cpufreq_policy *policy, unsigned int event); -#endif /* _CPUFREQ_GOVERNER_H */ +#endif /* _CPUFREQ_GOVERNOR_H */ diff --git a/trunk/drivers/dma/Kconfig b/trunk/drivers/dma/Kconfig index 80b69971cf28..aeaea32bcfda 100644 --- a/trunk/drivers/dma/Kconfig +++ b/trunk/drivers/dma/Kconfig @@ -83,6 +83,7 @@ config INTEL_IOP_ADMA config DW_DMAC tristate "Synopsys DesignWare AHB DMA support" + depends on GENERIC_HARDIRQS select DMA_ENGINE default y if CPU_AT32AP7000 help diff --git a/trunk/drivers/eisa/pci_eisa.c b/trunk/drivers/eisa/pci_eisa.c index cdae207028a7..6c3fca97d346 100644 --- a/trunk/drivers/eisa/pci_eisa.c +++ b/trunk/drivers/eisa/pci_eisa.c @@ -19,10 +19,10 @@ /* There is only *one* pci_eisa device per machine, right ? */ static struct eisa_root_device pci_eisa_root; -static int __init pci_eisa_init(struct pci_dev *pdev, - const struct pci_device_id *ent) +static int __init pci_eisa_init(struct pci_dev *pdev) { - int rc; + int rc, i; + struct resource *res, *bus_res = NULL; if ((rc = pci_enable_device (pdev))) { printk (KERN_ERR "pci_eisa : Could not enable device %s\n", @@ -30,9 +30,30 @@ static int __init pci_eisa_init(struct pci_dev *pdev, return rc; } + /* + * The Intel 82375 PCI-EISA bridge is a subtractive-decode PCI + * device, so the resources available on EISA are the same as those + * available on the 82375 bus. This works the same as a PCI-PCI + * bridge in subtractive-decode mode (see pci_read_bridge_bases()). + * We assume other PCI-EISA bridges are similar. + * + * eisa_root_register() can only deal with a single io port resource, + * so we use the first valid io port resource. + */ + pci_bus_for_each_resource(pdev->bus, res, i) + if (res && (res->flags & IORESOURCE_IO)) { + bus_res = res; + break; + } + + if (!bus_res) { + dev_err(&pdev->dev, "No resources available\n"); + return -1; + } + pci_eisa_root.dev = &pdev->dev; - pci_eisa_root.res = pdev->bus->resource[0]; - pci_eisa_root.bus_base_addr = pdev->bus->resource[0]->start; + pci_eisa_root.res = bus_res; + pci_eisa_root.bus_base_addr = bus_res->start; pci_eisa_root.slots = EISA_MAX_SLOTS; pci_eisa_root.dma_mask = pdev->dma_mask; dev_set_drvdata(pci_eisa_root.dev, &pci_eisa_root); @@ -45,22 +66,26 @@ static int __init pci_eisa_init(struct pci_dev *pdev, return 0; } -static struct pci_device_id pci_eisa_pci_tbl[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_CLASS_BRIDGE_EISA << 8, 0xffff00, 0 }, - { 0, } -}; +/* + * We have to call pci_eisa_init_early() before pnpacpi_init()/isapnp_init(). + * Otherwise pnp resource will get enabled early and could prevent eisa + * to be initialized. + * Also need to make sure pci_eisa_init_early() is called after + * x86/pci_subsys_init(). + * So need to use subsys_initcall_sync with it. + */ +static int __init pci_eisa_init_early(void) +{ + struct pci_dev *dev = NULL; + int ret; -static struct pci_driver __refdata pci_eisa_driver = { - .name = "pci_eisa", - .id_table = pci_eisa_pci_tbl, - .probe = pci_eisa_init, -}; + for_each_pci_dev(dev) + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_EISA) { + ret = pci_eisa_init(dev); + if (ret) + return ret; + } -static int __init pci_eisa_init_module (void) -{ - return pci_register_driver (&pci_eisa_driver); + return 0; } - -device_initcall(pci_eisa_init_module); -MODULE_DEVICE_TABLE(pci, pci_eisa_pci_tbl); +subsys_initcall_sync(pci_eisa_init_early); diff --git a/trunk/drivers/gpio/Kconfig b/trunk/drivers/gpio/Kconfig index d766e3cbef18..93aaadf99f28 100644 --- a/trunk/drivers/gpio/Kconfig +++ b/trunk/drivers/gpio/Kconfig @@ -204,12 +204,6 @@ config GPIO_PXA help Say yes here to support the PXA GPIO device -config GPIO_RCAR - tristate "Renesas R-Car GPIO" - depends on ARM - help - Say yes here to support GPIO on Renesas R-Car SoCs. - config GPIO_SPEAR_SPICS bool "ST SPEAr13xx SPI Chip Select as GPIO support" depends on PLAT_SPEAR diff --git a/trunk/drivers/gpio/Makefile b/trunk/drivers/gpio/Makefile index b41c74d45287..22e07bc9fcb5 100644 --- a/trunk/drivers/gpio/Makefile +++ b/trunk/drivers/gpio/Makefile @@ -57,7 +57,6 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o -obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o diff --git a/trunk/drivers/gpio/gpio-ich.c b/trunk/drivers/gpio/gpio-ich.c index f9dbd503fc40..de3c317bd3e2 100644 --- a/trunk/drivers/gpio/gpio-ich.c +++ b/trunk/drivers/gpio/gpio-ich.c @@ -214,7 +214,7 @@ static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) * If it can't be trusted, assume that the pin can be used as a GPIO. */ if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f))) - return 1; + return 0; return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; } diff --git a/trunk/drivers/gpio/gpio-msm-v2.c b/trunk/drivers/gpio/gpio-msm-v2.c index dd2eddeb1e0c..55a7e7769af6 100644 --- a/trunk/drivers/gpio/gpio-msm-v2.c +++ b/trunk/drivers/gpio/gpio-msm-v2.c @@ -23,12 +23,13 @@ #include #include #include -#include #include #include #include #include +#include + #include #include diff --git a/trunk/drivers/gpio/gpio-mxc.c b/trunk/drivers/gpio/gpio-mxc.c index 7176743915d3..7877335c4cc8 100644 --- a/trunk/drivers/gpio/gpio-mxc.c +++ b/trunk/drivers/gpio/gpio-mxc.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -33,6 +32,7 @@ #include #include #include +#include enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ diff --git a/trunk/drivers/gpio/gpio-omap.c b/trunk/drivers/gpio/gpio-omap.c index a612ea1c53cb..159f5c57eb45 100644 --- a/trunk/drivers/gpio/gpio-omap.c +++ b/trunk/drivers/gpio/gpio-omap.c @@ -25,10 +25,11 @@ #include #include #include -#include #include #include +#include + #define OFF_MODE 1 static LIST_HEAD(omap_gpio_list); diff --git a/trunk/drivers/gpio/gpio-pl061.c b/trunk/drivers/gpio/gpio-pl061.c index 5c06f3062599..b820869ca93c 100644 --- a/trunk/drivers/gpio/gpio-pl061.c +++ b/trunk/drivers/gpio/gpio-pl061.c @@ -15,8 +15,6 @@ #include #include #include -#include -#include #include #include #include @@ -24,8 +22,8 @@ #include #include #include -#include #include +#include #define GPIODIR 0x400 #define GPIOIS 0x404 @@ -53,7 +51,8 @@ struct pl061_gpio { spinlock_t lock; void __iomem *base; - struct irq_domain *domain; + int irq_base; + struct irq_chip_generic *irq_gc; struct gpio_chip gc; #ifdef CONFIG_PM @@ -61,17 +60,6 @@ struct pl061_gpio { #endif }; -static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - /* - * Map back to global GPIO space and request muxing, the direction - * parameter does not matter for this controller. - */ - int gpio = chip->base + offset; - - return pinctrl_request_gpio(gpio); -} - static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); @@ -134,20 +122,24 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset) { struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); - return irq_create_mapping(chip->domain, offset); + if (chip->irq_base <= 0) + return -EINVAL; + + return chip->irq_base + offset; } static int pl061_irq_type(struct irq_data *d, unsigned trigger) { - struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); - int offset = irqd_to_hwirq(d); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct pl061_gpio *chip = gc->private; + int offset = d->irq - chip->irq_base; unsigned long flags; u8 gpiois, gpioibe, gpioiev; if (offset < 0 || offset >= PL061_GPIO_NR) return -EINVAL; - spin_lock_irqsave(&chip->lock, flags); + raw_spin_lock_irqsave(&gc->lock, flags); gpioiev = readb(chip->base + GPIOIEV); @@ -176,7 +168,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) writeb(gpioiev, chip->base + GPIOIEV); - spin_unlock_irqrestore(&chip->lock, flags); + raw_spin_unlock_irqrestore(&gc->lock, flags); return 0; } @@ -200,61 +192,31 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_exit(irqchip, desc); } -static void pl061_irq_mask(struct irq_data *d) +static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base) { - struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); - u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; - - spin_lock(&chip->lock); - gpioie = readb(chip->base + GPIOIE) & ~mask; - writeb(gpioie, chip->base + GPIOIE); - spin_unlock(&chip->lock); -} - -static void pl061_irq_unmask(struct irq_data *d) -{ - struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); - u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; - - spin_lock(&chip->lock); - gpioie = readb(chip->base + GPIOIE) | mask; - writeb(gpioie, chip->base + GPIOIE); - spin_unlock(&chip->lock); -} + struct irq_chip_type *ct; -static struct irq_chip pl061_irqchip = { - .name = "pl061 gpio", - .irq_mask = pl061_irq_mask, - .irq_unmask = pl061_irq_unmask, - .irq_set_type = pl061_irq_type, -}; - -static int pl061_irq_map(struct irq_domain *d, unsigned int virq, - irq_hw_number_t hw) -{ - struct pl061_gpio *chip = d->host_data; + chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base, + chip->base, handle_simple_irq); + chip->irq_gc->private = chip; - irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq, - "pl061"); - irq_set_chip_data(virq, chip); - irq_set_irq_type(virq, IRQ_TYPE_NONE); + ct = chip->irq_gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_set_type = pl061_irq_type; + ct->chip.irq_set_wake = irq_gc_set_wake; + ct->regs.mask = GPIOIE; - return 0; + irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR), + IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0); } -static const struct irq_domain_ops pl061_domain_ops = { - .map = pl061_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; struct pl061_platform_data *pdata = dev->platform_data; struct pl061_gpio *chip; - int ret, irq, i, irq_base; + int ret, irq, i; chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (chip == NULL) @@ -262,31 +224,24 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) if (pdata) { chip->gc.base = pdata->gpio_base; - irq_base = pdata->irq_base; - if (irq_base <= 0) - return -ENODEV; - } else { + chip->irq_base = pdata->irq_base; + } else if (adev->dev.of_node) { chip->gc.base = -1; - irq_base = 0; - } + chip->irq_base = 0; + } else + return -ENODEV; if (!devm_request_mem_region(dev, adev->res.start, - resource_size(&adev->res), "pl061")) + resource_size(&adev->res), "pl061")) return -EBUSY; chip->base = devm_ioremap(dev, adev->res.start, - resource_size(&adev->res)); - if (!chip->base) + resource_size(&adev->res)); + if (chip->base == NULL) return -ENOMEM; - chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR, - irq_base, &pl061_domain_ops, chip); - if (!chip->domain) - return -ENODEV; - spin_lock_init(&chip->lock); - chip->gc.request = pl061_gpio_request; chip->gc.direction_input = pl061_direction_input; chip->gc.direction_output = pl061_direction_output; chip->gc.get = pl061_get_value; @@ -304,6 +259,12 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) /* * irq_chip support */ + + if (chip->irq_base <= 0) + return 0; + + pl061_init_gc(chip, chip->irq_base); + writeb(0, chip->base + GPIOIE); /* disable irqs */ irq = adev->irq[0]; if (irq < 0) diff --git a/trunk/drivers/gpio/gpio-pxa.c b/trunk/drivers/gpio/gpio-pxa.c index 7523b6d108d0..9cc108d2b770 100644 --- a/trunk/drivers/gpio/gpio-pxa.c +++ b/trunk/drivers/gpio/gpio-pxa.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -27,6 +26,8 @@ #include #include +#include + #include /* diff --git a/trunk/drivers/gpio/gpio-rcar.c b/trunk/drivers/gpio/gpio-rcar.c deleted file mode 100644 index b4ca450947b8..000000000000 --- a/trunk/drivers/gpio/gpio-rcar.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * Renesas R-Car GPIO Support - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct gpio_rcar_priv { - void __iomem *base; - spinlock_t lock; - struct gpio_rcar_config config; - struct platform_device *pdev; - struct gpio_chip gpio_chip; - struct irq_chip irq_chip; - struct irq_domain *irq_domain; -}; - -#define IOINTSEL 0x00 -#define INOUTSEL 0x04 -#define OUTDT 0x08 -#define INDT 0x0c -#define INTDT 0x10 -#define INTCLR 0x14 -#define INTMSK 0x18 -#define MSKCLR 0x1c -#define POSNEG 0x20 -#define EDGLEVEL 0x24 -#define FILONOFF 0x28 - -static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) -{ - return ioread32(p->base + offs); -} - -static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, - u32 value) -{ - iowrite32(value, p->base + offs); -} - -static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, - int bit, bool value) -{ - u32 tmp = gpio_rcar_read(p, offs); - - if (value) - tmp |= BIT(bit); - else - tmp &= ~BIT(bit); - - gpio_rcar_write(p, offs, tmp); -} - -static void gpio_rcar_irq_disable(struct irq_data *d) -{ - struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); - - gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); -} - -static void gpio_rcar_irq_enable(struct irq_data *d) -{ - struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); - - gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); -} - -static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, - unsigned int hwirq, - bool active_high_rising_edge, - bool level_trigger) -{ - unsigned long flags; - - /* follow steps in the GPIO documentation for - * "Setting Edge-Sensitive Interrupt Input Mode" and - * "Setting Level-Sensitive Interrupt Input Mode" - */ - - spin_lock_irqsave(&p->lock, flags); - - /* Configure postive or negative logic in POSNEG */ - gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); - - /* Configure edge or level trigger in EDGLEVEL */ - gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); - - /* Select "Interrupt Input Mode" in IOINTSEL */ - gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); - - /* Write INTCLR in case of edge trigger */ - if (!level_trigger) - gpio_rcar_write(p, INTCLR, BIT(hwirq)); - - spin_unlock_irqrestore(&p->lock, flags); -} - -static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); - unsigned int hwirq = irqd_to_hwirq(d); - - dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); - - switch (type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_LEVEL_HIGH: - gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); - break; - case IRQ_TYPE_LEVEL_LOW: - gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); - break; - case IRQ_TYPE_EDGE_RISING: - gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); - break; - case IRQ_TYPE_EDGE_FALLING: - gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false); - break; - default: - return -EINVAL; - } - return 0; -} - -static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) -{ - struct gpio_rcar_priv *p = dev_id; - u32 pending; - unsigned int offset, irqs_handled = 0; - - while ((pending = gpio_rcar_read(p, INTDT))) { - offset = __ffs(pending); - gpio_rcar_write(p, INTCLR, BIT(offset)); - generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); - irqs_handled++; - } - - return irqs_handled ? IRQ_HANDLED : IRQ_NONE; -} - -static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) -{ - return container_of(chip, struct gpio_rcar_priv, gpio_chip); -} - -static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, - unsigned int gpio, - bool output) -{ - struct gpio_rcar_priv *p = gpio_to_priv(chip); - unsigned long flags; - - /* follow steps in the GPIO documentation for - * "Setting General Output Mode" and - * "Setting General Input Mode" - */ - - spin_lock_irqsave(&p->lock, flags); - - /* Configure postive logic in POSNEG */ - gpio_rcar_modify_bit(p, POSNEG, gpio, false); - - /* Select "General Input/Output Mode" in IOINTSEL */ - gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); - - /* Select Input Mode or Output Mode in INOUTSEL */ - gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); - - spin_unlock_irqrestore(&p->lock, flags); -} - -static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) -{ - return pinctrl_request_gpio(chip->base + offset); -} - -static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) -{ - pinctrl_free_gpio(chip->base + offset); - - /* Set the GPIO as an input to ensure that the next GPIO request won't - * drive the GPIO pin as an output. - */ - gpio_rcar_config_general_input_output_mode(chip, offset, false); -} - -static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) -{ - gpio_rcar_config_general_input_output_mode(chip, offset, false); - return 0; -} - -static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) -{ - return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset)); -} - -static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) -{ - struct gpio_rcar_priv *p = gpio_to_priv(chip); - unsigned long flags; - - spin_lock_irqsave(&p->lock, flags); - gpio_rcar_modify_bit(p, OUTDT, offset, value); - spin_unlock_irqrestore(&p->lock, flags); -} - -static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - /* write GPIO value to output before selecting output mode of pin */ - gpio_rcar_set(chip, offset, value); - gpio_rcar_config_general_input_output_mode(chip, offset, true); - return 0; -} - -static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) -{ - return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); -} - -static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct gpio_rcar_priv *p = h->host_data; - - dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq); - - irq_set_chip_data(virq, h->host_data); - irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); - set_irq_flags(virq, IRQF_VALID); /* kill me now */ - return 0; -} - -static struct irq_domain_ops gpio_rcar_irq_domain_ops = { - .map = gpio_rcar_irq_domain_map, -}; - -static int gpio_rcar_probe(struct platform_device *pdev) -{ - struct gpio_rcar_config *pdata = pdev->dev.platform_data; - struct gpio_rcar_priv *p; - struct resource *io, *irq; - struct gpio_chip *gpio_chip; - struct irq_chip *irq_chip; - const char *name = dev_name(&pdev->dev); - int ret; - - p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); - if (!p) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - ret = -ENOMEM; - goto err0; - } - - /* deal with driver instance configuration */ - if (pdata) - p->config = *pdata; - - p->pdev = pdev; - platform_set_drvdata(pdev, p); - spin_lock_init(&p->lock); - - io = platform_get_resource(pdev, IORESOURCE_MEM, 0); - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - - if (!io || !irq) { - dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); - ret = -EINVAL; - goto err0; - } - - p->base = devm_ioremap_nocache(&pdev->dev, io->start, - resource_size(io)); - if (!p->base) { - dev_err(&pdev->dev, "failed to remap I/O memory\n"); - ret = -ENXIO; - goto err0; - } - - gpio_chip = &p->gpio_chip; - gpio_chip->request = gpio_rcar_request; - gpio_chip->free = gpio_rcar_free; - gpio_chip->direction_input = gpio_rcar_direction_input; - gpio_chip->get = gpio_rcar_get; - gpio_chip->direction_output = gpio_rcar_direction_output; - gpio_chip->set = gpio_rcar_set; - gpio_chip->to_irq = gpio_rcar_to_irq; - gpio_chip->label = name; - gpio_chip->owner = THIS_MODULE; - gpio_chip->base = p->config.gpio_base; - gpio_chip->ngpio = p->config.number_of_pins; - - irq_chip = &p->irq_chip; - irq_chip->name = name; - irq_chip->irq_mask = gpio_rcar_irq_disable; - irq_chip->irq_unmask = gpio_rcar_irq_enable; - irq_chip->irq_enable = gpio_rcar_irq_enable; - irq_chip->irq_disable = gpio_rcar_irq_disable; - irq_chip->irq_set_type = gpio_rcar_irq_set_type; - irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED; - - p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, - p->config.number_of_pins, - p->config.irq_base, - &gpio_rcar_irq_domain_ops, p); - if (!p->irq_domain) { - ret = -ENXIO; - dev_err(&pdev->dev, "cannot initialize irq domain\n"); - goto err1; - } - - if (devm_request_irq(&pdev->dev, irq->start, - gpio_rcar_irq_handler, 0, name, p)) { - dev_err(&pdev->dev, "failed to request IRQ\n"); - ret = -ENOENT; - goto err1; - } - - ret = gpiochip_add(gpio_chip); - if (ret) { - dev_err(&pdev->dev, "failed to add GPIO controller\n"); - goto err1; - } - - dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins); - - /* warn in case of mismatch if irq base is specified */ - if (p->config.irq_base) { - ret = irq_find_mapping(p->irq_domain, 0); - if (p->config.irq_base != ret) - dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n", - p->config.irq_base, ret); - } - - ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, - gpio_chip->base, gpio_chip->ngpio); - if (ret < 0) - dev_warn(&pdev->dev, "failed to add pin range\n"); - - return 0; - -err1: - irq_domain_remove(p->irq_domain); -err0: - return ret; -} - -static int gpio_rcar_remove(struct platform_device *pdev) -{ - struct gpio_rcar_priv *p = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&p->gpio_chip); - if (ret) - return ret; - - irq_domain_remove(p->irq_domain); - return 0; -} - -static struct platform_driver gpio_rcar_device_driver = { - .probe = gpio_rcar_probe, - .remove = gpio_rcar_remove, - .driver = { - .name = "gpio_rcar", - } -}; - -module_platform_driver(gpio_rcar_device_driver); - -MODULE_AUTHOR("Magnus Damm"); -MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/gpio/gpio-stmpe.c b/trunk/drivers/gpio/gpio-stmpe.c index 770476a9da87..3ce5bc38ac31 100644 --- a/trunk/drivers/gpio/gpio-stmpe.c +++ b/trunk/drivers/gpio/gpio-stmpe.c @@ -307,11 +307,15 @@ static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = { .xlate = irq_domain_xlate_twocell, }; -static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio) +static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, + struct device_node *np) { - int base = stmpe_gpio->irq_base; + int base = 0; - stmpe_gpio->domain = irq_domain_add_simple(NULL, + if (!np) + base = stmpe_gpio->irq_base; + + stmpe_gpio->domain = irq_domain_add_simple(np, stmpe_gpio->chip.ngpio, base, &stmpe_gpio_irq_simple_ops, stmpe_gpio); if (!stmpe_gpio->domain) { @@ -346,6 +350,9 @@ static int stmpe_gpio_probe(struct platform_device *pdev) stmpe_gpio->chip = template_chip; stmpe_gpio->chip.ngpio = stmpe->num_gpios; stmpe_gpio->chip.dev = &pdev->dev; +#ifdef CONFIG_OF + stmpe_gpio->chip.of_node = np; +#endif stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; if (pdata) @@ -366,7 +373,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev) goto out_free; if (irq >= 0) { - ret = stmpe_gpio_irq_init(stmpe_gpio); + ret = stmpe_gpio_irq_init(stmpe_gpio, np); if (ret) goto out_disable; diff --git a/trunk/drivers/gpio/gpio-tegra.c b/trunk/drivers/gpio/gpio-tegra.c index 8e2155548888..414ad912232f 100644 --- a/trunk/drivers/gpio/gpio-tegra.c +++ b/trunk/drivers/gpio/gpio-tegra.c @@ -27,10 +27,11 @@ #include #include #include -#include #include #include +#include + #define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) #define GPIO_BIT(x) ((x) & 0x7) diff --git a/trunk/drivers/gpio/gpiolib-of.c b/trunk/drivers/gpio/gpiolib-of.c index 465f4ca57e80..5150df6cba08 100644 --- a/trunk/drivers/gpio/gpiolib-of.c +++ b/trunk/drivers/gpio/gpiolib-of.c @@ -203,11 +203,22 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!pctldev) break; + /* + * This assumes that the n GPIO pins are consecutive in the + * GPIO number space, and that the pins are also consecutive + * in their local number space. Currently it is not possible + * to add different ranges for one and the same GPIO chip, + * as the code assumes that we have one consecutive range + * on both, mapping 1-to-1. + * + * TODO: make the OF bindings handle multiple sparse ranges + * on the same GPIO chip. + */ ret = gpiochip_add_pin_range(chip, pinctrl_dev_get_devname(pctldev), + 0, /* offset in gpiochip */ pinspec.args[0], - pinspec.args[1], - pinspec.args[2]); + pinspec.args[1]); if (ret) break; diff --git a/trunk/drivers/gpu/drm/drm_crtc.c b/trunk/drivers/gpu/drm/drm_crtc.c index 792c3e3795ca..dd64a06dc5b4 100644 --- a/trunk/drivers/gpu/drm/drm_crtc.c +++ b/trunk/drivers/gpu/drm/drm_crtc.c @@ -2326,7 +2326,6 @@ int drm_mode_addfb(struct drm_device *dev, fb = dev->mode_config.funcs->fb_create(dev, file_priv, &r); if (IS_ERR(fb)) { DRM_DEBUG_KMS("could not create framebuffer\n"); - drm_modeset_unlock_all(dev); return PTR_ERR(fb); } @@ -2506,7 +2505,6 @@ int drm_mode_addfb2(struct drm_device *dev, fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); if (IS_ERR(fb)) { DRM_DEBUG_KMS("could not create framebuffer\n"); - drm_modeset_unlock_all(dev); return PTR_ERR(fb); } diff --git a/trunk/drivers/gpu/drm/drm_fops.c b/trunk/drivers/gpu/drm/drm_fops.c index 13fdcd10a605..429e07d0b0f1 100644 --- a/trunk/drivers/gpu/drm/drm_fops.c +++ b/trunk/drivers/gpu/drm/drm_fops.c @@ -123,6 +123,7 @@ int drm_open(struct inode *inode, struct file *filp) int retcode = 0; int need_setup = 0; struct address_space *old_mapping; + struct address_space *old_imapping; minor = idr_find(&drm_minors_idr, minor_id); if (!minor) @@ -137,6 +138,7 @@ int drm_open(struct inode *inode, struct file *filp) if (!dev->open_count++) need_setup = 1; mutex_lock(&dev->struct_mutex); + old_imapping = inode->i_mapping; old_mapping = dev->dev_mapping; if (old_mapping == NULL) dev->dev_mapping = &inode->i_data; @@ -159,8 +161,8 @@ int drm_open(struct inode *inode, struct file *filp) err_undo: mutex_lock(&dev->struct_mutex); - filp->f_mapping = old_mapping; - inode->i_mapping = old_mapping; + filp->f_mapping = old_imapping; + inode->i_mapping = old_imapping; iput(container_of(dev->dev_mapping, struct inode, i_data)); dev->dev_mapping = old_mapping; mutex_unlock(&dev->struct_mutex); diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/trunk/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 3b11ab0fbc96..9a48e1a2d417 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -57,7 +57,7 @@ eb_create(struct drm_i915_gem_execbuffer2 *args) if (eb == NULL) { int size = args->buffer_count; int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; - BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head))); + BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); while (count > 2*size) count >>= 1; eb = kzalloc(count*sizeof(struct hlist_head) + diff --git a/trunk/drivers/gpu/drm/i915/intel_crt.c b/trunk/drivers/gpu/drm/i915/intel_crt.c index 32a3693905ec..1ce45a0a2d3e 100644 --- a/trunk/drivers/gpu/drm/i915/intel_crt.c +++ b/trunk/drivers/gpu/drm/i915/intel_crt.c @@ -45,6 +45,9 @@ struct intel_crt { struct intel_encoder base; + /* DPMS state is stored in the connector, which we need in the + * encoder's enable/disable callbacks */ + struct intel_connector *connector; bool force_hotplug_required; u32 adpa_reg; }; @@ -81,29 +84,6 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder, return true; } -static void intel_disable_crt(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; - struct intel_crt *crt = intel_encoder_to_crt(encoder); - u32 temp; - - temp = I915_READ(crt->adpa_reg); - temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; - temp &= ~ADPA_DAC_ENABLE; - I915_WRITE(crt->adpa_reg, temp); -} - -static void intel_enable_crt(struct intel_encoder *encoder) -{ - struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; - struct intel_crt *crt = intel_encoder_to_crt(encoder); - u32 temp; - - temp = I915_READ(crt->adpa_reg); - temp |= ADPA_DAC_ENABLE; - I915_WRITE(crt->adpa_reg, temp); -} - /* Note: The caller is required to filter out dpms modes not supported by the * platform. */ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) @@ -135,6 +115,19 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) I915_WRITE(crt->adpa_reg, temp); } +static void intel_disable_crt(struct intel_encoder *encoder) +{ + intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); +} + +static void intel_enable_crt(struct intel_encoder *encoder) +{ + struct intel_crt *crt = intel_encoder_to_crt(encoder); + + intel_crt_set_dpms(encoder, crt->connector->base.dpms); +} + + static void intel_crt_dpms(struct drm_connector *connector, int mode) { struct drm_device *dev = connector->dev; @@ -746,6 +739,7 @@ void intel_crt_init(struct drm_device *dev) } connector = &intel_connector->base; + crt->connector = intel_connector; drm_connector_init(dev, &intel_connector->base, &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c index d7d4afe01341..8fc93f90a7cd 100644 --- a/trunk/drivers/gpu/drm/i915/intel_dp.c +++ b/trunk/drivers/gpu/drm/i915/intel_dp.c @@ -2559,12 +2559,15 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) { struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &intel_dig_port->dp; + struct drm_device *dev = intel_dp_to_dev(intel_dp); i2c_del_adapter(&intel_dp->adapter); drm_encoder_cleanup(encoder); if (is_edp(intel_dp)) { cancel_delayed_work_sync(&intel_dp->panel_vdd_work); + mutex_lock(&dev->mode_config.mutex); ironlake_panel_vdd_off_sync(intel_dp); + mutex_unlock(&dev->mode_config.mutex); } kfree(intel_dig_port); } diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/base.c index e816f06637a7..0e2c1a4f1659 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/base.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/bios/base.c @@ -248,6 +248,22 @@ nouveau_bios_shadow_pci(struct nouveau_bios *bios) } } +static void +nouveau_bios_shadow_platform(struct nouveau_bios *bios) +{ + struct pci_dev *pdev = nv_device(bios)->pdev; + size_t size; + + void __iomem *rom = pci_platform_rom(pdev, &size); + if (rom && size) { + bios->data = kmalloc(size, GFP_KERNEL); + if (bios->data) { + memcpy_fromio(bios->data, rom, size); + bios->size = size; + } + } +} + static int nouveau_bios_score(struct nouveau_bios *bios, const bool writeable) { @@ -288,6 +304,7 @@ nouveau_bios_shadow(struct nouveau_bios *bios) { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL }, { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL }, { "PCIROM", nouveau_bios_shadow_pci, true, 0, 0, NULL }, + { "PLATFORM", nouveau_bios_shadow_platform, true, 0, 0, NULL }, {} }; struct methods *mthd, *best; diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c b/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c index 3b6dc883e150..5eb3e0da7c6e 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -391,7 +391,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_device *device = nv_device(drm->device); struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); - struct nouveau_abi16_chan *chan, *temp; + struct nouveau_abi16_chan *chan = NULL, *temp; struct nouveau_abi16_ntfy *ntfy; struct nouveau_object *object; struct nv_dma_class args = {}; @@ -404,10 +404,11 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) if (unlikely(nv_device(abi16->device)->card_type >= NV_C0)) return nouveau_abi16_put(abi16, -EINVAL); - list_for_each_entry_safe(chan, temp, &abi16->channels, head) { - if (chan->chan->handle == (NVDRM_CHAN | info->channel)) + list_for_each_entry(temp, &abi16->channels, head) { + if (temp->chan->handle == (NVDRM_CHAN | info->channel)) { + chan = temp; break; - chan = NULL; + } } if (!chan) @@ -459,17 +460,18 @@ nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS) { struct drm_nouveau_gpuobj_free *fini = data; struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); - struct nouveau_abi16_chan *chan, *temp; + struct nouveau_abi16_chan *chan = NULL, *temp; struct nouveau_abi16_ntfy *ntfy; int ret; if (unlikely(!abi16)) return -ENOMEM; - list_for_each_entry_safe(chan, temp, &abi16->channels, head) { - if (chan->chan->handle == (NVDRM_CHAN | fini->channel)) + list_for_each_entry(temp, &abi16->channels, head) { + if (temp->chan->handle == (NVDRM_CHAN | fini->channel)) { + chan = temp; break; - chan = NULL; + } } if (!chan) diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c index d1099365bfc1..c95decf543e9 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -71,12 +71,26 @@ module_param_named(modeset, nouveau_modeset, int, 0400); static struct drm_driver driver; +static int +nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head) +{ + struct nouveau_drm *drm = + container_of(event, struct nouveau_drm, vblank[head]); + drm_handle_vblank(drm->dev, head); + return NVKM_EVENT_KEEP; +} + static int nouveau_drm_vblank_enable(struct drm_device *dev, int head) { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_disp *pdisp = nouveau_disp(drm->device); - nouveau_event_get(pdisp->vblank, head, &drm->vblank); + + if (WARN_ON_ONCE(head > ARRAY_SIZE(drm->vblank))) + return -EIO; + WARN_ON_ONCE(drm->vblank[head].func); + drm->vblank[head].func = nouveau_drm_vblank_handler; + nouveau_event_get(pdisp->vblank, head, &drm->vblank[head]); return 0; } @@ -85,16 +99,11 @@ nouveau_drm_vblank_disable(struct drm_device *dev, int head) { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_disp *pdisp = nouveau_disp(drm->device); - nouveau_event_put(pdisp->vblank, head, &drm->vblank); -} - -static int -nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head) -{ - struct nouveau_drm *drm = - container_of(event, struct nouveau_drm, vblank); - drm_handle_vblank(drm->dev, head); - return NVKM_EVENT_KEEP; + if (drm->vblank[head].func) + nouveau_event_put(pdisp->vblank, head, &drm->vblank[head]); + else + WARN_ON_ONCE(1); + drm->vblank[head].func = NULL; } static u64 @@ -292,7 +301,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) dev->dev_private = drm; drm->dev = dev; - drm->vblank.func = nouveau_drm_vblank_handler; INIT_LIST_HEAD(&drm->clients); spin_lock_init(&drm->tile.lock); diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.h b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.h index b25df374c901..9c39bafbef2c 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -113,7 +113,7 @@ struct nouveau_drm { struct nvbios vbios; struct nouveau_display *display; struct backlight_device *backlight; - struct nouveau_eventh vblank; + struct nouveau_eventh vblank[4]; /* power management */ struct nouveau_pm *pm; diff --git a/trunk/drivers/gpu/drm/radeon/radeon_bios.c b/trunk/drivers/gpu/drm/radeon/radeon_bios.c index b8015913d382..fa3c56fba294 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_bios.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_bios.c @@ -99,6 +99,29 @@ static bool radeon_read_bios(struct radeon_device *rdev) return true; } +static bool radeon_read_platform_bios(struct radeon_device *rdev) +{ + uint8_t __iomem *bios; + size_t size; + + rdev->bios = NULL; + + bios = pci_platform_rom(rdev->pdev, &size); + if (!bios) { + return false; + } + + if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { + return false; + } + rdev->bios = kmemdup(bios, size, GFP_KERNEL); + if (rdev->bios == NULL) { + return false; + } + + return true; +} + #ifdef CONFIG_ACPI /* ATRM is used to get the BIOS on the discrete cards in * dual-gpu systems. @@ -620,6 +643,9 @@ bool radeon_get_bios(struct radeon_device *rdev) if (r == false) { r = radeon_read_disabled_bios(rdev); } + if (r == false) { + r = radeon_read_platform_bios(rdev); + } if (r == false || rdev->bios == NULL) { DRM_ERROR("Unable to locate a BIOS ROM\n"); rdev->bios = NULL; diff --git a/trunk/drivers/hid/hid-core.c b/trunk/drivers/hid/hid-core.c index 512b01c04ea7..aa341d135867 100644 --- a/trunk/drivers/hid/hid-core.c +++ b/trunk/drivers/hid/hid-core.c @@ -2077,7 +2077,6 @@ static const struct hid_device_id hid_ignore_list[] = { { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HYBRID) }, { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HEATCONTROL) }, { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_BEATPAD) }, - { HID_USB_DEVICE(USB_VENDOR_ID_MASTERKIT, USB_DEVICE_ID_MASTERKIT_MA901RADIO) }, { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1024LS) }, { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1208LS) }, { HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICKIT1) }, @@ -2244,6 +2243,18 @@ bool hid_ignore(struct hid_device *hdev) hdev->product <= USB_DEVICE_ID_VELLEMAN_K8061_LAST)) return true; break; + case USB_VENDOR_ID_ATMEL_V_USB: + /* Masterkit MA901 usb radio based on Atmel tiny85 chip and + * it has the same USB ID as many Atmel V-USB devices. This + * usb radio is handled by radio-ma901.c driver so we want + * ignore the hid. Check the name, bus, product and ignore + * if we have MA901 usb radio. + */ + if (hdev->product == USB_DEVICE_ID_ATMEL_V_USB && + hdev->bus == BUS_USB && + strncmp(hdev->name, "www.masterkit.ru MA901", 22) == 0) + return true; + break; } if (hdev->type == HID_TYPE_USBMOUSE && diff --git a/trunk/drivers/hid/hid-ids.h b/trunk/drivers/hid/hid-ids.h index c4388776f4e4..5309fd5eb0eb 100644 --- a/trunk/drivers/hid/hid-ids.h +++ b/trunk/drivers/hid/hid-ids.h @@ -158,6 +158,8 @@ #define USB_VENDOR_ID_ATMEL 0x03eb #define USB_DEVICE_ID_ATMEL_MULTITOUCH 0x211c #define USB_DEVICE_ID_ATMEL_MXT_DIGITIZER 0x2118 +#define USB_VENDOR_ID_ATMEL_V_USB 0x16c0 +#define USB_DEVICE_ID_ATMEL_V_USB 0x05df #define USB_VENDOR_ID_AUREAL 0x0755 #define USB_DEVICE_ID_AUREAL_W01RN 0x2626 @@ -557,9 +559,6 @@ #define USB_VENDOR_ID_MADCATZ 0x0738 #define USB_DEVICE_ID_MADCATZ_BEATPAD 0x4540 -#define USB_VENDOR_ID_MASTERKIT 0x16c0 -#define USB_DEVICE_ID_MASTERKIT_MA901RADIO 0x05df - #define USB_VENDOR_ID_MCC 0x09db #define USB_DEVICE_ID_MCC_PMD1024LS 0x0076 #define USB_DEVICE_ID_MCC_PMD1208LS 0x007a diff --git a/trunk/drivers/hid/hid-magicmouse.c b/trunk/drivers/hid/hid-magicmouse.c index f7f113ba083e..a8ce44296cfd 100644 --- a/trunk/drivers/hid/hid-magicmouse.c +++ b/trunk/drivers/hid/hid-magicmouse.c @@ -462,6 +462,21 @@ static int magicmouse_input_mapping(struct hid_device *hdev, return 0; } +static void magicmouse_input_configured(struct hid_device *hdev, + struct hid_input *hi) + +{ + struct magicmouse_sc *msc = hid_get_drvdata(hdev); + + int ret = magicmouse_setup_input(msc->input, hdev); + if (ret) { + hid_err(hdev, "magicmouse setup input failed (%d)\n", ret); + /* clean msc->input to notify probe() of the failure */ + msc->input = NULL; + } +} + + static int magicmouse_probe(struct hid_device *hdev, const struct hid_device_id *id) { @@ -493,15 +508,10 @@ static int magicmouse_probe(struct hid_device *hdev, goto err_free; } - /* We do this after hid-input is done parsing reports so that - * hid-input uses the most natural button and axis IDs. - */ - if (msc->input) { - ret = magicmouse_setup_input(msc->input, hdev); - if (ret) { - hid_err(hdev, "magicmouse setup input failed (%d)\n", ret); - goto err_stop_hw; - } + if (!msc->input) { + hid_err(hdev, "magicmouse input not registered\n"); + ret = -ENOMEM; + goto err_stop_hw; } if (id->product == USB_DEVICE_ID_APPLE_MAGICMOUSE) @@ -568,6 +578,7 @@ static struct hid_driver magicmouse_driver = { .remove = magicmouse_remove, .raw_event = magicmouse_raw_event, .input_mapping = magicmouse_input_mapping, + .input_configured = magicmouse_input_configured, }; module_hid_driver(magicmouse_driver); diff --git a/trunk/drivers/i2c/busses/i2c-designware-platdrv.c b/trunk/drivers/i2c/busses/i2c-designware-platdrv.c index 0ceb6e1b0f65..e3085c487ace 100644 --- a/trunk/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/trunk/drivers/i2c/busses/i2c-designware-platdrv.c @@ -182,7 +182,6 @@ static int dw_i2c_probe(struct platform_device *pdev) adap->algo = &i2c_dw_algo; adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; - ACPI_HANDLE_SET(&adap->dev, ACPI_HANDLE(&pdev->dev)); r = i2c_add_numbered_adapter(adap); if (r) { diff --git a/trunk/drivers/infiniband/hw/qib/qib_sd7220.c b/trunk/drivers/infiniband/hw/qib/qib_sd7220.c index 08a6c6d39e56..911205d3d5a0 100644 --- a/trunk/drivers/infiniband/hw/qib/qib_sd7220.c +++ b/trunk/drivers/infiniband/hw/qib/qib_sd7220.c @@ -44,7 +44,7 @@ #include "qib.h" #include "qib_7220.h" -#define SD7220_FW_NAME "intel/sd7220.fw" +#define SD7220_FW_NAME "qlogic/sd7220.fw" MODULE_FIRMWARE(SD7220_FW_NAME); /* diff --git a/trunk/drivers/irqchip/Kconfig b/trunk/drivers/irqchip/Kconfig index 4a33351c25dc..a350969e5efe 100644 --- a/trunk/drivers/irqchip/Kconfig +++ b/trunk/drivers/irqchip/Kconfig @@ -25,14 +25,6 @@ config ARM_VIC_NR The maximum number of VICs available in the system, for power management. -config RENESAS_INTC_IRQPIN - bool - select IRQ_DOMAIN - -config RENESAS_IRQC - bool - select IRQ_DOMAIN - config VERSATILE_FPGA_IRQ bool select IRQ_DOMAIN diff --git a/trunk/drivers/irqchip/Makefile b/trunk/drivers/irqchip/Makefile index e41ceb9bec22..98e3b87bdf1b 100644 --- a/trunk/drivers/irqchip/Makefile +++ b/trunk/drivers/irqchip/Makefile @@ -8,6 +8,4 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o -obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o -obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o diff --git a/trunk/drivers/irqchip/exynos-combiner.c b/trunk/drivers/irqchip/exynos-combiner.c index 6a5201351507..04d86a9803f4 100644 --- a/trunk/drivers/irqchip/exynos-combiner.c +++ b/trunk/drivers/irqchip/exynos-combiner.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/trunk/drivers/irqchip/irq-gic.c b/trunk/drivers/irqchip/irq-gic.c index add1fd84fc4b..a32e0d5aa45f 100644 --- a/trunk/drivers/irqchip/irq-gic.c +++ b/trunk/drivers/irqchip/irq-gic.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -39,12 +38,12 @@ #include #include #include -#include #include #include #include #include +#include #include "irqchip.h" @@ -324,7 +323,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); if (unlikely(gic_irq < 32 || gic_irq > 1020)) - handle_bad_irq(cascade_irq, desc); + do_bad_IRQ(cascade_irq, desc); else generic_handle_irq(cascade_irq); @@ -700,25 +699,6 @@ static int gic_irq_domain_xlate(struct irq_domain *d, return 0; } -#ifdef CONFIG_SMP -static int __cpuinit gic_secondary_init(struct notifier_block *nfb, - unsigned long action, void *hcpu) -{ - if (action == CPU_STARTING) - gic_cpu_init(&gic_data[0]); - return NOTIFY_OK; -} - -/* - * Notifier for enabling the GIC CPU interface. Set an arbitrarily high - * priority because the GIC needs to be up before the ARM generic timers. - */ -static struct notifier_block __cpuinitdata gic_cpu_notifier = { - .notifier_call = gic_secondary_init, - .priority = 100, -}; -#endif - const struct irq_domain_ops gic_irq_domain_ops = { .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate, @@ -809,7 +789,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, #ifdef CONFIG_SMP set_smp_cross_call(gic_raise_softirq); - register_cpu_notifier(&gic_cpu_notifier); #endif set_handle_irq(gic_handle_irq); @@ -820,6 +799,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, gic_pm_init(gic); } +void __cpuinit gic_secondary_init(unsigned int gic_nr) +{ + BUG_ON(gic_nr >= MAX_GIC_NR); + + gic_cpu_init(&gic_data[gic_nr]); +} + #ifdef CONFIG_OF static int gic_cnt __initdata = 0; diff --git a/trunk/drivers/irqchip/irq-renesas-intc-irqpin.c b/trunk/drivers/irqchip/irq-renesas-intc-irqpin.c deleted file mode 100644 index 5a68e5accec1..000000000000 --- a/trunk/drivers/irqchip/irq-renesas-intc-irqpin.c +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Renesas INTC External IRQ Pin Driver - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ - -#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ -#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ -#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ -#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ -#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ -#define INTC_IRQPIN_REG_NR 5 - -/* INTC external IRQ PIN hardware register access: - * - * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) - * PRIO is read-write 32-bit with 4-bits per IRQ (**) - * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) - * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) - * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) - * - * (*) May be accessed by more than one driver instance - lock needed - * (**) Read-modify-write access by one driver instance - lock needed - * (***) Accessed by one driver instance only - no locking needed - */ - -struct intc_irqpin_iomem { - void __iomem *iomem; - unsigned long (*read)(void __iomem *iomem); - void (*write)(void __iomem *iomem, unsigned long data); - int width; -}; - -struct intc_irqpin_irq { - int hw_irq; - int requested_irq; - int domain_irq; - struct intc_irqpin_priv *p; -}; - -struct intc_irqpin_priv { - struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; - struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; - struct renesas_intc_irqpin_config config; - unsigned int number_of_irqs; - struct platform_device *pdev; - struct irq_chip irq_chip; - struct irq_domain *irq_domain; - bool shared_irqs; - u8 shared_irq_mask; -}; - -static unsigned long intc_irqpin_read32(void __iomem *iomem) -{ - return ioread32(iomem); -} - -static unsigned long intc_irqpin_read8(void __iomem *iomem) -{ - return ioread8(iomem); -} - -static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) -{ - iowrite32(data, iomem); -} - -static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) -{ - iowrite8(data, iomem); -} - -static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, - int reg) -{ - struct intc_irqpin_iomem *i = &p->iomem[reg]; - - return i->read(i->iomem); -} - -static inline void intc_irqpin_write(struct intc_irqpin_priv *p, - int reg, unsigned long data) -{ - struct intc_irqpin_iomem *i = &p->iomem[reg]; - - i->write(i->iomem, data); -} - -static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, - int reg, int hw_irq) -{ - return BIT((p->iomem[reg].width - 1) - hw_irq); -} - -static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, - int reg, int hw_irq) -{ - intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); -} - -static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ - -static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, - int reg, int shift, - int width, int value) -{ - unsigned long flags; - unsigned long tmp; - - raw_spin_lock_irqsave(&intc_irqpin_lock, flags); - - tmp = intc_irqpin_read(p, reg); - tmp &= ~(((1 << width) - 1) << shift); - tmp |= value << shift; - intc_irqpin_write(p, reg, tmp); - - raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); -} - -static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, - int irq, int do_mask) -{ - int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ - int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ - - intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, - shift, bitfield_width, - do_mask ? 0 : (1 << bitfield_width) - 1); -} - -static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) -{ - int bitfield_width = p->config.sense_bitfield_width; - int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ - - dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); - - if (value >= (1 << bitfield_width)) - return -EINVAL; - - intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, - bitfield_width, value); - return 0; -} - -static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) -{ - dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", - str, i->requested_irq, i->hw_irq, i->domain_irq); -} - -static void intc_irqpin_irq_enable(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - intc_irqpin_dbg(&p->irq[hw_irq], "enable"); - intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); -} - -static void intc_irqpin_irq_disable(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - intc_irqpin_dbg(&p->irq[hw_irq], "disable"); - intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); -} - -static void intc_irqpin_shared_irq_enable(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); - intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); - - p->shared_irq_mask &= ~BIT(hw_irq); -} - -static void intc_irqpin_shared_irq_disable(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); - intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); - - p->shared_irq_mask |= BIT(hw_irq); -} - -static void intc_irqpin_irq_enable_force(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].requested_irq; - - intc_irqpin_irq_enable(d); - - /* enable interrupt through parent interrupt controller, - * assumes non-shared interrupt with 1:1 mapping - * needed for busted IRQs on some SoCs like sh73a0 - */ - irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); -} - -static void intc_irqpin_irq_disable_force(struct irq_data *d) -{ - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - int irq = p->irq[irqd_to_hwirq(d)].requested_irq; - - /* disable interrupt through parent interrupt controller, - * assumes non-shared interrupt with 1:1 mapping - * needed for busted IRQs on some SoCs like sh73a0 - */ - irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); - intc_irqpin_irq_disable(d); -} - -#define INTC_IRQ_SENSE_VALID 0x10 -#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) - -static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { - [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), - [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), - [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), - [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), - [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), -}; - -static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) -{ - unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; - struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); - - if (!(value & INTC_IRQ_SENSE_VALID)) - return -EINVAL; - - return intc_irqpin_set_sense(p, irqd_to_hwirq(d), - value ^ INTC_IRQ_SENSE_VALID); -} - -static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) -{ - struct intc_irqpin_irq *i = dev_id; - struct intc_irqpin_priv *p = i->p; - unsigned long bit; - - intc_irqpin_dbg(i, "demux1"); - bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); - - if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { - intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); - intc_irqpin_dbg(i, "demux2"); - generic_handle_irq(i->domain_irq); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) -{ - struct intc_irqpin_priv *p = dev_id; - unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); - irqreturn_t status = IRQ_NONE; - int k; - - for (k = 0; k < 8; k++) { - if (reg_source & BIT(7 - k)) { - if (BIT(k) & p->shared_irq_mask) - continue; - - status |= intc_irqpin_irq_handler(irq, &p->irq[k]); - } - } - - return status; -} - -static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct intc_irqpin_priv *p = h->host_data; - - p->irq[hw].domain_irq = virq; - p->irq[hw].hw_irq = hw; - - intc_irqpin_dbg(&p->irq[hw], "map"); - irq_set_chip_data(virq, h->host_data); - irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); - set_irq_flags(virq, IRQF_VALID); /* kill me now */ - return 0; -} - -static struct irq_domain_ops intc_irqpin_irq_domain_ops = { - .map = intc_irqpin_irq_domain_map, - .xlate = irq_domain_xlate_twocell, -}; - -static int intc_irqpin_probe(struct platform_device *pdev) -{ - struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data; - struct intc_irqpin_priv *p; - struct intc_irqpin_iomem *i; - struct resource *io[INTC_IRQPIN_REG_NR]; - struct resource *irq; - struct irq_chip *irq_chip; - void (*enable_fn)(struct irq_data *d); - void (*disable_fn)(struct irq_data *d); - const char *name = dev_name(&pdev->dev); - int ref_irq; - int ret; - int k; - - p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); - if (!p) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - ret = -ENOMEM; - goto err0; - } - - /* deal with driver instance configuration */ - if (pdata) - memcpy(&p->config, pdata, sizeof(*pdata)); - if (!p->config.sense_bitfield_width) - p->config.sense_bitfield_width = 4; /* default to 4 bits */ - - p->pdev = pdev; - platform_set_drvdata(pdev, p); - - /* get hold of manadatory IOMEM */ - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { - io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); - if (!io[k]) { - dev_err(&pdev->dev, "not enough IOMEM resources\n"); - ret = -EINVAL; - goto err0; - } - } - - /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ - for (k = 0; k < INTC_IRQPIN_MAX; k++) { - irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); - if (!irq) - break; - - p->irq[k].p = p; - p->irq[k].requested_irq = irq->start; - } - - p->number_of_irqs = k; - if (p->number_of_irqs < 1) { - dev_err(&pdev->dev, "not enough IRQ resources\n"); - ret = -EINVAL; - goto err0; - } - - /* ioremap IOMEM and setup read/write callbacks */ - for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { - i = &p->iomem[k]; - - switch (resource_size(io[k])) { - case 1: - i->width = 8; - i->read = intc_irqpin_read8; - i->write = intc_irqpin_write8; - break; - case 4: - i->width = 32; - i->read = intc_irqpin_read32; - i->write = intc_irqpin_write32; - break; - default: - dev_err(&pdev->dev, "IOMEM size mismatch\n"); - ret = -EINVAL; - goto err0; - } - - i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start, - resource_size(io[k])); - if (!i->iomem) { - dev_err(&pdev->dev, "failed to remap IOMEM\n"); - ret = -ENXIO; - goto err0; - } - } - - /* mask all interrupts using priority */ - for (k = 0; k < p->number_of_irqs; k++) - intc_irqpin_mask_unmask_prio(p, k, 1); - - /* clear all pending interrupts */ - intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); - - /* scan for shared interrupt lines */ - ref_irq = p->irq[0].requested_irq; - p->shared_irqs = true; - for (k = 1; k < p->number_of_irqs; k++) { - if (ref_irq != p->irq[k].requested_irq) { - p->shared_irqs = false; - break; - } - } - - /* use more severe masking method if requested */ - if (p->config.control_parent) { - enable_fn = intc_irqpin_irq_enable_force; - disable_fn = intc_irqpin_irq_disable_force; - } else if (!p->shared_irqs) { - enable_fn = intc_irqpin_irq_enable; - disable_fn = intc_irqpin_irq_disable; - } else { - enable_fn = intc_irqpin_shared_irq_enable; - disable_fn = intc_irqpin_shared_irq_disable; - } - - irq_chip = &p->irq_chip; - irq_chip->name = name; - irq_chip->irq_mask = disable_fn; - irq_chip->irq_unmask = enable_fn; - irq_chip->irq_enable = enable_fn; - irq_chip->irq_disable = disable_fn; - irq_chip->irq_set_type = intc_irqpin_irq_set_type; - irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; - - p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, - p->number_of_irqs, - p->config.irq_base, - &intc_irqpin_irq_domain_ops, p); - if (!p->irq_domain) { - ret = -ENXIO; - dev_err(&pdev->dev, "cannot initialize irq domain\n"); - goto err0; - } - - if (p->shared_irqs) { - /* request one shared interrupt */ - if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, - intc_irqpin_shared_irq_handler, - IRQF_SHARED, name, p)) { - dev_err(&pdev->dev, "failed to request low IRQ\n"); - ret = -ENOENT; - goto err1; - } - } else { - /* request interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (devm_request_irq(&pdev->dev, - p->irq[k].requested_irq, - intc_irqpin_irq_handler, - 0, name, &p->irq[k])) { - dev_err(&pdev->dev, - "failed to request low IRQ\n"); - ret = -ENOENT; - goto err1; - } - } - } - - /* unmask all interrupts on prio level */ - for (k = 0; k < p->number_of_irqs; k++) - intc_irqpin_mask_unmask_prio(p, k, 0); - - dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); - - /* warn in case of mismatch if irq base is specified */ - if (p->config.irq_base) { - if (p->config.irq_base != p->irq[0].domain_irq) - dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", - p->config.irq_base, p->irq[0].domain_irq); - } - - return 0; - -err1: - irq_domain_remove(p->irq_domain); -err0: - return ret; -} - -static int intc_irqpin_remove(struct platform_device *pdev) -{ - struct intc_irqpin_priv *p = platform_get_drvdata(pdev); - - irq_domain_remove(p->irq_domain); - - return 0; -} - -static const struct of_device_id intc_irqpin_dt_ids[] = { - { .compatible = "renesas,intc-irqpin", }, - {}, -}; -MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); - -static struct platform_driver intc_irqpin_device_driver = { - .probe = intc_irqpin_probe, - .remove = intc_irqpin_remove, - .driver = { - .name = "renesas_intc_irqpin", - .of_match_table = intc_irqpin_dt_ids, - .owner = THIS_MODULE, - } -}; - -static int __init intc_irqpin_init(void) -{ - return platform_driver_register(&intc_irqpin_device_driver); -} -postcore_initcall(intc_irqpin_init); - -static void __exit intc_irqpin_exit(void) -{ - platform_driver_unregister(&intc_irqpin_device_driver); -} -module_exit(intc_irqpin_exit); - -MODULE_AUTHOR("Magnus Damm"); -MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/irqchip/irq-renesas-irqc.c b/trunk/drivers/irqchip/irq-renesas-irqc.c deleted file mode 100644 index 927bff373aac..000000000000 --- a/trunk/drivers/irqchip/irq-renesas-irqc.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Renesas IRQC Driver - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ - -#define IRQC_REQ_STS 0x00 -#define IRQC_EN_STS 0x04 -#define IRQC_EN_SET 0x08 -#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) -#define DETECT_STATUS 0x100 -#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) - -struct irqc_irq { - int hw_irq; - int requested_irq; - int domain_irq; - struct irqc_priv *p; -}; - -struct irqc_priv { - void __iomem *iomem; - void __iomem *cpu_int_base; - struct irqc_irq irq[IRQC_IRQ_MAX]; - struct renesas_irqc_config config; - unsigned int number_of_irqs; - struct platform_device *pdev; - struct irq_chip irq_chip; - struct irq_domain *irq_domain; -}; - -static void irqc_dbg(struct irqc_irq *i, char *str) -{ - dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", - str, i->requested_irq, i->hw_irq, i->domain_irq); -} - -static void irqc_irq_enable(struct irq_data *d) -{ - struct irqc_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - irqc_dbg(&p->irq[hw_irq], "enable"); - iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); -} - -static void irqc_irq_disable(struct irq_data *d) -{ - struct irqc_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - - irqc_dbg(&p->irq[hw_irq], "disable"); - iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); -} - -#define INTC_IRQ_SENSE_VALID 0x10 -#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) - -static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { - [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), - [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), - [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ - [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ - [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ -}; - -static int irqc_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct irqc_priv *p = irq_data_get_irq_chip_data(d); - int hw_irq = irqd_to_hwirq(d); - unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; - unsigned long tmp; - - irqc_dbg(&p->irq[hw_irq], "sense"); - - if (!(value & INTC_IRQ_SENSE_VALID)) - return -EINVAL; - - tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); - tmp &= ~0x3f; - tmp |= value ^ INTC_IRQ_SENSE_VALID; - iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); - return 0; -} - -static irqreturn_t irqc_irq_handler(int irq, void *dev_id) -{ - struct irqc_irq *i = dev_id; - struct irqc_priv *p = i->p; - unsigned long bit = BIT(i->hw_irq); - - irqc_dbg(i, "demux1"); - - if (ioread32(p->iomem + DETECT_STATUS) & bit) { - iowrite32(bit, p->iomem + DETECT_STATUS); - irqc_dbg(i, "demux2"); - generic_handle_irq(i->domain_irq); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct irqc_priv *p = h->host_data; - - p->irq[hw].domain_irq = virq; - p->irq[hw].hw_irq = hw; - - irqc_dbg(&p->irq[hw], "map"); - irq_set_chip_data(virq, h->host_data); - irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); - set_irq_flags(virq, IRQF_VALID); /* kill me now */ - return 0; -} - -static struct irq_domain_ops irqc_irq_domain_ops = { - .map = irqc_irq_domain_map, - .xlate = irq_domain_xlate_twocell, -}; - -static int irqc_probe(struct platform_device *pdev) -{ - struct renesas_irqc_config *pdata = pdev->dev.platform_data; - struct irqc_priv *p; - struct resource *io; - struct resource *irq; - struct irq_chip *irq_chip; - const char *name = dev_name(&pdev->dev); - int ret; - int k; - - p = kzalloc(sizeof(*p), GFP_KERNEL); - if (!p) { - dev_err(&pdev->dev, "failed to allocate driver data\n"); - ret = -ENOMEM; - goto err0; - } - - /* deal with driver instance configuration */ - if (pdata) - memcpy(&p->config, pdata, sizeof(*pdata)); - - p->pdev = pdev; - platform_set_drvdata(pdev, p); - - /* get hold of manadatory IOMEM */ - io = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!io) { - dev_err(&pdev->dev, "not enough IOMEM resources\n"); - ret = -EINVAL; - goto err1; - } - - /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ - for (k = 0; k < IRQC_IRQ_MAX; k++) { - irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); - if (!irq) - break; - - p->irq[k].p = p; - p->irq[k].requested_irq = irq->start; - } - - p->number_of_irqs = k; - if (p->number_of_irqs < 1) { - dev_err(&pdev->dev, "not enough IRQ resources\n"); - ret = -EINVAL; - goto err1; - } - - /* ioremap IOMEM and setup read/write callbacks */ - p->iomem = ioremap_nocache(io->start, resource_size(io)); - if (!p->iomem) { - dev_err(&pdev->dev, "failed to remap IOMEM\n"); - ret = -ENXIO; - goto err2; - } - - p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ - - irq_chip = &p->irq_chip; - irq_chip->name = name; - irq_chip->irq_mask = irqc_irq_disable; - irq_chip->irq_unmask = irqc_irq_enable; - irq_chip->irq_enable = irqc_irq_enable; - irq_chip->irq_disable = irqc_irq_disable; - irq_chip->irq_set_type = irqc_irq_set_type; - irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; - - p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, - p->number_of_irqs, - p->config.irq_base, - &irqc_irq_domain_ops, p); - if (!p->irq_domain) { - ret = -ENXIO; - dev_err(&pdev->dev, "cannot initialize irq domain\n"); - goto err2; - } - - /* request interrupts one by one */ - for (k = 0; k < p->number_of_irqs; k++) { - if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, - 0, name, &p->irq[k])) { - dev_err(&pdev->dev, "failed to request IRQ\n"); - ret = -ENOENT; - goto err3; - } - } - - dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); - - /* warn in case of mismatch if irq base is specified */ - if (p->config.irq_base) { - if (p->config.irq_base != p->irq[0].domain_irq) - dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", - p->config.irq_base, p->irq[0].domain_irq); - } - - return 0; -err3: - for (; k >= 0; k--) - free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); - - irq_domain_remove(p->irq_domain); -err2: - iounmap(p->iomem); -err1: - kfree(p); -err0: - return ret; -} - -static int irqc_remove(struct platform_device *pdev) -{ - struct irqc_priv *p = platform_get_drvdata(pdev); - int k; - - for (k = 0; k < p->number_of_irqs; k++) - free_irq(p->irq[k].requested_irq, &p->irq[k]); - - irq_domain_remove(p->irq_domain); - iounmap(p->iomem); - kfree(p); - return 0; -} - -static const struct of_device_id irqc_dt_ids[] = { - { .compatible = "renesas,irqc", }, - {}, -}; -MODULE_DEVICE_TABLE(of, irqc_dt_ids); - -static struct platform_driver irqc_device_driver = { - .probe = irqc_probe, - .remove = irqc_remove, - .driver = { - .name = "renesas_irqc", - .of_match_table = irqc_dt_ids, - .owner = THIS_MODULE, - } -}; - -static int __init irqc_init(void) -{ - return platform_driver_register(&irqc_device_driver); -} -postcore_initcall(irqc_init); - -static void __exit irqc_exit(void) -{ - platform_driver_unregister(&irqc_device_driver); -} -module_exit(irqc_exit); - -MODULE_AUTHOR("Magnus Damm"); -MODULE_DESCRIPTION("Renesas IRQC Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/irqchip/irq-vic.c b/trunk/drivers/irqchip/irq-vic.c index 884d11c7355f..3cf97aaebe40 100644 --- a/trunk/drivers/irqchip/irq-vic.c +++ b/trunk/drivers/irqchip/irq-vic.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,7 @@ #include #include -#include +#include #include "irqchip.h" diff --git a/trunk/drivers/md/dm-cache-target.c b/trunk/drivers/md/dm-cache-target.c index 66120bd46d15..10744091e6ca 100644 --- a/trunk/drivers/md/dm-cache-target.c +++ b/trunk/drivers/md/dm-cache-target.c @@ -6,6 +6,7 @@ #include "dm.h" #include "dm-bio-prison.h" +#include "dm-bio-record.h" #include "dm-cache-metadata.h" #include @@ -201,10 +202,15 @@ struct per_bio_data { unsigned req_nr:2; struct dm_deferred_entry *all_io_entry; - /* writethrough fields */ + /* + * writethrough fields. These MUST remain at the end of this + * structure and the 'cache' member must be the first as it + * is used to determine the offsetof the writethrough fields. + */ struct cache *cache; dm_cblock_t cblock; bio_end_io_t *saved_bi_end_io; + struct dm_bio_details bio_details; }; struct dm_cache_migration { @@ -513,16 +519,28 @@ static void save_stats(struct cache *cache) /*---------------------------------------------------------------- * Per bio data *--------------------------------------------------------------*/ -static struct per_bio_data *get_per_bio_data(struct bio *bio) + +/* + * If using writeback, leave out struct per_bio_data's writethrough fields. + */ +#define PB_DATA_SIZE_WB (offsetof(struct per_bio_data, cache)) +#define PB_DATA_SIZE_WT (sizeof(struct per_bio_data)) + +static size_t get_per_bio_data_size(struct cache *cache) +{ + return cache->features.write_through ? PB_DATA_SIZE_WT : PB_DATA_SIZE_WB; +} + +static struct per_bio_data *get_per_bio_data(struct bio *bio, size_t data_size) { - struct per_bio_data *pb = dm_per_bio_data(bio, sizeof(struct per_bio_data)); + struct per_bio_data *pb = dm_per_bio_data(bio, data_size); BUG_ON(!pb); return pb; } -static struct per_bio_data *init_per_bio_data(struct bio *bio) +static struct per_bio_data *init_per_bio_data(struct bio *bio, size_t data_size) { - struct per_bio_data *pb = get_per_bio_data(bio); + struct per_bio_data *pb = get_per_bio_data(bio, data_size); pb->tick = false; pb->req_nr = dm_bio_get_target_bio_nr(bio); @@ -556,7 +574,8 @@ static void remap_to_cache(struct cache *cache, struct bio *bio, static void check_if_tick_bio_needed(struct cache *cache, struct bio *bio) { unsigned long flags; - struct per_bio_data *pb = get_per_bio_data(bio); + size_t pb_data_size = get_per_bio_data_size(cache); + struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size); spin_lock_irqsave(&cache->lock, flags); if (cache->need_tick_bio && @@ -635,7 +654,7 @@ static void defer_writethrough_bio(struct cache *cache, struct bio *bio) static void writethrough_endio(struct bio *bio, int err) { - struct per_bio_data *pb = get_per_bio_data(bio); + struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT); bio->bi_end_io = pb->saved_bi_end_io; if (err) { @@ -643,6 +662,7 @@ static void writethrough_endio(struct bio *bio, int err) return; } + dm_bio_restore(&pb->bio_details, bio); remap_to_cache(pb->cache, bio, pb->cblock); /* @@ -662,11 +682,12 @@ static void writethrough_endio(struct bio *bio, int err) static void remap_to_origin_then_cache(struct cache *cache, struct bio *bio, dm_oblock_t oblock, dm_cblock_t cblock) { - struct per_bio_data *pb = get_per_bio_data(bio); + struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT); pb->cache = cache; pb->cblock = cblock; pb->saved_bi_end_io = bio->bi_end_io; + dm_bio_record(&pb->bio_details, bio); bio->bi_end_io = writethrough_endio; remap_to_origin_clear_discard(pb->cache, bio, oblock); @@ -1035,7 +1056,8 @@ static void defer_bio(struct cache *cache, struct bio *bio) static void process_flush_bio(struct cache *cache, struct bio *bio) { - struct per_bio_data *pb = get_per_bio_data(bio); + size_t pb_data_size = get_per_bio_data_size(cache); + struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size); BUG_ON(bio->bi_size); if (!pb->req_nr) @@ -1107,7 +1129,8 @@ static void process_bio(struct cache *cache, struct prealloc *structs, dm_oblock_t block = get_bio_block(cache, bio); struct dm_bio_prison_cell *cell_prealloc, *old_ocell, *new_ocell; struct policy_result lookup_result; - struct per_bio_data *pb = get_per_bio_data(bio); + size_t pb_data_size = get_per_bio_data_size(cache); + struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size); bool discarded_block = is_discarded_oblock(cache, block); bool can_migrate = discarded_block || spare_migration_bandwidth(cache); @@ -1881,7 +1904,6 @@ static int cache_create(struct cache_args *ca, struct cache **result) cache->ti = ca->ti; ti->private = cache; - ti->per_bio_data_size = sizeof(struct per_bio_data); ti->num_flush_bios = 2; ti->flush_supported = true; @@ -1890,6 +1912,7 @@ static int cache_create(struct cache_args *ca, struct cache **result) ti->discard_zeroes_data_unsupported = true; memcpy(&cache->features, &ca->features, sizeof(cache->features)); + ti->per_bio_data_size = get_per_bio_data_size(cache); cache->callbacks.congested_fn = cache_is_congested; dm_table_add_target_callbacks(ti->table, &cache->callbacks); @@ -2092,6 +2115,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio) int r; dm_oblock_t block = get_bio_block(cache, bio); + size_t pb_data_size = get_per_bio_data_size(cache); bool can_migrate = false; bool discarded_block; struct dm_bio_prison_cell *cell; @@ -2108,7 +2132,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio) return DM_MAPIO_REMAPPED; } - pb = init_per_bio_data(bio); + pb = init_per_bio_data(bio, pb_data_size); if (bio->bi_rw & (REQ_FLUSH | REQ_FUA | REQ_DISCARD)) { defer_bio(cache, bio); @@ -2193,7 +2217,8 @@ static int cache_end_io(struct dm_target *ti, struct bio *bio, int error) { struct cache *cache = ti->private; unsigned long flags; - struct per_bio_data *pb = get_per_bio_data(bio); + size_t pb_data_size = get_per_bio_data_size(cache); + struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size); if (pb->tick) { policy_tick(cache->policy); diff --git a/trunk/drivers/media/platform/Kconfig b/trunk/drivers/media/platform/Kconfig index 05d7b6333461..a0639e779973 100644 --- a/trunk/drivers/media/platform/Kconfig +++ b/trunk/drivers/media/platform/Kconfig @@ -204,7 +204,7 @@ config VIDEO_SAMSUNG_EXYNOS_GSC config VIDEO_SH_VEU tristate "SuperH VEU mem2mem video processing driver" - depends on VIDEO_DEV && VIDEO_V4L2 + depends on VIDEO_DEV && VIDEO_V4L2 && GENERIC_HARDIRQS select VIDEOBUF2_DMA_CONTIG select V4L2_MEM2MEM_DEV help diff --git a/trunk/drivers/media/radio/radio-ma901.c b/trunk/drivers/media/radio/radio-ma901.c index c61f590029ad..348dafc0318a 100644 --- a/trunk/drivers/media/radio/radio-ma901.c +++ b/trunk/drivers/media/radio/radio-ma901.c @@ -347,9 +347,20 @@ static void usb_ma901radio_release(struct v4l2_device *v4l2_dev) static int usb_ma901radio_probe(struct usb_interface *intf, const struct usb_device_id *id) { + struct usb_device *dev = interface_to_usbdev(intf); struct ma901radio_device *radio; int retval = 0; + /* Masterkit MA901 usb radio has the same USB ID as many others + * Atmel V-USB devices. Let's make additional checks to be sure + * that this is our device. + */ + + if (dev->product && dev->manufacturer && + (strncmp(dev->product, "MA901", 5) != 0 + || strncmp(dev->manufacturer, "www.masterkit.ru", 16) != 0)) + return -ENODEV; + radio = kzalloc(sizeof(struct ma901radio_device), GFP_KERNEL); if (!radio) { dev_err(&intf->dev, "kzalloc for ma901radio_device failed\n"); diff --git a/trunk/drivers/net/bonding/bond_main.c b/trunk/drivers/net/bonding/bond_main.c index 6bbd90e1123c..171b10f167a5 100644 --- a/trunk/drivers/net/bonding/bond_main.c +++ b/trunk/drivers/net/bonding/bond_main.c @@ -1976,12 +1976,11 @@ static int __bond_release_one(struct net_device *bond_dev, return -EINVAL; } + write_unlock_bh(&bond->lock); /* unregister rx_handler early so bond_handle_frame wouldn't be called * for this slave anymore. */ netdev_rx_handler_unregister(slave_dev); - write_unlock_bh(&bond->lock); - synchronize_net(); write_lock_bh(&bond->lock); if (!all && !bond->params.fail_over_mac) { @@ -4903,8 +4902,8 @@ static void __exit bonding_exit(void) bond_destroy_debugfs(); - rtnl_link_unregister(&bond_link_ops); unregister_pernet_subsys(&bond_net_ops); + rtnl_link_unregister(&bond_link_ops); #ifdef CONFIG_NET_POLL_CONTROLLER /* diff --git a/trunk/drivers/net/bonding/bond_sysfs.c b/trunk/drivers/net/bonding/bond_sysfs.c index db103e03ba05..ea7a388f4843 100644 --- a/trunk/drivers/net/bonding/bond_sysfs.c +++ b/trunk/drivers/net/bonding/bond_sysfs.c @@ -527,7 +527,7 @@ static ssize_t bonding_store_arp_interval(struct device *d, goto out; } if (new_value < 0) { - pr_err("%s: Invalid arp_interval value %d not in range 1-%d; rejected.\n", + pr_err("%s: Invalid arp_interval value %d not in range 0-%d; rejected.\n", bond->dev->name, new_value, INT_MAX); ret = -EINVAL; goto out; @@ -542,14 +542,15 @@ static ssize_t bonding_store_arp_interval(struct device *d, pr_info("%s: Setting ARP monitoring interval to %d.\n", bond->dev->name, new_value); bond->params.arp_interval = new_value; - if (bond->params.miimon) { - pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n", - bond->dev->name, bond->dev->name); - bond->params.miimon = 0; - } - if (!bond->params.arp_targets[0]) { - pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n", - bond->dev->name); + if (new_value) { + if (bond->params.miimon) { + pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n", + bond->dev->name, bond->dev->name); + bond->params.miimon = 0; + } + if (!bond->params.arp_targets[0]) + pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n", + bond->dev->name); } if (bond->dev->flags & IFF_UP) { /* If the interface is up, we may need to fire off @@ -557,10 +558,13 @@ static ssize_t bonding_store_arp_interval(struct device *d, * timer will get fired off when the open function * is called. */ - cancel_delayed_work_sync(&bond->mii_work); - queue_delayed_work(bond->wq, &bond->arp_work, 0); + if (!new_value) { + cancel_delayed_work_sync(&bond->arp_work); + } else { + cancel_delayed_work_sync(&bond->mii_work); + queue_delayed_work(bond->wq, &bond->arp_work, 0); + } } - out: rtnl_unlock(); return ret; @@ -702,7 +706,7 @@ static ssize_t bonding_store_downdelay(struct device *d, } if (new_value < 0) { pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n", - bond->dev->name, new_value, 1, INT_MAX); + bond->dev->name, new_value, 0, INT_MAX); ret = -EINVAL; goto out; } else { @@ -757,8 +761,8 @@ static ssize_t bonding_store_updelay(struct device *d, goto out; } if (new_value < 0) { - pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n", - bond->dev->name, new_value, 1, INT_MAX); + pr_err("%s: Invalid up delay value %d not in range %d-%d; rejected.\n", + bond->dev->name, new_value, 0, INT_MAX); ret = -EINVAL; goto out; } else { @@ -968,37 +972,37 @@ static ssize_t bonding_store_miimon(struct device *d, } if (new_value < 0) { pr_err("%s: Invalid miimon value %d not in range %d-%d; rejected.\n", - bond->dev->name, new_value, 1, INT_MAX); + bond->dev->name, new_value, 0, INT_MAX); ret = -EINVAL; goto out; - } else { - pr_info("%s: Setting MII monitoring interval to %d.\n", - bond->dev->name, new_value); - bond->params.miimon = new_value; - if (bond->params.updelay) - pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n", - bond->dev->name, - bond->params.updelay * bond->params.miimon); - if (bond->params.downdelay) - pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n", - bond->dev->name, - bond->params.downdelay * bond->params.miimon); - if (bond->params.arp_interval) { - pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n", - bond->dev->name); - bond->params.arp_interval = 0; - if (bond->params.arp_validate) { - bond->params.arp_validate = - BOND_ARP_VALIDATE_NONE; - } - } - - if (bond->dev->flags & IFF_UP) { - /* If the interface is up, we may need to fire off - * the MII timer. If the interface is down, the - * timer will get fired off when the open function - * is called. - */ + } + pr_info("%s: Setting MII monitoring interval to %d.\n", + bond->dev->name, new_value); + bond->params.miimon = new_value; + if (bond->params.updelay) + pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n", + bond->dev->name, + bond->params.updelay * bond->params.miimon); + if (bond->params.downdelay) + pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n", + bond->dev->name, + bond->params.downdelay * bond->params.miimon); + if (new_value && bond->params.arp_interval) { + pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n", + bond->dev->name); + bond->params.arp_interval = 0; + if (bond->params.arp_validate) + bond->params.arp_validate = BOND_ARP_VALIDATE_NONE; + } + if (bond->dev->flags & IFF_UP) { + /* If the interface is up, we may need to fire off + * the MII timer. If the interface is down, the + * timer will get fired off when the open function + * is called. + */ + if (!new_value) { + cancel_delayed_work_sync(&bond->mii_work); + } else { cancel_delayed_work_sync(&bond->arp_work); queue_delayed_work(bond->wq, &bond->mii_work, 0); } diff --git a/trunk/drivers/net/can/sja1000/Kconfig b/trunk/drivers/net/can/sja1000/Kconfig index b39ca5b3ea7f..ff2ba86cd4a4 100644 --- a/trunk/drivers/net/can/sja1000/Kconfig +++ b/trunk/drivers/net/can/sja1000/Kconfig @@ -46,6 +46,7 @@ config CAN_EMS_PCI config CAN_PEAK_PCMCIA tristate "PEAK PCAN-PC Card" depends on PCMCIA + depends on HAS_IOPORT ---help--- This driver is for the PCAN-PC Card PCMCIA adapter (1 or 2 channels) from PEAK-System (http://www.peak-system.com). To compile this diff --git a/trunk/drivers/net/can/sja1000/plx_pci.c b/trunk/drivers/net/can/sja1000/plx_pci.c index a042cdc260dc..3c18d7d000ed 100644 --- a/trunk/drivers/net/can/sja1000/plx_pci.c +++ b/trunk/drivers/net/can/sja1000/plx_pci.c @@ -348,7 +348,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) */ if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == REG_CR_BASICCAN_INITIAL && - (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) && + (priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) && (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL)) flag = 1; @@ -360,7 +360,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) * See states on p. 23 of the Datasheet. */ if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL && - priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL && + priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL && priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL) return flag; diff --git a/trunk/drivers/net/can/sja1000/sja1000.c b/trunk/drivers/net/can/sja1000/sja1000.c index daf4013a8fc7..e4df307eaa90 100644 --- a/trunk/drivers/net/can/sja1000/sja1000.c +++ b/trunk/drivers/net/can/sja1000/sja1000.c @@ -92,7 +92,7 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val) */ spin_lock_irqsave(&priv->cmdreg_lock, flags); priv->write_reg(priv, REG_CMR, val); - priv->read_reg(priv, REG_SR); + priv->read_reg(priv, SJA1000_REG_SR); spin_unlock_irqrestore(&priv->cmdreg_lock, flags); } @@ -502,7 +502,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) { n++; - status = priv->read_reg(priv, REG_SR); + status = priv->read_reg(priv, SJA1000_REG_SR); /* check for absent controller due to hw unplug */ if (status == 0xFF && sja1000_is_absent(priv)) return IRQ_NONE; @@ -530,7 +530,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) /* receive interrupt */ while (status & SR_RBS) { sja1000_rx(dev); - status = priv->read_reg(priv, REG_SR); + status = priv->read_reg(priv, SJA1000_REG_SR); /* check for absent controller */ if (status == 0xFF && sja1000_is_absent(priv)) return IRQ_NONE; diff --git a/trunk/drivers/net/can/sja1000/sja1000.h b/trunk/drivers/net/can/sja1000/sja1000.h index afa99847a510..aa48e053da27 100644 --- a/trunk/drivers/net/can/sja1000/sja1000.h +++ b/trunk/drivers/net/can/sja1000/sja1000.h @@ -56,7 +56,7 @@ /* SJA1000 registers - manual section 6.4 (Pelican Mode) */ #define REG_MOD 0x00 #define REG_CMR 0x01 -#define REG_SR 0x02 +#define SJA1000_REG_SR 0x02 #define REG_IR 0x03 #define REG_IER 0x04 #define REG_ALC 0x0B diff --git a/trunk/drivers/net/ethernet/atheros/atl1e/atl1e.h b/trunk/drivers/net/ethernet/atheros/atl1e/atl1e.h index 829b5ad71d0d..b5fd934585e9 100644 --- a/trunk/drivers/net/ethernet/atheros/atl1e/atl1e.h +++ b/trunk/drivers/net/ethernet/atheros/atl1e/atl1e.h @@ -186,7 +186,7 @@ struct atl1e_tpd_desc { /* how about 0x2000 */ #define MAX_TX_BUF_LEN 0x2000 #define MAX_TX_BUF_SHIFT 13 -/*#define MAX_TX_BUF_LEN 0x3000 */ +#define MAX_TSO_SEG_SIZE 0x3c00 /* rrs word 1 bit 0:31 */ #define RRS_RX_CSUM_MASK 0xFFFF @@ -438,7 +438,6 @@ struct atl1e_adapter { struct atl1e_hw hw; struct atl1e_hw_stats hw_stats; - bool have_msi; u32 wol; u16 link_speed; u16 link_duplex; diff --git a/trunk/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/trunk/drivers/net/ethernet/atheros/atl1e/atl1e_main.c index 92f4734f860d..ac25f05ff68f 100644 --- a/trunk/drivers/net/ethernet/atheros/atl1e/atl1e_main.c +++ b/trunk/drivers/net/ethernet/atheros/atl1e/atl1e_main.c @@ -1849,34 +1849,19 @@ static void atl1e_free_irq(struct atl1e_adapter *adapter) struct net_device *netdev = adapter->netdev; free_irq(adapter->pdev->irq, netdev); - - if (adapter->have_msi) - pci_disable_msi(adapter->pdev); } static int atl1e_request_irq(struct atl1e_adapter *adapter) { struct pci_dev *pdev = adapter->pdev; struct net_device *netdev = adapter->netdev; - int flags = 0; int err = 0; - adapter->have_msi = true; - err = pci_enable_msi(pdev); - if (err) { - netdev_dbg(netdev, - "Unable to allocate MSI interrupt Error: %d\n", err); - adapter->have_msi = false; - } - - if (!adapter->have_msi) - flags |= IRQF_SHARED; - err = request_irq(pdev->irq, atl1e_intr, flags, netdev->name, netdev); + err = request_irq(pdev->irq, atl1e_intr, IRQF_SHARED, netdev->name, + netdev); if (err) { netdev_dbg(adapter->netdev, "Unable to allocate interrupt Error: %d\n", err); - if (adapter->have_msi) - pci_disable_msi(pdev); return err; } netdev_dbg(netdev, "atl1e_request_irq OK\n"); @@ -2344,6 +2329,7 @@ static int atl1e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) INIT_WORK(&adapter->reset_task, atl1e_reset_task); INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task); + netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE); err = register_netdev(netdev); if (err) { netdev_err(netdev, "register netdevice failed\n"); diff --git a/trunk/drivers/net/ethernet/broadcom/tg3.c b/trunk/drivers/net/ethernet/broadcom/tg3.c index 67d2663b3974..17a972734ba7 100644 --- a/trunk/drivers/net/ethernet/broadcom/tg3.c +++ b/trunk/drivers/net/ethernet/broadcom/tg3.c @@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp) if (j + len > block_end) goto partno; - memcpy(tp->fw_ver, &vpd_data[j], len); - strncat(tp->fw_ver, " bc ", vpdlen - len - 1); + if (len >= sizeof(tp->fw_ver)) + len = sizeof(tp->fw_ver) - 1; + memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); + snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, + &vpd_data[j]); } partno: diff --git a/trunk/drivers/net/ethernet/calxeda/xgmac.c b/trunk/drivers/net/ethernet/calxeda/xgmac.c index a170065b5973..b0ebc9f6d55e 100644 --- a/trunk/drivers/net/ethernet/calxeda/xgmac.c +++ b/trunk/drivers/net/ethernet/calxeda/xgmac.c @@ -163,6 +163,7 @@ #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ /* XGMAC_INT_STAT reg */ +#define XGMAC_INT_STAT_PMTIM 0x00800000 /* PMT Interrupt Mask */ #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */ #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */ @@ -960,6 +961,9 @@ static int xgmac_hw_init(struct net_device *dev) writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS); writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); + /* Mask power mgt interrupt */ + writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT); + /* XGMAC requires AXI bus init. This is a 'magic number' for now */ writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS); @@ -1141,6 +1145,9 @@ static int xgmac_rx(struct xgmac_priv *priv, int limit) struct sk_buff *skb; int frame_len; + if (!dma_ring_cnt(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ)) + break; + entry = priv->rx_tail; p = priv->dma_rx + entry; if (desc_get_owner(p)) @@ -1825,7 +1832,7 @@ static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode) unsigned int pmt = 0; if (mode & WAKE_MAGIC) - pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT; + pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT_EN; if (mode & WAKE_UCAST) pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST; diff --git a/trunk/drivers/net/ethernet/davicom/dm9000.c b/trunk/drivers/net/ethernet/davicom/dm9000.c index 8cdf02503d13..9eada8e86078 100644 --- a/trunk/drivers/net/ethernet/davicom/dm9000.c +++ b/trunk/drivers/net/ethernet/davicom/dm9000.c @@ -257,6 +257,107 @@ static void dm9000_dumpblk_32bit(void __iomem *reg, int count) tmp = readl(reg); } +/* + * Sleep, either by using msleep() or if we are suspending, then + * use mdelay() to sleep. + */ +static void dm9000_msleep(board_info_t *db, unsigned int ms) +{ + if (db->in_suspend) + mdelay(ms); + else + msleep(ms); +} + +/* Read a word from phyxcer */ +static int +dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) +{ + board_info_t *db = netdev_priv(dev); + unsigned long flags; + unsigned int reg_save; + int ret; + + mutex_lock(&db->addr_lock); + + spin_lock_irqsave(&db->lock, flags); + + /* Save previous register address */ + reg_save = readb(db->io_addr); + + /* Fill the phyxcer register into REG_0C */ + iow(db, DM9000_EPAR, DM9000_PHY | reg); + + /* Issue phyxcer read command */ + iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); + + writeb(reg_save, db->io_addr); + spin_unlock_irqrestore(&db->lock, flags); + + dm9000_msleep(db, 1); /* Wait read complete */ + + spin_lock_irqsave(&db->lock, flags); + reg_save = readb(db->io_addr); + + iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + + /* The read data keeps on REG_0D & REG_0E */ + ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); + + /* restore the previous address */ + writeb(reg_save, db->io_addr); + spin_unlock_irqrestore(&db->lock, flags); + + mutex_unlock(&db->addr_lock); + + dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); + return ret; +} + +/* Write a word to phyxcer */ +static void +dm9000_phy_write(struct net_device *dev, + int phyaddr_unused, int reg, int value) +{ + board_info_t *db = netdev_priv(dev); + unsigned long flags; + unsigned long reg_save; + + dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); + mutex_lock(&db->addr_lock); + + spin_lock_irqsave(&db->lock, flags); + + /* Save previous register address */ + reg_save = readb(db->io_addr); + + /* Fill the phyxcer register into REG_0C */ + iow(db, DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ + iow(db, DM9000_EPDRL, value); + iow(db, DM9000_EPDRH, value >> 8); + + /* Issue phyxcer write command */ + iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); + + writeb(reg_save, db->io_addr); + spin_unlock_irqrestore(&db->lock, flags); + + dm9000_msleep(db, 1); /* Wait write complete */ + + spin_lock_irqsave(&db->lock, flags); + reg_save = readb(db->io_addr); + + iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + + /* restore the previous address */ + writeb(reg_save, db->io_addr); + + spin_unlock_irqrestore(&db->lock, flags); + mutex_unlock(&db->addr_lock); +} + /* dm9000_set_io * * select the specified set of io routines to use with the @@ -795,6 +896,9 @@ dm9000_init_dm9000(struct net_device *dev) iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ + dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ + dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */ + ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0; /* if wol is needed, then always set NCR_WAKEEN otherwise we end @@ -1201,109 +1305,6 @@ dm9000_open(struct net_device *dev) return 0; } -/* - * Sleep, either by using msleep() or if we are suspending, then - * use mdelay() to sleep. - */ -static void dm9000_msleep(board_info_t *db, unsigned int ms) -{ - if (db->in_suspend) - mdelay(ms); - else - msleep(ms); -} - -/* - * Read a word from phyxcer - */ -static int -dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) -{ - board_info_t *db = netdev_priv(dev); - unsigned long flags; - unsigned int reg_save; - int ret; - - mutex_lock(&db->addr_lock); - - spin_lock_irqsave(&db->lock,flags); - - /* Save previous register address */ - reg_save = readb(db->io_addr); - - /* Fill the phyxcer register into REG_0C */ - iow(db, DM9000_EPAR, DM9000_PHY | reg); - - iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */ - - writeb(reg_save, db->io_addr); - spin_unlock_irqrestore(&db->lock,flags); - - dm9000_msleep(db, 1); /* Wait read complete */ - - spin_lock_irqsave(&db->lock,flags); - reg_save = readb(db->io_addr); - - iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ - - /* The read data keeps on REG_0D & REG_0E */ - ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); - - /* restore the previous address */ - writeb(reg_save, db->io_addr); - spin_unlock_irqrestore(&db->lock,flags); - - mutex_unlock(&db->addr_lock); - - dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); - return ret; -} - -/* - * Write a word to phyxcer - */ -static void -dm9000_phy_write(struct net_device *dev, - int phyaddr_unused, int reg, int value) -{ - board_info_t *db = netdev_priv(dev); - unsigned long flags; - unsigned long reg_save; - - dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); - mutex_lock(&db->addr_lock); - - spin_lock_irqsave(&db->lock,flags); - - /* Save previous register address */ - reg_save = readb(db->io_addr); - - /* Fill the phyxcer register into REG_0C */ - iow(db, DM9000_EPAR, DM9000_PHY | reg); - - /* Fill the written data into REG_0D & REG_0E */ - iow(db, DM9000_EPDRL, value); - iow(db, DM9000_EPDRH, value >> 8); - - iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */ - - writeb(reg_save, db->io_addr); - spin_unlock_irqrestore(&db->lock, flags); - - dm9000_msleep(db, 1); /* Wait write complete */ - - spin_lock_irqsave(&db->lock,flags); - reg_save = readb(db->io_addr); - - iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ - - /* restore the previous address */ - writeb(reg_save, db->io_addr); - - spin_unlock_irqrestore(&db->lock, flags); - mutex_unlock(&db->addr_lock); -} - static void dm9000_shutdown(struct net_device *dev) { @@ -1502,7 +1503,12 @@ dm9000_probe(struct platform_device *pdev) db->flags |= DM9000_PLATF_SIMPLE_PHY; #endif - dm9000_reset(db); + /* Fixing bug on dm9000_probe, takeover dm9000_reset(db), + * Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo + * while probe stage. + */ + + iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST); /* try multiple times, DM9000 sometimes gets the read wrong */ for (i = 0; i < 8; i++) { diff --git a/trunk/drivers/net/ethernet/davicom/dm9000.h b/trunk/drivers/net/ethernet/davicom/dm9000.h index 55688bd1a3ef..9ce058adabab 100644 --- a/trunk/drivers/net/ethernet/davicom/dm9000.h +++ b/trunk/drivers/net/ethernet/davicom/dm9000.h @@ -69,7 +69,9 @@ #define NCR_WAKEEN (1<<6) #define NCR_FCOL (1<<4) #define NCR_FDX (1<<3) -#define NCR_LBK (3<<1) + +#define NCR_RESERVED (3<<1) +#define NCR_MAC_LBK (1<<1) #define NCR_RST (1<<0) #define NSR_SPEED (1<<7) @@ -167,5 +169,12 @@ #define ISR_LNKCHNG (1<<5) #define ISR_UNDERRUN (1<<4) +/* Davicom MII registers. + */ + +#define MII_DM_DSPCR 0x1b /* DSP Control Register */ + +#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */ + #endif /* _DM9000X_H_ */ diff --git a/trunk/drivers/net/ethernet/freescale/fec.c b/trunk/drivers/net/ethernet/freescale/fec.c index 911d0253dbb2..f292c3aa423f 100644 --- a/trunk/drivers/net/ethernet/freescale/fec.c +++ b/trunk/drivers/net/ethernet/freescale/fec.c @@ -345,6 +345,53 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) return NETDEV_TX_OK; } +/* Init RX & TX buffer descriptors + */ +static void fec_enet_bd_init(struct net_device *dev) +{ + struct fec_enet_private *fep = netdev_priv(dev); + struct bufdesc *bdp; + unsigned int i; + + /* Initialize the receive buffer descriptors. */ + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + + /* Initialize the BD for every fragment in the page. */ + if (bdp->cbd_bufaddr) + bdp->cbd_sc = BD_ENET_RX_EMPTY; + else + bdp->cbd_sc = 0; + bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + } + + /* Set the last buffer to wrap */ + bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); + bdp->cbd_sc |= BD_SC_WRAP; + + fep->cur_rx = fep->rx_bd_base; + + /* ...and the same for transmit */ + bdp = fep->tx_bd_base; + fep->cur_tx = bdp; + for (i = 0; i < TX_RING_SIZE; i++) { + + /* Initialize the BD for every fragment in the page. */ + bdp->cbd_sc = 0; + if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { + dev_kfree_skb_any(fep->tx_skbuff[i]); + fep->tx_skbuff[i] = NULL; + } + bdp->cbd_bufaddr = 0; + bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); + } + + /* Set the last buffer to wrap */ + bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); + bdp->cbd_sc |= BD_SC_WRAP; + fep->dirty_tx = bdp; +} + /* This function is called to start or restart the FEC during a link * change. This only happens when switching between half and full * duplex. @@ -388,6 +435,8 @@ fec_restart(struct net_device *ndev, int duplex) /* Set maximum receive buffer size. */ writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); + fec_enet_bd_init(ndev); + /* Set receive and transmit descriptor base. */ writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); if (fep->bufdesc_ex) @@ -397,7 +446,6 @@ fec_restart(struct net_device *ndev, int duplex) writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); - fep->cur_rx = fep->rx_bd_base; for (i = 0; i <= TX_RING_MOD_MASK; i++) { if (fep->tx_skbuff[i]) { @@ -1597,8 +1645,6 @@ static int fec_enet_init(struct net_device *ndev) { struct fec_enet_private *fep = netdev_priv(ndev); struct bufdesc *cbd_base; - struct bufdesc *bdp; - unsigned int i; /* Allocate memory for buffer descriptors. */ cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, @@ -1608,6 +1654,7 @@ static int fec_enet_init(struct net_device *ndev) return -ENOMEM; } + memset(cbd_base, 0, PAGE_SIZE); spin_lock_init(&fep->hw_lock); fep->netdev = ndev; @@ -1631,35 +1678,6 @@ static int fec_enet_init(struct net_device *ndev) writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); - /* Initialize the receive buffer descriptors. */ - bdp = fep->rx_bd_base; - for (i = 0; i < RX_RING_SIZE; i++) { - - /* Initialize the BD for every fragment in the page. */ - bdp->cbd_sc = 0; - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); - } - - /* Set the last buffer to wrap */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - - /* ...and the same for transmit */ - bdp = fep->tx_bd_base; - fep->cur_tx = bdp; - for (i = 0; i < TX_RING_SIZE; i++) { - - /* Initialize the BD for every fragment in the page. */ - bdp->cbd_sc = 0; - bdp->cbd_bufaddr = 0; - bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); - } - - /* Set the last buffer to wrap */ - bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); - bdp->cbd_sc |= BD_SC_WRAP; - fep->dirty_tx = bdp; - fec_restart(ndev, 0); return 0; diff --git a/trunk/drivers/net/ethernet/intel/e1000/e1000_ethtool.c b/trunk/drivers/net/ethernet/intel/e1000/e1000_ethtool.c index 43462d596a4e..ffd287196bf8 100644 --- a/trunk/drivers/net/ethernet/intel/e1000/e1000_ethtool.c +++ b/trunk/drivers/net/ethernet/intel/e1000/e1000_ethtool.c @@ -1053,6 +1053,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) txdr->buffer_info[i].dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); + if (dma_mapping_error(&pdev->dev, txdr->buffer_info[i].dma)) { + ret_val = 4; + goto err_nomem; + } tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma); tx_desc->lower.data = cpu_to_le32(skb->len); tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP | @@ -1069,7 +1073,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer), GFP_KERNEL); if (!rxdr->buffer_info) { - ret_val = 4; + ret_val = 5; goto err_nomem; } @@ -1077,7 +1081,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size, &rxdr->dma, GFP_KERNEL); if (!rxdr->desc) { - ret_val = 5; + ret_val = 6; goto err_nomem; } memset(rxdr->desc, 0, rxdr->size); @@ -1101,7 +1105,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL); if (!skb) { - ret_val = 6; + ret_val = 7; goto err_nomem; } skb_reserve(skb, NET_IP_ALIGN); @@ -1110,6 +1114,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter) rxdr->buffer_info[i].dma = dma_map_single(&pdev->dev, skb->data, E1000_RXBUFFER_2048, DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, rxdr->buffer_info[i].dma)) { + ret_val = 8; + goto err_nomem; + } rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma); memset(skb->data, 0x00, skb->len); } diff --git a/trunk/drivers/net/ethernet/intel/e1000e/netdev.c b/trunk/drivers/net/ethernet/intel/e1000e/netdev.c index 948b86ffa4f0..7e615e2bf7e6 100644 --- a/trunk/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/trunk/drivers/net/ethernet/intel/e1000e/netdev.c @@ -848,11 +848,16 @@ static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, } } - if (!buffer_info->dma) + if (!buffer_info->dma) { buffer_info->dma = dma_map_page(&pdev->dev, buffer_info->page, 0, PAGE_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { + adapter->alloc_rx_buff_failed++; + break; + } + } rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); diff --git a/trunk/drivers/net/ethernet/intel/ixgb/ixgb_main.c b/trunk/drivers/net/ethernet/intel/ixgb/ixgb_main.c index ea4808373435..b5f94abe3cff 100644 --- a/trunk/drivers/net/ethernet/intel/ixgb/ixgb_main.c +++ b/trunk/drivers/net/ethernet/intel/ixgb/ixgb_main.c @@ -2159,6 +2159,10 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter, int cleaned_count) skb->data, adapter->rx_buffer_len, DMA_FROM_DEVICE); + if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { + adapter->alloc_rx_buff_failed++; + break; + } rx_desc = IXGB_RX_DESC(*rx_ring, i); rx_desc->buff_addr = cpu_to_le64(buffer_info->dma); @@ -2168,7 +2172,8 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter, int cleaned_count) rx_desc->status = 0; - if (++i == rx_ring->count) i = 0; + if (++i == rx_ring->count) + i = 0; buffer_info = &rx_ring->buffer_info[i]; } diff --git a/trunk/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/trunk/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index db5611ae407e..79f4a26ea6cc 100644 --- a/trunk/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/trunk/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -7922,12 +7922,19 @@ static int __init ixgbe_init_module(void) ixgbe_dbg_init(); #endif /* CONFIG_DEBUG_FS */ + ret = pci_register_driver(&ixgbe_driver); + if (ret) { +#ifdef CONFIG_DEBUG_FS + ixgbe_dbg_exit(); +#endif /* CONFIG_DEBUG_FS */ + return ret; + } + #ifdef CONFIG_IXGBE_DCA dca_register_notify(&dca_notifier); #endif - ret = pci_register_driver(&ixgbe_driver); - return ret; + return 0; } module_init(ixgbe_init_module); diff --git a/trunk/drivers/net/ethernet/marvell/sky2.c b/trunk/drivers/net/ethernet/marvell/sky2.c index fc07ca35721b..6a0e671fcecd 100644 --- a/trunk/drivers/net/ethernet/marvell/sky2.c +++ b/trunk/drivers/net/ethernet/marvell/sky2.c @@ -1067,7 +1067,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); - tp = space - 2048/8; + tp = space - 8192/8; sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); } else { diff --git a/trunk/drivers/net/ethernet/marvell/sky2.h b/trunk/drivers/net/ethernet/marvell/sky2.h index 615ac63ea860..ec6dcd80152b 100644 --- a/trunk/drivers/net/ethernet/marvell/sky2.h +++ b/trunk/drivers/net/ethernet/marvell/sky2.h @@ -2074,7 +2074,7 @@ enum { GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ -#define GMAC_DEF_MSK GM_IS_TX_FF_UR +#define GMAC_DEF_MSK (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR) }; /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ diff --git a/trunk/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/trunk/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index f278b10ef714..30d78f806dc3 100644 --- a/trunk/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/trunk/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -411,8 +411,8 @@ static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac) { - unsigned int i; - for (i = ETH_ALEN - 1; i; --i) { + int i; + for (i = ETH_ALEN - 1; i >= 0; --i) { dst_mac[i] = src_mac & 0xff; src_mac >>= 8; } diff --git a/trunk/drivers/net/ethernet/micrel/ks8851.c b/trunk/drivers/net/ethernet/micrel/ks8851.c index 33bcb63d56a2..8fb481252e2c 100644 --- a/trunk/drivers/net/ethernet/micrel/ks8851.c +++ b/trunk/drivers/net/ethernet/micrel/ks8851.c @@ -528,7 +528,7 @@ static void ks8851_rx_pkts(struct ks8851_net *ks) for (; rxfc != 0; rxfc--) { rxh = ks8851_rdreg32(ks, KS_RXFHSR); rxstat = rxh & 0xffff; - rxlen = rxh >> 16; + rxlen = (rxh >> 16) & 0xfff; netif_dbg(ks, rx_status, ks->netdev, "rx: stat 0x%04x, len 0x%04x\n", rxstat, rxlen); diff --git a/trunk/drivers/net/ethernet/realtek/r8169.c b/trunk/drivers/net/ethernet/realtek/r8169.c index 28fb50a1e9c3..4ecbe64a758d 100644 --- a/trunk/drivers/net/ethernet/realtek/r8169.c +++ b/trunk/drivers/net/ethernet/realtek/r8169.c @@ -3818,6 +3818,30 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp) } } +static void rtl_speed_down(struct rtl8169_private *tp) +{ + u32 adv; + int lpa; + + rtl_writephy(tp, 0x1f, 0x0000); + lpa = rtl_readphy(tp, MII_LPA); + + if (lpa & (LPA_10HALF | LPA_10FULL)) + adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; + else if (lpa & (LPA_100HALF | LPA_100FULL)) + adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; + else + adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | + (tp->mii.supports_gmii ? + ADVERTISED_1000baseT_Half | + ADVERTISED_1000baseT_Full : 0); + + rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, + adv); +} + static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) { void __iomem *ioaddr = tp->mmio_addr; @@ -3848,9 +3872,7 @@ static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) return false; - rtl_writephy(tp, 0x1f, 0x0000); - rtl_writephy(tp, MII_BMCR, 0x0000); - + rtl_speed_down(tp); rtl_wol_suspend_quirk(tp); return true; diff --git a/trunk/drivers/net/ethernet/renesas/sh_eth.c b/trunk/drivers/net/ethernet/renesas/sh_eth.c index bf5e3cf97c4d..6ed333fe5c04 100644 --- a/trunk/drivers/net/ethernet/renesas/sh_eth.c +++ b/trunk/drivers/net/ethernet/renesas/sh_eth.c @@ -1216,10 +1216,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status) if (felic_stat & ECSR_LCHNG) { /* Link Changed */ if (mdp->cd->no_psr || mdp->no_ether_link) { - if (mdp->link == PHY_DOWN) - link_stat = 0; - else - link_stat = PHY_ST_LINK; + goto ignore_link; } else { link_stat = (sh_eth_read(ndev, PSR)); if (mdp->ether_link_active_low) @@ -1242,6 +1239,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status) } } +ignore_link: if (intr_status & EESR_TWB) { /* Write buck end. unused write back interrupt */ if (intr_status & EESR_TABT) /* Transmit Abort int */ @@ -1326,12 +1324,18 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_cpu_data *cd = mdp->cd; irqreturn_t ret = IRQ_NONE; - u32 intr_status = 0; + unsigned long intr_status; spin_lock(&mdp->lock); - /* Get interrpt stat */ + /* Get interrupt status */ intr_status = sh_eth_read(ndev, EESR); + /* Mask it with the interrupt mask, forcing ECI interrupt to be always + * enabled since it's the one that comes thru regardless of the mask, + * and we need to fully handle it in sh_eth_error() in order to quench + * it as it doesn't get cleared by just writing 1 to the ECI bit... + */ + intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI; /* Clear interrupt */ if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | @@ -1373,7 +1377,7 @@ static void sh_eth_adjust_link(struct net_device *ndev) struct phy_device *phydev = mdp->phydev; int new_state = 0; - if (phydev->link != PHY_DOWN) { + if (phydev->link) { if (phydev->duplex != mdp->duplex) { new_state = 1; mdp->duplex = phydev->duplex; @@ -1387,17 +1391,21 @@ static void sh_eth_adjust_link(struct net_device *ndev) if (mdp->cd->set_rate) mdp->cd->set_rate(ndev); } - if (mdp->link == PHY_DOWN) { + if (!mdp->link) { sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); new_state = 1; mdp->link = phydev->link; + if (mdp->cd->no_psr || mdp->no_ether_link) + sh_eth_rcv_snd_enable(ndev); } } else if (mdp->link) { new_state = 1; - mdp->link = PHY_DOWN; + mdp->link = 0; mdp->speed = 0; mdp->duplex = -1; + if (mdp->cd->no_psr || mdp->no_ether_link) + sh_eth_rcv_snd_disable(ndev); } if (new_state && netif_msg_link(mdp)) @@ -1414,7 +1422,7 @@ static int sh_eth_phy_init(struct net_device *ndev) snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, mdp->mii_bus->id , mdp->phy_id); - mdp->link = PHY_DOWN; + mdp->link = 0; mdp->speed = 0; mdp->duplex = -1; diff --git a/trunk/drivers/net/ethernet/renesas/sh_eth.h b/trunk/drivers/net/ethernet/renesas/sh_eth.h index e6655678458e..828be4515008 100644 --- a/trunk/drivers/net/ethernet/renesas/sh_eth.h +++ b/trunk/drivers/net/ethernet/renesas/sh_eth.h @@ -723,7 +723,7 @@ struct sh_eth_private { u32 phy_id; /* PHY ID */ struct mii_bus *mii_bus; /* MDIO bus control */ struct phy_device *phydev; /* PHY device control */ - enum phy_state link; + int link; phy_interface_t phy_interface; int msg_enable; int speed; diff --git a/trunk/drivers/net/ethernet/ti/cpsw.c b/trunk/drivers/net/ethernet/ti/cpsw.c index df32a090d08e..80cad06e5eb2 100644 --- a/trunk/drivers/net/ethernet/ti/cpsw.c +++ b/trunk/drivers/net/ethernet/ti/cpsw.c @@ -436,7 +436,7 @@ void cpsw_tx_handler(void *token, int len, int status) * queue is stopped then start the queue as we have free desc for tx */ if (unlikely(netif_queue_stopped(ndev))) - netif_start_queue(ndev); + netif_wake_queue(ndev); cpts_tx_timestamp(priv->cpts, skb); priv->stats.tx_packets++; priv->stats.tx_bytes += len; diff --git a/trunk/drivers/net/ethernet/ti/davinci_emac.c b/trunk/drivers/net/ethernet/ti/davinci_emac.c index ae1b77aa199f..72300bc9e378 100644 --- a/trunk/drivers/net/ethernet/ti/davinci_emac.c +++ b/trunk/drivers/net/ethernet/ti/davinci_emac.c @@ -1053,7 +1053,7 @@ static void emac_tx_handler(void *token, int len, int status) * queue is stopped then start the queue as we have free desc for tx */ if (unlikely(netif_queue_stopped(ndev))) - netif_start_queue(ndev); + netif_wake_queue(ndev); ndev->stats.tx_packets++; ndev->stats.tx_bytes += len; dev_kfree_skb_any(skb); diff --git a/trunk/drivers/net/usb/smsc75xx.c b/trunk/drivers/net/usb/smsc75xx.c index 9abe51710f22..1a15ec14c386 100644 --- a/trunk/drivers/net/usb/smsc75xx.c +++ b/trunk/drivers/net/usb/smsc75xx.c @@ -914,8 +914,12 @@ static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size) static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu) { struct usbnet *dev = netdev_priv(netdev); + int ret; + + if (new_mtu > MAX_SINGLE_PACKET_SIZE) + return -EINVAL; - int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu); + ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN); if (ret < 0) { netdev_warn(dev->net, "Failed to set mac rx frame length\n"); return ret; @@ -1324,7 +1328,7 @@ static int smsc75xx_reset(struct usbnet *dev) netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf); - ret = smsc75xx_set_rx_max_frame_length(dev, 1514); + ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN); if (ret < 0) { netdev_warn(dev->net, "Failed to set max rx frame length\n"); return ret; @@ -2134,8 +2138,8 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT)) dev->net->stats.rx_frame_errors++; } else { - /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */ - if (unlikely(size > (ETH_FRAME_LEN + 12))) { + /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */ + if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) { netif_dbg(dev, rx_err, dev->net, "size err rx_cmd_a=0x%08x\n", rx_cmd_a); diff --git a/trunk/drivers/net/wireless/ath/ath9k/link.c b/trunk/drivers/net/wireless/ath/ath9k/link.c index 39c84ecf6a42..7fdac6c7b3ea 100644 --- a/trunk/drivers/net/wireless/ath/ath9k/link.c +++ b/trunk/drivers/net/wireless/ath/ath9k/link.c @@ -170,7 +170,8 @@ void ath_rx_poll(unsigned long data) { struct ath_softc *sc = (struct ath_softc *)data; - ieee80211_queue_work(sc->hw, &sc->hw_check_work); + if (!test_bit(SC_OP_INVALID, &sc->sc_flags)) + ieee80211_queue_work(sc->hw, &sc->hw_check_work); } /* diff --git a/trunk/drivers/net/wireless/b43/dma.c b/trunk/drivers/net/wireless/b43/dma.c index 38bc5a7997ff..122146943bf2 100644 --- a/trunk/drivers/net/wireless/b43/dma.c +++ b/trunk/drivers/net/wireless/b43/dma.c @@ -1487,8 +1487,12 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, const struct b43_dma_ops *ops; struct b43_dmaring *ring; struct b43_dmadesc_meta *meta; + static const struct b43_txstatus fake; /* filled with 0 */ + const struct b43_txstatus *txstat; int slot, firstused; bool frame_succeed; + int skip; + static u8 err_out1, err_out2; ring = parse_cookie(dev, status->cookie, &slot); if (unlikely(!ring)) @@ -1501,13 +1505,36 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, firstused = ring->current_slot - ring->used_slots + 1; if (firstused < 0) firstused = ring->nr_slots + firstused; + + skip = 0; if (unlikely(slot != firstused)) { /* This possibly is a firmware bug and will result in - * malfunction, memory leaks and/or stall of DMA functionality. */ - b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. " - "Expected %d, but got %d\n", - ring->index, firstused, slot); - return; + * malfunction, memory leaks and/or stall of DMA functionality. + */ + if (slot == next_slot(ring, next_slot(ring, firstused))) { + /* If a single header/data pair was missed, skip over + * the first two slots in an attempt to recover. + */ + slot = firstused; + skip = 2; + if (!err_out1) { + /* Report the error once. */ + b43dbg(dev->wl, + "Skip on DMA ring %d slot %d.\n", + ring->index, slot); + err_out1 = 1; + } + } else { + /* More than a single header/data pair were missed. + * Report this error once. + */ + if (!err_out2) + b43dbg(dev->wl, + "Out of order TX status report on DMA ring %d. Expected %d, but got %d\n", + ring->index, firstused, slot); + err_out2 = 1; + return; + } } ops = ring->ops; @@ -1522,11 +1549,13 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, slot, firstused, ring->index); break; } + if (meta->skb) { struct b43_private_tx_info *priv_info = - b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb)); + b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb)); - unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1); + unmap_descbuffer(ring, meta->dmaaddr, + meta->skb->len, 1); kfree(priv_info->bouncebuffer); priv_info->bouncebuffer = NULL; } else { @@ -1538,8 +1567,9 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, struct ieee80211_tx_info *info; if (unlikely(!meta->skb)) { - /* This is a scatter-gather fragment of a frame, so - * the skb pointer must not be NULL. */ + /* This is a scatter-gather fragment of a frame, + * so the skb pointer must not be NULL. + */ b43dbg(dev->wl, "TX status unexpected NULL skb " "at slot %d (first=%d) on ring %d\n", slot, firstused, ring->index); @@ -1550,9 +1580,18 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, /* * Call back to inform the ieee80211 subsystem about - * the status of the transmission. + * the status of the transmission. When skipping over + * a missed TX status report, use a status structure + * filled with zeros to indicate that the frame was not + * sent (frame_count 0) and not acknowledged */ - frame_succeed = b43_fill_txstatus_report(dev, info, status); + if (unlikely(skip)) + txstat = &fake; + else + txstat = status; + + frame_succeed = b43_fill_txstatus_report(dev, info, + txstat); #ifdef CONFIG_B43_DEBUG if (frame_succeed) ring->nr_succeed_tx_packets++; @@ -1580,12 +1619,14 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev, /* Everything unmapped and free'd. So it's not used anymore. */ ring->used_slots--; - if (meta->is_last_fragment) { + if (meta->is_last_fragment && !skip) { /* This is the last scatter-gather * fragment of the frame. We are done. */ break; } slot = next_slot(ring, slot); + if (skip > 0) + --skip; } if (ring->stopped) { B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME); diff --git a/trunk/drivers/net/wireless/b43/phy_n.c b/trunk/drivers/net/wireless/b43/phy_n.c index 3c35382ee6c2..e8486c1e091a 100644 --- a/trunk/drivers/net/wireless/b43/phy_n.c +++ b/trunk/drivers/net/wireless/b43/phy_n.c @@ -1564,7 +1564,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) u16 clip_off[2] = { 0xFFFF, 0xFFFF }; u8 vcm_final = 0; - s8 offset[4]; + s32 offset[4]; s32 results[8][4] = { }; s32 results_min[4] = { }; s32 poll_results[4] = { }; @@ -1615,7 +1615,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) } for (i = 0; i < 4; i += 2) { s32 curr; - s32 mind = 40; + s32 mind = 0x100000; s32 minpoll = 249; u8 minvcm = 0; if (2 * core != i) @@ -1732,7 +1732,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) u8 regs_save_radio[2]; u16 regs_save_phy[2]; - s8 offset[4]; + s32 offset[4]; u8 core; u8 rail; @@ -1799,7 +1799,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) } for (i = 0; i < 4; i++) { - s32 mind = 40; + s32 mind = 0x100000; u8 minvcm = 0; s32 minpoll = 249; s32 curr; diff --git a/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c b/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c index 21a824232478..18d37645e2cd 100644 --- a/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c +++ b/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c @@ -1137,9 +1137,8 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi, gain0_15 = ((biq1 & 0xf) << 12) | ((tia & 0xf) << 8) | ((lna2 & 0x3) << 6) | - ((lna2 & 0x3) << 4) | - ((lna1 & 0x3) << 2) | - ((lna1 & 0x3) << 0); + ((lna2 & + 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0); mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0); mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0); @@ -1157,8 +1156,6 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi, } mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0); - mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11); - mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3); } @@ -1331,43 +1328,6 @@ static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi, u16 nsamples) return (iq_est.i_pwr + iq_est.q_pwr) / nsamples; } -static bool wlc_lcnphy_rx_iq_cal_gain(struct brcms_phy *pi, u16 biq1_gain, - u16 tia_gain, u16 lna2_gain) -{ - u32 i_thresh_l, q_thresh_l; - u32 i_thresh_h, q_thresh_h; - struct lcnphy_iq_est iq_est_h, iq_est_l; - - wlc_lcnphy_set_rx_gain_by_distribution(pi, 0, 0, 0, biq1_gain, tia_gain, - lna2_gain, 0); - - wlc_lcnphy_rx_gain_override_enable(pi, true); - wlc_lcnphy_start_tx_tone(pi, 2000, (40 >> 1), 0); - udelay(500); - write_radio_reg(pi, RADIO_2064_REG112, 0); - if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_l)) - return false; - - wlc_lcnphy_start_tx_tone(pi, 2000, 40, 0); - udelay(500); - write_radio_reg(pi, RADIO_2064_REG112, 0); - if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_h)) - return false; - - i_thresh_l = (iq_est_l.i_pwr << 1); - i_thresh_h = (iq_est_l.i_pwr << 2) + iq_est_l.i_pwr; - - q_thresh_l = (iq_est_l.q_pwr << 1); - q_thresh_h = (iq_est_l.q_pwr << 2) + iq_est_l.q_pwr; - if ((iq_est_h.i_pwr > i_thresh_l) && - (iq_est_h.i_pwr < i_thresh_h) && - (iq_est_h.q_pwr > q_thresh_l) && - (iq_est_h.q_pwr < q_thresh_h)) - return true; - - return false; -} - static bool wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi, const struct lcnphy_rx_iqcomp *iqcomp, @@ -1382,8 +1342,8 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi, RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old, rfoverride3_old, rfoverride3val_old, rfoverride4_old, rfoverride4val_old, afectrlovr_old, afectrlovrval_old; - int tia_gain, lna2_gain, biq1_gain; - bool set_gain; + int tia_gain; + u32 received_power, rx_pwr_threshold; u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl; u16 values_to_save[11]; s16 *ptr; @@ -1408,134 +1368,126 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi, goto cal_done; } - WARN_ON(module != 1); - tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); - wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF); - - for (i = 0; i < 11; i++) - values_to_save[i] = - read_radio_reg(pi, rxiq_cal_rf_reg[i]); - Core1TxControl_old = read_phy_reg(pi, 0x631); - - or_phy_reg(pi, 0x631, 0x0015); - - RFOverride0_old = read_phy_reg(pi, 0x44c); - RFOverrideVal0_old = read_phy_reg(pi, 0x44d); - rfoverride2_old = read_phy_reg(pi, 0x4b0); - rfoverride2val_old = read_phy_reg(pi, 0x4b1); - rfoverride3_old = read_phy_reg(pi, 0x4f9); - rfoverride3val_old = read_phy_reg(pi, 0x4fa); - rfoverride4_old = read_phy_reg(pi, 0x938); - rfoverride4val_old = read_phy_reg(pi, 0x939); - afectrlovr_old = read_phy_reg(pi, 0x43b); - afectrlovrval_old = read_phy_reg(pi, 0x43c); - old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da); - old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db); - - tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi); - if (tx_gain_override_old) { - wlc_lcnphy_get_tx_gain(pi, &old_gains); - tx_gain_index_old = pi_lcn->lcnphy_current_index; - } - - wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx); + if (module == 1) { - mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0); - mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0); + tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi); + wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF); - mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1); - mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1); + for (i = 0; i < 11; i++) + values_to_save[i] = + read_radio_reg(pi, rxiq_cal_rf_reg[i]); + Core1TxControl_old = read_phy_reg(pi, 0x631); + + or_phy_reg(pi, 0x631, 0x0015); + + RFOverride0_old = read_phy_reg(pi, 0x44c); + RFOverrideVal0_old = read_phy_reg(pi, 0x44d); + rfoverride2_old = read_phy_reg(pi, 0x4b0); + rfoverride2val_old = read_phy_reg(pi, 0x4b1); + rfoverride3_old = read_phy_reg(pi, 0x4f9); + rfoverride3val_old = read_phy_reg(pi, 0x4fa); + rfoverride4_old = read_phy_reg(pi, 0x938); + rfoverride4val_old = read_phy_reg(pi, 0x939); + afectrlovr_old = read_phy_reg(pi, 0x43b); + afectrlovrval_old = read_phy_reg(pi, 0x43c); + old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da); + old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db); + + tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi); + if (tx_gain_override_old) { + wlc_lcnphy_get_tx_gain(pi, &old_gains); + tx_gain_index_old = pi_lcn->lcnphy_current_index; + } - write_radio_reg(pi, RADIO_2064_REG116, 0x06); - write_radio_reg(pi, RADIO_2064_REG12C, 0x07); - write_radio_reg(pi, RADIO_2064_REG06A, 0xd3); - write_radio_reg(pi, RADIO_2064_REG098, 0x03); - write_radio_reg(pi, RADIO_2064_REG00B, 0x7); - mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4); - write_radio_reg(pi, RADIO_2064_REG01D, 0x01); - write_radio_reg(pi, RADIO_2064_REG114, 0x01); - write_radio_reg(pi, RADIO_2064_REG02E, 0x10); - write_radio_reg(pi, RADIO_2064_REG12A, 0x08); - - mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0); - mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0); - mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1); - mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1); - mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2); - mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2); - mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3); - mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3); - mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5); - mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5); + wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx); - mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0); - mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0); + mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0); + mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0); - write_phy_reg(pi, 0x6da, 0xffff); - or_phy_reg(pi, 0x6db, 0x3); + mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1); + mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1); - wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch); - set_gain = false; - - lna2_gain = 3; - while ((lna2_gain >= 0) && !set_gain) { - tia_gain = 4; - - while ((tia_gain >= 0) && !set_gain) { - biq1_gain = 6; - - while ((biq1_gain >= 0) && !set_gain) { - set_gain = wlc_lcnphy_rx_iq_cal_gain(pi, - (u16) - biq1_gain, - (u16) - tia_gain, - (u16) - lna2_gain); - biq1_gain -= 1; - } + write_radio_reg(pi, RADIO_2064_REG116, 0x06); + write_radio_reg(pi, RADIO_2064_REG12C, 0x07); + write_radio_reg(pi, RADIO_2064_REG06A, 0xd3); + write_radio_reg(pi, RADIO_2064_REG098, 0x03); + write_radio_reg(pi, RADIO_2064_REG00B, 0x7); + mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4); + write_radio_reg(pi, RADIO_2064_REG01D, 0x01); + write_radio_reg(pi, RADIO_2064_REG114, 0x01); + write_radio_reg(pi, RADIO_2064_REG02E, 0x10); + write_radio_reg(pi, RADIO_2064_REG12A, 0x08); + + mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0); + mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0); + mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1); + mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1); + mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2); + mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2); + mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3); + mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3); + mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5); + mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5); + + mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0); + mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0); + + wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0); + write_phy_reg(pi, 0x6da, 0xffff); + or_phy_reg(pi, 0x6db, 0x3); + wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch); + wlc_lcnphy_rx_gain_override_enable(pi, true); + + tia_gain = 8; + rx_pwr_threshold = 950; + while (tia_gain > 0) { tia_gain -= 1; + wlc_lcnphy_set_rx_gain_by_distribution(pi, + 0, 0, 2, 2, + (u16) + tia_gain, 1, 0); + udelay(500); + + received_power = + wlc_lcnphy_measure_digital_power(pi, 2000); + if (received_power < rx_pwr_threshold) + break; } - lna2_gain -= 1; - } + result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff); - if (set_gain) - result = wlc_lcnphy_calc_rx_iq_comp(pi, 1024); - else - result = false; + wlc_lcnphy_stop_tx_tone(pi); - wlc_lcnphy_stop_tx_tone(pi); + write_phy_reg(pi, 0x631, Core1TxControl_old); - write_phy_reg(pi, 0x631, Core1TxControl_old); - - write_phy_reg(pi, 0x44c, RFOverrideVal0_old); - write_phy_reg(pi, 0x44d, RFOverrideVal0_old); - write_phy_reg(pi, 0x4b0, rfoverride2_old); - write_phy_reg(pi, 0x4b1, rfoverride2val_old); - write_phy_reg(pi, 0x4f9, rfoverride3_old); - write_phy_reg(pi, 0x4fa, rfoverride3val_old); - write_phy_reg(pi, 0x938, rfoverride4_old); - write_phy_reg(pi, 0x939, rfoverride4val_old); - write_phy_reg(pi, 0x43b, afectrlovr_old); - write_phy_reg(pi, 0x43c, afectrlovrval_old); - write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl); - write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl); + write_phy_reg(pi, 0x44c, RFOverrideVal0_old); + write_phy_reg(pi, 0x44d, RFOverrideVal0_old); + write_phy_reg(pi, 0x4b0, rfoverride2_old); + write_phy_reg(pi, 0x4b1, rfoverride2val_old); + write_phy_reg(pi, 0x4f9, rfoverride3_old); + write_phy_reg(pi, 0x4fa, rfoverride3val_old); + write_phy_reg(pi, 0x938, rfoverride4_old); + write_phy_reg(pi, 0x939, rfoverride4val_old); + write_phy_reg(pi, 0x43b, afectrlovr_old); + write_phy_reg(pi, 0x43c, afectrlovrval_old); + write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl); + write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl); - wlc_lcnphy_clear_trsw_override(pi); + wlc_lcnphy_clear_trsw_override(pi); - mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2); + mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2); - for (i = 0; i < 11; i++) - write_radio_reg(pi, rxiq_cal_rf_reg[i], - values_to_save[i]); + for (i = 0; i < 11; i++) + write_radio_reg(pi, rxiq_cal_rf_reg[i], + values_to_save[i]); - if (tx_gain_override_old) - wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old); - else - wlc_lcnphy_disable_tx_gain_override(pi); + if (tx_gain_override_old) + wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old); + else + wlc_lcnphy_disable_tx_gain_override(pi); - wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl); - wlc_lcnphy_rx_gain_override_enable(pi, false); + wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl); + wlc_lcnphy_rx_gain_override_enable(pi, false); + } cal_done: kfree(ptr); @@ -1829,17 +1781,6 @@ wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi, u8 channel) write_radio_reg(pi, RADIO_2064_REG038, 3); write_radio_reg(pi, RADIO_2064_REG091, 7); } - - if (!(pi->sh->boardflags & BFL_FEM)) { - u8 reg038[14] = {0xd, 0xe, 0xd, 0xd, 0xd, 0xc, - 0xa, 0xb, 0xb, 0x3, 0x3, 0x2, 0x0, 0x0}; - - write_radio_reg(pi, RADIO_2064_REG02A, 0xf); - write_radio_reg(pi, RADIO_2064_REG091, 0x3); - write_radio_reg(pi, RADIO_2064_REG038, 0x3); - - write_radio_reg(pi, RADIO_2064_REG038, reg038[channel - 1]); - } } static int @@ -2034,16 +1975,6 @@ wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos) } else { mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1); mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8); - mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0); - mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2); - mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0); - mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4); - mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0); - mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77); - mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1); - mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7); - mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1); - mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4); } } else { mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2); @@ -2130,14 +2061,12 @@ static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi) (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12)); mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5)); - mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0)); } static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) { struct phytbl_info tab; u32 rfseq, ind; - u8 tssi_sel; tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL; tab.tbl_width = 32; @@ -2159,13 +2088,7 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4); - if (pi->sh->boardflags & BFL_FEM) { - tssi_sel = 0x1; - wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT); - } else { - tssi_sel = 0xe; - wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_POST_PA); - } + wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT); mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14); mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15); @@ -2201,10 +2124,9 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0); if (LCNREV_IS(pi->pubpi.phy_rev, 2)) { - mod_radio_reg(pi, RADIO_2064_REG028, 0xf, tssi_sel); + mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe); mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4); } else { - mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, tssi_sel << 1); mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1); mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3); } @@ -2251,10 +2173,6 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8); - mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0); - mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0); - mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8); - wlc_lcnphy_pwrctrl_rssiparams(pi); } @@ -2873,8 +2791,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi) read_radio_reg(pi, RADIO_2064_REG007) & 1; u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10; u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4; - u8 SAVE_bbmult = wlc_lcnphy_get_bbmult(pi); - idleTssi = read_phy_reg(pi, 0x4ab); suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) & MCTL_EN_MAC)); @@ -2892,12 +2808,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi) mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4); mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2); wlc_lcnphy_tssi_setup(pi); - - mod_phy_reg(pi, 0x4d7, (0x1 << 0), (1 << 0)); - mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1 << 6)); - - wlc_lcnphy_set_bbmult(pi, 0x0); - wlc_phy_do_dummy_tx(pi, true, OFF); idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0)) >> 0); @@ -2919,7 +2829,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi) mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12); - wlc_lcnphy_set_bbmult(pi, SAVE_bbmult); wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old); wlc_lcnphy_set_tx_gain(pi, &old_gains); wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl); @@ -3133,11 +3042,6 @@ static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi) wlc_lcnphy_write_table(pi, &tab); tab.tbl_offset++; } - mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0); - mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0); - mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8); - mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4); - mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2); mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7); @@ -3939,6 +3843,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi) target_gains.pad_gain = 21; target_gains.dac_gain = 0; wlc_lcnphy_set_tx_gain(pi, &target_gains); + wlc_lcnphy_set_tx_pwr_by_index(pi, 16); if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) { @@ -3949,7 +3854,6 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi) lcnphy_recal ? LCNPHY_CAL_RECAL : LCNPHY_CAL_FULL), false); } else { - wlc_lcnphy_set_tx_pwr_by_index(pi, 16); wlc_lcnphy_tx_iqlo_soft_cal_full(pi); } @@ -4374,22 +4278,17 @@ wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi, if (CHSPEC_IS5G(pi->radio_chanspec)) pa_gain = 0x70; else - pa_gain = 0x60; + pa_gain = 0x70; if (pi->sh->boardflags & BFL_FEM) pa_gain = 0x10; - tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL; tab.tbl_width = 32; tab.tbl_len = 1; tab.tbl_ptr = &val; for (j = 0; j < 128; j++) { - if (pi->sh->boardflags & BFL_FEM) - gm_gain = gain_table[j].gm; - else - gm_gain = 15; - + gm_gain = gain_table[j].gm; val = (((u32) pa_gain << 24) | (gain_table[j].pad << 16) | (gain_table[j].pga << 8) | gm_gain); @@ -4600,10 +4499,7 @@ static void wlc_radio_2064_init(struct brcms_phy *pi) write_phy_reg(pi, 0x4ea, 0x4688); - if (pi->sh->boardflags & BFL_FEM) - mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0); - else - mod_phy_reg(pi, 0x4eb, (0x7 << 0), 3 << 0); + mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0); mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6); @@ -4614,13 +4510,6 @@ static void wlc_radio_2064_init(struct brcms_phy *pi) wlc_lcnphy_rcal(pi); wlc_lcnphy_rc_cal(pi); - - if (!(pi->sh->boardflags & BFL_FEM)) { - write_radio_reg(pi, RADIO_2064_REG032, 0x6f); - write_radio_reg(pi, RADIO_2064_REG033, 0x19); - write_radio_reg(pi, RADIO_2064_REG039, 0xe); - } - } static void wlc_lcnphy_radio_init(struct brcms_phy *pi) @@ -4650,20 +4539,22 @@ static void wlc_lcnphy_tbl_init(struct brcms_phy *pi) wlc_lcnphy_write_table(pi, &tab); } - if (!(pi->sh->boardflags & BFL_FEM)) { - tab.tbl_id = LCNPHY_TBL_ID_RFSEQ; - tab.tbl_width = 16; - tab.tbl_ptr = &val; - tab.tbl_len = 1; + tab.tbl_id = LCNPHY_TBL_ID_RFSEQ; + tab.tbl_width = 16; + tab.tbl_ptr = &val; + tab.tbl_len = 1; - val = 150; - tab.tbl_offset = 0; - wlc_lcnphy_write_table(pi, &tab); + val = 114; + tab.tbl_offset = 0; + wlc_lcnphy_write_table(pi, &tab); - val = 220; - tab.tbl_offset = 1; - wlc_lcnphy_write_table(pi, &tab); - } + val = 130; + tab.tbl_offset = 1; + wlc_lcnphy_write_table(pi, &tab); + + val = 6; + tab.tbl_offset = 8; + wlc_lcnphy_write_table(pi, &tab); if (CHSPEC_IS2G(pi->radio_chanspec)) { if (pi->sh->boardflags & BFL_FEM) @@ -5055,7 +4946,6 @@ void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec) wlc_lcnphy_load_tx_iir_filter(pi, true, 3); mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3); - wlc_lcnphy_tssi_setup(pi); } void wlc_phy_detach_lcnphy(struct brcms_phy *pi) @@ -5094,7 +4984,8 @@ bool wlc_phy_attach_lcnphy(struct brcms_phy *pi) if (!wlc_phy_txpwr_srom_read_lcnphy(pi)) return false; - if (LCNREV_IS(pi->pubpi.phy_rev, 1)) { + if ((pi->sh->boardflags & BFL_FEM) && + (LCNREV_IS(pi->pubpi.phy_rev, 1))) { if (pi_lcn->lcnphy_tempsense_option == 3) { pi->hwpwrctrl = true; pi->hwpwrctrl_capable = true; diff --git a/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c b/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c index b7e95acc2084..622c01ca72c5 100644 --- a/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c +++ b/trunk/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c @@ -1992,70 +1992,70 @@ static const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = { }; static const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = { - 0x0009, 0x000a, - 0x0005, - 0x0006, 0x0009, - 0x000a, - 0x0005, 0x0006, - 0x0009, - 0x000a, 0x0005, - 0x0006, - 0x0009, 0x000a, - 0x0005, - 0x0006, 0x0009, - 0x000a, - 0x0005, 0x0006, - 0x0009, - 0x000a, 0x0005, - 0x0006, - 0x0009, 0x000a, - 0x0005, - 0x0006, 0x0009, - 0x000a, - 0x0005, 0x0006, - 0x0009, - 0x000a, 0x0005, - 0x0006, - 0x0009, 0x000a, - 0x0005, - 0x0006, 0x0009, - 0x000a, - 0x0005, 0x0006, - 0x0009, - 0x000a, 0x0005, - 0x0006, + 0x000a, 0x0009, + 0x0006, + 0x0005, 0x000a, + 0x0009, + 0x0006, 0x0005, + 0x000a, + 0x0009, 0x0006, + 0x0005, + 0x000a, 0x0009, + 0x0006, + 0x0005, 0x000a, + 0x0009, + 0x0006, 0x0005, + 0x000a, + 0x0009, 0x0006, + 0x0005, + 0x000a, 0x0009, + 0x0006, + 0x0005, 0x000a, + 0x0009, + 0x0006, 0x0005, + 0x000a, + 0x0009, 0x0006, + 0x0005, + 0x000a, 0x0009, + 0x0006, + 0x0005, 0x000a, + 0x0009, + 0x0006, 0x0005, + 0x000a, + 0x0009, 0x0006, + 0x0005, }; static const u16 dot11lcn_sw_ctrl_tbl_rev0[] = { diff --git a/trunk/drivers/net/wireless/iwlegacy/4965-rs.c b/trunk/drivers/net/wireless/iwlegacy/4965-rs.c index e8324b5e5bfe..6c7493c2d698 100644 --- a/trunk/drivers/net/wireless/iwlegacy/4965-rs.c +++ b/trunk/drivers/net/wireless/iwlegacy/4965-rs.c @@ -2152,7 +2152,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf, int rate_idx; int i; u32 rate; - u8 use_green = il4965_rs_use_green(il, sta); + u8 use_green; u8 active_tbl = 0; u8 valid_tx_ant; struct il_station_priv *sta_priv; @@ -2160,6 +2160,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf, if (!sta || !lq_sta) return; + use_green = il4965_rs_use_green(il, sta); sta_priv = (void *)sta->drv_priv; i = lq_sta->last_txrate_idx; diff --git a/trunk/drivers/net/wireless/iwlwifi/dvm/lib.c b/trunk/drivers/net/wireless/iwlwifi/dvm/lib.c index 86ea5f4c3939..44ca0e57f9f7 100644 --- a/trunk/drivers/net/wireless/iwlwifi/dvm/lib.c +++ b/trunk/drivers/net/wireless/iwlwifi/dvm/lib.c @@ -1261,6 +1261,15 @@ int iwl_dvm_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) return -EIO; } + /* + * This can happen upon FW ASSERT: we clear the STATUS_FW_ERROR flag + * in iwl_down but cancel the workers only later. + */ + if (!priv->ucode_loaded) { + IWL_ERR(priv, "Fw not loaded - dropping CMD: %x\n", cmd->id); + return -EIO; + } + /* * Synchronous commands from this op-mode must hold * the mutex, this ensures we don't try to send two diff --git a/trunk/drivers/net/wireless/iwlwifi/dvm/rxon.c b/trunk/drivers/net/wireless/iwlwifi/dvm/rxon.c index 23be948cf162..a82b6b39d4ff 100644 --- a/trunk/drivers/net/wireless/iwlwifi/dvm/rxon.c +++ b/trunk/drivers/net/wireless/iwlwifi/dvm/rxon.c @@ -1419,6 +1419,14 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw, mutex_lock(&priv->mutex); + if (changes & BSS_CHANGED_IDLE && bss_conf->idle) { + /* + * If we go idle, then clearly no "passive-no-rx" + * workaround is needed any more, this is a reset. + */ + iwlagn_lift_passive_no_rx(priv); + } + if (unlikely(!iwl_is_ready(priv))) { IWL_DEBUG_MAC80211(priv, "leave - not ready\n"); mutex_unlock(&priv->mutex); @@ -1450,16 +1458,6 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw, priv->timestamp = bss_conf->sync_tsf; ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; } else { - /* - * If we disassociate while there are pending - * frames, just wake up the queues and let the - * frames "escape" ... This shouldn't really - * be happening to start with, but we should - * not get stuck in this case either since it - * can happen if userspace gets confused. - */ - iwlagn_lift_passive_no_rx(priv); - ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; if (ctx->ctxid == IWL_RXON_CTX_BSS) diff --git a/trunk/drivers/net/wireless/iwlwifi/dvm/tx.c b/trunk/drivers/net/wireless/iwlwifi/dvm/tx.c index 6aec2df3bb27..d1a670d7b10c 100644 --- a/trunk/drivers/net/wireless/iwlwifi/dvm/tx.c +++ b/trunk/drivers/net/wireless/iwlwifi/dvm/tx.c @@ -1192,7 +1192,7 @@ int iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_cmd_buffer *rxb, memset(&info->status, 0, sizeof(info->status)); if (status == TX_STATUS_FAIL_PASSIVE_NO_RX && - iwl_is_associated_ctx(ctx) && ctx->vif && + ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION) { /* block and stop all queues */ priv->passive_no_rx = true; diff --git a/trunk/drivers/net/wireless/iwlwifi/dvm/ucode.c b/trunk/drivers/net/wireless/iwlwifi/dvm/ucode.c index 736fe9bb140e..1a4ac9236a44 100644 --- a/trunk/drivers/net/wireless/iwlwifi/dvm/ucode.c +++ b/trunk/drivers/net/wireless/iwlwifi/dvm/ucode.c @@ -367,6 +367,8 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv, return -EIO; } + priv->ucode_loaded = true; + if (ucode_type != IWL_UCODE_WOWLAN) { /* delay a bit to give rfkill time to run */ msleep(5); @@ -380,8 +382,6 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv, return ret; } - priv->ucode_loaded = true; - return 0; } diff --git a/trunk/drivers/net/wireless/iwlwifi/pcie/trans.c b/trunk/drivers/net/wireless/iwlwifi/pcie/trans.c index 17bedc50e753..12c4f31ca8fb 100644 --- a/trunk/drivers/net/wireless/iwlwifi/pcie/trans.c +++ b/trunk/drivers/net/wireless/iwlwifi/pcie/trans.c @@ -475,6 +475,10 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, /* If platform's RF_KILL switch is NOT set to KILL */ hw_rfkill = iwl_is_rfkill_set(trans); + if (hw_rfkill) + set_bit(STATUS_RFKILL, &trans_pcie->status); + else + clear_bit(STATUS_RFKILL, &trans_pcie->status); iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); if (hw_rfkill && !run_in_rfkill) return -ERFKILL; @@ -641,6 +645,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) { + struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); bool hw_rfkill; int err; @@ -656,6 +661,10 @@ static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) iwl_enable_rfkill_int(trans); hw_rfkill = iwl_is_rfkill_set(trans); + if (hw_rfkill) + set_bit(STATUS_RFKILL, &trans_pcie->status); + else + clear_bit(STATUS_RFKILL, &trans_pcie->status); iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); return 0; @@ -694,6 +703,10 @@ static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans, * op_mode. */ hw_rfkill = iwl_is_rfkill_set(trans); + if (hw_rfkill) + set_bit(STATUS_RFKILL, &trans_pcie->status); + else + clear_bit(STATUS_RFKILL, &trans_pcie->status); iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill); } } diff --git a/trunk/drivers/net/wireless/iwlwifi/pcie/tx.c b/trunk/drivers/net/wireless/iwlwifi/pcie/tx.c index 8595c16f74de..cb5c6792e3a8 100644 --- a/trunk/drivers/net/wireless/iwlwifi/pcie/tx.c +++ b/trunk/drivers/net/wireless/iwlwifi/pcie/tx.c @@ -1264,7 +1264,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { int copy = 0; - if (!cmd->len) + if (!cmd->len[i]) continue; /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ diff --git a/trunk/drivers/net/wireless/mwifiex/cfg80211.c b/trunk/drivers/net/wireless/mwifiex/cfg80211.c index a44023a7bd57..8aaf56ade4d9 100644 --- a/trunk/drivers/net/wireless/mwifiex/cfg80211.c +++ b/trunk/drivers/net/wireless/mwifiex/cfg80211.c @@ -1892,7 +1892,8 @@ mwifiex_cfg80211_scan(struct wiphy *wiphy, } } - for (i = 0; i < request->n_channels; i++) { + for (i = 0; i < min_t(u32, request->n_channels, + MWIFIEX_USER_SCAN_CHAN_MAX); i++) { chan = request->channels[i]; priv->user_scan_cfg->chan_list[i].chan_number = chan->hw_value; priv->user_scan_cfg->chan_list[i].radio_type = chan->band; diff --git a/trunk/drivers/net/wireless/mwifiex/pcie.c b/trunk/drivers/net/wireless/mwifiex/pcie.c index 5c395e2e6a2b..feb204613397 100644 --- a/trunk/drivers/net/wireless/mwifiex/pcie.c +++ b/trunk/drivers/net/wireless/mwifiex/pcie.c @@ -1508,6 +1508,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) } memcpy(adapter->upld_buf, skb->data, min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); + skb_push(skb, INTF_HEADER_LEN); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, PCI_DMA_FROMDEVICE)) return -1; diff --git a/trunk/drivers/nfc/microread/mei.c b/trunk/drivers/nfc/microread/mei.c index eef38cfd812e..ca33ae193935 100644 --- a/trunk/drivers/nfc/microread/mei.c +++ b/trunk/drivers/nfc/microread/mei.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include @@ -32,9 +32,6 @@ #define MICROREAD_DRIVER_NAME "microread" -#define MICROREAD_UUID UUID_LE(0x0bb17a78, 0x2a8e, 0x4c50, 0x94, \ - 0xd4, 0x50, 0x26, 0x67, 0x23, 0x77, 0x5c) - struct mei_nfc_hdr { u8 cmd; u8 status; @@ -48,7 +45,7 @@ struct mei_nfc_hdr { #define MEI_NFC_MAX_READ (MEI_NFC_HEADER_SIZE + MEI_NFC_MAX_HCI_PAYLOAD) struct microread_mei_phy { - struct mei_device *mei_device; + struct mei_cl_device *device; struct nfc_hci_dev *hdev; int powered; @@ -105,14 +102,14 @@ static int microread_mei_write(void *phy_id, struct sk_buff *skb) MEI_DUMP_SKB_OUT("mei frame sent", skb); - r = mei_send(phy->device, skb->data, skb->len); + r = mei_cl_send(phy->device, skb->data, skb->len); if (r > 0) r = 0; return r; } -static void microread_event_cb(struct mei_device *device, u32 events, +static void microread_event_cb(struct mei_cl_device *device, u32 events, void *context) { struct microread_mei_phy *phy = context; @@ -120,7 +117,7 @@ static void microread_event_cb(struct mei_device *device, u32 events, if (phy->hard_fault != 0) return; - if (events & BIT(MEI_EVENT_RX)) { + if (events & BIT(MEI_CL_EVENT_RX)) { struct sk_buff *skb; int reply_size; @@ -128,7 +125,7 @@ static void microread_event_cb(struct mei_device *device, u32 events, if (!skb) return; - reply_size = mei_recv(device, skb->data, MEI_NFC_MAX_READ); + reply_size = mei_cl_recv(device, skb->data, MEI_NFC_MAX_READ); if (reply_size < MEI_NFC_HEADER_SIZE) { kfree(skb); return; @@ -149,8 +146,8 @@ static struct nfc_phy_ops mei_phy_ops = { .disable = microread_mei_disable, }; -static int microread_mei_probe(struct mei_device *device, - const struct mei_id *id) +static int microread_mei_probe(struct mei_cl_device *device, + const struct mei_cl_device_id *id) { struct microread_mei_phy *phy; int r; @@ -164,9 +161,9 @@ static int microread_mei_probe(struct mei_device *device, } phy->device = device; - mei_set_clientdata(device, phy); + mei_cl_set_drvdata(device, phy); - r = mei_register_event_cb(device, microread_event_cb, phy); + r = mei_cl_register_event_cb(device, microread_event_cb, phy); if (r) { pr_err(MICROREAD_DRIVER_NAME ": event cb registration failed\n"); goto err_out; @@ -186,9 +183,9 @@ static int microread_mei_probe(struct mei_device *device, return r; } -static int microread_mei_remove(struct mei_device *device) +static int microread_mei_remove(struct mei_cl_device *device) { - struct microread_mei_phy *phy = mei_get_clientdata(device); + struct microread_mei_phy *phy = mei_cl_get_drvdata(device); pr_info("Removing microread\n"); @@ -202,16 +199,15 @@ static int microread_mei_remove(struct mei_device *device) return 0; } -static struct mei_id microread_mei_tbl[] = { - { MICROREAD_DRIVER_NAME, MICROREAD_UUID }, +static struct mei_cl_device_id microread_mei_tbl[] = { + { MICROREAD_DRIVER_NAME }, /* required last entry */ { } }; - MODULE_DEVICE_TABLE(mei, microread_mei_tbl); -static struct mei_driver microread_driver = { +static struct mei_cl_driver microread_driver = { .id_table = microread_mei_tbl, .name = MICROREAD_DRIVER_NAME, @@ -225,7 +221,7 @@ static int microread_mei_init(void) pr_debug(DRIVER_DESC ": %s\n", __func__); - r = mei_driver_register(µread_driver); + r = mei_cl_driver_register(µread_driver); if (r) { pr_err(MICROREAD_DRIVER_NAME ": driver registration failed\n"); return r; @@ -236,7 +232,7 @@ static int microread_mei_init(void) static void microread_mei_exit(void) { - mei_driver_unregister(µread_driver); + mei_cl_driver_unregister(µread_driver); } module_init(microread_mei_init); diff --git a/trunk/drivers/pci/pci-acpi.c b/trunk/drivers/pci/pci-acpi.c index dee5dddaa292..5147c210df52 100644 --- a/trunk/drivers/pci/pci-acpi.c +++ b/trunk/drivers/pci/pci-acpi.c @@ -53,14 +53,15 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context) return; } - if (!pci_dev->pm_cap || !pci_dev->pme_support - || pci_check_pme_status(pci_dev)) { - if (pci_dev->pme_poll) - pci_dev->pme_poll = false; + /* Clear PME Status if set. */ + if (pci_dev->pme_support) + pci_check_pme_status(pci_dev); - pci_wakeup_event(pci_dev); - pm_runtime_resume(&pci_dev->dev); - } + if (pci_dev->pme_poll) + pci_dev->pme_poll = false; + + pci_wakeup_event(pci_dev); + pm_runtime_resume(&pci_dev->dev); if (pci_dev->subordinate) pci_pme_wakeup_bus(pci_dev->subordinate); diff --git a/trunk/drivers/pci/pci-driver.c b/trunk/drivers/pci/pci-driver.c index 1fa1e482a999..79277fb36c6b 100644 --- a/trunk/drivers/pci/pci-driver.c +++ b/trunk/drivers/pci/pci-driver.c @@ -390,9 +390,10 @@ static void pci_device_shutdown(struct device *dev) /* * Turn off Bus Master bit on the device to tell it to not - * continue to do DMA + * continue to do DMA. Don't touch devices in D3cold or unknown states. */ - pci_clear_master(pci_dev); + if (pci_dev->current_state <= PCI_D3hot) + pci_clear_master(pci_dev); } #ifdef CONFIG_PM diff --git a/trunk/drivers/pci/pcie/portdrv_pci.c b/trunk/drivers/pci/pcie/portdrv_pci.c index 08c243ab034e..ed4d09498337 100644 --- a/trunk/drivers/pci/pcie/portdrv_pci.c +++ b/trunk/drivers/pci/pcie/portdrv_pci.c @@ -184,14 +184,6 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { #define PCIE_PORTDRV_PM_OPS NULL #endif /* !PM */ -/* - * PCIe port runtime suspend is broken for some chipsets, so use a - * black list to disable runtime PM for these chipsets. - */ -static const struct pci_device_id port_runtime_pm_black_list[] = { - { /* end: all zeroes */ } -}; - /* * pcie_portdrv_probe - Probe PCI-Express port devices * @dev: PCI-Express port device being probed @@ -225,16 +217,11 @@ static int pcie_portdrv_probe(struct pci_dev *dev, * it by default. */ dev->d3cold_allowed = false; - if (!pci_match_id(port_runtime_pm_black_list, dev)) - pm_runtime_put_noidle(&dev->dev); - return 0; } static void pcie_portdrv_remove(struct pci_dev *dev) { - if (!pci_match_id(port_runtime_pm_black_list, dev)) - pm_runtime_get_noresume(&dev->dev); pcie_port_device_remove(dev); pci_disable_device(dev); } diff --git a/trunk/drivers/pci/rom.c b/trunk/drivers/pci/rom.c index b41ac7756a4b..c5d0a08a8747 100644 --- a/trunk/drivers/pci/rom.c +++ b/trunk/drivers/pci/rom.c @@ -100,27 +100,6 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) return min((size_t)(image - rom), size); } -static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size) -{ - struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; - loff_t start; - - /* assign the ROM an address if it doesn't have one */ - if (res->parent == NULL && pci_assign_resource(pdev, PCI_ROM_RESOURCE)) - return 0; - start = pci_resource_start(pdev, PCI_ROM_RESOURCE); - *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); - - if (*size == 0) - return 0; - - /* Enable ROM space decodes */ - if (pci_enable_rom(pdev)) - return 0; - - return start; -} - /** * pci_map_rom - map a PCI ROM to kernel space * @pdev: pointer to pci device struct @@ -135,7 +114,7 @@ static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size) void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) { struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; - loff_t start = 0; + loff_t start; void __iomem *rom; /* @@ -154,21 +133,21 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) return (void __iomem *)(unsigned long) pci_resource_start(pdev, PCI_ROM_RESOURCE); } else { - start = pci_find_rom(pdev, size); - } - } + /* assign the ROM an address if it doesn't have one */ + if (res->parent == NULL && + pci_assign_resource(pdev,PCI_ROM_RESOURCE)) + return NULL; + start = pci_resource_start(pdev, PCI_ROM_RESOURCE); + *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); + if (*size == 0) + return NULL; - /* - * Some devices may provide ROMs via a source other than the BAR - */ - if (!start && pdev->rom && pdev->romlen) { - *size = pdev->romlen; - return phys_to_virt(pdev->rom); + /* Enable ROM space decodes */ + if (pci_enable_rom(pdev)) + return NULL; + } } - if (!start) - return NULL; - rom = ioremap(start, *size); if (!rom) { /* restore enable if ioremap fails */ @@ -202,8 +181,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) return; - if (!pdev->rom || !pdev->romlen) - iounmap(rom); + iounmap(rom); /* Disable again before continuing, leave enabled if pci=rom */ if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) @@ -227,7 +205,24 @@ void pci_cleanup_rom(struct pci_dev *pdev) } } +/** + * pci_platform_rom - provides a pointer to any ROM image provided by the + * platform + * @pdev: pointer to pci device struct + * @size: pointer to receive size of pci window over ROM + */ +void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size) +{ + if (pdev->rom && pdev->romlen) { + *size = pdev->romlen; + return phys_to_virt((phys_addr_t)pdev->rom); + } + + return NULL; +} + EXPORT_SYMBOL(pci_map_rom); EXPORT_SYMBOL(pci_unmap_rom); EXPORT_SYMBOL_GPL(pci_enable_rom); EXPORT_SYMBOL_GPL(pci_disable_rom); +EXPORT_SYMBOL(pci_platform_rom); diff --git a/trunk/drivers/pinctrl/Kconfig b/trunk/drivers/pinctrl/Kconfig index 5a690ce6d60d..34f51d2d90d2 100644 --- a/trunk/drivers/pinctrl/Kconfig +++ b/trunk/drivers/pinctrl/Kconfig @@ -166,7 +166,6 @@ config PINCTRL_SINGLE depends on OF select PINMUX select PINCONF - select GENERIC_PINCONF help This selects the device tree based generic pinctrl driver. diff --git a/trunk/drivers/pinctrl/core.c b/trunk/drivers/pinctrl/core.c index f8a632dc877b..b0de6e7f1fdb 100644 --- a/trunk/drivers/pinctrl/core.c +++ b/trunk/drivers/pinctrl/core.c @@ -27,7 +27,6 @@ #include #include #include -#include #include "core.h" #include "devicetree.h" #include "pinmux.h" @@ -277,39 +276,6 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio) return NULL; } -/** - * pinctrl_ready_for_gpio_range() - check if other GPIO pins of - * the same GPIO chip are in range - * @gpio: gpio pin to check taken from the global GPIO pin space - * - * This function is complement of pinctrl_match_gpio_range(). If the return - * value of pinctrl_match_gpio_range() is NULL, this function could be used - * to check whether pinctrl device is ready or not. Maybe some GPIO pins - * of the same GPIO chip don't have back-end pinctrl interface. - * If the return value is true, it means that pinctrl device is ready & the - * certain GPIO pin doesn't have back-end pinctrl device. If the return value - * is false, it means that pinctrl device may not be ready. - */ -static bool pinctrl_ready_for_gpio_range(unsigned gpio) -{ - struct pinctrl_dev *pctldev; - struct pinctrl_gpio_range *range = NULL; - struct gpio_chip *chip = gpio_to_chip(gpio); - - /* Loop over the pin controllers */ - list_for_each_entry(pctldev, &pinctrldev_list, node) { - /* Loop over the ranges */ - list_for_each_entry(range, &pctldev->gpio_ranges, node) { - /* Check if any gpio range overlapped with gpio chip */ - if (range->base + range->npins - 1 < chip->base || - range->base > chip->base + chip->ngpio - 1) - continue; - return true; - } - } - return false; -} - /** * pinctrl_get_device_gpio_range() - find device for GPIO range * @gpio: the pin to locate the pin controller for @@ -477,8 +443,6 @@ int pinctrl_request_gpio(unsigned gpio) ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { - if (pinctrl_ready_for_gpio_range(gpio)) - ret = 0; mutex_unlock(&pinctrl_mutex); return ret; } @@ -1015,8 +979,9 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data) */ void devm_pinctrl_put(struct pinctrl *p) { - WARN_ON(devres_release(p->dev, devm_pinctrl_release, + WARN_ON(devres_destroy(p->dev, devm_pinctrl_release, devm_pinctrl_match, p)); + pinctrl_put(p); } EXPORT_SYMBOL_GPL(devm_pinctrl_put); diff --git a/trunk/drivers/pinctrl/devicetree.c b/trunk/drivers/pinctrl/devicetree.c index c7b7cb477129..fd40a11ad645 100644 --- a/trunk/drivers/pinctrl/devicetree.c +++ b/trunk/drivers/pinctrl/devicetree.c @@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { if (pctldev) { - const struct pinctrl_ops *ops = pctldev->desc->pctlops; + struct pinctrl_ops *ops = pctldev->desc->pctlops; ops->dt_free_map(pctldev, map, num_maps); } else { /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ @@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename, { struct device_node *np_pctldev; struct pinctrl_dev *pctldev; - const struct pinctrl_ops *ops; + struct pinctrl_ops *ops; int ret; struct pinctrl_map *map; unsigned num_maps; diff --git a/trunk/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/trunk/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 7f34a2b212d2..2d2f0a43d36b 100644 --- a/trunk/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/trunk/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, return; } -static const struct pinconf_ops mvebu_pinconf_ops = { +static struct pinconf_ops mvebu_pinconf_ops = { .pin_config_group_get = mvebu_pinconf_group_get, .pin_config_group_set = mvebu_pinconf_group_set, .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show, @@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, return -ENOTSUPP; } -static const struct pinmux_ops mvebu_pinmux_ops = { +static struct pinmux_ops mvebu_pinmux_ops = { .get_functions_count = mvebu_pinmux_get_funcs_count, .get_function_name = mvebu_pinmux_get_func_name, .get_function_groups = mvebu_pinmux_get_groups, @@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops mvebu_pinctrl_ops = { +static struct pinctrl_ops mvebu_pinctrl_ops = { .get_groups_count = mvebu_pinctrl_get_groups_count, .get_group_name = mvebu_pinctrl_get_group_name, .get_group_pins = mvebu_pinctrl_get_group_pins, diff --git a/trunk/drivers/pinctrl/pinconf-generic.c b/trunk/drivers/pinctrl/pinconf-generic.c index 9c436858812c..06c304ac6f7d 100644 --- a/trunk/drivers/pinctrl/pinconf-generic.c +++ b/trunk/drivers/pinctrl/pinconf-generic.c @@ -12,7 +12,6 @@ #define pr_fmt(fmt) "generic pinconfig core: " fmt #include -#include #include #include #include @@ -121,17 +120,4 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, } } -void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned long config) -{ - int i; - - for(i = 0; i < ARRAY_SIZE(conf_items); i++) { - if (pinconf_to_config_param(config) != conf_items[i].param) - continue; - seq_printf(s, "%s: 0x%x", conf_items[i].display, - pinconf_to_config_argument(config)); - } -} -EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); #endif diff --git a/trunk/drivers/pinctrl/pinconf.c b/trunk/drivers/pinctrl/pinconf.c index dae927f91088..d611ecfcbf70 100644 --- a/trunk/drivers/pinctrl/pinconf.c +++ b/trunk/drivers/pinctrl/pinconf.c @@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d) struct pinctrl_maps *maps_node; struct pinctrl_map const *map; struct pinctrl_dev *pctldev = NULL; - const struct pinconf_ops *confops = NULL; + struct pinconf_ops *confops = NULL; int i, j; bool found = false; diff --git a/trunk/drivers/pinctrl/pinconf.h b/trunk/drivers/pinctrl/pinconf.h index 92c7267244d2..bfda73d64eed 100644 --- a/trunk/drivers/pinctrl/pinconf.h +++ b/trunk/drivers/pinctrl/pinconf.h @@ -98,8 +98,6 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, struct seq_file *s, const char *gname); -void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned long config); #else static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, @@ -116,10 +114,4 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, return; } -static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned long config) -{ - return; -} #endif diff --git a/trunk/drivers/pinctrl/pinctrl-abx500.c b/trunk/drivers/pinctrl/pinctrl-abx500.c index 0cf3fa4a21ae..c542a97c82f3 100644 --- a/trunk/drivers/pinctrl/pinctrl-abx500.c +++ b/trunk/drivers/pinctrl/pinctrl-abx500.c @@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, { } -static const struct pinmux_ops abx500_pinmux_ops = { +static struct pinmux_ops abx500_pinmux_ops = { .get_functions_count = abx500_pmx_get_funcs_cnt, .get_function_name = abx500_pmx_get_func_name, .get_function_groups = abx500_pmx_get_func_groups, @@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, chip->base + offset - 1); } -static const struct pinctrl_ops abx500_pinctrl_ops = { +static struct pinctrl_ops abx500_pinctrl_ops = { .get_groups_count = abx500_get_groups_cnt, .get_group_name = abx500_get_group_name, .get_group_pins = abx500_get_group_pins, @@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev, return ret; } -static const struct pinconf_ops abx500_pinconf_ops = { +static struct pinconf_ops abx500_pinconf_ops = { .pin_config_get = abx500_pin_config_get, .pin_config_set = abx500_pin_config_set, }; @@ -834,7 +834,6 @@ static const struct of_device_id abx500_gpio_match[] = { { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, - { } }; static int abx500_gpio_probe(struct platform_device *pdev) diff --git a/trunk/drivers/pinctrl/pinctrl-at91.c b/trunk/drivers/pinctrl/pinctrl-at91.c index 49bdc4410075..efb7f10e902a 100644 --- a/trunk/drivers/pinctrl/pinctrl-at91.c +++ b/trunk/drivers/pinctrl/pinctrl-at91.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -28,6 +27,8 @@ /* Since we request GPIOs from ourself */ #include +#include + #include #include @@ -293,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev, { } -static const struct pinctrl_ops at91_pctrl_ops = { +static struct pinctrl_ops at91_pctrl_ops = { .get_groups_count = at91_get_groups_count, .get_group_name = at91_get_group_name, .get_group_pins = at91_get_group_pins, @@ -695,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, /* Set the pin to some default state, GPIO is usually default */ } -static const struct pinmux_ops at91_pmx_ops = { +static struct pinmux_ops at91_pmx_ops = { .get_functions_count = at91_pmx_get_funcs_count, .get_function_name = at91_pmx_get_func_name, .get_function_groups = at91_pmx_get_groups, @@ -775,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, { } -static const struct pinconf_ops at91_pinconf_ops = { +static struct pinconf_ops at91_pinconf_ops = { .pin_config_get = at91_pinconf_get, .pin_config_set = at91_pinconf_set, .pin_config_dbg_show = at91_pinconf_dbg_show, diff --git a/trunk/drivers/pinctrl/pinctrl-bcm2835.c b/trunk/drivers/pinctrl/pinctrl-bcm2835.c index f28d4b08771a..4eb6d2c4e4df 100644 --- a/trunk/drivers/pinctrl/pinctrl-bcm2835.c +++ b/trunk/drivers/pinctrl/pinctrl-bcm2835.c @@ -795,7 +795,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, return err; } -static const struct pinctrl_ops bcm2835_pctl_ops = { +static struct pinctrl_ops bcm2835_pctl_ops = { .get_groups_count = bcm2835_pctl_get_groups_count, .get_group_name = bcm2835_pctl_get_group_name, .get_group_pins = bcm2835_pctl_get_group_pins, @@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static const struct pinmux_ops bcm2835_pmx_ops = { +static struct pinmux_ops bcm2835_pmx_ops = { .get_functions_count = bcm2835_pmx_get_functions_count, .get_function_name = bcm2835_pmx_get_function_name, .get_function_groups = bcm2835_pmx_get_function_groups, @@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, return 0; } -static const struct pinconf_ops bcm2835_pinconf_ops = { +static struct pinconf_ops bcm2835_pinconf_ops = { .pin_config_get = bcm2835_pinconf_get, .pin_config_set = bcm2835_pinconf_set, }; diff --git a/trunk/drivers/pinctrl/pinctrl-exynos.c b/trunk/drivers/pinctrl/pinctrl-exynos.c index 7265e551dddb..538b9ddaadf7 100644 --- a/trunk/drivers/pinctrl/pinctrl-exynos.c +++ b/trunk/drivers/pinctrl/pinctrl-exynos.c @@ -23,12 +23,13 @@ #include #include #include -#include #include #include #include #include +#include + #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" diff --git a/trunk/drivers/pinctrl/pinctrl-exynos5440.c b/trunk/drivers/pinctrl/pinctrl-exynos5440.c index 169ea3e5f777..1376eb7305db 100644 --- a/trunk/drivers/pinctrl/pinctrl-exynos5440.c +++ b/trunk/drivers/pinctrl/pinctrl-exynos5440.c @@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, } /* list of pinctrl callbacks for the pinctrl core */ -static const struct pinctrl_ops exynos5440_pctrl_ops = { +static struct pinctrl_ops exynos5440_pctrl_ops = { .get_groups_count = exynos5440_get_group_count, .get_group_name = exynos5440_get_group_name, .get_group_pins = exynos5440_get_group_pins, @@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, } /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static const struct pinmux_ops exynos5440_pinmux_ops = { +static struct pinmux_ops exynos5440_pinmux_ops = { .get_functions_count = exynos5440_get_functions_count, .get_function_name = exynos5440_pinmux_get_fname, .get_function_groups = exynos5440_pinmux_get_groups, @@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, } /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static const struct pinconf_ops exynos5440_pinconf_ops = { +static struct pinconf_ops exynos5440_pinconf_ops = { .pin_config_get = exynos5440_pinconf_get, .pin_config_set = exynos5440_pinconf_set, .pin_config_group_get = exynos5440_pinconf_group_get, diff --git a/trunk/drivers/pinctrl/pinctrl-falcon.c b/trunk/drivers/pinctrl/pinctrl-falcon.c index f9b2a1d4854f..af97a1f90007 100644 --- a/trunk/drivers/pinctrl/pinctrl-falcon.c +++ b/trunk/drivers/pinctrl/pinctrl-falcon.c @@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, { } -static const struct pinconf_ops falcon_pinconf_ops = { +static struct pinconf_ops falcon_pinconf_ops = { .pin_config_get = falcon_pinconf_get, .pin_config_set = falcon_pinconf_set, .pin_config_group_get = falcon_pinconf_group_get, diff --git a/trunk/drivers/pinctrl/pinctrl-imx.c b/trunk/drivers/pinctrl/pinctrl-imx.c index 0ef190449eab..4cebb9c6c5c5 100644 --- a/trunk/drivers/pinctrl/pinctrl-imx.c +++ b/trunk/drivers/pinctrl/pinctrl-imx.c @@ -207,7 +207,7 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops imx_pctrl_ops = { +static struct pinctrl_ops imx_pctrl_ops = { .get_groups_count = imx_get_groups_count, .get_group_name = imx_get_group_name, .get_group_pins = imx_get_group_pins, @@ -299,7 +299,7 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static const struct pinmux_ops imx_pmx_ops = { +static struct pinmux_ops imx_pmx_ops = { .get_functions_count = imx_pmx_get_funcs_count, .get_function_name = imx_pmx_get_func_name, .get_function_groups = imx_pmx_get_groups, @@ -397,7 +397,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, } } -static const struct pinconf_ops imx_pinconf_ops = { +static struct pinconf_ops imx_pinconf_ops = { .pin_config_get = imx_pinconf_get, .pin_config_set = imx_pinconf_set, .pin_config_dbg_show = imx_pinconf_dbg_show, diff --git a/trunk/drivers/pinctrl/pinctrl-lantiq.c b/trunk/drivers/pinctrl/pinctrl-lantiq.c index 615c5002b757..a70384611351 100644 --- a/trunk/drivers/pinctrl/pinctrl-lantiq.c +++ b/trunk/drivers/pinctrl/pinctrl-lantiq.c @@ -169,7 +169,7 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static const struct pinctrl_ops ltq_pctrl_ops = { +static struct pinctrl_ops ltq_pctrl_ops = { .get_groups_count = ltq_get_group_count, .get_group_name = ltq_get_group_name, .get_group_pins = ltq_get_group_pins, @@ -311,7 +311,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev, return info->apply_mux(pctrldev, mfp, pin_func); } -static const struct pinmux_ops ltq_pmx_ops = { +static struct pinmux_ops ltq_pmx_ops = { .get_functions_count = ltq_pmx_func_count, .get_function_name = ltq_pmx_func_name, .get_function_groups = ltq_pmx_get_groups, diff --git a/trunk/drivers/pinctrl/pinctrl-mxs.c b/trunk/drivers/pinctrl/pinctrl-mxs.c index b45c4eb35798..23af9f1f9c35 100644 --- a/trunk/drivers/pinctrl/pinctrl-mxs.c +++ b/trunk/drivers/pinctrl/pinctrl-mxs.c @@ -158,7 +158,7 @@ static void mxs_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops mxs_pinctrl_ops = { +static struct pinctrl_ops mxs_pinctrl_ops = { .get_groups_count = mxs_get_groups_count, .get_group_name = mxs_get_group_name, .get_group_pins = mxs_get_group_pins, @@ -219,7 +219,7 @@ static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static const struct pinmux_ops mxs_pinmux_ops = { +static struct pinmux_ops mxs_pinmux_ops = { .get_functions_count = mxs_pinctrl_get_funcs_count, .get_function_name = mxs_pinctrl_get_func_name, .get_function_groups = mxs_pinctrl_get_func_groups, @@ -319,7 +319,7 @@ static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "0x%lx", config); } -static const struct pinconf_ops mxs_pinconf_ops = { +static struct pinconf_ops mxs_pinconf_ops = { .pin_config_get = mxs_pinconf_get, .pin_config_set = mxs_pinconf_set, .pin_config_group_get = mxs_pinconf_group_get, diff --git a/trunk/drivers/pinctrl/pinctrl-nomadik.c b/trunk/drivers/pinctrl/pinctrl-nomadik.c index 3fc8b9941963..36d20293de5c 100644 --- a/trunk/drivers/pinctrl/pinctrl-nomadik.c +++ b/trunk/drivers/pinctrl/pinctrl-nomadik.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -34,6 +33,7 @@ /* Since we request GPIOs from ourself */ #include #include +#include #include "pinctrl-nomadik.h" #include "core.h" @@ -1764,7 +1764,7 @@ int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static const struct pinctrl_ops nmk_pinctrl_ops = { +static struct pinctrl_ops nmk_pinctrl_ops = { .get_groups_count = nmk_get_groups_cnt, .get_group_name = nmk_get_group_name, .get_group_pins = nmk_get_group_pins, @@ -1975,7 +1975,7 @@ static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, /* Set the pin to some default state, GPIO is usually default */ } -static const struct pinmux_ops nmk_pinmux_ops = { +static struct pinmux_ops nmk_pinmux_ops = { .get_functions_count = nmk_pmx_get_funcs_cnt, .get_function_name = nmk_pmx_get_func_name, .get_function_groups = nmk_pmx_get_func_groups, @@ -2089,7 +2089,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static const struct pinconf_ops nmk_pinconf_ops = { +static struct pinconf_ops nmk_pinconf_ops = { .pin_config_get = nmk_pin_config_get, .pin_config_set = nmk_pin_config_set, }; diff --git a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c index 05e11de1d144..1f49bb02a6af 100644 --- a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c +++ b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c @@ -53,7 +53,7 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinctrl_ops pxa3xx_pctrl_ops = { +static struct pinctrl_ops pxa3xx_pctrl_ops = { .get_groups_count = pxa3xx_get_groups_count, .get_group_name = pxa3xx_get_group_name, .get_group_pins = pxa3xx_get_group_pins, @@ -161,7 +161,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinmux_ops pxa3xx_pmx_ops = { +static struct pinmux_ops pxa3xx_pmx_ops = { .get_functions_count = pxa3xx_pmx_get_funcs_count, .get_function_name = pxa3xx_pmx_get_func_name, .get_function_groups = pxa3xx_pmx_get_groups, diff --git a/trunk/drivers/pinctrl/pinctrl-samsung.c b/trunk/drivers/pinctrl/pinctrl-samsung.c index 3475b92b24a4..f206df175656 100644 --- a/trunk/drivers/pinctrl/pinctrl-samsung.c +++ b/trunk/drivers/pinctrl/pinctrl-samsung.c @@ -214,7 +214,7 @@ static void samsung_dt_free_map(struct pinctrl_dev *pctldev, } /* list of pinctrl callbacks for the pinctrl core */ -static const struct pinctrl_ops samsung_pctrl_ops = { +static struct pinctrl_ops samsung_pctrl_ops = { .get_groups_count = samsung_get_group_count, .get_group_name = samsung_get_group_name, .get_group_pins = samsung_get_group_pins, @@ -357,7 +357,7 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, } /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ -static const struct pinmux_ops samsung_pinmux_ops = { +static struct pinmux_ops samsung_pinmux_ops = { .get_functions_count = samsung_get_functions_count, .get_function_name = samsung_pinmux_get_fname, .get_function_groups = samsung_pinmux_get_groups, @@ -468,7 +468,7 @@ static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev, } /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ -static const struct pinconf_ops samsung_pinconf_ops = { +static struct pinconf_ops samsung_pinconf_ops = { .pin_config_get = samsung_pinconf_get, .pin_config_set = samsung_pinconf_set, .pin_config_group_get = samsung_pinconf_group_get, diff --git a/trunk/drivers/pinctrl/pinctrl-single.c b/trunk/drivers/pinctrl/pinctrl-single.c index e35dabd3135d..5c32e880bcb2 100644 --- a/trunk/drivers/pinctrl/pinctrl-single.c +++ b/trunk/drivers/pinctrl/pinctrl-single.c @@ -22,10 +22,8 @@ #include #include -#include #include "core.h" -#include "pinconf.h" #define DRIVER_NAME "pinctrl-single" #define PCS_MUX_PINS_NAME "pinctrl-single,pins" @@ -60,33 +58,6 @@ struct pcs_func_vals { unsigned mask; }; -/** - * struct pcs_conf_vals - pinconf parameter, pinconf register offset - * and value, enable, disable, mask - * @param: config parameter - * @val: user input bits in the pinconf register - * @enable: enable bits in the pinconf register - * @disable: disable bits in the pinconf register - * @mask: mask bits in the register value - */ -struct pcs_conf_vals { - enum pin_config_param param; - unsigned val; - unsigned enable; - unsigned disable; - unsigned mask; -}; - -/** - * struct pcs_conf_type - pinconf property name, pinconf param pair - * @name: property name in DTS file - * @param: config parameter - */ -struct pcs_conf_type { - const char *name; - enum pin_config_param param; -}; - /** * struct pcs_function - pinctrl function * @name: pinctrl function name @@ -102,22 +73,6 @@ struct pcs_function { unsigned nvals; const char **pgnames; int npgnames; - struct pcs_conf_vals *conf; - int nconfs; - struct list_head node; -}; - -/** - * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function - * @offset: offset base of pins - * @npins: number pins with the same mux value of gpio function - * @gpiofunc: mux value of gpio function - * @node: list node - */ -struct pcs_gpiofunc_range { - unsigned offset; - unsigned npins; - unsigned gpiofunc; struct list_head node; }; @@ -162,14 +117,12 @@ struct pcs_name { * @fshift: function register shift * @foff: value to turn mux off * @fmax: max number of functions in fmask - * @is_pinconf: whether supports pinconf * @names: array of register names for pins * @pins: physical pins on the SoC * @pgtree: pingroup index radix tree * @ftree: function index radix tree * @pingroups: list of pingroups * @functions: list of functions - * @gpiofuncs: list of gpio functions * @ngroups: number of pingroups * @nfuncs: number of functions * @desc: pin controller descriptor @@ -189,14 +142,12 @@ struct pcs_device { unsigned foff; unsigned fmax; bool bits_per_mux; - bool is_pinconf; struct pcs_name *names; struct pcs_data pins; struct radix_tree_root pgtree; struct radix_tree_root ftree; struct list_head pingroups; struct list_head functions; - struct list_head gpiofuncs; unsigned ngroups; unsigned nfuncs; struct pinctrl_desc desc; @@ -204,16 +155,6 @@ struct pcs_device { void (*write)(unsigned val, void __iomem *reg); }; -static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config); -static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long config); - -static enum pin_config_param pcs_bias[] = { - PIN_CONFIG_BIAS_PULL_DOWN, - PIN_CONFIG_BIAS_PULL_UP, -}; - /* * REVISIT: Reads and writes could eventually use regmap or something * generic. But at least on omaps, some mux registers are performance @@ -329,7 +270,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps); -static const struct pinctrl_ops pcs_pinctrl_ops = { +static struct pinctrl_ops pcs_pinctrl_ops = { .get_groups_count = pcs_get_groups_count, .get_group_name = pcs_get_group_name, .get_group_pins = pcs_get_group_pins, @@ -385,28 +326,6 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev, return 0; } -static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, - struct pcs_function **func) -{ - struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); - struct pin_desc *pdesc = pin_desc_get(pctldev, pin); - const struct pinctrl_setting_mux *setting; - unsigned fselector; - - /* If pin is not described in DTS & enabled, mux_setting is NULL. */ - setting = pdesc->mux_setting; - if (!setting) - return -ENOTSUPP; - fselector = setting->func; - *func = radix_tree_lookup(&pcs->ftree, fselector); - if (!(*func)) { - dev_err(pcs->dev, "%s could not find function%i\n", - __func__, fselector); - return -ENOTSUPP; - } - return 0; -} - static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, unsigned group) { @@ -415,9 +334,6 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); - /* If function mask is null, needn't enable it. */ - if (!pcs->fmask) - return 0; func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) return -EINVAL; @@ -452,10 +368,6 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); - /* If function mask is null, needn't disable it. */ - if (!pcs->fmask) - return; - func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) { dev_err(pcs->dev, "%s could not find function%i\n", @@ -491,33 +403,12 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, } static int pcs_request_gpio(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned pin) + struct pinctrl_gpio_range *range, unsigned offset) { - struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); - struct pcs_gpiofunc_range *frange = NULL; - struct list_head *pos, *tmp; - int mux_bytes = 0; - unsigned data; - - /* If function mask is null, return directly. */ - if (!pcs->fmask) - return -ENOTSUPP; - - list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { - frange = list_entry(pos, struct pcs_gpiofunc_range, node); - if (pin >= frange->offset + frange->npins - || pin < frange->offset) - continue; - mux_bytes = pcs->width / BITS_PER_BYTE; - data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; - data |= frange->gpiofunc; - pcs->write(data, pcs->base + pin * mux_bytes); - break; - } - return 0; + return -ENOTSUPP; } -static const struct pinmux_ops pcs_pinmux_ops = { +static struct pinmux_ops pcs_pinmux_ops = { .get_functions_count = pcs_get_functions_count, .get_function_name = pcs_get_function_name, .get_function_groups = pcs_get_function_groups, @@ -526,191 +417,32 @@ static const struct pinmux_ops pcs_pinmux_ops = { .gpio_request_enable = pcs_request_gpio, }; -/* Clear BIAS value */ -static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) -{ - unsigned long config; - int i; - for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { - config = pinconf_to_config_packed(pcs_bias[i], 0); - pcs_pinconf_set(pctldev, pin, config); - } -} - -/* - * Check whether PIN_CONFIG_BIAS_DISABLE is valid. - * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. - */ -static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) -{ - unsigned long config; - int i; - - for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { - config = pinconf_to_config_packed(pcs_bias[i], 0); - if (!pcs_pinconf_get(pctldev, pin, &config)) - goto out; - } - return true; -out: - return false; -} - static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config) { - struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); - struct pcs_function *func; - enum pin_config_param param; - unsigned offset = 0, data = 0, i, j, ret; - - ret = pcs_get_function(pctldev, pin, &func); - if (ret) - return ret; - - for (i = 0; i < func->nconfs; i++) { - param = pinconf_to_config_param(*config); - if (param == PIN_CONFIG_BIAS_DISABLE) { - if (pcs_pinconf_bias_disable(pctldev, pin)) { - *config = 0; - return 0; - } else { - return -ENOTSUPP; - } - } else if (param != func->conf[i].param) { - continue; - } - - offset = pin * (pcs->width / BITS_PER_BYTE); - data = pcs->read(pcs->base + offset) & func->conf[i].mask; - switch (func->conf[i].param) { - /* 4 parameters */ - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if ((data != func->conf[i].enable) || - (data == func->conf[i].disable)) - return -ENOTSUPP; - *config = 0; - break; - /* 2 parameters */ - case PIN_CONFIG_INPUT_SCHMITT: - for (j = 0; j < func->nconfs; j++) { - switch (func->conf[j].param) { - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if (data != func->conf[j].enable) - return -ENOTSUPP; - break; - default: - break; - } - } - *config = data; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - case PIN_CONFIG_SLEW_RATE: - default: - *config = data; - break; - } - return 0; - } return -ENOTSUPP; } static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long config) { - struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); - struct pcs_function *func; - unsigned offset = 0, shift = 0, arg = 0, i, data, ret; - u16 argument; - - ret = pcs_get_function(pctldev, pin, &func); - if (ret) - return ret; - - for (i = 0; i < func->nconfs; i++) { - if (pinconf_to_config_param(config) == func->conf[i].param) { - offset = pin * (pcs->width / BITS_PER_BYTE); - data = pcs->read(pcs->base + offset); - argument = pinconf_to_config_argument(config); - switch (func->conf[i].param) { - /* 2 parameters */ - case PIN_CONFIG_INPUT_SCHMITT: - case PIN_CONFIG_DRIVE_STRENGTH: - case PIN_CONFIG_SLEW_RATE: - shift = ffs(func->conf[i].mask) - 1; - arg = pinconf_to_config_argument(config); - data &= ~func->conf[i].mask; - data |= (arg << shift) & func->conf[i].mask; - break; - /* 4 parameters */ - case PIN_CONFIG_BIAS_DISABLE: - pcs_pinconf_clear_bias(pctldev, pin); - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_PULL_UP: - if (argument) - pcs_pinconf_clear_bias(pctldev, pin); - /* fall through */ - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - data &= ~func->conf[i].mask; - if (argument) - data |= func->conf[i].enable; - else - data |= func->conf[i].disable; - break; - default: - return -ENOTSUPP; - } - pcs->write(data, pcs->base + offset); - return 0; - } - } return -ENOTSUPP; } static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { - const unsigned *pins; - unsigned npins, old = 0; - int i, ret; - - ret = pcs_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - for (i = 0; i < npins; i++) { - if (pcs_pinconf_get(pctldev, pins[i], config)) - return -ENOTSUPP; - /* configs do not match between two pins */ - if (i && (old != *config)) - return -ENOTSUPP; - old = *config; - } - return 0; + return -ENOTSUPP; } static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long config) { - const unsigned *pins; - unsigned npins; - int i, ret; - - ret = pcs_get_group_pins(pctldev, group, &pins, &npins); - if (ret) - return ret; - for (i = 0; i < npins; i++) { - if (pcs_pinconf_set(pctldev, pins[i], config)) - return -ENOTSUPP; - } - return 0; + return -ENOTSUPP; } static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) + struct seq_file *s, unsigned offset) { } @@ -719,22 +451,13 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, { } -static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned long config) -{ - pinconf_generic_dump_config(pctldev, s, config); -} - -static const struct pinconf_ops pcs_pinconf_ops = { +static struct pinconf_ops pcs_pinconf_ops = { .pin_config_get = pcs_pinconf_get, .pin_config_set = pcs_pinconf_set, .pin_config_group_get = pcs_pinconf_group_get, .pin_config_group_set = pcs_pinconf_group_set, .pin_config_dbg_show = pcs_pinconf_dbg_show, .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, - .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, - .is_generic = true, }; /** @@ -925,157 +648,11 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) return index; } -/* - * check whether data matches enable bits or disable bits - * Return value: 1 for matching enable bits, 0 for matching disable bits, - * and negative value for matching failure. - */ -static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) -{ - int ret = -EINVAL; - - if (data == enable) - ret = 1; - else if (data == disable) - ret = 0; - return ret; -} - -static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, - unsigned value, unsigned enable, unsigned disable, - unsigned mask) -{ - (*conf)->param = param; - (*conf)->val = value; - (*conf)->enable = enable; - (*conf)->disable = disable; - (*conf)->mask = mask; - (*conf)++; -} - -static void add_setting(unsigned long **setting, enum pin_config_param param, - unsigned arg) -{ - **setting = pinconf_to_config_packed(param, arg); - (*setting)++; -} - -/* add pinconf setting with 2 parameters */ -static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, - const char *name, enum pin_config_param param, - struct pcs_conf_vals **conf, unsigned long **settings) -{ - unsigned value[2]; - int ret; - - ret = of_property_read_u32_array(np, name, value, 2); - if (ret) - return; - /* set value & mask */ - value[0] &= value[1]; - /* skip enable & disable */ - add_config(conf, param, value[0], 0, 0, value[1]); - add_setting(settings, param, value[0]); -} - -/* add pinconf setting with 4 parameters */ -static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, - const char *name, enum pin_config_param param, - struct pcs_conf_vals **conf, unsigned long **settings) -{ - unsigned value[4]; - int ret; - - /* value to set, enable, disable, mask */ - ret = of_property_read_u32_array(np, name, value, 4); - if (ret) - return; - if (!value[3]) { - dev_err(pcs->dev, "mask field of the property can't be 0\n"); - return; - } - value[0] &= value[3]; - value[1] &= value[3]; - value[2] &= value[3]; - ret = pcs_config_match(value[0], value[1], value[2]); - if (ret < 0) - dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); - add_config(conf, param, value[0], value[1], value[2], value[3]); - add_setting(settings, param, ret); -} - -static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, - struct pcs_function *func, - struct pinctrl_map **map) - -{ - struct pinctrl_map *m = *map; - int i = 0, nconfs = 0; - unsigned long *settings = NULL, *s = NULL; - struct pcs_conf_vals *conf = NULL; - struct pcs_conf_type prop2[] = { - { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, - { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, - { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, - }; - struct pcs_conf_type prop4[] = { - { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, - { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, - { "pinctrl-single,input-schmitt-enable", - PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, - }; - - /* If pinconf isn't supported, don't parse properties in below. */ - if (!pcs->is_pinconf) - return 0; - - /* cacluate how much properties are supported in current node */ - for (i = 0; i < ARRAY_SIZE(prop2); i++) { - if (of_find_property(np, prop2[i].name, NULL)) - nconfs++; - } - for (i = 0; i < ARRAY_SIZE(prop4); i++) { - if (of_find_property(np, prop4[i].name, NULL)) - nconfs++; - } - if (!nconfs) - return 0; - - func->conf = devm_kzalloc(pcs->dev, - sizeof(struct pcs_conf_vals) * nconfs, - GFP_KERNEL); - if (!func->conf) - return -ENOMEM; - func->nconfs = nconfs; - conf = &(func->conf[0]); - m++; - settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs, - GFP_KERNEL); - if (!settings) - return -ENOMEM; - s = &settings[0]; - - for (i = 0; i < ARRAY_SIZE(prop2); i++) - pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, - &conf, &s); - for (i = 0; i < ARRAY_SIZE(prop4); i++) - pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, - &conf, &s); - m->type = PIN_MAP_TYPE_CONFIGS_GROUP; - m->data.configs.group_or_pin = np->name; - m->data.configs.configs = settings; - m->data.configs.num_configs = nconfs; - return 0; -} - -static void pcs_free_pingroups(struct pcs_device *pcs); - /** * smux_parse_one_pinctrl_entry() - parses a device tree mux entry * @pcs: pinctrl driver instance * @np: device node of the mux entry * @map: map entry - * @num_maps: number of map * @pgnames: pingroup names * * Note that this binding currently supports only sets of one register + value. @@ -1092,7 +669,6 @@ static void pcs_free_pingroups(struct pcs_device *pcs); static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, struct device_node *np, struct pinctrl_map **map, - unsigned *num_maps, const char **pgnames) { struct pcs_func_vals *vals; @@ -1165,18 +741,8 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, (*map)->data.mux.group = np->name; (*map)->data.mux.function = np->name; - if (pcs->is_pinconf) { - if (pcs_parse_pinconf(pcs, np, function, map)) - goto free_pingroups; - *num_maps = 2; - } else { - *num_maps = 1; - } return 0; -free_pingroups: - pcs_free_pingroups(pcs); - *num_maps = 1; free_function: pcs_remove_function(pcs, function); @@ -1205,8 +771,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, pcs = pinctrl_dev_get_drvdata(pctldev); - /* create 2 maps. One is for pinmux, and the other is for pinconf. */ - *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL); + *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); if (!*map) return -ENOMEM; @@ -1218,13 +783,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, goto free_map; } - ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps, - pgnames); + ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); if (ret < 0) { dev_err(pcs->dev, "no pins entries for %s\n", np_config->name); goto free_pgnames; } + *num_maps = 1; return 0; @@ -1314,37 +879,6 @@ static void pcs_free_resources(struct pcs_device *pcs) static struct of_device_id pcs_of_match[]; -static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) -{ - const char *propname = "pinctrl-single,gpio-range"; - const char *cellname = "#pinctrl-single,gpio-range-cells"; - struct of_phandle_args gpiospec; - struct pcs_gpiofunc_range *range; - int ret, i; - - for (i = 0; ; i++) { - ret = of_parse_phandle_with_args(node, propname, cellname, - i, &gpiospec); - /* Do not treat it as error. Only treat it as end condition. */ - if (ret) { - ret = 0; - break; - } - range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); - if (!range) { - ret = -ENOMEM; - break; - } - range->offset = gpiospec.args[0]; - range->npins = gpiospec.args[1]; - range->gpiofunc = gpiospec.args[2]; - mutex_lock(&pcs->mutex); - list_add_tail(&range->node, &pcs->gpiofuncs); - mutex_unlock(&pcs->mutex); - } - return ret; -} - static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1366,23 +900,14 @@ static int pcs_probe(struct platform_device *pdev) mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->pingroups); INIT_LIST_HEAD(&pcs->functions); - INIT_LIST_HEAD(&pcs->gpiofuncs); - pcs->is_pinconf = match->data; PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); - ret = of_property_read_u32(np, "pinctrl-single,function-mask", - &pcs->fmask); - if (!ret) { - pcs->fshift = ffs(pcs->fmask) - 1; - pcs->fmax = pcs->fmask >> pcs->fshift; - } else { - /* If mask property doesn't exist, function mux is invalid. */ - pcs->fmask = 0; - pcs->fshift = 0; - pcs->fmax = 0; - } + PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, + "function register mask not specified\n"); + pcs->fshift = ffs(pcs->fmask) - 1; + pcs->fmax = pcs->fmask >> pcs->fshift; ret = of_property_read_u32(np, "pinctrl-single,function-off", &pcs->foff); @@ -1436,8 +961,7 @@ static int pcs_probe(struct platform_device *pdev) pcs->desc.name = DRIVER_NAME; pcs->desc.pctlops = &pcs_pinctrl_ops; pcs->desc.pmxops = &pcs_pinmux_ops; - if (pcs->is_pinconf) - pcs->desc.confops = &pcs_pinconf_ops; + pcs->desc.confops = &pcs_pinconf_ops; pcs->desc.owner = THIS_MODULE; ret = pcs_allocate_pin_table(pcs); @@ -1451,10 +975,6 @@ static int pcs_probe(struct platform_device *pdev) goto free; } - ret = pcs_add_gpio_func(np, pcs); - if (ret < 0) - goto free; - dev_info(pcs->dev, "%i pins at pa %p size %u\n", pcs->desc.npins, pcs->base, pcs->size); @@ -1479,8 +999,7 @@ static int pcs_remove(struct platform_device *pdev) } static struct of_device_id pcs_of_match[] = { - { .compatible = "pinctrl-single", .data = (void *)false }, - { .compatible = "pinconf-single", .data = (void *)true }, + { .compatible = DRIVER_NAME, }, { }, }; MODULE_DEVICE_TABLE(of, pcs_of_match); diff --git a/trunk/drivers/pinctrl/pinctrl-sirf.c b/trunk/drivers/pinctrl/pinctrl-sirf.c index 08582fecdf1b..d02498b30c6e 100644 --- a/trunk/drivers/pinctrl/pinctrl-sirf.c +++ b/trunk/drivers/pinctrl/pinctrl-sirf.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -26,6 +25,7 @@ #include #include #include +#include #define DRIVER_NAME "pinmux-sirf" @@ -979,7 +979,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops sirfsoc_pctrl_ops = { +static struct pinctrl_ops sirfsoc_pctrl_ops = { .get_groups_count = sirfsoc_get_groups_count, .get_group_name = sirfsoc_get_group_name, .get_group_pins = sirfsoc_get_group_pins, @@ -1181,7 +1181,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, return 0; } -static const struct pinmux_ops sirfsoc_pinmux_ops = { +static struct pinmux_ops sirfsoc_pinmux_ops = { .enable = sirfsoc_pinmux_enable, .disable = sirfsoc_pinmux_disable, .get_functions_count = sirfsoc_pinmux_get_funcs_count, diff --git a/trunk/drivers/pinctrl/pinctrl-sunxi.c b/trunk/drivers/pinctrl/pinctrl-sunxi.c index cb491d6ba601..80b11e3415bc 100644 --- a/trunk/drivers/pinctrl/pinctrl-sunxi.c +++ b/trunk/drivers/pinctrl/pinctrl-sunxi.c @@ -30,856 +30,482 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x4, "uart2")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x4, "uart2")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */ - SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */ - SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */ - SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */ - SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */ - SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */ - SUNXI_FUNCTION(0x3, "can"), /* TX */ SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */ - SUNXI_FUNCTION(0x3, "can"), /* RX */ SUNXI_FUNCTION(0x4, "uart1")), /* RING */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ - SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ - SUNXI_FUNCTION(0x3, "ac97")), /* DO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DI */ - SUNXI_FUNCTION(0x3, "ac97")), /* DI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ - SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ - SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ - SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ - SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_FUNCTION(0x2, "uart0")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* RX */ - SUNXI_FUNCTION(0x3, "ir1")), /* RX */ + SUNXI_FUNCTION(0x2, "uart0")), /* RX */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ - SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ - SUNXI_FUNCTION(0x3, "sim")), /* DET */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ - SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ - SUNXI_FUNCTION(0x3, "sim")), /* RST */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi0")), /* CK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ - SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ - SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ SUNXI_FUNCTION(0x4, "uart0")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ - SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ SUNXI_FUNCTION(0x4, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ - SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi1"), /* CK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ - SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ - SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ - SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x5, "sim"), /* RST */ - SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ - SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ - SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ - SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ - SUNXI_FUNCTION(0x5, "sim"), /* SCK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ - SUNXI_FUNCTION(0x5, "sim"), /* SDA */ - SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ - SUNXI_FUNCTION(0x4, "can"), /* TX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ - SUNXI_FUNCTION(0x4, "can"), /* RX */ - SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, SUNXI_FUNCTION(0x0, "gpio_in"), @@ -892,401 +518,277 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart5")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart5")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart6")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart6")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart2")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart2")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), }; static const struct sunxi_desc_pin sun5i_a13_pins[] = { /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ - SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ - SUNXI_FUNCTION(0x4, "spi2")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */ + SUNXI_FUNCTION(0x1, "gpio_out")), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1300,34 +802,24 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ SUNXI_FUNCTION(0x4, "uart1")), /* TX */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ SUNXI_FUNCTION(0x4, "uart1")), /* RX */ -/* Hole */ + /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart3")), /* TX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart3")), /* RX */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart3")), /* CTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ + SUNXI_FUNCTION(0x1, "gpio_out")), }; static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { @@ -1537,7 +1029,7 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops sunxi_pctrl_ops = { +static struct pinctrl_ops sunxi_pctrl_ops = { .dt_node_to_map = sunxi_pctrl_dt_node_to_map, .dt_free_map = sunxi_pctrl_dt_free_map, .get_groups_count = sunxi_pctrl_get_groups_count, @@ -1606,7 +1098,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, return 0; } -static const struct pinconf_ops sunxi_pconf_ops = { +static struct pinconf_ops sunxi_pconf_ops = { .pin_config_group_get = sunxi_pconf_group_get, .pin_config_group_set = sunxi_pconf_group_set, }; @@ -1712,7 +1204,7 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return ret; } -static const struct pinmux_ops sunxi_pmx_ops = { +static struct pinmux_ops sunxi_pmx_ops = { .get_functions_count = sunxi_pmx_get_funcs_cnt, .get_function_name = sunxi_pmx_get_func_name, .get_function_groups = sunxi_pmx_get_func_groups, diff --git a/trunk/drivers/pinctrl/pinctrl-tegra.c b/trunk/drivers/pinctrl/pinctrl-tegra.c index 2fa9bc6cd7ab..f195d77a3572 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra.c +++ b/trunk/drivers/pinctrl/pinctrl-tegra.c @@ -316,7 +316,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static const struct pinctrl_ops tegra_pinctrl_ops = { +static struct pinctrl_ops tegra_pinctrl_ops = { .get_groups_count = tegra_pinctrl_get_groups_count, .get_group_name = tegra_pinctrl_get_group_name, .get_group_pins = tegra_pinctrl_get_group_pins, @@ -401,7 +401,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, pmx_writel(pmx, val, g->mux_bank, g->mux_reg); } -static const struct pinmux_ops tegra_pinmux_ops = { +static struct pinmux_ops tegra_pinmux_ops = { .get_functions_count = tegra_pinctrl_get_funcs_count, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, @@ -676,7 +676,7 @@ static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, } #endif -static const struct pinconf_ops tegra_pinconf_ops = { +static struct pinconf_ops tegra_pinconf_ops = { .pin_config_get = tegra_pinconf_get, .pin_config_set = tegra_pinconf_set, .pin_config_group_get = tegra_pinconf_group_get, diff --git a/trunk/drivers/pinctrl/pinctrl-u300.c b/trunk/drivers/pinctrl/pinctrl-u300.c index 6a3a7503e6a0..2b5772550836 100644 --- a/trunk/drivers/pinctrl/pinctrl-u300.c +++ b/trunk/drivers/pinctrl/pinctrl-u300.c @@ -860,7 +860,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, " " DRIVER_NAME); } -static const struct pinctrl_ops u300_pctrl_ops = { +static struct pinctrl_ops u300_pctrl_ops = { .get_groups_count = u300_get_groups_count, .get_group_name = u300_get_group_name, .get_group_pins = u300_get_group_pins, @@ -1003,7 +1003,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static const struct pinmux_ops u300_pmx_ops = { +static struct pinmux_ops u300_pmx_ops = { .get_functions_count = u300_pmx_get_funcs_count, .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, @@ -1046,7 +1046,7 @@ static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static const struct pinconf_ops u300_pconf_ops = { +static struct pinconf_ops u300_pconf_ops = { .is_generic = true, .pin_config_get = u300_pin_config_get, .pin_config_set = u300_pin_config_set, diff --git a/trunk/drivers/pinctrl/pinctrl-xway.c b/trunk/drivers/pinctrl/pinctrl-xway.c index f2977cff8366..068224efa6fa 100644 --- a/trunk/drivers/pinctrl/pinctrl-xway.c +++ b/trunk/drivers/pinctrl/pinctrl-xway.c @@ -553,7 +553,7 @@ int xway_pinconf_group_set(struct pinctrl_dev *pctldev, return ret; } -static const struct pinconf_ops xway_pinconf_ops = { +static struct pinconf_ops xway_pinconf_ops = { .pin_config_get = xway_pinconf_get, .pin_config_set = xway_pinconf_set, .pin_config_group_set = xway_pinconf_group_set, diff --git a/trunk/drivers/pinctrl/sh-pfc/Kconfig b/trunk/drivers/pinctrl/sh-pfc/Kconfig index 0e1f99c33d47..c3340f54d2ad 100644 --- a/trunk/drivers/pinctrl/sh-pfc/Kconfig +++ b/trunk/drivers/pinctrl/sh-pfc/Kconfig @@ -10,7 +10,6 @@ config PINCTRL_SH_PFC select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF - select GENERIC_PINCONF def_bool y help This enables pin control drivers for SH and SH Mobile platforms @@ -22,11 +21,6 @@ config GPIO_SH_PFC This enables support for GPIOs within the SoC's pin function controller. -config PINCTRL_PFC_R8A73A4 - def_bool y - depends on ARCH_R8A73A4 - select PINCTRL_SH_PFC - config PINCTRL_PFC_R8A7740 def_bool y depends on ARCH_R8A7740 diff --git a/trunk/drivers/pinctrl/sh-pfc/Makefile b/trunk/drivers/pinctrl/sh-pfc/Makefile index 211cd8e98a8a..e8b9562c47e1 100644 --- a/trunk/drivers/pinctrl/sh-pfc/Makefile +++ b/trunk/drivers/pinctrl/sh-pfc/Makefile @@ -3,7 +3,6 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y) sh-pfc-objs += gpio.o endif obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o -obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o diff --git a/trunk/drivers/pinctrl/sh-pfc/core.c b/trunk/drivers/pinctrl/sh-pfc/core.c index b551336924a5..970ddff2b0b6 100644 --- a/trunk/drivers/pinctrl/sh-pfc/core.c +++ b/trunk/drivers/pinctrl/sh-pfc/core.c @@ -10,6 +10,7 @@ */ #define DRV_NAME "sh-pfc" +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include #include @@ -29,8 +30,10 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) struct resource *res; int k; - if (pdev->num_resources == 0) - return -EINVAL; + if (pdev->num_resources == 0) { + pfc->num_windows = 0; + return 0; + } pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * sizeof(*pfc->window), GFP_NOWAIT); @@ -56,11 +59,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, unsigned long address) { struct sh_pfc_window *window; - unsigned int i; + int k; /* scan through physical windows and convert address */ - for (i = 0; i < pfc->num_windows; i++) { - window = pfc->window + i; + for (k = 0; k < pfc->num_windows; k++) { + window = pfc->window + k; if (address < window->phys) continue; @@ -71,33 +74,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, return window->virt + (address - window->phys); } - BUG(); - return NULL; -} - -int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) -{ - unsigned int offset; - unsigned int i; - - if (pfc->info->ranges == NULL) - return pin; - - for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) { - const struct pinmux_range *range = &pfc->info->ranges[i]; - - if (pin <= range->end) - return pin >= range->begin - ? offset + pin - range->begin : -1; - - offset += range->end - range->begin + 1; - } - - return -EINVAL; + /* no windows defined, register must be 1:1 mapped virt:phys */ + return (void __iomem *)address; } -static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, - const struct pinmux_range *r) +static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) { if (enum_id < r->begin) return 0; @@ -108,8 +89,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, return 1; } -unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width) +static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width) { switch (reg_width) { case 8: @@ -124,8 +105,8 @@ unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, return 0; } -void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long data) +static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, + unsigned long reg_width, unsigned long data) { switch (reg_width) { case 8: @@ -142,8 +123,39 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, BUG(); } +int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) +{ + unsigned long pos; + + pos = dr->reg_width - (in_pos + 1); + + pr_debug("read_bit: addr = %lx, pos = %ld, " + "r_width = %ld\n", dr->reg, pos, dr->reg_width); + + return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; +} + +void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, + unsigned long value) +{ + unsigned long pos; + + pos = dr->reg_width - (in_pos + 1); + + pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " + "r_width = %ld\n", + dr->reg, !!value, pos, dr->reg_width); + + if (value) + set_bit(pos, &dr->reg_shadow); + else + clear_bit(pos, &dr->reg_shadow); + + sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); +} + static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, - const struct pinmux_cfg_reg *crp, + struct pinmux_cfg_reg *crp, unsigned long in_pos, void __iomem **mapped_regp, unsigned long *maskp, @@ -164,8 +176,24 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, } } +static int sh_pfc_read_config_reg(struct sh_pfc *pfc, + struct pinmux_cfg_reg *crp, + unsigned long field) +{ + void __iomem *mapped_reg; + unsigned long mask, pos; + + sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); + + pr_debug("read_reg: addr = %lx, field = %ld, " + "r_width = %ld, f_width = %ld\n", + crp->reg, field, crp->reg_width, crp->field_width); + + return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; +} + static void sh_pfc_write_config_reg(struct sh_pfc *pfc, - const struct pinmux_cfg_reg *crp, + struct pinmux_cfg_reg *crp, unsigned long field, unsigned long value) { void __iomem *mapped_reg; @@ -173,9 +201,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); - dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, " - "r_width = %ld, f_width = %ld\n", - crp->reg, value, field, crp->reg_width, crp->field_width); + pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " + "r_width = %ld, f_width = %ld\n", + crp->reg, value, field, crp->reg_width, crp->field_width); mask = ~(mask << pos); value = value << pos; @@ -192,11 +220,83 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); } +static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) +{ + struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; + struct pinmux_data_reg *data_reg; + int k, n; + + if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) + return -1; + + k = 0; + while (1) { + data_reg = pfc->info->data_regs + k; + + if (!data_reg->reg_width) + break; + + data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); + + for (n = 0; n < data_reg->reg_width; n++) { + if (data_reg->enum_ids[n] == gpiop->enum_id) { + gpiop->flags &= ~PINMUX_FLAG_DREG; + gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); + gpiop->flags &= ~PINMUX_FLAG_DBIT; + gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); + return 0; + } + } + k++; + } + + BUG(); + + return -1; +} + +static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) +{ + struct pinmux_data_reg *drp; + int k; + + for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++) + sh_pfc_setup_data_reg(pfc, k); + + k = 0; + while (1) { + drp = pfc->info->data_regs + k; + + if (!drp->reg_width) + break; + + drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, + drp->reg_width); + k++; + } +} + +int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, + struct pinmux_data_reg **drp, int *bitp) +{ + struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio]; + int k, n; + + if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data)) + return -1; + + k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; + n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; + *drp = pfc->info->data_regs + k; + *bitp = n; + return 0; +} + static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, - const struct pinmux_cfg_reg **crp, int *fieldp, - int *valuep) + struct pinmux_cfg_reg **crp, int *fieldp, + int *valuep, unsigned long **cntp) { - const struct pinmux_cfg_reg *config_reg; + struct pinmux_cfg_reg *config_reg; unsigned long r_width, f_width, curr_width, ncomb; int k, m, n, pos, bit_pos; @@ -224,6 +324,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, *crp = config_reg; *fieldp = m; *valuep = n; + *cntp = &config_reg->cnt[m]; return 0; } } @@ -233,42 +334,50 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, k++; } - return -EINVAL; + return -1; } -static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, - pinmux_enum_t *enum_idp) +int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, + pinmux_enum_t *enum_idp) { - const pinmux_enum_t *data = pfc->info->gpio_data; + pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; + pinmux_enum_t *data = pfc->info->gpio_data; int k; + if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) { + if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) { + pr_err("non data/mark enum_id for gpio %d\n", gpio); + return -1; + } + } + if (pos) { *enum_idp = data[pos + 1]; return pos + 1; } for (k = 0; k < pfc->info->gpio_data_size; k++) { - if (data[k] == mark) { + if (data[k] == enum_id) { *enum_idp = data[k + 1]; return k + 1; } } - dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", - mark); - return -EINVAL; + pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); + return -1; } -int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) +int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, + int cfg_mode) { - const struct pinmux_cfg_reg *cr = NULL; + struct pinmux_cfg_reg *cr = NULL; pinmux_enum_t enum_id; - const struct pinmux_range *range; + struct pinmux_range *range; int in_range, pos, field, value; - int ret; + unsigned long *cntp; switch (pinmux_type) { - case PINMUX_TYPE_GPIO: + case PINMUX_TYPE_FUNCTION: range = NULL; break; @@ -290,37 +399,33 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) break; default: - return -EINVAL; + goto out_err; } pos = 0; enum_id = 0; field = 0; value = 0; - - /* Iterate over all the configuration fields we need to update. */ while (1) { - pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); - if (pos < 0) - return pos; + pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); + if (pos <= 0) + goto out_err; if (!enum_id) break; - /* Check if the configuration field selects a function. If it - * doesn't, skip the field if it's not applicable to the - * requested pinmux type. - */ + /* first check if this is a function enum */ in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); if (!in_range) { - if (pinmux_type == PINMUX_TYPE_FUNCTION) { - /* Functions are allowed to modify all - * fields. - */ - in_range = 1; - } else if (pinmux_type != PINMUX_TYPE_GPIO) { - /* Input/output types can only modify fields - * that correspond to their respective ranges. + /* not a function enum */ + if (range) { + /* + * other range exists, so this pin is + * a regular GPIO pin that now is being + * bound to a specific direction. + * + * for this case we only allow function enums + * and the enums that match the other range. */ in_range = sh_pfc_enum_in_range(enum_id, range); @@ -331,29 +436,60 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) */ if (in_range && enum_id == range->force) continue; + } else { + /* + * no other range exists, so this pin + * must then be of the function type. + * + * allow function type pins to select + * any combination of function/in/out + * in their MARK lists. + */ + in_range = 1; } - /* GPIOs are only allowed to modify function fields. */ } if (!in_range) continue; - ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); - if (ret < 0) - return ret; + if (sh_pfc_get_config_reg(pfc, enum_id, &cr, + &field, &value, &cntp) != 0) + goto out_err; + + switch (cfg_mode) { + case GPIO_CFG_DRYRUN: + if (!*cntp || + (sh_pfc_read_config_reg(pfc, cr, field) != value)) + continue; + break; + + case GPIO_CFG_REQ: + sh_pfc_write_config_reg(pfc, cr, field, value); + *cntp = *cntp + 1; + break; - sh_pfc_write_config_reg(pfc, cr, field, value); + case GPIO_CFG_FREE: + *cntp = *cntp - 1; + break; + } } return 0; + out_err: + return -1; } static int sh_pfc_probe(struct platform_device *pdev) { - const struct sh_pfc_soc_info *info; + struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; + /* + * Ensure that the type encoding fits + */ + BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); + info = pdev->id_entry->driver_data ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; if (info == NULL) @@ -373,6 +509,7 @@ static int sh_pfc_probe(struct platform_device *pdev) spin_lock_init(&pfc->lock); pinctrl_provide_dummies(); + sh_pfc_setup_data_regs(pfc); /* * Initialize pinctrl bindings first @@ -392,13 +529,13 @@ static int sh_pfc_probe(struct platform_device *pdev) * PFC state as it is, given that there are already * extant users of it that have succeeded by this point. */ - dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); + pr_notice("failed to init GPIO chip, ignoring...\n"); } #endif platform_set_drvdata(pdev, pfc); - dev_info(pfc->dev, "%s support registered\n", info->name); + pr_info("%s support registered\n", info->name); return 0; } @@ -418,9 +555,6 @@ static int sh_pfc_remove(struct platform_device *pdev) } static const struct platform_device_id sh_pfc_id_table[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A73A4 - { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, -#endif #ifdef CONFIG_PINCTRL_PFC_R8A7740 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, #endif diff --git a/trunk/drivers/pinctrl/sh-pfc/core.h b/trunk/drivers/pinctrl/sh-pfc/core.h index 89cb4289d761..ba7c33c33599 100644 --- a/trunk/drivers/pinctrl/sh-pfc/core.h +++ b/trunk/drivers/pinctrl/sh-pfc/core.h @@ -26,17 +26,13 @@ struct sh_pfc_pinctrl; struct sh_pfc { struct device *dev; - const struct sh_pfc_soc_info *info; + struct sh_pfc_soc_info *info; spinlock_t lock; unsigned int num_windows; struct sh_pfc_window *window; - unsigned int nr_pins; - struct sh_pfc_chip *gpio; - struct sh_pfc_chip *func; - struct sh_pfc_pinctrl *pinctrl; }; @@ -46,30 +42,31 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc); int sh_pfc_register_pinctrl(struct sh_pfc *pfc); int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); -unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, - unsigned long reg_width); -void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, - unsigned long data); - -int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); -int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); +int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); +void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, + unsigned long value); +int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, + struct pinmux_data_reg **drp, int *bitp); +int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, + pinmux_enum_t *enum_idp); +int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, + int cfg_mode); -extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; -extern const struct sh_pfc_soc_info r8a7740_pinmux_info; -extern const struct sh_pfc_soc_info r8a7779_pinmux_info; -extern const struct sh_pfc_soc_info sh7203_pinmux_info; -extern const struct sh_pfc_soc_info sh7264_pinmux_info; -extern const struct sh_pfc_soc_info sh7269_pinmux_info; -extern const struct sh_pfc_soc_info sh7372_pinmux_info; -extern const struct sh_pfc_soc_info sh73a0_pinmux_info; -extern const struct sh_pfc_soc_info sh7720_pinmux_info; -extern const struct sh_pfc_soc_info sh7722_pinmux_info; -extern const struct sh_pfc_soc_info sh7723_pinmux_info; -extern const struct sh_pfc_soc_info sh7724_pinmux_info; -extern const struct sh_pfc_soc_info sh7734_pinmux_info; -extern const struct sh_pfc_soc_info sh7757_pinmux_info; -extern const struct sh_pfc_soc_info sh7785_pinmux_info; -extern const struct sh_pfc_soc_info sh7786_pinmux_info; -extern const struct sh_pfc_soc_info shx3_pinmux_info; +extern struct sh_pfc_soc_info r8a7740_pinmux_info; +extern struct sh_pfc_soc_info r8a7779_pinmux_info; +extern struct sh_pfc_soc_info sh7203_pinmux_info; +extern struct sh_pfc_soc_info sh7264_pinmux_info; +extern struct sh_pfc_soc_info sh7269_pinmux_info; +extern struct sh_pfc_soc_info sh7372_pinmux_info; +extern struct sh_pfc_soc_info sh73a0_pinmux_info; +extern struct sh_pfc_soc_info sh7720_pinmux_info; +extern struct sh_pfc_soc_info sh7722_pinmux_info; +extern struct sh_pfc_soc_info sh7723_pinmux_info; +extern struct sh_pfc_soc_info sh7724_pinmux_info; +extern struct sh_pfc_soc_info sh7734_pinmux_info; +extern struct sh_pfc_soc_info sh7757_pinmux_info; +extern struct sh_pfc_soc_info sh7785_pinmux_info; +extern struct sh_pfc_soc_info sh7786_pinmux_info; +extern struct sh_pfc_soc_info shx3_pinmux_info; #endif /* __SH_PFC_CORE_H__ */ diff --git a/trunk/drivers/pinctrl/sh-pfc/gpio.c b/trunk/drivers/pinctrl/sh-pfc/gpio.c index d37efa7dcf90..a535075c8b69 100644 --- a/trunk/drivers/pinctrl/sh-pfc/gpio.c +++ b/trunk/drivers/pinctrl/sh-pfc/gpio.c @@ -9,6 +9,8 @@ * for more details. */ +#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt + #include #include #include @@ -19,23 +21,9 @@ #include "core.h" -struct sh_pfc_gpio_data_reg { - const struct pinmux_data_reg *info; - unsigned long shadow; -}; - -struct sh_pfc_gpio_pin { - u8 dbit; - u8 dreg; -}; - struct sh_pfc_chip { - struct sh_pfc *pfc; - struct gpio_chip gpio_chip; - - struct sh_pfc_window *mem; - struct sh_pfc_gpio_data_reg *regs; - struct sh_pfc_gpio_pin *pins; + struct sh_pfc *pfc; + struct gpio_chip gpio_chip; }; static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) @@ -48,367 +36,143 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) return gpio_to_pfc_chip(gc)->pfc; } -static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio, - struct sh_pfc_gpio_data_reg **reg, - unsigned int *bit) +static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) { - int idx = sh_pfc_get_pin_index(chip->pfc, gpio); - struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; - - *reg = &chip->regs[gpio_pin->dreg]; - *bit = gpio_pin->dbit; -} - -static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, - const struct pinmux_data_reg *dreg) -{ - void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; - - return sh_pfc_read_raw_reg(mem, dreg->reg_width); -} - -static void gpio_write_data_reg(struct sh_pfc_chip *chip, - const struct pinmux_data_reg *dreg, - unsigned long value) -{ - void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; - - sh_pfc_write_raw_reg(mem, dreg->reg_width, value); + return pinctrl_request_gpio(offset); } -static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio) +static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc *pfc = chip->pfc; - struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio]; - const struct sh_pfc_pin *pin = &pfc->info->pins[gpio]; - const struct pinmux_data_reg *dreg; - unsigned int bit; - unsigned int i; - - for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { - for (bit = 0; bit < dreg->reg_width; bit++) { - if (dreg->enum_ids[bit] == pin->enum_id) { - gpio_pin->dreg = i; - gpio_pin->dbit = bit; - return; - } - } - } - - BUG(); + pinctrl_free_gpio(offset); } -static int gpio_setup_data_regs(struct sh_pfc_chip *chip) +static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) { - struct sh_pfc *pfc = chip->pfc; - const struct pinmux_data_reg *dreg; - unsigned int i; - - /* Count the number of data registers, allocate memory and initialize - * them. - */ - for (i = 0; pfc->info->data_regs[i].reg_width; ++i) - ; - - chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), - GFP_KERNEL); - if (chip->regs == NULL) - return -ENOMEM; - - for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { - chip->regs[i].info = dreg; - chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); - } - - for (i = 0; i < pfc->info->nr_pins; i++) { - if (pfc->info->pins[i].enum_id == 0) - continue; + struct pinmux_data_reg *dr = NULL; + int bit = 0; - gpio_setup_data_reg(chip, i); - } - - return 0; + if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) + BUG(); + else + sh_pfc_write_bit(dr, bit, value); } -/* ----------------------------------------------------------------------------- - * Pin GPIOs - */ - -static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) +static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) { - struct sh_pfc *pfc = gpio_to_pfc(gc); - int idx = sh_pfc_get_pin_index(pfc, offset); + struct pinmux_data_reg *dr = NULL; + int bit = 0; - if (idx < 0 || pfc->info->pins[idx].enum_id == 0) + if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) return -EINVAL; - return pinctrl_request_gpio(offset); -} - -static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) -{ - return pinctrl_free_gpio(offset); -} - -static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, - int value) -{ - struct sh_pfc_gpio_data_reg *reg; - unsigned long pos; - unsigned int bit; - - gpio_get_data_reg(chip, offset, ®, &bit); - - pos = reg->info->reg_width - (bit + 1); - - if (value) - set_bit(pos, ®->shadow); - else - clear_bit(pos, ®->shadow); - - gpio_write_data_reg(chip, reg->info, reg->shadow); + return sh_pfc_read_bit(dr, bit); } -static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) +static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { return pinctrl_gpio_direction_input(offset); } -static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, +static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int value) { - gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); + sh_gpio_set_value(gpio_to_pfc(gc), offset, value); return pinctrl_gpio_direction_output(offset); } -static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) +static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) { - struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); - struct sh_pfc_gpio_data_reg *reg; - unsigned long pos; - unsigned int bit; - - gpio_get_data_reg(chip, offset, ®, &bit); - - pos = reg->info->reg_width - (bit + 1); - - return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; + return sh_gpio_get_value(gpio_to_pfc(gc), offset); } -static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) +static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) { - gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); + sh_gpio_set_value(gpio_to_pfc(gc), offset, value); } -static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) +static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct sh_pfc *pfc = gpio_to_pfc(gc); - int i, k; - - for (i = 0; i < pfc->info->gpio_irq_size; i++) { - unsigned short *gpios = pfc->info->gpio_irq[i].gpios; + pinmux_enum_t enum_id; + pinmux_enum_t *enum_ids; + int i, k, pos; + + pos = 0; + enum_id = 0; + while (1) { + pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id); + if (pos <= 0 || !enum_id) + break; - for (k = 0; gpios[k]; k++) { - if (gpios[k] == offset) - return pfc->info->gpio_irq[i].irq; + for (i = 0; i < pfc->info->gpio_irq_size; i++) { + enum_ids = pfc->info->gpio_irq[i].enum_ids; + for (k = 0; enum_ids[k]; k++) { + if (enum_ids[k] == enum_id) + return pfc->info->gpio_irq[i].irq; + } } } return -ENOSYS; } -static int gpio_pin_setup(struct sh_pfc_chip *chip) +static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) { struct sh_pfc *pfc = chip->pfc; struct gpio_chip *gc = &chip->gpio_chip; - int ret; - - chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins), - GFP_KERNEL); - if (chip->pins == NULL) - return -ENOMEM; - - ret = gpio_setup_data_regs(chip); - if (ret < 0) - return ret; - - gc->request = gpio_pin_request; - gc->free = gpio_pin_free; - gc->direction_input = gpio_pin_direction_input; - gc->get = gpio_pin_get; - gc->direction_output = gpio_pin_direction_output; - gc->set = gpio_pin_set; - gc->to_irq = gpio_pin_to_irq; - gc->label = pfc->info->name; - gc->dev = pfc->dev; - gc->owner = THIS_MODULE; - gc->base = 0; - gc->ngpio = pfc->nr_pins; - - return 0; -} - -/* ----------------------------------------------------------------------------- - * Function GPIOs - */ - -static int gpio_function_request(struct gpio_chip *gc, unsigned offset) -{ - static bool __print_once; - struct sh_pfc *pfc = gpio_to_pfc(gc); - unsigned int mark = pfc->info->func_gpios[offset].enum_id; - unsigned long flags; - int ret; - - if (!__print_once) { - dev_notice(pfc->dev, - "Use of GPIO API for function requests is deprecated." - " Convert to pinctrl\n"); - __print_once = true; - } - - if (mark == 0) - return -EINVAL; + gc->request = sh_gpio_request; + gc->free = sh_gpio_free; + gc->direction_input = sh_gpio_direction_input; + gc->get = sh_gpio_get; + gc->direction_output = sh_gpio_direction_output; + gc->set = sh_gpio_set; + gc->to_irq = sh_gpio_to_irq; - spin_lock_irqsave(&pfc->lock, flags); - ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION); - spin_unlock_irqrestore(&pfc->lock, flags); - - return ret; -} - -static void gpio_function_free(struct gpio_chip *gc, unsigned offset) -{ -} - -static int gpio_function_setup(struct sh_pfc_chip *chip) -{ - struct sh_pfc *pfc = chip->pfc; - struct gpio_chip *gc = &chip->gpio_chip; - - gc->request = gpio_function_request; - gc->free = gpio_function_free; + WARN_ON(pfc->info->first_gpio != 0); /* needs testing */ gc->label = pfc->info->name; gc->owner = THIS_MODULE; - gc->base = pfc->nr_pins; - gc->ngpio = pfc->info->nr_func_gpios; - - return 0; + gc->base = pfc->info->first_gpio; + gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1; } -/* ----------------------------------------------------------------------------- - * Register/unregister - */ - -static struct sh_pfc_chip * -sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), - struct sh_pfc_window *mem) +int sh_pfc_register_gpiochip(struct sh_pfc *pfc) { struct sh_pfc_chip *chip; int ret; chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); if (unlikely(!chip)) - return ERR_PTR(-ENOMEM); + return -ENOMEM; - chip->mem = mem; chip->pfc = pfc; - ret = setup(chip); - if (ret < 0) - return ERR_PTR(ret); + sh_pfc_gpio_setup(chip); ret = gpiochip_add(&chip->gpio_chip); if (unlikely(ret < 0)) - return ERR_PTR(ret); - - dev_info(pfc->dev, "%s handling gpio %u -> %u\n", - chip->gpio_chip.label, chip->gpio_chip.base, - chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); - - return chip; -} - -int sh_pfc_register_gpiochip(struct sh_pfc *pfc) -{ - const struct pinmux_range *ranges; - struct pinmux_range def_range; - struct sh_pfc_chip *chip; - unsigned int nr_ranges; - unsigned int i; - int ret; - - if (pfc->info->data_regs == NULL) - return 0; - - /* Find the memory window that contain the GPIO registers. Boards that - * register a separate GPIO device will not supply a memory resource - * that covers the data registers. In that case don't try to handle - * GPIOs. - */ - for (i = 0; i < pfc->num_windows; ++i) { - struct sh_pfc_window *window = &pfc->window[i]; - - if (pfc->info->data_regs[0].reg >= window->phys && - pfc->info->data_regs[0].reg < window->phys + window->size) - break; - } - - if (i == pfc->num_windows) - return 0; - - /* Register the real GPIOs chip. */ - chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]); - if (IS_ERR(chip)) - return PTR_ERR(chip); + return ret; pfc->gpio = chip; - /* Register the GPIO to pin mappings. */ - if (pfc->info->ranges == NULL) { - def_range.begin = 0; - def_range.end = pfc->info->nr_pins - 1; - ranges = &def_range; - nr_ranges = 1; - } else { - ranges = pfc->info->ranges; - nr_ranges = pfc->info->nr_ranges; - } - - for (i = 0; i < nr_ranges; ++i) { - const struct pinmux_range *range = &ranges[i]; - - ret = gpiochip_add_pin_range(&chip->gpio_chip, - dev_name(pfc->dev), - range->begin, range->begin, - range->end - range->begin + 1); - if (ret < 0) - return ret; - } - - /* Register the function GPIOs chip. */ - if (pfc->info->nr_func_gpios == 0) - return 0; - - chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); - if (IS_ERR(chip)) - return PTR_ERR(chip); - - pfc->func = chip; + pr_info("%s handling gpio %d -> %d\n", + pfc->info->name, pfc->info->first_gpio, + pfc->info->last_gpio); return 0; } int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) { - int err; + struct sh_pfc_chip *chip = pfc->gpio; int ret; - ret = gpiochip_remove(&pfc->gpio->gpio_chip); - err = gpiochip_remove(&pfc->func->gpio_chip); + ret = gpiochip_remove(&chip->gpio_chip); + if (unlikely(ret < 0)) + return ret; - return ret < 0 ? ret : err; + pfc->gpio = NULL; + return 0; } diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/trunk/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c deleted file mode 100644 index bbff5596e922..000000000000 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ /dev/null @@ -1,2587 +0,0 @@ -/* - * Copyright (C) 2012-2013 Renesas Solutions Corp. - * Copyright (C) 2013 Magnus Damm - * Copyright (C) 2012 Kuninori Morimoto - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include - -#include "core.h" -#include "sh_pfc.h" - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - /* Port0 - Port30 */ \ - PORT_10(fn, pfx, sfx), \ - PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##30, sfx), \ - /* Port32 - Port40 */ \ - PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \ - PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \ - PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \ - PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \ - PORT_1(fn, pfx##40, sfx), \ - /* Port64 - Port85 */ \ - PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \ - PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \ - PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \ - PORT_10(fn, pfx##7, sfx), \ - PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \ - PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \ - PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \ - /* Port96 - Port126 */ \ - PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \ - PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \ - PORT_10(fn, pfx##10, sfx), \ - PORT_10(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \ - PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \ - PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \ - PORT_1(fn, pfx##126, sfx), \ - /* Port128 - Port134 */ \ - PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ - PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \ - PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \ - PORT_1(fn, pfx##134, sfx), \ - /* Port160 - Port178 */ \ - PORT_10(fn, pfx##16, sfx), \ - PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \ - PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \ - PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \ - PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \ - PORT_1(fn, pfx##178, sfx), \ - /* Port192 - Port222 */ \ - PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ - PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ - PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ - PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ - PORT_10(fn, pfx##20, sfx), \ - PORT_10(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \ - PORT_1(fn, pfx##222, sfx), \ - /* Port224 - Port250 */ \ - PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \ - PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \ - PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \ - PORT_10(fn, pfx##23, sfx), \ - PORT_10(fn, pfx##24, sfx), \ - PORT_1(fn, pfx##250, sfx), \ - /* Port256 - Port283 */ \ - PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \ - PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \ - PORT_10(fn, pfx##26, sfx), \ - PORT_10(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ - PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \ - /* Port288 - Port308 */ \ - PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ - PORT_10(fn, pfx##29, sfx), \ - PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \ - PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \ - PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \ - PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \ - PORT_1(fn, pfx##308, sfx), \ - /* Port320 - Port329 */ \ - PORT_10(fn, pfx##32, sfx) - - -enum { - PINMUX_RESERVED = 0, - - /* PORT0_DATA -> PORT329_DATA */ - PINMUX_DATA_BEGIN, - PORT_ALL(DATA), - PINMUX_DATA_END, - - /* PORT0_IN -> PORT329_IN */ - PINMUX_INPUT_BEGIN, - PORT_ALL(IN), - PINMUX_INPUT_END, - - /* PORT0_OUT -> PORT329_OUT */ - PINMUX_OUTPUT_BEGIN, - PORT_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */ - PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */ - PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */ - PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */ - PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */ - PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */ - PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */ - PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */ - PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */ - PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */ - - MSEL1CR_31_0, MSEL1CR_31_1, - MSEL1CR_27_0, MSEL1CR_27_1, - MSEL1CR_25_0, MSEL1CR_25_1, - MSEL1CR_24_0, MSEL1CR_24_1, - MSEL1CR_22_0, MSEL1CR_22_1, - MSEL1CR_21_0, MSEL1CR_21_1, - MSEL1CR_20_0, MSEL1CR_20_1, - MSEL1CR_19_0, MSEL1CR_19_1, - MSEL1CR_18_0, MSEL1CR_18_1, - MSEL1CR_17_0, MSEL1CR_17_1, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - MSEL1CR_11_0, MSEL1CR_11_1, - MSEL1CR_10_0, MSEL1CR_10_1, - MSEL1CR_09_0, MSEL1CR_09_1, - MSEL1CR_08_0, MSEL1CR_08_1, - MSEL1CR_07_0, MSEL1CR_07_1, - MSEL1CR_06_0, MSEL1CR_06_1, - MSEL1CR_05_0, MSEL1CR_05_1, - MSEL1CR_04_0, MSEL1CR_04_1, - MSEL1CR_03_0, MSEL1CR_03_1, - MSEL1CR_02_0, MSEL1CR_02_1, - MSEL1CR_01_0, MSEL1CR_01_1, - MSEL1CR_00_0, MSEL1CR_00_1, - - MSEL3CR_31_0, MSEL3CR_31_1, - MSEL3CR_28_0, MSEL3CR_28_1, - MSEL3CR_27_0, MSEL3CR_27_1, - MSEL3CR_26_0, MSEL3CR_26_1, - MSEL3CR_23_0, MSEL3CR_23_1, - MSEL3CR_22_0, MSEL3CR_22_1, - MSEL3CR_21_0, MSEL3CR_21_1, - MSEL3CR_20_0, MSEL3CR_20_1, - MSEL3CR_19_0, MSEL3CR_19_1, - MSEL3CR_18_0, MSEL3CR_18_1, - MSEL3CR_17_0, MSEL3CR_17_1, - MSEL3CR_16_0, MSEL3CR_16_1, - MSEL3CR_15_0, MSEL3CR_15_1, - MSEL3CR_12_0, MSEL3CR_12_1, - MSEL3CR_11_0, MSEL3CR_11_1, - MSEL3CR_10_0, MSEL3CR_10_1, - MSEL3CR_09_0, MSEL3CR_09_1, - MSEL3CR_06_0, MSEL3CR_06_1, - MSEL3CR_03_0, MSEL3CR_03_1, - MSEL3CR_01_0, MSEL3CR_01_1, - MSEL3CR_00_0, MSEL3CR_00_1, - - MSEL4CR_30_0, MSEL4CR_30_1, - MSEL4CR_29_0, MSEL4CR_29_1, - MSEL4CR_28_0, MSEL4CR_28_1, - MSEL4CR_27_0, MSEL4CR_27_1, - MSEL4CR_26_0, MSEL4CR_26_1, - MSEL4CR_25_0, MSEL4CR_25_1, - MSEL4CR_24_0, MSEL4CR_24_1, - MSEL4CR_23_0, MSEL4CR_23_1, - MSEL4CR_22_0, MSEL4CR_22_1, - MSEL4CR_21_0, MSEL4CR_21_1, - MSEL4CR_20_0, MSEL4CR_20_1, - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - MSEL4CR_17_0, MSEL4CR_17_1, - MSEL4CR_16_0, MSEL4CR_16_1, - MSEL4CR_15_0, MSEL4CR_15_1, - MSEL4CR_14_0, MSEL4CR_14_1, - MSEL4CR_13_0, MSEL4CR_13_1, - MSEL4CR_12_0, MSEL4CR_12_1, - MSEL4CR_11_0, MSEL4CR_11_1, - MSEL4CR_10_0, MSEL4CR_10_1, - MSEL4CR_09_0, MSEL4CR_09_1, - MSEL4CR_07_0, MSEL4CR_07_1, - MSEL4CR_04_0, MSEL4CR_04_1, - MSEL4CR_01_0, MSEL4CR_01_1, - - MSEL5CR_31_0, MSEL5CR_31_1, - MSEL5CR_30_0, MSEL5CR_30_1, - MSEL5CR_29_0, MSEL5CR_29_1, - MSEL5CR_28_0, MSEL5CR_28_1, - MSEL5CR_27_0, MSEL5CR_27_1, - MSEL5CR_26_0, MSEL5CR_26_1, - MSEL5CR_25_0, MSEL5CR_25_1, - MSEL5CR_24_0, MSEL5CR_24_1, - MSEL5CR_23_0, MSEL5CR_23_1, - MSEL5CR_22_0, MSEL5CR_22_1, - MSEL5CR_21_0, MSEL5CR_21_1, - MSEL5CR_20_0, MSEL5CR_20_1, - MSEL5CR_19_0, MSEL5CR_19_1, - MSEL5CR_18_0, MSEL5CR_18_1, - MSEL5CR_17_0, MSEL5CR_17_1, - MSEL5CR_16_0, MSEL5CR_16_1, - MSEL5CR_15_0, MSEL5CR_15_1, - MSEL5CR_14_0, MSEL5CR_14_1, - MSEL5CR_13_0, MSEL5CR_13_1, - MSEL5CR_12_0, MSEL5CR_12_1, - MSEL5CR_11_0, MSEL5CR_11_1, - MSEL5CR_10_0, MSEL5CR_10_1, - MSEL5CR_09_0, MSEL5CR_09_1, - MSEL5CR_08_0, MSEL5CR_08_1, - MSEL5CR_07_0, MSEL5CR_07_1, - MSEL5CR_06_0, MSEL5CR_06_1, - - MSEL8CR_16_0, MSEL8CR_16_1, - MSEL8CR_01_0, MSEL8CR_01_1, - MSEL8CR_00_0, MSEL8CR_00_1, - - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - -#define F1(a) a##_MARK -#define F2(a) a##_MARK -#define F3(a) a##_MARK -#define F4(a) a##_MARK -#define F5(a) a##_MARK -#define F6(a) a##_MARK -#define F7(a) a##_MARK -#define IRQ(a) IRQ##a##_MARK - - F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */ - F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1), - F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2), - F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3), - F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4), - F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5), - F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6), - F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7), - F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8), - F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9), - F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */ - F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11), - F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12), - F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13), - F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14), - F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15), - F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0), - F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1), - F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2), - F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3), - F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */ - F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5), - F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6), - F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7), - F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24), - F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N), - F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N), - F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN), - F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT), - F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB), - F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE), - F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */ - - F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */ - F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS), - F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK), - F1(SCIFA1_RTS), F7(CSCIF1_RTS), - F1(SCIFA1_CTS), F7(CSCIF1_CTS), - F1(SCIFA1_SCK), F7(CSCIF1_SCK), - F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS), - F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS), - F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40), - F7(CHSCIF0_HSCK), /* Port40 */ - - F1(PDM0_DATA), /* Port64 */ - F1(PDM1_DATA), - F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4), - IRQ(40), - F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX), - F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68), - F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69), - F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0), - F7(CHSCIF1_HRTS), /* Port70 */ - F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1), - F7(CHSCIF1_HCTS), - F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX), - F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73), - F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0), - F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */ - F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */ - - F1(KEYIN0), /* Port96 */ - F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */ - F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42), - F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3), - F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */ - F2(KEYOUT7), F5(RFANAEN), IRQ(45), - F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46), - F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47), - F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48), - F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49), - F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX), - F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX), - F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */ - F3(SF_PORT_0_121), F4(SCIFB3_TXD_121), - F1(SCIFB0_TXD), F7(CHSCIF0_HTX), - F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124), - F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0), - F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1), - F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC), - F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1), - F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD), - F5(SIM0_VOLTSEL1), /* Port130 */ - F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK), - F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK), - F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1), - IRQ(20), /* Port160 */ - IRQ(21), IRQ(22), IRQ(23), - F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3), - F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */ - F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST), - IRQ(24), IRQ(25), IRQ(26), IRQ(27), - F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */ - F1(A9), F2(MMCD1_6), IRQ(32), - F1(A8), F2(MMCD1_5), IRQ(33), - F1(A7), F2(MMCD1_4), IRQ(34), - F1(A6), F2(MMCD1_3), IRQ(35), - F1(A5), F2(MMCD1_2), IRQ(36), - F1(A4), F2(MMCD1_1), IRQ(37), - F1(A3), F2(MMCD1_0), IRQ(38), - F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */ - F1(A1), - F1(A0), F2(BS), - F1(CKO), F2(MMCCLK1), - F1(CS0_N), F5(SIM0_GPO1), - F1(CS2_N), F5(SIM0_GPO2), - F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0), - F1(D15), F5(GIO_OUT15), - F1(D14), F5(GIO_OUT14), - F1(D13), F5(GIO_OUT13), - F1(D12), F5(GIO_OUT12), /* Port210 */ - F1(D11), F5(WGM_TXP2), - F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK), - F1(D9), F2(VIO_D9), F5(GIO_OUT9), - F1(D8), F2(VIO_D8), F5(GIO_OUT8), - F1(D7), F2(VIO_D7), F5(GIO_OUT7), - F1(D6), F2(VIO_D6), F5(GIO_OUT6), - F1(D5), F2(VIO_D5), F5(GIO_OUT5_217), - F1(D4), F2(VIO_D4), F5(GIO_OUT4_218), - F1(D3), F2(VIO_D3), F5(GIO_OUT3_219), - F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */ - F1(D1), F2(VIO_D1), F5(GIO_OUT1_221), - F1(D0), F2(VIO_D0), F5(GIO_OUT0_222), - F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2), - F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1), - F1(WE0_N), F2(RDWR_227), - F1(WE1_N), F5(SIM0_GPO0), - F1(PWMO), F2(VIO_CKO1_229), - F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */ - F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232), - F2(VIO_CKO3_233), F4(SF_PORT_1_233), - F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234), - F1(FSIAISLD), F2(PDM3_DATA_235), - F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236), - F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT), - F1(FSIAOSLD), F2(PDM0_OUTDATA_239), - F1(FSIBISLD), /* Port240 */ - F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242), - F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF), - F1(FSIBCK), F3(ISP_SHUTTER0_245), - F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248), - F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */ - F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2), - F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */ - F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262), - F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD), - F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1), - F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK), - F1(MSIOF1_SYNC), F4(MSIOF5_SYNC), - F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */ - F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272), - F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0), - F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP), - F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */ - F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282), - F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2), - F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */ - F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2), - F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2), - F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD), - F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52), - F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD), - F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC), - F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK), - F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300), - F4(MSIOF6_SS1), /* Port300 */ - F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1), - F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1), - F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1), - F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */ - IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54), - IRQ(55), IRQ(56), IRQ(57), - PINMUX_MARK_END, -}; - -#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) -#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) - -static const pinmux_enum_t pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - PINMUX_DATA_ALL(), - - /* Port0 */ - PINMUX_DATA(LCDD0_MARK, PORT0_FN1), - PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3), - PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7), - PINMUX_DATA(IRQ0_MARK, PORT0_FN0), - - /* Port1 */ - PINMUX_DATA(LCDD1_MARK, PORT1_FN1), - PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0), - PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7), - PINMUX_DATA(IRQ1_MARK, PORT1_FN0), - - /* Port2 */ - PINMUX_DATA(LCDD2_MARK, PORT2_FN1), - PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3), - PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7), - PINMUX_DATA(IRQ2_MARK, PORT2_FN0), - - /* Port3 */ - PINMUX_DATA(LCDD3_MARK, PORT3_FN1), - PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0), - PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7), - PINMUX_DATA(IRQ3_MARK, PORT3_FN0), - - /* Port4 */ - PINMUX_DATA(LCDD4_MARK, PORT4_FN1), - PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3), - PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7), - PINMUX_DATA(IRQ4_MARK, PORT4_FN0), - - /* Port5 */ - PINMUX_DATA(LCDD5_MARK, PORT5_FN1), - PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0), - PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7), - PINMUX_DATA(IRQ5_MARK, PORT5_FN0), - - /* Port6 */ - PINMUX_DATA(LCDD6_MARK, PORT6_FN1), - PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3), - PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7), - PINMUX_DATA(IRQ6_MARK, PORT6_FN0), - - /* Port7 */ - PINMUX_DATA(LCDD7_MARK, PORT7_FN1), - PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3), - PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7), - PINMUX_DATA(IRQ7_MARK, PORT7_FN0), - - /* Port8 */ - PINMUX_DATA(LCDD8_MARK, PORT8_FN1), - PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3), - PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7), - PINMUX_DATA(IRQ8_MARK, PORT8_FN0), - - /* Port9 */ - PINMUX_DATA(LCDD9_MARK, PORT9_FN1), - PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3), - PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7), - PINMUX_DATA(IRQ9_MARK, PORT9_FN0), - - /* Port10 */ - PINMUX_DATA(LCDD10_MARK, PORT10_FN1), - PINMUX_DATA(FSICCK_MARK, PORT10_FN3), - PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7), - PINMUX_DATA(IRQ10_MARK, PORT10_FN0), - - /* Port11 */ - PINMUX_DATA(LCDD11_MARK, PORT11_FN1), - PINMUX_DATA(FSICISLD_MARK, PORT11_FN3), - PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7), - PINMUX_DATA(IRQ11_MARK, PORT11_FN0), - - /* Port12 */ - PINMUX_DATA(LCDD12_MARK, PORT12_FN1), - PINMUX_DATA(FSICOMC_MARK, PORT12_FN3), - PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7), - PINMUX_DATA(IRQ12_MARK, PORT12_FN0), - - /* Port13 */ - PINMUX_DATA(LCDD13_MARK, PORT13_FN1), - PINMUX_DATA(FSICOLR_MARK, PORT13_FN3), - PINMUX_DATA(FSICILR_MARK, PORT13_FN4), - PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7), - PINMUX_DATA(IRQ13_MARK, PORT13_FN0), - - /* Port14 */ - PINMUX_DATA(LCDD14_MARK, PORT14_FN1), - PINMUX_DATA(FSICOBT_MARK, PORT14_FN3), - PINMUX_DATA(FSICIBT_MARK, PORT14_FN4), - PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7), - PINMUX_DATA(IRQ14_MARK, PORT14_FN0), - - /* Port15 */ - PINMUX_DATA(LCDD15_MARK, PORT15_FN1), - PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3), - PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7), - PINMUX_DATA(IRQ15_MARK, PORT15_FN0), - - /* Port16 */ - PINMUX_DATA(LCDD16_MARK, PORT16_FN1), - PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4), - PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7), - - /* Port17 */ - PINMUX_DATA(LCDD17_MARK, PORT17_FN1), - PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4), - PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7), - - /* Port18 */ - PINMUX_DATA(LCDD18_MARK, PORT18_FN1), - PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4), - PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7), - - /* Port19 */ - PINMUX_DATA(LCDD19_MARK, PORT19_FN1), - PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3), - PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7), - - /* Port20 */ - PINMUX_DATA(LCDD20_MARK, PORT20_FN1), - PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0), - PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7), - - /* Port21 */ - PINMUX_DATA(LCDD21_MARK, PORT21_FN1), - PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0), - PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7), - - /* Port22 */ - PINMUX_DATA(LCDD22_MARK, PORT22_FN1), - PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0), - PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7), - - /* Port23 */ - PINMUX_DATA(LCDD23_MARK, PORT23_FN1), - PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3), - PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7), - - /* Port24 */ - PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1), - PINMUX_DATA(LCDCS_MARK, PORT24_FN2), - PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3), - PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7), - - /* Port25 */ - PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1), - PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0), - PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7), - - /* Port26 */ - PINMUX_DATA(LCDDCK_MARK, PORT26_FN1), - PINMUX_DATA(LCDWR_MARK, PORT26_FN2), - PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0), - PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7), - - /* Port27 */ - PINMUX_DATA(LCDDISP_MARK, PORT27_FN1), - PINMUX_DATA(LCDRS_MARK, PORT27_FN2), - PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0), - PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7), - - /* Port28 */ - PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1), - PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3), - PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7), - - /* Port29 */ - PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1), - PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4), - PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7), - - /* Port30 */ - PINMUX_DATA(LCDDON_MARK, PORT30_FN1), - PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4), - PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7), - - /* Port32 */ - PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1), - PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5), - PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7), - - /* Port33 */ - PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1), - PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5), - PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7), - - /* Port34 */ - PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1), - PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5), - PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7), - - /* Port35 */ - PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1), - PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7), - - /* Port36 */ - PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1), - PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7), - - /* Port37 */ - PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1), - PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7), - - /* Port38 */ - PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1), - PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3), - PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4), - PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7), - - /* Port39 */ - PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1), - PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3), - PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1), - PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7), - - /* Port40 */ - PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1), - PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3), - PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4), - PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7), - - /* Port64 */ - PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1), - - /* Port65 */ - PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1), - - /* Port66 */ - PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1), - PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0), - PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3), - PINMUX_DATA(GenIO4_MARK, PORT66_FN5), - PINMUX_DATA(IRQ40_MARK, PORT66_FN0), - - /* Port67 */ - PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1), - PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1), - PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5), - PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7), - - /* Port68 */ - PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1), - PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0), - PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3), - PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5), - - /* Port69 */ - PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1), - PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0), - PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3), - PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5), - - /* Port70 */ - PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1), - PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2), - PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5), - PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6), - PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7), - - /* Port71 */ - PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1), - PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1), - PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5), - PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6), - PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7), - - /* Port72 */ - PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1), - PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1), - PINMUX_DATA(GenIO8_MARK, PORT72_FN5), - PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7), - - /* Port73 */ - PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1), - PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2), - PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3), - PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5), - - /* Port74 - Port85 */ - PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1), - PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1), - PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1), - PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1), - PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1), - PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1), - PINMUX_DATA(TXP_MARK, PORT80_FN1), - PINMUX_DATA(TXP2_MARK, PORT81_FN1), - PINMUX_DATA(COEX_0_MARK, PORT82_FN1), - PINMUX_DATA(COEX_1_MARK, PORT83_FN1), - PINMUX_DATA(IRQ19_MARK, PORT84_FN0), - PINMUX_DATA(IRQ18_MARK, PORT85_FN0), - - /* Port96 - Port101 */ - PINMUX_DATA(KEYIN0_MARK, PORT96_FN1), - PINMUX_DATA(KEYIN1_MARK, PORT97_FN1), - PINMUX_DATA(KEYIN2_MARK, PORT98_FN1), - PINMUX_DATA(KEYIN3_MARK, PORT99_FN1), - PINMUX_DATA(KEYIN4_MARK, PORT100_FN1), - PINMUX_DATA(KEYIN5_MARK, PORT101_FN1), - - /* Port102 */ - PINMUX_DATA(KEYIN6_MARK, PORT102_FN1), - PINMUX_DATA(IRQ41_MARK, PORT102_FN0), - - /* Port103 */ - PINMUX_DATA(KEYIN7_MARK, PORT103_FN1), - PINMUX_DATA(IRQ42_MARK, PORT103_FN0), - - /* Port104 - Port108 */ - PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2), - PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2), - PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2), - PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2), - PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2), - - /* Port109 */ - PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2), - PINMUX_DATA(IRQ43_MARK, PORT109_FN0), - - /* Port110 */ - PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2), - PINMUX_DATA(IRQ44_MARK, PORT110_FN0), - - /* Port111 */ - PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2), - PINMUX_DATA(RFANAEN_MARK, PORT111_FN5), - PINMUX_DATA(IRQ45_MARK, PORT111_FN0), - - /* Port112 */ - PINMUX_DATA(KEYIN8_MARK, PORT112_FN1), - PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2), - PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4), - PINMUX_DATA(IRQ46_MARK, PORT112_FN0), - - /* Port113 */ - PINMUX_DATA(KEYIN9_MARK, PORT113_FN1), - PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2), - PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4), - PINMUX_DATA(IRQ47_MARK, PORT113_FN0), - - /* Port114 */ - PINMUX_DATA(KEYIN10_MARK, PORT114_FN1), - PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2), - PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4), - PINMUX_DATA(IRQ48_MARK, PORT114_FN0), - - /* Port115 */ - PINMUX_DATA(KEYIN11_MARK, PORT115_FN1), - PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2), - PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4), - PINMUX_DATA(IRQ49_MARK, PORT115_FN0), - - /* Port116 */ - PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1), - PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7), - - /* Port117 */ - PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1), - PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7), - - /* Port118 */ - PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1), - PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7), - - /* Port119 */ - PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1), - PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7), - - /* Port120 */ - PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3), - PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1), - PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7), - - /* Port121 */ - PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3), - PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1), - - /* Port122 */ - PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1), - PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7), - - /* Port123 */ - PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1), - PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7), - - /* Port124 */ - PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3), - - /* Port125 */ - PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1), - PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2), - PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3), - PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5), - - /* Port126 */ - PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1), - PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2), - PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3), - - /* Port128 */ - PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1), - PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2), - PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3), - PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5), - - /* Port129 */ - PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1), - PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2), - PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3), - - /* Port130 */ - PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1), - PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1), - PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3), - PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5), - - /* Port131 */ - PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1), - PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5), - - /* Port132 */ - PINMUX_DATA(TS_SCK_MARK, PORT132_FN1), - PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2), - PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3), - - /* Port133 */ - PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1), - PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2), - PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3), - PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5), - - /* Port134 */ - PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1), - PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2), - PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3), - - /* Port160 - Port178 */ - PINMUX_DATA(IRQ20_MARK, PORT160_FN0), - PINMUX_DATA(IRQ21_MARK, PORT161_FN0), - PINMUX_DATA(IRQ22_MARK, PORT162_FN0), - PINMUX_DATA(IRQ23_MARK, PORT163_FN0), - PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1), - PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1), - PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1), - PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1), - PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1), - PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1), - PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1), - PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1), - PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1), - PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1), - PINMUX_DATA(MMCRST_MARK, PORT174_FN1), - PINMUX_DATA(IRQ24_MARK, PORT175_FN0), - PINMUX_DATA(IRQ25_MARK, PORT176_FN0), - PINMUX_DATA(IRQ26_MARK, PORT177_FN0), - PINMUX_DATA(IRQ27_MARK, PORT178_FN0), - - /* Port192 - Port200 FN1 */ - PINMUX_DATA(A10_MARK, PORT192_FN1), - PINMUX_DATA(A9_MARK, PORT193_FN1), - PINMUX_DATA(A8_MARK, PORT194_FN1), - PINMUX_DATA(A7_MARK, PORT195_FN1), - PINMUX_DATA(A6_MARK, PORT196_FN1), - PINMUX_DATA(A5_MARK, PORT197_FN1), - PINMUX_DATA(A4_MARK, PORT198_FN1), - PINMUX_DATA(A3_MARK, PORT199_FN1), - PINMUX_DATA(A2_MARK, PORT200_FN1), - - /* Port192 - Port200 FN2 */ - PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2), - PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2), - PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2), - PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2), - PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2), - PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2), - PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2), - PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2), - PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2), - - /* Port192 - Port200 IRQ */ - PINMUX_DATA(IRQ31_MARK, PORT192_FN0), - PINMUX_DATA(IRQ32_MARK, PORT193_FN0), - PINMUX_DATA(IRQ33_MARK, PORT194_FN0), - PINMUX_DATA(IRQ34_MARK, PORT195_FN0), - PINMUX_DATA(IRQ35_MARK, PORT196_FN0), - PINMUX_DATA(IRQ36_MARK, PORT197_FN0), - PINMUX_DATA(IRQ37_MARK, PORT198_FN0), - PINMUX_DATA(IRQ38_MARK, PORT199_FN0), - PINMUX_DATA(IRQ39_MARK, PORT200_FN0), - - /* Port201 */ - PINMUX_DATA(A1_MARK, PORT201_FN1), - - /* Port202 */ - PINMUX_DATA(A0_MARK, PORT202_FN1), - PINMUX_DATA(BS_MARK, PORT202_FN2), - - /* Port203 */ - PINMUX_DATA(CKO_MARK, PORT203_FN1), - PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2), - - /* Port204 */ - PINMUX_DATA(CS0_N_MARK, PORT204_FN1), - PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5), - - /* Port205 */ - PINMUX_DATA(CS2_N_MARK, PORT205_FN1), - PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5), - - /* Port206 */ - PINMUX_DATA(CS4_N_MARK, PORT206_FN1), - PINMUX_DATA(VIO_VD_MARK, PORT206_FN2), - PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5), - - /* Port207 - Port212 FN1 */ - PINMUX_DATA(D15_MARK, PORT207_FN1), - PINMUX_DATA(D14_MARK, PORT208_FN1), - PINMUX_DATA(D13_MARK, PORT209_FN1), - PINMUX_DATA(D12_MARK, PORT210_FN1), - PINMUX_DATA(D11_MARK, PORT211_FN1), - PINMUX_DATA(D10_MARK, PORT212_FN1), - - /* Port207 - Port212 FN5 */ - PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5), - PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5), - PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5), - PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5), - PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5), - PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5), - - /* Port213 - Port222 FN1 */ - PINMUX_DATA(D9_MARK, PORT213_FN1), - PINMUX_DATA(D8_MARK, PORT214_FN1), - PINMUX_DATA(D7_MARK, PORT215_FN1), - PINMUX_DATA(D6_MARK, PORT216_FN1), - PINMUX_DATA(D5_MARK, PORT217_FN1), - PINMUX_DATA(D4_MARK, PORT218_FN1), - PINMUX_DATA(D3_MARK, PORT219_FN1), - PINMUX_DATA(D2_MARK, PORT220_FN1), - PINMUX_DATA(D1_MARK, PORT221_FN1), - PINMUX_DATA(D0_MARK, PORT222_FN1), - - /* Port213 - Port222 FN2 */ - PINMUX_DATA(VIO_D9_MARK, PORT213_FN2), - PINMUX_DATA(VIO_D8_MARK, PORT214_FN2), - PINMUX_DATA(VIO_D7_MARK, PORT215_FN2), - PINMUX_DATA(VIO_D6_MARK, PORT216_FN2), - PINMUX_DATA(VIO_D5_MARK, PORT217_FN2), - PINMUX_DATA(VIO_D4_MARK, PORT218_FN2), - PINMUX_DATA(VIO_D3_MARK, PORT219_FN2), - PINMUX_DATA(VIO_D2_MARK, PORT220_FN2), - PINMUX_DATA(VIO_D1_MARK, PORT221_FN2), - PINMUX_DATA(VIO_D0_MARK, PORT222_FN2), - - /* Port213 - Port222 FN5 */ - PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5), - PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5), - PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5), - PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5), - PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5), - PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5), - PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5), - PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5), - PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5), - PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5), - - /* Port224 */ - PINMUX_DATA(RDWR_224_MARK, PORT224_FN1), - PINMUX_DATA(VIO_HD_MARK, PORT224_FN2), - PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5), - - /* Port225 */ - PINMUX_DATA(RD_N_MARK, PORT225_FN1), - - /* Port226 */ - PINMUX_DATA(WAIT_N_MARK, PORT226_FN1), - PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2), - PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5), - - /* Port227 */ - PINMUX_DATA(WE0_N_MARK, PORT227_FN1), - PINMUX_DATA(RDWR_227_MARK, PORT227_FN2), - - /* Port228 */ - PINMUX_DATA(WE1_N_MARK, PORT228_FN1), - PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5), - - /* Port229 */ - PINMUX_DATA(PWMO_MARK, PORT229_FN1), - PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2), - - /* Port230 */ - PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1), - PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2), - - /* Port231 */ - PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1), - PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2), - - /* Port232 */ - PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2), - PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4), - - /* Port233 */ - PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2), - PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4), - - /* Port234 */ - PINMUX_DATA(FSIACK_MARK, PORT234_FN1), - PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2), - PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3), - - /* Port235 */ - PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1), - PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1), - - /* Port236 */ - PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1), - PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2), - PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3), - - /* Port237 */ - PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1), - PINMUX_DATA(FSIAILR_MARK, PORT237_FN2), - - /* Port238 */ - PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1), - PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2), - - /* Port239 */ - PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1), - PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2), - - /* Port240 */ - PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1), - - /* Port241 */ - PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1), - PINMUX_DATA(FSIBILR_MARK, PORT241_FN2), - - /* Port242 */ - PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1), - PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3), - - /* Port243 */ - PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1), - PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2), - - /* Port244 */ - PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1), - PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2), - - /* Port245 */ - PINMUX_DATA(FSIBCK_MARK, PORT245_FN1), - PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3), - - /* Port246 - Port250 FN1 */ - PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1), - PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1), - PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1), - PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1), - PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1), - - /* Port256 - Port258 */ - PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1), - PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1), - PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1), - - /* Port259 */ - PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1), - PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3), - - /* Port260 */ - PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1), - - /* Port261 */ - PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2), - PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7), - - /* Port262 */ - PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2), - - /* Port263 - Port266 FN1 */ - PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1), - PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1), - PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1), - PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1), - - /* Port263 - Port266 FN4 */ - PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4), - PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4), - PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4), - PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4), - - /* Port267 */ - PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1), - - /* Port268 */ - PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1), - PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4), - - /* Port269 */ - PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1), - PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4), - - /* Port270 - Port273 FN1 */ - PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1), - PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1), - PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1), - PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1), - - /* Port270 - Port273 FN3 */ - PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3), - PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3), - PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3), - PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3), - - /* Port274 */ - PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1), - PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4), - - /* Port275 - Port280 */ - PINMUX_DATA(IC_DP_MARK, PORT275_FN1), - PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1), - PINMUX_DATA(IC_DM_MARK, PORT277_FN1), - PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1), - PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1), - PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1), - - /* Port281 */ - PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1), - PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1), - - /* Port282 */ - PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1), - PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2), - - /* Port283 */ - PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1), - - /* Port289 */ - PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1), - PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3), - - /* Port290 */ - PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1), - PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3), - PINMUX_DATA(IRQ51_MARK, PORT290_FN0), - - /* Port291 - Port294 FN1 */ - PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1), - PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1), - PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1), - PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1), - - /* Port291 - Port294 FN3 */ - PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3), - PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3), - PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3), - PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3), - - /* Port295 */ - PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1), - PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2), - PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1), - PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4), - - /* Port296 */ - PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1), - PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4), - PINMUX_DATA(IRQ52_MARK, PORT296_FN0), - - /* Port297 - Port300 FN1 */ - PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1), - PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1), - PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1), - PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1), - - /* Port297 - Port300 FN2 */ - PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2), - PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2), - PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2), - PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2), - - /* Port297 - Port300 FN3 */ - PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1), - PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1), - PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3), - PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3), - - /* Port297 - Port300 FN4 */ - PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4), - PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4), - PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4), - PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4), - - /* Port301 */ - PINMUX_DATA(SDHICD0_MARK, PORT301_FN1), - PINMUX_DATA(IRQ50_MARK, PORT301_FN0), - - /* Port302 - Port306 FN1 */ - PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1), - PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1), - PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1), - PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1), - PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1), - - /* Port302 - Port306 FN3 */ - PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3), - PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3), - PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3), - PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3), - PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3), - - /* Port307 */ - PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1), - - /* Port308 */ - PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1), - PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3), - - /* Port320 - Port329 */ - PINMUX_DATA(IRQ16_MARK, PORT320_FN0), - PINMUX_DATA(IRQ17_MARK, PORT321_FN0), - PINMUX_DATA(IRQ28_MARK, PORT322_FN0), - PINMUX_DATA(IRQ29_MARK, PORT323_FN0), - PINMUX_DATA(IRQ30_MARK, PORT324_FN0), - PINMUX_DATA(IRQ53_MARK, PORT325_FN0), - PINMUX_DATA(IRQ54_MARK, PORT326_FN0), - PINMUX_DATA(IRQ55_MARK, PORT327_FN0), - PINMUX_DATA(IRQ56_MARK, PORT328_FN0), - PINMUX_DATA(IRQ57_MARK, PORT329_FN0), -}; - -#define R8A73A4_PIN(pin, cfgs) \ - { \ - .name = __stringify(PORT##pin), \ - .enum_id = PORT##pin##_DATA, \ - .configs = cfgs, \ - } - -#define __O (SH_PFC_PIN_CFG_OUTPUT) -#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) - -#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD) -#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O) - -static struct sh_pfc_pin pinmux_pins[] = { - R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), - R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), - R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), - R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7), - R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9), - R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11), - R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13), - R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15), - R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17), - R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19), - R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21), - R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23), - R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25), - R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27), - R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29), - R8A73A4_PIN_IO_PU_PD(30), - R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33), - R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35), - R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37), - R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39), - R8A73A4_PIN_IO_PU_PD(40), - R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65), - R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67), - R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69), - R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71), - R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73), - R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75), - R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77), - R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79), - R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81), - R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83), - R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85), - R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97), - R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99), - R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101), - R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103), - R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105), - R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107), - R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109), - R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111), - R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113), - R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115), - R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117), - R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119), - R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121), - R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123), - R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125), - R8A73A4_PIN_IO_PU_PD(126), - R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129), - R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131), - R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133), - R8A73A4_PIN_IO_PU_PD(134), - R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161), - R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163), - R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165), - R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167), - R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169), - R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171), - R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173), - R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175), - R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177), - R8A73A4_PIN_IO_PU_PD(178), - R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193), - R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195), - R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197), - R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199), - R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201), - R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203), - R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205), - R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207), - R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209), - R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211), - R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213), - R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215), - R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217), - R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219), - R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221), - R8A73A4_PIN_IO_PU_PD(222), - R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225), - R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227), - R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229), - R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231), - R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233), - R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235), - R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237), - R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239), - R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241), - R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243), - R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245), - R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247), - R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249), - R8A73A4_PIN_IO_PU_PD(250), - R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257), - R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259), - R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261), - R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263), - R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265), - R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267), - R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269), - R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271), - R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273), - R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275), - R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277), - R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279), - R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281), - R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283), - R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289), - R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291), - R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293), - R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295), - R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297), - R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299), - R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301), - R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303), - R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305), - R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307), - R8A73A4_PIN_IO_PU_PD(308), - R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321), - R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323), - R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325), - R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327), - R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329), -}; - -static const struct pinmux_range pinmux_ranges[] = { - {.begin = 0, .end = 30,}, - {.begin = 32, .end = 40,}, - {.begin = 64, .end = 85,}, - {.begin = 96, .end = 126,}, - {.begin = 128, .end = 134,}, - {.begin = 160, .end = 178,}, - {.begin = 192, .end = 222,}, - {.begin = 224, .end = 250,}, - {.begin = 256, .end = 283,}, - {.begin = 288, .end = 308,}, - {.begin = 320, .end = 329,}, -}; - -/* - IRQC ------------------------------------------------------------------- */ -#define IRQC_PINS_MUX(pin, irq_mark) \ -static const unsigned int irqc_irq##irq_mark##_pins[] = { \ - pin, \ -}; \ -static const unsigned int irqc_irq##irq_mark##_mux[] = { \ - IRQ##irq_mark##_MARK, \ -} -IRQC_PINS_MUX(0, 0); -IRQC_PINS_MUX(1, 1); -IRQC_PINS_MUX(2, 2); -IRQC_PINS_MUX(3, 3); -IRQC_PINS_MUX(4, 4); -IRQC_PINS_MUX(5, 5); -IRQC_PINS_MUX(6, 6); -IRQC_PINS_MUX(7, 7); -IRQC_PINS_MUX(8, 8); -IRQC_PINS_MUX(9, 9); -IRQC_PINS_MUX(10, 10); -IRQC_PINS_MUX(11, 11); -IRQC_PINS_MUX(12, 12); -IRQC_PINS_MUX(13, 13); -IRQC_PINS_MUX(14, 14); -IRQC_PINS_MUX(15, 15); -IRQC_PINS_MUX(66, 40); -IRQC_PINS_MUX(84, 19); -IRQC_PINS_MUX(85, 18); -IRQC_PINS_MUX(102, 41); -IRQC_PINS_MUX(103, 42); -IRQC_PINS_MUX(109, 43); -IRQC_PINS_MUX(110, 44); -IRQC_PINS_MUX(111, 45); -IRQC_PINS_MUX(112, 46); -IRQC_PINS_MUX(113, 47); -IRQC_PINS_MUX(114, 48); -IRQC_PINS_MUX(115, 49); -IRQC_PINS_MUX(160, 20); -IRQC_PINS_MUX(161, 21); -IRQC_PINS_MUX(162, 22); -IRQC_PINS_MUX(163, 23); -IRQC_PINS_MUX(175, 24); -IRQC_PINS_MUX(176, 25); -IRQC_PINS_MUX(177, 26); -IRQC_PINS_MUX(178, 27); -IRQC_PINS_MUX(192, 31); -IRQC_PINS_MUX(193, 32); -IRQC_PINS_MUX(194, 33); -IRQC_PINS_MUX(195, 34); -IRQC_PINS_MUX(196, 35); -IRQC_PINS_MUX(197, 36); -IRQC_PINS_MUX(198, 37); -IRQC_PINS_MUX(199, 38); -IRQC_PINS_MUX(200, 39); -IRQC_PINS_MUX(290, 51); -IRQC_PINS_MUX(296, 52); -IRQC_PINS_MUX(301, 50); -IRQC_PINS_MUX(320, 16); -IRQC_PINS_MUX(321, 17); -IRQC_PINS_MUX(322, 28); -IRQC_PINS_MUX(323, 29); -IRQC_PINS_MUX(324, 30); -IRQC_PINS_MUX(325, 53); -IRQC_PINS_MUX(326, 54); -IRQC_PINS_MUX(327, 55); -IRQC_PINS_MUX(328, 56); -IRQC_PINS_MUX(329, 57); -/* - SCIFA0 ----------------------------------------------------------------- */ -static const unsigned int scifa0_data_pins[] = { - /* SCIFA0_RXD, SCIFA0_TXD */ - 117, 116, -}; -static const unsigned int scifa0_data_mux[] = { - SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, -}; -static const unsigned int scifa0_clk_pins[] = { - /* SCIFA0_SCK */ - 34, -}; -static const unsigned int scifa0_clk_mux[] = { - SCIFA0_SCK_MARK, -}; -static const unsigned int scifa0_ctrl_pins[] = { - /* SCIFA0_RTS, SCIFA0_CTS */ - 32, 33, -}; -static const unsigned int scifa0_ctrl_mux[] = { - SCIFA0_RTS_MARK, SCIFA0_CTS_MARK, -}; -/* - SCIFA1 ----------------------------------------------------------------- */ -static const unsigned int scifa1_data_pins[] = { - /* SCIFA1_RXD, SCIFA1_TXD */ - 119, 118, -}; -static const unsigned int scifa1_data_mux[] = { - SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, -}; -static const unsigned int scifa1_clk_pins[] = { - /* SCIFA1_SCK */ - 37, -}; -static const unsigned int scifa1_clk_mux[] = { - SCIFA1_SCK_MARK, -}; -static const unsigned int scifa1_ctrl_pins[] = { - /* SCIFA1_RTS, SCIFA1_CTS */ - 35, 36, -}; -static const unsigned int scifa1_ctrl_mux[] = { - SCIFA1_RTS_MARK, SCIFA1_CTS_MARK, -}; -/* - SCIFB0 ----------------------------------------------------------------- */ -static const unsigned int scifb0_data_pins[] = { - /* SCIFB0_RXD, SCIFB0_TXD */ - 123, 122, -}; -static const unsigned int scifb0_data_mux[] = { - SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, -}; -static const unsigned int scifb0_clk_pins[] = { - /* SCIFB0_SCK */ - 40, -}; -static const unsigned int scifb0_clk_mux[] = { - SCIFB0_SCK_MARK, -}; -static const unsigned int scifb0_ctrl_pins[] = { - /* SCIFB0_RTS, SCIFB0_CTS */ - 38, 39, -}; -static const unsigned int scifb0_ctrl_mux[] = { - SCIFB0_RTS_MARK, SCIFB0_CTS_MARK, -}; -/* - SCIFB1 ----------------------------------------------------------------- */ -static const unsigned int scifb1_data_pins[] = { - /* SCIFB1_RXD, SCIFB1_TXD */ - 27, 26, -}; -static const unsigned int scifb1_data_mux[] = { - SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK, -}; -static const unsigned int scifb1_clk_pins[] = { - /* SCIFB1_SCK */ - 28, -}; -static const unsigned int scifb1_clk_mux[] = { - SCIFB1_SCK_28_MARK, -}; -static const unsigned int scifb1_ctrl_pins[] = { - /* SCIFB1_RTS, SCIFB1_CTS */ - 24, 25, -}; -static const unsigned int scifb1_ctrl_mux[] = { - SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK, -}; -static const unsigned int scifb1_data_b_pins[] = { - /* SCIFB1_RXD, SCIFB1_TXD */ - 72, 67, -}; -static const unsigned int scifb1_data_b_mux[] = { - SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK, -}; -static const unsigned int scifb1_clk_b_pins[] = { - /* SCIFB1_SCK */ - 261, -}; -static const unsigned int scifb1_clk_b_mux[] = { - SCIFB1_SCK_261_MARK, -}; -static const unsigned int scifb1_ctrl_b_pins[] = { - /* SCIFB1_RTS, SCIFB1_CTS */ - 70, 71, -}; -static const unsigned int scifb1_ctrl_b_mux[] = { - SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK, -}; -/* - SCIFB2 ----------------------------------------------------------------- */ -static const unsigned int scifb2_data_pins[] = { - /* SCIFB2_RXD, SCIFB2_TXD */ - 69, 68, -}; -static const unsigned int scifb2_data_mux[] = { - SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK, -}; -static const unsigned int scifb2_clk_pins[] = { - /* SCIFB2_SCK */ - 262, -}; -static const unsigned int scifb2_clk_mux[] = { - SCIFB2_SCK_262_MARK, -}; -static const unsigned int scifb2_ctrl_pins[] = { - /* SCIFB2_RTS, SCIFB2_CTS */ - 73, 66, -}; -static const unsigned int scifb2_ctrl_mux[] = { - SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK, -}; -static const unsigned int scifb2_data_b_pins[] = { - /* SCIFB2_RXD, SCIFB2_TXD */ - 297, 295, -}; -static const unsigned int scifb2_data_b_mux[] = { - SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK, -}; -static const unsigned int scifb2_clk_b_pins[] = { - /* SCIFB2_SCK */ - 299, -}; -static const unsigned int scifb2_clk_b_mux[] = { - SCIFB2_SCK_299_MARK, -}; -static const unsigned int scifb2_ctrl_b_pins[] = { - /* SCIFB2_RTS, SCIFB2_CTS */ - 300, 298, -}; -static const unsigned int scifb2_ctrl_b_mux[] = { - SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK, -}; -/* - SCIFB3 ----------------------------------------------------------------- */ -static const unsigned int scifb3_data_pins[] = { - /* SCIFB3_RXD, SCIFB3_TXD */ - 22, 21, -}; -static const unsigned int scifb3_data_mux[] = { - SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK, -}; -static const unsigned int scifb3_clk_pins[] = { - /* SCIFB3_SCK */ - 23, -}; -static const unsigned int scifb3_clk_mux[] = { - SCIFB3_SCK_23_MARK, -}; -static const unsigned int scifb3_ctrl_pins[] = { - /* SCIFB3_RTS, SCIFB3_CTS */ - 19, 20, -}; -static const unsigned int scifb3_ctrl_mux[] = { - SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK, -}; -static const unsigned int scifb3_data_b_pins[] = { - /* SCIFB3_RXD, SCIFB3_TXD */ - 120, 121, -}; -static const unsigned int scifb3_data_b_mux[] = { - SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK, -}; -static const unsigned int scifb3_clk_b_pins[] = { - /* SCIFB3_SCK */ - 40, -}; -static const unsigned int scifb3_clk_b_mux[] = { - SCIFB3_SCK_40_MARK, -}; -static const unsigned int scifb3_ctrl_b_pins[] = { - /* SCIFB3_RTS, SCIFB3_CTS */ - 38, 39, -}; -static const unsigned int scifb3_ctrl_b_mux[] = { - SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(irqc_irq0), - SH_PFC_PIN_GROUP(irqc_irq1), - SH_PFC_PIN_GROUP(irqc_irq2), - SH_PFC_PIN_GROUP(irqc_irq3), - SH_PFC_PIN_GROUP(irqc_irq4), - SH_PFC_PIN_GROUP(irqc_irq5), - SH_PFC_PIN_GROUP(irqc_irq6), - SH_PFC_PIN_GROUP(irqc_irq7), - SH_PFC_PIN_GROUP(irqc_irq8), - SH_PFC_PIN_GROUP(irqc_irq9), - SH_PFC_PIN_GROUP(irqc_irq10), - SH_PFC_PIN_GROUP(irqc_irq11), - SH_PFC_PIN_GROUP(irqc_irq12), - SH_PFC_PIN_GROUP(irqc_irq13), - SH_PFC_PIN_GROUP(irqc_irq14), - SH_PFC_PIN_GROUP(irqc_irq15), - SH_PFC_PIN_GROUP(irqc_irq16), - SH_PFC_PIN_GROUP(irqc_irq17), - SH_PFC_PIN_GROUP(irqc_irq18), - SH_PFC_PIN_GROUP(irqc_irq19), - SH_PFC_PIN_GROUP(irqc_irq20), - SH_PFC_PIN_GROUP(irqc_irq21), - SH_PFC_PIN_GROUP(irqc_irq22), - SH_PFC_PIN_GROUP(irqc_irq23), - SH_PFC_PIN_GROUP(irqc_irq24), - SH_PFC_PIN_GROUP(irqc_irq25), - SH_PFC_PIN_GROUP(irqc_irq26), - SH_PFC_PIN_GROUP(irqc_irq27), - SH_PFC_PIN_GROUP(irqc_irq28), - SH_PFC_PIN_GROUP(irqc_irq29), - SH_PFC_PIN_GROUP(irqc_irq30), - SH_PFC_PIN_GROUP(irqc_irq31), - SH_PFC_PIN_GROUP(irqc_irq32), - SH_PFC_PIN_GROUP(irqc_irq33), - SH_PFC_PIN_GROUP(irqc_irq34), - SH_PFC_PIN_GROUP(irqc_irq35), - SH_PFC_PIN_GROUP(irqc_irq36), - SH_PFC_PIN_GROUP(irqc_irq37), - SH_PFC_PIN_GROUP(irqc_irq38), - SH_PFC_PIN_GROUP(irqc_irq39), - SH_PFC_PIN_GROUP(irqc_irq40), - SH_PFC_PIN_GROUP(irqc_irq41), - SH_PFC_PIN_GROUP(irqc_irq42), - SH_PFC_PIN_GROUP(irqc_irq43), - SH_PFC_PIN_GROUP(irqc_irq44), - SH_PFC_PIN_GROUP(irqc_irq45), - SH_PFC_PIN_GROUP(irqc_irq46), - SH_PFC_PIN_GROUP(irqc_irq47), - SH_PFC_PIN_GROUP(irqc_irq48), - SH_PFC_PIN_GROUP(irqc_irq49), - SH_PFC_PIN_GROUP(irqc_irq50), - SH_PFC_PIN_GROUP(irqc_irq51), - SH_PFC_PIN_GROUP(irqc_irq52), - SH_PFC_PIN_GROUP(irqc_irq53), - SH_PFC_PIN_GROUP(irqc_irq54), - SH_PFC_PIN_GROUP(irqc_irq55), - SH_PFC_PIN_GROUP(irqc_irq56), - SH_PFC_PIN_GROUP(irqc_irq57), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb3_data), - SH_PFC_PIN_GROUP(scifb3_clk), - SH_PFC_PIN_GROUP(scifb3_ctrl), - SH_PFC_PIN_GROUP(scifb3_data_b), - SH_PFC_PIN_GROUP(scifb3_clk_b), - SH_PFC_PIN_GROUP(scifb3_ctrl_b), -}; - -static const char * const irqc_groups[] = { - "irqc_irq0", - "irqc_irq1", - "irqc_irq2", - "irqc_irq3", - "irqc_irq4", - "irqc_irq5", - "irqc_irq6", - "irqc_irq7", - "irqc_irq8", - "irqc_irq9", - "irqc_irq10", - "irqc_irq11", - "irqc_irq12", - "irqc_irq13", - "irqc_irq14", - "irqc_irq15", - "irqc_irq16", - "irqc_irq17", - "irqc_irq18", - "irqc_irq19", - "irqc_irq20", - "irqc_irq21", - "irqc_irq22", - "irqc_irq23", - "irqc_irq24", - "irqc_irq25", - "irqc_irq26", - "irqc_irq27", - "irqc_irq28", - "irqc_irq29", - "irqc_irq30", - "irqc_irq31", - "irqc_irq32", - "irqc_irq33", - "irqc_irq34", - "irqc_irq35", - "irqc_irq36", - "irqc_irq37", - "irqc_irq38", - "irqc_irq39", - "irqc_irq40", - "irqc_irq41", - "irqc_irq42", - "irqc_irq43", - "irqc_irq44", - "irqc_irq45", - "irqc_irq46", - "irqc_irq47", - "irqc_irq48", - "irqc_irq49", - "irqc_irq50", - "irqc_irq51", - "irqc_irq52", - "irqc_irq53", - "irqc_irq54", - "irqc_irq55", - "irqc_irq56", - "irqc_irq57", -}; - -static const char * const scifa0_groups[] = { - "scifa0_data", - "scifa0_clk", - "scifa0_ctrl", -}; - -static const char * const scifa1_groups[] = { - "scifa1_data", - "scifa1_clk", - "scifa1_ctrl", -}; - -static const char * const scifb0_groups[] = { - "scifb0_data", - "scifb0_clk", - "scifb0_ctrl", -}; - -static const char * const scifb1_groups[] = { - "scifb1_data", - "scifb1_clk", - "scifb1_ctrl", - "scifb1_data_b", - "scifb1_clk_b", - "scifb1_ctrl_b", -}; - -static const char * const scifb2_groups[] = { - "scifb2_data", - "scifb2_clk", - "scifb2_ctrl", - "scifb2_data_b", - "scifb2_clk_b", - "scifb2_ctrl_b", -}; - -static const char * const scifb3_groups[] = { - "scifb3_data", - "scifb3_clk", - "scifb3_ctrl", - "scifb3_data_b", - "scifb3_clk_b", - "scifb3_ctrl_b", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(irqc), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scifb3), -}; - -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } - -static const struct pinmux_cfg_reg pinmux_config_regs[] = { - PORTCR(0, 0xe6050000), - PORTCR(1, 0xe6050001), - PORTCR(2, 0xe6050002), - PORTCR(3, 0xe6050003), - PORTCR(4, 0xe6050004), - PORTCR(5, 0xe6050005), - PORTCR(6, 0xe6050006), - PORTCR(7, 0xe6050007), - PORTCR(8, 0xe6050008), - PORTCR(9, 0xe6050009), - PORTCR(10, 0xe605000A), - PORTCR(11, 0xe605000B), - PORTCR(12, 0xe605000C), - PORTCR(13, 0xe605000D), - PORTCR(14, 0xe605000E), - PORTCR(15, 0xe605000F), - PORTCR(16, 0xe6050010), - PORTCR(17, 0xe6050011), - PORTCR(18, 0xe6050012), - PORTCR(19, 0xe6050013), - PORTCR(20, 0xe6050014), - PORTCR(21, 0xe6050015), - PORTCR(22, 0xe6050016), - PORTCR(23, 0xe6050017), - PORTCR(24, 0xe6050018), - PORTCR(25, 0xe6050019), - PORTCR(26, 0xe605001A), - PORTCR(27, 0xe605001B), - PORTCR(28, 0xe605001C), - PORTCR(29, 0xe605001D), - PORTCR(30, 0xe605001E), - PORTCR(32, 0xe6051020), - PORTCR(33, 0xe6051021), - PORTCR(34, 0xe6051022), - PORTCR(35, 0xe6051023), - PORTCR(36, 0xe6051024), - PORTCR(37, 0xe6051025), - PORTCR(38, 0xe6051026), - PORTCR(39, 0xe6051027), - PORTCR(40, 0xe6051028), - PORTCR(64, 0xe6050040), - PORTCR(65, 0xe6050041), - PORTCR(66, 0xe6050042), - PORTCR(67, 0xe6050043), - PORTCR(68, 0xe6050044), - PORTCR(69, 0xe6050045), - PORTCR(70, 0xe6050046), - PORTCR(71, 0xe6050047), - PORTCR(72, 0xe6050048), - PORTCR(73, 0xe6050049), - PORTCR(74, 0xe605004A), - PORTCR(75, 0xe605004B), - PORTCR(76, 0xe605004C), - PORTCR(77, 0xe605004D), - PORTCR(78, 0xe605004E), - PORTCR(79, 0xe605004F), - PORTCR(80, 0xe6050050), - PORTCR(81, 0xe6050051), - PORTCR(82, 0xe6050052), - PORTCR(83, 0xe6050053), - PORTCR(84, 0xe6050054), - PORTCR(85, 0xe6050055), - PORTCR(96, 0xe6051060), - PORTCR(97, 0xe6051061), - PORTCR(98, 0xe6051062), - PORTCR(99, 0xe6051063), - PORTCR(100, 0xe6051064), - PORTCR(101, 0xe6051065), - PORTCR(102, 0xe6051066), - PORTCR(103, 0xe6051067), - PORTCR(104, 0xe6051068), - PORTCR(105, 0xe6051069), - PORTCR(106, 0xe605106A), - PORTCR(107, 0xe605106B), - PORTCR(108, 0xe605106C), - PORTCR(109, 0xe605106D), - PORTCR(110, 0xe605106E), - PORTCR(111, 0xe605106F), - PORTCR(112, 0xe6051070), - PORTCR(113, 0xe6051071), - PORTCR(114, 0xe6051072), - PORTCR(115, 0xe6051073), - PORTCR(116, 0xe6051074), - PORTCR(117, 0xe6051075), - PORTCR(118, 0xe6051076), - PORTCR(119, 0xe6051077), - PORTCR(120, 0xe6051078), - PORTCR(121, 0xe6051079), - PORTCR(122, 0xe605107A), - PORTCR(123, 0xe605107B), - PORTCR(124, 0xe605107C), - PORTCR(125, 0xe605107D), - PORTCR(126, 0xe605107E), - PORTCR(128, 0xe6051080), - PORTCR(129, 0xe6051081), - PORTCR(130, 0xe6051082), - PORTCR(131, 0xe6051083), - PORTCR(132, 0xe6051084), - PORTCR(133, 0xe6051085), - PORTCR(134, 0xe6051086), - PORTCR(160, 0xe60520A0), - PORTCR(161, 0xe60520A1), - PORTCR(162, 0xe60520A2), - PORTCR(163, 0xe60520A3), - PORTCR(164, 0xe60520A4), - PORTCR(165, 0xe60520A5), - PORTCR(166, 0xe60520A6), - PORTCR(167, 0xe60520A7), - PORTCR(168, 0xe60520A8), - PORTCR(169, 0xe60520A9), - PORTCR(170, 0xe60520AA), - PORTCR(171, 0xe60520AB), - PORTCR(172, 0xe60520AC), - PORTCR(173, 0xe60520AD), - PORTCR(174, 0xe60520AE), - PORTCR(175, 0xe60520AF), - PORTCR(176, 0xe60520B0), - PORTCR(177, 0xe60520B1), - PORTCR(178, 0xe60520B2), - PORTCR(192, 0xe60520C0), - PORTCR(193, 0xe60520C1), - PORTCR(194, 0xe60520C2), - PORTCR(195, 0xe60520C3), - PORTCR(196, 0xe60520C4), - PORTCR(197, 0xe60520C5), - PORTCR(198, 0xe60520C6), - PORTCR(199, 0xe60520C7), - PORTCR(200, 0xe60520C8), - PORTCR(201, 0xe60520C9), - PORTCR(202, 0xe60520CA), - PORTCR(203, 0xe60520CB), - PORTCR(204, 0xe60520CC), - PORTCR(205, 0xe60520CD), - PORTCR(206, 0xe60520CE), - PORTCR(207, 0xe60520CF), - PORTCR(208, 0xe60520D0), - PORTCR(209, 0xe60520D1), - PORTCR(210, 0xe60520D2), - PORTCR(211, 0xe60520D3), - PORTCR(212, 0xe60520D4), - PORTCR(213, 0xe60520D5), - PORTCR(214, 0xe60520D6), - PORTCR(215, 0xe60520D7), - PORTCR(216, 0xe60520D8), - PORTCR(217, 0xe60520D9), - PORTCR(218, 0xe60520DA), - PORTCR(219, 0xe60520DB), - PORTCR(220, 0xe60520DC), - PORTCR(221, 0xe60520DD), - PORTCR(222, 0xe60520DE), - PORTCR(224, 0xe60520E0), - PORTCR(225, 0xe60520E1), - PORTCR(226, 0xe60520E2), - PORTCR(227, 0xe60520E3), - PORTCR(228, 0xe60520E4), - PORTCR(229, 0xe60520E5), - PORTCR(230, 0xe60520e6), - PORTCR(231, 0xe60520E7), - PORTCR(232, 0xe60520E8), - PORTCR(233, 0xe60520E9), - PORTCR(234, 0xe60520EA), - PORTCR(235, 0xe60520EB), - PORTCR(236, 0xe60520EC), - PORTCR(237, 0xe60520ED), - PORTCR(238, 0xe60520EE), - PORTCR(239, 0xe60520EF), - PORTCR(240, 0xe60520F0), - PORTCR(241, 0xe60520F1), - PORTCR(242, 0xe60520F2), - PORTCR(243, 0xe60520F3), - PORTCR(244, 0xe60520F4), - PORTCR(245, 0xe60520F5), - PORTCR(246, 0xe60520F6), - PORTCR(247, 0xe60520F7), - PORTCR(248, 0xe60520F8), - PORTCR(249, 0xe60520F9), - PORTCR(250, 0xe60520FA), - PORTCR(256, 0xe6052100), - PORTCR(257, 0xe6052101), - PORTCR(258, 0xe6052102), - PORTCR(259, 0xe6052103), - PORTCR(260, 0xe6052104), - PORTCR(261, 0xe6052105), - PORTCR(262, 0xe6052106), - PORTCR(263, 0xe6052107), - PORTCR(264, 0xe6052108), - PORTCR(265, 0xe6052109), - PORTCR(266, 0xe605210A), - PORTCR(267, 0xe605210B), - PORTCR(268, 0xe605210C), - PORTCR(269, 0xe605210D), - PORTCR(270, 0xe605210E), - PORTCR(271, 0xe605210F), - PORTCR(272, 0xe6052110), - PORTCR(273, 0xe6052111), - PORTCR(274, 0xe6052112), - PORTCR(275, 0xe6052113), - PORTCR(276, 0xe6052114), - PORTCR(277, 0xe6052115), - PORTCR(278, 0xe6052116), - PORTCR(279, 0xe6052117), - PORTCR(280, 0xe6052118), - PORTCR(281, 0xe6052119), - PORTCR(282, 0xe605211A), - PORTCR(283, 0xe605211B), - PORTCR(288, 0xe6053120), - PORTCR(289, 0xe6053121), - PORTCR(290, 0xe6053122), - PORTCR(291, 0xe6053123), - PORTCR(292, 0xe6053124), - PORTCR(293, 0xe6053125), - PORTCR(294, 0xe6053126), - PORTCR(295, 0xe6053127), - PORTCR(296, 0xe6053128), - PORTCR(297, 0xe6053129), - PORTCR(298, 0xe605312A), - PORTCR(299, 0xe605312B), - PORTCR(300, 0xe605312C), - PORTCR(301, 0xe605312D), - PORTCR(302, 0xe605312E), - PORTCR(303, 0xe605312F), - PORTCR(304, 0xe6053130), - PORTCR(305, 0xe6053131), - PORTCR(306, 0xe6053132), - PORTCR(307, 0xe6053133), - PORTCR(308, 0xe6053134), - PORTCR(320, 0xe6053140), - PORTCR(321, 0xe6053141), - PORTCR(322, 0xe6053142), - PORTCR(323, 0xe6053143), - PORTCR(324, 0xe6053144), - PORTCR(325, 0xe6053145), - PORTCR(326, 0xe6053146), - PORTCR(327, 0xe6053147), - PORTCR(328, 0xe6053148), - PORTCR(329, 0xe6053149), - - { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { - MSEL1CR_31_0, MSEL1CR_31_1, - 0, 0, - 0, 0, - 0, 0, - MSEL1CR_27_0, MSEL1CR_27_1, - 0, 0, - MSEL1CR_25_0, MSEL1CR_25_1, - MSEL1CR_24_0, MSEL1CR_24_1, - 0, 0, - MSEL1CR_22_0, MSEL1CR_22_1, - MSEL1CR_21_0, MSEL1CR_21_1, - MSEL1CR_20_0, MSEL1CR_20_1, - MSEL1CR_19_0, MSEL1CR_19_1, - MSEL1CR_18_0, MSEL1CR_18_1, - MSEL1CR_17_0, MSEL1CR_17_1, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - MSEL1CR_11_0, MSEL1CR_11_1, - MSEL1CR_10_0, MSEL1CR_10_1, - MSEL1CR_09_0, MSEL1CR_09_1, - MSEL1CR_08_0, MSEL1CR_08_1, - MSEL1CR_07_0, MSEL1CR_07_1, - MSEL1CR_06_0, MSEL1CR_06_1, - MSEL1CR_05_0, MSEL1CR_05_1, - MSEL1CR_04_0, MSEL1CR_04_1, - MSEL1CR_03_0, MSEL1CR_03_1, - MSEL1CR_02_0, MSEL1CR_02_1, - MSEL1CR_01_0, MSEL1CR_01_1, - MSEL1CR_00_0, MSEL1CR_00_1, - } - }, - { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { - MSEL3CR_31_0, MSEL3CR_31_1, - 0, 0, - 0, 0, - MSEL3CR_28_0, MSEL3CR_28_1, - MSEL3CR_27_0, MSEL3CR_27_1, - MSEL3CR_26_0, MSEL3CR_26_1, - 0, 0, - 0, 0, - MSEL3CR_23_0, MSEL3CR_23_1, - MSEL3CR_22_0, MSEL3CR_22_1, - MSEL3CR_21_0, MSEL3CR_21_1, - MSEL3CR_20_0, MSEL3CR_20_1, - MSEL3CR_19_0, MSEL3CR_19_1, - MSEL3CR_18_0, MSEL3CR_18_1, - MSEL3CR_17_0, MSEL3CR_17_1, - MSEL3CR_16_0, MSEL3CR_16_1, - MSEL3CR_15_0, MSEL3CR_15_1, - 0, 0, - 0, 0, - MSEL3CR_12_0, MSEL3CR_12_1, - MSEL3CR_11_0, MSEL3CR_11_1, - MSEL3CR_10_0, MSEL3CR_10_1, - MSEL3CR_09_0, MSEL3CR_09_1, - 0, 0, - 0, 0, - MSEL3CR_06_0, MSEL3CR_06_1, - 0, 0, - 0, 0, - MSEL3CR_03_0, MSEL3CR_03_1, - 0, 0, - MSEL3CR_01_0, MSEL3CR_01_1, - MSEL3CR_00_0, MSEL3CR_00_1, - } - }, - { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { - 0, 0, - MSEL4CR_30_0, MSEL4CR_30_1, - MSEL4CR_29_0, MSEL4CR_29_1, - MSEL4CR_28_0, MSEL4CR_28_1, - MSEL4CR_27_0, MSEL4CR_27_1, - MSEL4CR_26_0, MSEL4CR_26_1, - MSEL4CR_25_0, MSEL4CR_25_1, - MSEL4CR_24_0, MSEL4CR_24_1, - MSEL4CR_23_0, MSEL4CR_23_1, - MSEL4CR_22_0, MSEL4CR_22_1, - MSEL4CR_21_0, MSEL4CR_21_1, - MSEL4CR_20_0, MSEL4CR_20_1, - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - MSEL4CR_17_0, MSEL4CR_17_1, - MSEL4CR_16_0, MSEL4CR_16_1, - MSEL4CR_15_0, MSEL4CR_15_1, - MSEL4CR_14_0, MSEL4CR_14_1, - MSEL4CR_13_0, MSEL4CR_13_1, - MSEL4CR_12_0, MSEL4CR_12_1, - MSEL4CR_11_0, MSEL4CR_11_1, - MSEL4CR_10_0, MSEL4CR_10_1, - MSEL4CR_09_0, MSEL4CR_09_1, - 0, 0, - MSEL4CR_07_0, MSEL4CR_07_1, - 0, 0, - 0, 0, - MSEL4CR_04_0, MSEL4CR_04_1, - 0, 0, - 0, 0, - MSEL4CR_01_0, MSEL4CR_01_1, - 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { - MSEL5CR_31_0, MSEL5CR_31_1, - MSEL5CR_30_0, MSEL5CR_30_1, - MSEL5CR_29_0, MSEL5CR_29_1, - MSEL5CR_28_0, MSEL5CR_28_1, - MSEL5CR_27_0, MSEL5CR_27_1, - MSEL5CR_26_0, MSEL5CR_26_1, - MSEL5CR_25_0, MSEL5CR_25_1, - MSEL5CR_24_0, MSEL5CR_24_1, - MSEL5CR_23_0, MSEL5CR_23_1, - MSEL5CR_22_0, MSEL5CR_22_1, - MSEL5CR_21_0, MSEL5CR_21_1, - MSEL5CR_20_0, MSEL5CR_20_1, - MSEL5CR_19_0, MSEL5CR_19_1, - MSEL5CR_18_0, MSEL5CR_18_1, - MSEL5CR_17_0, MSEL5CR_17_1, - MSEL5CR_16_0, MSEL5CR_16_1, - MSEL5CR_15_0, MSEL5CR_15_1, - MSEL5CR_14_0, MSEL5CR_14_1, - MSEL5CR_13_0, MSEL5CR_13_1, - MSEL5CR_12_0, MSEL5CR_12_1, - MSEL5CR_11_0, MSEL5CR_11_1, - MSEL5CR_10_0, MSEL5CR_10_1, - MSEL5CR_09_0, MSEL5CR_09_1, - MSEL5CR_08_0, MSEL5CR_08_1, - MSEL5CR_07_0, MSEL5CR_07_1, - MSEL5CR_06_0, MSEL5CR_06_1, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - MSEL8CR_16_0, MSEL8CR_16_1, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - MSEL8CR_01_0, MSEL8CR_01_1, - MSEL8CR_00_0, MSEL8CR_00_1, - } - }, - { }, -}; - -static const struct pinmux_data_reg pinmux_data_regs[] = { - - { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { - 0, PORT30_DATA, PORT29_DATA, PORT28_DATA, - PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, - PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, - PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, - PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, - PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, - PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, - PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA, - } - }, - { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, PORT40_DATA, - PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, - PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA, - } - }, - { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, PORT85_DATA, PORT84_DATA, - PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, - PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, - PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, - PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, - PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA, - } - }, - { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) { - 0, PORT126_DATA, PORT125_DATA, PORT124_DATA, - PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, - PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, - PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, - PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, - PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, - PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, - PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA, - } - }, - { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, PORT134_DATA, PORT133_DATA, PORT132_DATA, - PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA, - } - }, - { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, PORT178_DATA, PORT177_DATA, PORT176_DATA, - PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, - PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, - PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, - PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA, - } - }, - { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) { - 0, PORT222_DATA, PORT221_DATA, PORT220_DATA, - PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, - PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, - PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, - PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, - PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, - PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, - PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA, - } - }, - { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) { - 0, 0, 0, 0, - 0, PORT250_DATA, PORT249_DATA, PORT248_DATA, - PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, - PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, - PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, - PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, - PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, - PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA, - } - }, - { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) { - 0, 0, 0, 0, - PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA, - PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, - PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, - PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, - PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, - PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, - PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA, - } - }, - { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, PORT308_DATA, - PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, - PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, - PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, - PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, - PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA, - } - }, - { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, PORT329_DATA, PORT328_DATA, - PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA, - PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA, - } - }, - { }, -}; - -static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), 0), - PINMUX_IRQ(irq_pin(1), 1), - PINMUX_IRQ(irq_pin(2), 2), - PINMUX_IRQ(irq_pin(3), 3), - PINMUX_IRQ(irq_pin(4), 4), - PINMUX_IRQ(irq_pin(5), 5), - PINMUX_IRQ(irq_pin(6), 6), - PINMUX_IRQ(irq_pin(7), 7), - PINMUX_IRQ(irq_pin(8), 8), - PINMUX_IRQ(irq_pin(9), 9), - PINMUX_IRQ(irq_pin(10), 10), - PINMUX_IRQ(irq_pin(11), 11), - PINMUX_IRQ(irq_pin(12), 12), - PINMUX_IRQ(irq_pin(13), 13), - PINMUX_IRQ(irq_pin(14), 14), - PINMUX_IRQ(irq_pin(15), 15), - PINMUX_IRQ(irq_pin(16), 320), - PINMUX_IRQ(irq_pin(17), 321), - PINMUX_IRQ(irq_pin(18), 85), - PINMUX_IRQ(irq_pin(19), 84), - PINMUX_IRQ(irq_pin(20), 160), - PINMUX_IRQ(irq_pin(21), 161), - PINMUX_IRQ(irq_pin(22), 162), - PINMUX_IRQ(irq_pin(23), 163), - PINMUX_IRQ(irq_pin(24), 175), - PINMUX_IRQ(irq_pin(25), 176), - PINMUX_IRQ(irq_pin(26), 177), - PINMUX_IRQ(irq_pin(27), 178), - PINMUX_IRQ(irq_pin(28), 322), - PINMUX_IRQ(irq_pin(29), 323), - PINMUX_IRQ(irq_pin(30), 324), - PINMUX_IRQ(irq_pin(31), 192), - PINMUX_IRQ(irq_pin(32), 193), - PINMUX_IRQ(irq_pin(33), 194), - PINMUX_IRQ(irq_pin(34), 195), - PINMUX_IRQ(irq_pin(35), 196), - PINMUX_IRQ(irq_pin(36), 197), - PINMUX_IRQ(irq_pin(37), 198), - PINMUX_IRQ(irq_pin(38), 199), - PINMUX_IRQ(irq_pin(39), 200), - PINMUX_IRQ(irq_pin(40), 66), - PINMUX_IRQ(irq_pin(41), 102), - PINMUX_IRQ(irq_pin(42), 103), - PINMUX_IRQ(irq_pin(43), 109), - PINMUX_IRQ(irq_pin(44), 110), - PINMUX_IRQ(irq_pin(45), 111), - PINMUX_IRQ(irq_pin(46), 112), - PINMUX_IRQ(irq_pin(47), 113), - PINMUX_IRQ(irq_pin(48), 114), - PINMUX_IRQ(irq_pin(49), 115), - PINMUX_IRQ(irq_pin(50), 301), - PINMUX_IRQ(irq_pin(51), 290), - PINMUX_IRQ(irq_pin(52), 296), - PINMUX_IRQ(irq_pin(53), 325), - PINMUX_IRQ(irq_pin(54), 326), - PINMUX_IRQ(irq_pin(55), 327), - PINMUX_IRQ(irq_pin(56), 328), - PINMUX_IRQ(irq_pin(57), 329), -}; - -#define PORTCR_PULMD_OFF (0 << 6) -#define PORTCR_PULMD_DOWN (2 << 6) -#define PORTCR_PULMD_UP (3 << 6) -#define PORTCR_PULMD_MASK (3 << 6) - -static const unsigned int r8a73a4_portcr_offsets[] = { - 0x00000000, 0x00001000, 0x00000000, 0x00001000, - 0x00001000, 0x00002000, 0x00002000, 0x00002000, - 0x00002000, 0x00003000, 0x00003000, -}; - -static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - void __iomem *addr; - - addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; - - switch (ioread8(addr) & PORTCR_PULMD_MASK) { - case PORTCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - void __iomem *addr; - u32 value; - - addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; - value = ioread8(addr) & ~PORTCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); -} - -static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { - .get_bias = r8a73a4_pinmux_get_bias, - .set_bias = r8a73a4_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info r8a73a4_pinmux_info = { - .name = "r8a73a4_pfc", - .ops = &r8a73a4_pinmux_ops, - - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - - .ranges = pinmux_ranges, - .nr_ranges = ARRAY_SIZE(pinmux_ranges), - - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), - - .gpio_irq = pinmux_irqs, - .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), -}; diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index bbd87d29bfd0..214788c4a606 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -577,7 +577,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ /* I/O and Pull U/D */ @@ -1654,532 +1654,11 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), }; -static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), -}; - -/* - LCD0 ------------------------------------------------------------------- */ -static const unsigned int lcd0_data8_pins[] = { - /* D[0:7] */ - 58, 57, 56, 55, 54, 53, 52, 51, -}; -static const unsigned int lcd0_data8_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, -}; -static const unsigned int lcd0_data9_pins[] = { - /* D[0:8] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, -}; -static const unsigned int lcd0_data9_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, -}; -static const unsigned int lcd0_data12_pins[] = { - /* D[0:11] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, -}; -static const unsigned int lcd0_data12_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, -}; -static const unsigned int lcd0_data16_pins[] = { - /* D[0:15] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, -}; -static const unsigned int lcd0_data16_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, -}; -static const unsigned int lcd0_data18_pins[] = { - /* D[0:17] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, -}; -static const unsigned int lcd0_data18_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, -}; -static const unsigned int lcd0_data24_0_pins[] = { - /* D[0:23] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, 40, 4, 3, 2, 0, 1, -}; -static const unsigned int lcd0_data24_0_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK, - LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK, - LCD0_D23_PORT1_MARK, -}; -static const unsigned int lcd0_data24_1_pins[] = { - /* D[0:23] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, 163, 162, 161, 158, 160, 159, -}; -static const unsigned int lcd0_data24_1_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK, - LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK, - LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK, -}; -static const unsigned int lcd0_display_pins[] = { - /* DON, VCPWC, VEPWC */ - 61, 59, 60, -}; -static const unsigned int lcd0_display_mux[] = { - LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, -}; -static const unsigned int lcd0_lclk_0_pins[] = { - /* LCLK */ - 102, -}; -static const unsigned int lcd0_lclk_0_mux[] = { - LCD0_LCLK_PORT102_MARK, -}; -static const unsigned int lcd0_lclk_1_pins[] = { - /* LCLK */ - 165, -}; -static const unsigned int lcd0_lclk_1_mux[] = { - LCD0_LCLK_PORT165_MARK, -}; -static const unsigned int lcd0_sync_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 63, 64, 62, 65, -}; -static const unsigned int lcd0_sync_mux[] = { - LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK, -}; -static const unsigned int lcd0_sys_pins[] = { - /* CS, WR, RD, RS */ - 64, 62, 164, 65, -}; -static const unsigned int lcd0_sys_mux[] = { - LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, -}; -/* - LCD1 ------------------------------------------------------------------- */ -static const unsigned int lcd1_data8_pins[] = { - /* D[0:7] */ - 4, 3, 2, 1, 0, 91, 92, 23, -}; -static const unsigned int lcd1_data8_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, -}; -static const unsigned int lcd1_data9_pins[] = { - /* D[0:8] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, -}; -static const unsigned int lcd1_data9_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, -}; -static const unsigned int lcd1_data12_pins[] = { - /* D[0:12] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, -}; -static const unsigned int lcd1_data12_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, -}; -static const unsigned int lcd1_data16_pins[] = { - /* D[0:15] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, -}; -static const unsigned int lcd1_data16_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, -}; -static const unsigned int lcd1_data18_pins[] = { - /* D[0:17] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, - 194, 193, -}; -static const unsigned int lcd1_data18_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, - LCD1_D16_MARK, LCD1_D17_MARK, -}; -static const unsigned int lcd1_data24_pins[] = { - /* D[0:23] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, - 194, 193, 198, 197, 75, 74, 15, 14, -}; -static const unsigned int lcd1_data24_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, - LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, - LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, -}; -static const unsigned int lcd1_display_pins[] = { - /* DON, VCPWC, VEPWC */ - 100, 5, 6, -}; -static const unsigned int lcd1_display_mux[] = { - LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK, -}; -static const unsigned int lcd1_lclk_pins[] = { - /* LCLK */ - 40, -}; -static const unsigned int lcd1_lclk_mux[] = { - LCD1_LCLK_MARK, -}; -static const unsigned int lcd1_sync_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 98, 97, 99, 12, -}; -static const unsigned int lcd1_sync_mux[] = { - LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK, -}; -static const unsigned int lcd1_sys_pins[] = { - /* CS, WR, RD, RS */ - 97, 99, 13, 12, -}; -static const unsigned int lcd1_sys_mux[] = { - LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, -}; -/* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 68, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMC0_D0_PORT68_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 68, 69, 70, 71, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { - /* D[0:7] */ - 68, 69, 70, 71, 72, 73, 74, 75, -}; -static const unsigned int mmc0_data8_0_mux[] = { - MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, - MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, -}; -static const unsigned int mmc0_ctrl_0_pins[] = { - /* CMD, CLK */ - 67, 66, -}; -static const unsigned int mmc0_ctrl_0_mux[] = { - MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, -}; - -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 149, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMC1_D0_PORT149_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 149, 148, 147, 146, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { - /* D[0:7] */ - 149, 148, 147, 146, 145, 144, 143, 142, -}; -static const unsigned int mmc0_data8_1_mux[] = { - MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, - MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, -}; -static const unsigned int mmc0_ctrl_1_pins[] = { - /* CMD, CLK */ - 104, 103, -}; -static const unsigned int mmc0_ctrl_1_mux[] = { - MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, -}; -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 77, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHI0_D0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { - /* D[0:3] */ - 77, 78, 79, 80, -}; -static const unsigned int sdhi0_data4_mux[] = { - SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CMD, CLK */ - 76, 82, -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SDHI0_CMD_MARK, SDHI0_CLK_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - 81, -}; -static const unsigned int sdhi0_cd_mux[] = { - SDHI0_CD_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - 83, -}; -static const unsigned int sdhi0_wp_mux[] = { - SDHI0_WP_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 68, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHI1_D0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - 68, 69, 70, 71, -}; -static const unsigned int sdhi1_data4_mux[] = { - SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CMD, CLK */ - 67, 66, -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SDHI1_CMD_MARK, SDHI1_CLK_MARK, -}; -static const unsigned int sdhi1_cd_pins[] = { - /* CD */ - 72, -}; -static const unsigned int sdhi1_cd_mux[] = { - SDHI1_CD_MARK, -}; -static const unsigned int sdhi1_wp_pins[] = { - /* WP */ - 73, -}; -static const unsigned int sdhi1_wp_mux[] = { - SDHI1_WP_MARK, -}; -/* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 205, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHI2_D0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - 205, 206, 207, 208, -}; -static const unsigned int sdhi2_data4_mux[] = { - SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CMD, CLK */ - 204, 203, -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SDHI2_CMD_MARK, SDHI2_CLK_MARK, -}; -static const unsigned int sdhi2_cd_0_pins[] = { - /* CD */ - 202, -}; -static const unsigned int sdhi2_cd_0_mux[] = { - SDHI2_CD_PORT202_MARK, -}; -static const unsigned int sdhi2_wp_0_pins[] = { - /* WP */ - 177, -}; -static const unsigned int sdhi2_wp_0_mux[] = { - SDHI2_WP_PORT177_MARK, -}; -static const unsigned int sdhi2_cd_1_pins[] = { - /* CD */ - 24, -}; -static const unsigned int sdhi2_cd_1_mux[] = { - SDHI2_CD_PORT24_MARK, -}; -static const unsigned int sdhi2_wp_1_pins[] = { - /* WP */ - 25, -}; -static const unsigned int sdhi2_wp_1_mux[] = { - SDHI2_WP_PORT25_MARK, -}; +static struct pinmux_gpio pinmux_gpios[] = { -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(lcd0_data8), - SH_PFC_PIN_GROUP(lcd0_data9), - SH_PFC_PIN_GROUP(lcd0_data12), - SH_PFC_PIN_GROUP(lcd0_data16), - SH_PFC_PIN_GROUP(lcd0_data18), - SH_PFC_PIN_GROUP(lcd0_data24_0), - SH_PFC_PIN_GROUP(lcd0_data24_1), - SH_PFC_PIN_GROUP(lcd0_display), - SH_PFC_PIN_GROUP(lcd0_lclk_0), - SH_PFC_PIN_GROUP(lcd0_lclk_1), - SH_PFC_PIN_GROUP(lcd0_sync), - SH_PFC_PIN_GROUP(lcd0_sys), - SH_PFC_PIN_GROUP(lcd1_data8), - SH_PFC_PIN_GROUP(lcd1_data9), - SH_PFC_PIN_GROUP(lcd1_data12), - SH_PFC_PIN_GROUP(lcd1_data16), - SH_PFC_PIN_GROUP(lcd1_data18), - SH_PFC_PIN_GROUP(lcd1_data24), - SH_PFC_PIN_GROUP(lcd1_display), - SH_PFC_PIN_GROUP(lcd1_lclk), - SH_PFC_PIN_GROUP(lcd1_sync), - SH_PFC_PIN_GROUP(lcd1_sys), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), - SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), - SH_PFC_PIN_GROUP(mmc0_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd_0), - SH_PFC_PIN_GROUP(sdhi2_wp_0), - SH_PFC_PIN_GROUP(sdhi2_cd_1), - SH_PFC_PIN_GROUP(sdhi2_wp_1), -}; - -static const char * const lcd0_groups[] = { - "lcd0_data8", - "lcd0_data9", - "lcd0_data12", - "lcd0_data16", - "lcd0_data18", - "lcd0_data24_0", - "lcd0_data24_1", - "lcd0_display", - "lcd0_lclk_0", - "lcd0_lclk_1", - "lcd0_sync", - "lcd0_sys", -}; - -static const char * const lcd1_groups[] = { - "lcd1_data8", - "lcd1_data9", - "lcd1_data12", - "lcd1_data16", - "lcd1_data18", - "lcd1_data24", - "lcd1_display", - "lcd1_lclk", - "lcd1_sync", - "lcd1_sys", -}; - -static const char * const mmc0_groups[] = { - "mmc0_data1_0", - "mmc0_data4_0", - "mmc0_data8_0", - "mmc0_ctrl_0", - "mmc0_data1_1", - "mmc0_data4_1", - "mmc0_data8_1", - "mmc0_ctrl_1", -}; - -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; - -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", - "sdhi1_cd", - "sdhi1_wp", -}; - -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_ctrl", - "sdhi2_cd_0", - "sdhi2_wp_0", - "sdhi2_cd_1", - "sdhi2_wp_1", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(lcd0), - SH_PFC_FUNCTION(lcd1), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + /* PORT */ + GPIO_PORT_ALL(), -static const struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), GPIO_FN(IRQ1), @@ -2313,6 +1792,43 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SCIFB_RTS_PORT172), GPIO_FN(SCIFB_CTS_PORT173), + /* LCD0 */ + GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), + GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), + GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), + GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), + GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), + GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), + GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), + GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), + GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), + GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), + GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), + + GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), + GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), + GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), + GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ + + GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), + GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), + GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), + GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), + GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), + GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), + GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), + GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), + GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), + GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), + GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), + GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), + GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), + GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), + GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), + /* RSPI */ GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), @@ -2373,6 +1889,26 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ GPIO_FN(SIM_D_PORT199), + /* SDHI0 */ + GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), + GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), + GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), + + /* SDHI1 */ + GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), + GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), + GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), + + /* SDHI2 */ + GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), + GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), + + GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ + GPIO_FN(SDHI2_WP_PORT25), + + GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ + GPIO_FN(SDHI2_CD_PORT202), + /* MSIOF2 */ GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), @@ -2417,6 +1953,21 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), GPIO_FN(MEMC_A0), + /* MMC */ + GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), + GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), + GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), + GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), + GPIO_FN(MMC0_CLK_PORT66), + GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ + + GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), + GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), + GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), + GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), + GPIO_FN(MMC1_CLK_PORT103), + GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ + /* MSIOF0 */ GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), @@ -2575,7 +2126,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TRACEAUD_FROM_MEMC), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -2889,7 +2440,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -2993,43 +2544,46 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ - PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ - PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ - PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ - PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ - PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ - PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ - PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ - PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ - PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ - PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ - PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ - PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ - PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ - PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ - PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ - PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ - PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ - PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ - PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ - PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ - PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ - PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ - PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ - PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ - PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ - PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ - PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ - PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ - PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ - PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ - PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ -}; - -const struct sh_pfc_soc_info r8a7740_pinmux_info = { +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ + PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ + PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ + PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ + PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ + PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ + PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ + PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ + PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ + PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ + PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ + PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ + PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ + PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ + PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ + PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ + PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ + PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ + PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ + PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ + PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ + PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ + PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ + PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ + PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ + PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ + PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ + PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ + PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ + PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ + PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ + PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ +}; + +struct sh_pfc_soc_info r8a7740_pinmux_info = { .name = "r8a7740_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, + PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, @@ -3038,19 +2592,15 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = { PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, + PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index 791a6719d8a9..13feaa0c0eb7 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -19,77 +19,57 @@ */ #include +#include #include "sh_pfc.h" -#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) - -#define PORT_GP_32(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ - PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ - PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ - PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ - PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ - PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ - PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ - PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ - PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ - PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ - PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ - PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) - -#define PORT_GP_32_9(bank, fn, sfx) \ - PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ - PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ - PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ - PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ - PORT_GP_1(bank, 8, fn, sfx) - -#define PORT_GP_32_REV(bank, fn, sfx) \ - PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ - PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ - PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ - PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ - PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ - PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ - PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ - PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ - PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ - PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ - PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ - PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ - PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ - PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ - PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ - PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) - -#define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx), \ - PORT_GP_32_9(6, fn, sfx) - -#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx - -#define _GP_GPIO(bank, pin, _name, sfx) \ - [(bank * 32) + pin] = { \ - .name = __stringify(_name), \ - .enum_id = _name##_DATA, \ - } - -#define _GP_DATA(bank, pin, name, sfx) \ - PINMUX_DATA(name##_DATA, name##_FN) - -#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT6(fn, pfx, sfx) \ + PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ + PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ + PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ + PORT_1(fn, pfx##8, sfx) + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT6(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ @@ -102,6 +82,14 @@ enum { GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ PINMUX_DATA_END, + PINMUX_INPUT_BEGIN, + GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */ + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */ + PINMUX_OUTPUT_END, + PINMUX_FUNCTION_BEGIN, GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ @@ -383,7 +371,7 @@ enum { FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, - FN_TS_SCK1, FN_DREQ2_B, FN_TX2, + FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, @@ -459,8 +447,7 @@ enum { A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, - USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK, - SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, + USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, SCIF_CLK_MARK, TCLK0_C_MARK, EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, @@ -645,7 +632,7 @@ enum { HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, - VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK, + VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, @@ -662,7 +649,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(AVS1_MARK, FN_AVS1), @@ -671,9 +658,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(A18_MARK, FN_A18), PINMUX_DATA(A19_MARK, FN_A19), - PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0), - PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), - PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), PINMUX_IPSR_DATA(IP0_2_0, PWM1), @@ -1415,6 +1399,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), + PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1), PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), PINMUX_IPSR_DATA(IP11_26_24, TX2), @@ -1465,1260 +1450,280 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO_GP_ALL(), -}; - -/* - DU0 -------------------------------------------------------------------- */ -static const unsigned int du0_rgb666_pins[] = { - /* R[7:2], G[7:2], B[7:2] */ - 188, 187, 186, 185, 184, 183, - 194, 193, 192, 191, 190, 189, - 200, 199, 198, 197, 196, 195, -}; -static const unsigned int du0_rgb666_mux[] = { - DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, - DU0_DR3_MARK, DU0_DR2_MARK, - DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, - DU0_DG3_MARK, DU0_DG2_MARK, - DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, - DU0_DB3_MARK, DU0_DB2_MARK, -}; -static const unsigned int du0_rgb888_pins[] = { - /* R[7:0], G[7:0], B[7:0] */ - 188, 187, 186, 185, 184, 183, 24, 23, - 194, 193, 192, 191, 190, 189, 26, 25, - 200, 199, 198, 197, 196, 195, 28, 27, -}; -static const unsigned int du0_rgb888_mux[] = { - DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, - DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, - DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, - DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, - DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, - DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, -}; -static const unsigned int du0_clk_in_pins[] = { - /* CLKIN */ - 29, -}; -static const unsigned int du0_clk_in_mux[] = { - DU0_DOTCLKIN_MARK, -}; -static const unsigned int du0_clk_out_0_pins[] = { - /* CLKOUT */ - 180, -}; -static const unsigned int du0_clk_out_0_mux[] = { - DU0_DOTCLKOUT0_MARK, -}; -static const unsigned int du0_clk_out_1_pins[] = { - /* CLKOUT */ - 30, -}; -static const unsigned int du0_clk_out_1_mux[] = { - DU0_DOTCLKOUT1_MARK, -}; -static const unsigned int du0_sync_0_pins[] = { - /* VSYNC, HSYNC, DISP */ - 182, 181, 31, -}; -static const unsigned int du0_sync_0_mux[] = { - DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, - DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK -}; -static const unsigned int du0_sync_1_pins[] = { - /* VSYNC, HSYNC, DISP */ - 182, 181, 32, -}; -static const unsigned int du0_sync_1_mux[] = { - DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, - DU0_DISP_MARK -}; -static const unsigned int du0_oddf_pins[] = { - /* ODDF */ - 31, -}; -static const unsigned int du0_oddf_mux[] = { - DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK -}; -static const unsigned int du0_cde_pins[] = { - /* CDE */ - 33, -}; -static const unsigned int du0_cde_mux[] = { - DU0_CDE_MARK -}; -/* - DU1 -------------------------------------------------------------------- */ -static const unsigned int du1_rgb666_pins[] = { - /* R[7:2], G[7:2], B[7:2] */ - 41, 40, 39, 38, 37, 36, - 49, 48, 47, 46, 45, 44, - 57, 56, 55, 54, 53, 52, -}; -static const unsigned int du1_rgb666_mux[] = { - DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, - DU1_DR3_MARK, DU1_DR2_MARK, - DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, - DU1_DG3_MARK, DU1_DG2_MARK, - DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, - DU1_DB3_MARK, DU1_DB2_MARK, -}; -static const unsigned int du1_rgb888_pins[] = { - /* R[7:0], G[7:0], B[7:0] */ - 41, 40, 39, 38, 37, 36, 35, 34, - 49, 48, 47, 46, 45, 44, 43, 32, - 57, 56, 55, 54, 53, 52, 51, 50, -}; -static const unsigned int du1_rgb888_mux[] = { - DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK, - DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK, - DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK, - DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK, - DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, - DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, -}; -static const unsigned int du1_clk_in_pins[] = { - /* CLKIN */ - 58, -}; -static const unsigned int du1_clk_in_mux[] = { - DU1_DOTCLKIN_MARK, -}; -static const unsigned int du1_clk_out_pins[] = { - /* CLKOUT */ - 59, -}; -static const unsigned int du1_clk_out_mux[] = { - DU1_DOTCLKOUT_MARK, -}; -static const unsigned int du1_sync_0_pins[] = { - /* VSYNC, HSYNC, DISP */ - 61, 60, 62, -}; -static const unsigned int du1_sync_0_mux[] = { - DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, - DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK -}; -static const unsigned int du1_sync_1_pins[] = { - /* VSYNC, HSYNC, DISP */ - 61, 60, 63, -}; -static const unsigned int du1_sync_1_mux[] = { - DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, - DU1_DISP_MARK -}; -static const unsigned int du1_oddf_pins[] = { - /* ODDF */ - 62, -}; -static const unsigned int du1_oddf_mux[] = { - DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK -}; -static const unsigned int du1_cde_pins[] = { - /* CDE */ - 64, -}; -static const unsigned int du1_cde_mux[] = { - DU1_CDE_MARK -}; -/* - HSPI0 ------------------------------------------------------------------ */ -static const unsigned int hspi0_pins[] = { - /* CLK, CS, RX, TX */ - 150, 151, 153, 152, -}; -static const unsigned int hspi0_mux[] = { - HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK, -}; -/* - HSPI1 ------------------------------------------------------------------ */ -static const unsigned int hspi1_pins[] = { - /* CLK, CS, RX, TX */ - 63, 58, 64, 62, -}; -static const unsigned int hspi1_mux[] = { - HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK, -}; -static const unsigned int hspi1_b_pins[] = { - /* CLK, CS, RX, TX */ - 90, 91, 93, 92, -}; -static const unsigned int hspi1_b_mux[] = { - HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK, -}; -static const unsigned int hspi1_c_pins[] = { - /* CLK, CS, RX, TX */ - 141, 142, 144, 143, -}; -static const unsigned int hspi1_c_mux[] = { - HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK, -}; -static const unsigned int hspi1_d_pins[] = { - /* CLK, CS, RX, TX */ - 101, 102, 104, 103, -}; -static const unsigned int hspi1_d_mux[] = { - HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK, -}; -/* - HSPI2 ------------------------------------------------------------------ */ -static const unsigned int hspi2_pins[] = { - /* CLK, CS, RX, TX */ - 9, 10, 11, 14, -}; -static const unsigned int hspi2_mux[] = { - HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK, -}; -static const unsigned int hspi2_b_pins[] = { - /* CLK, CS, RX, TX */ - 7, 13, 8, 6, -}; -static const unsigned int hspi2_b_mux[] = { - HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK, -}; -/* - INTC ------------------------------------------------------------------- */ -static const unsigned int intc_irq0_pins[] = { - /* IRQ */ - 78, -}; -static const unsigned int intc_irq0_mux[] = { - IRQ0_MARK, -}; -static const unsigned int intc_irq0_b_pins[] = { - /* IRQ */ - 141, -}; -static const unsigned int intc_irq0_b_mux[] = { - IRQ0_B_MARK, -}; -static const unsigned int intc_irq1_pins[] = { - /* IRQ */ - 79, -}; -static const unsigned int intc_irq1_mux[] = { - IRQ1_MARK, -}; -static const unsigned int intc_irq1_b_pins[] = { - /* IRQ */ - 142, -}; -static const unsigned int intc_irq1_b_mux[] = { - IRQ1_B_MARK, -}; -static const unsigned int intc_irq2_pins[] = { - /* IRQ */ - 88, -}; -static const unsigned int intc_irq2_mux[] = { - IRQ2_MARK, -}; -static const unsigned int intc_irq2_b_pins[] = { - /* IRQ */ - 143, -}; -static const unsigned int intc_irq2_b_mux[] = { - IRQ2_B_MARK, -}; -static const unsigned int intc_irq3_pins[] = { - /* IRQ */ - 89, -}; -static const unsigned int intc_irq3_mux[] = { - IRQ3_MARK, -}; -static const unsigned int intc_irq3_b_pins[] = { - /* IRQ */ - 144, -}; -static const unsigned int intc_irq3_b_mux[] = { - IRQ3_B_MARK, -}; -/* - LSBC ------------------------------------------------------------------- */ -static const unsigned int lbsc_cs0_pins[] = { - /* CS */ - 13, -}; -static const unsigned int lbsc_cs0_mux[] = { - CS0_MARK, -}; -static const unsigned int lbsc_cs1_pins[] = { - /* CS */ - 14, -}; -static const unsigned int lbsc_cs1_mux[] = { - CS1_A26_MARK, -}; -static const unsigned int lbsc_ex_cs0_pins[] = { - /* CS */ - 15, -}; -static const unsigned int lbsc_ex_cs0_mux[] = { - EX_CS0_MARK, -}; -static const unsigned int lbsc_ex_cs1_pins[] = { - /* CS */ - 16, -}; -static const unsigned int lbsc_ex_cs1_mux[] = { - EX_CS1_MARK, -}; -static const unsigned int lbsc_ex_cs2_pins[] = { - /* CS */ - 17, -}; -static const unsigned int lbsc_ex_cs2_mux[] = { - EX_CS2_MARK, -}; -static const unsigned int lbsc_ex_cs3_pins[] = { - /* CS */ - 18, -}; -static const unsigned int lbsc_ex_cs3_mux[] = { - EX_CS3_MARK, -}; -static const unsigned int lbsc_ex_cs4_pins[] = { - /* CS */ - 19, -}; -static const unsigned int lbsc_ex_cs4_mux[] = { - EX_CS4_MARK, -}; -static const unsigned int lbsc_ex_cs5_pins[] = { - /* CS */ - 20, -}; -static const unsigned int lbsc_ex_cs5_mux[] = { - EX_CS5_MARK, -}; -/* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - 19, -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - 19, 20, 21, 2, -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { - /* D[0:7] */ - 19, 20, 21, 2, 10, 11, 15, 16, -}; -static const unsigned int mmc0_data8_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, - MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, -}; -static const unsigned int mmc0_ctrl_pins[] = { - /* CMD, CLK */ - 18, 17, -}; -static const unsigned int mmc0_ctrl_mux[] = { - MMC0_CMD_MARK, MMC0_CLK_MARK, -}; -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - 72, -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - 72, 73, 74, 75, -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { - /* D[0:7] */ - 72, 73, 74, 75, 76, 77, 80, 81, -}; -static const unsigned int mmc1_data8_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, - MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, -}; -static const unsigned int mmc1_ctrl_pins[] = { - /* CMD, CLK */ - 68, 65, -}; -static const unsigned int mmc1_ctrl_mux[] = { - MMC1_CMD_MARK, MMC1_CLK_MARK, -}; -/* - SCIF0 ------------------------------------------------------------------ */ -static const unsigned int scif0_data_pins[] = { - /* RXD, TXD */ - 153, 152, -}; -static const unsigned int scif0_data_mux[] = { - RX0_MARK, TX0_MARK, -}; -static const unsigned int scif0_clk_pins[] = { - /* SCK */ - 156, -}; -static const unsigned int scif0_clk_mux[] = { - SCK0_MARK, -}; -static const unsigned int scif0_ctrl_pins[] = { - /* RTS, CTS */ - 151, 150, -}; -static const unsigned int scif0_ctrl_mux[] = { - RTS0_TANS_MARK, CTS0_MARK, -}; -static const unsigned int scif0_data_b_pins[] = { - /* RXD, TXD */ - 20, 19, -}; -static const unsigned int scif0_data_b_mux[] = { - RX0_B_MARK, TX0_B_MARK, -}; -static const unsigned int scif0_clk_b_pins[] = { - /* SCK */ - 33, -}; -static const unsigned int scif0_clk_b_mux[] = { - SCK0_B_MARK, -}; -static const unsigned int scif0_ctrl_b_pins[] = { - /* RTS, CTS */ - 18, 11, -}; -static const unsigned int scif0_ctrl_b_mux[] = { - RTS0_B_TANS_B_MARK, CTS0_B_MARK, -}; -static const unsigned int scif0_data_c_pins[] = { - /* RXD, TXD */ - 146, 147, -}; -static const unsigned int scif0_data_c_mux[] = { - RX0_C_MARK, TX0_C_MARK, -}; -static const unsigned int scif0_clk_c_pins[] = { - /* SCK */ - 145, -}; -static const unsigned int scif0_clk_c_mux[] = { - SCK0_C_MARK, -}; -static const unsigned int scif0_ctrl_c_pins[] = { - /* RTS, CTS */ - 149, 148, -}; -static const unsigned int scif0_ctrl_c_mux[] = { - RTS0_C_TANS_C_MARK, CTS0_C_MARK, -}; -static const unsigned int scif0_data_d_pins[] = { - /* RXD, TXD */ - 43, 42, -}; -static const unsigned int scif0_data_d_mux[] = { - RX0_D_MARK, TX0_D_MARK, -}; -static const unsigned int scif0_clk_d_pins[] = { - /* SCK */ - 50, -}; -static const unsigned int scif0_clk_d_mux[] = { - SCK0_D_MARK, -}; -static const unsigned int scif0_ctrl_d_pins[] = { - /* RTS, CTS */ - 51, 35, -}; -static const unsigned int scif0_ctrl_d_mux[] = { - RTS0_D_TANS_D_MARK, CTS0_D_MARK, -}; -/* - SCIF1 ------------------------------------------------------------------ */ -static const unsigned int scif1_data_pins[] = { - /* RXD, TXD */ - 149, 148, -}; -static const unsigned int scif1_data_mux[] = { - RX1_MARK, TX1_MARK, -}; -static const unsigned int scif1_clk_pins[] = { - /* SCK */ - 145, -}; -static const unsigned int scif1_clk_mux[] = { - SCK1_MARK, -}; -static const unsigned int scif1_ctrl_pins[] = { - /* RTS, CTS */ - 147, 146, -}; -static const unsigned int scif1_ctrl_mux[] = { - RTS1_TANS_MARK, CTS1_MARK, -}; -static const unsigned int scif1_data_b_pins[] = { - /* RXD, TXD */ - 117, 114, -}; -static const unsigned int scif1_data_b_mux[] = { - RX1_B_MARK, TX1_B_MARK, -}; -static const unsigned int scif1_clk_b_pins[] = { - /* SCK */ - 113, -}; -static const unsigned int scif1_clk_b_mux[] = { - SCK1_B_MARK, -}; -static const unsigned int scif1_ctrl_b_pins[] = { - /* RTS, CTS */ - 115, 116, -}; -static const unsigned int scif1_ctrl_b_mux[] = { - RTS1_B_TANS_B_MARK, CTS1_B_MARK, -}; -static const unsigned int scif1_data_c_pins[] = { - /* RXD, TXD */ - 67, 66, -}; -static const unsigned int scif1_data_c_mux[] = { - RX1_C_MARK, TX1_C_MARK, -}; -static const unsigned int scif1_clk_c_pins[] = { - /* SCK */ - 86, -}; -static const unsigned int scif1_clk_c_mux[] = { - SCK1_C_MARK, -}; -static const unsigned int scif1_ctrl_c_pins[] = { - /* RTS, CTS */ - 69, 68, -}; -static const unsigned int scif1_ctrl_c_mux[] = { - RTS1_C_TANS_C_MARK, CTS1_C_MARK, -}; -/* - SCIF2 ------------------------------------------------------------------ */ -static const unsigned int scif2_data_pins[] = { - /* RXD, TXD */ - 106, 105, -}; -static const unsigned int scif2_data_mux[] = { - RX2_MARK, TX2_MARK, -}; -static const unsigned int scif2_clk_pins[] = { - /* SCK */ - 107, -}; -static const unsigned int scif2_clk_mux[] = { - SCK2_MARK, -}; -static const unsigned int scif2_data_b_pins[] = { - /* RXD, TXD */ - 120, 119, -}; -static const unsigned int scif2_data_b_mux[] = { - RX2_B_MARK, TX2_B_MARK, -}; -static const unsigned int scif2_clk_b_pins[] = { - /* SCK */ - 118, -}; -static const unsigned int scif2_clk_b_mux[] = { - SCK2_B_MARK, -}; -static const unsigned int scif2_data_c_pins[] = { - /* RXD, TXD */ - 33, 31, -}; -static const unsigned int scif2_data_c_mux[] = { - RX2_C_MARK, TX2_C_MARK, -}; -static const unsigned int scif2_clk_c_pins[] = { - /* SCK */ - 32, -}; -static const unsigned int scif2_clk_c_mux[] = { - SCK2_C_MARK, -}; -static const unsigned int scif2_data_d_pins[] = { - /* RXD, TXD */ - 64, 62, -}; -static const unsigned int scif2_data_d_mux[] = { - RX2_D_MARK, TX2_D_MARK, -}; -static const unsigned int scif2_clk_d_pins[] = { - /* SCK */ - 63, -}; -static const unsigned int scif2_clk_d_mux[] = { - SCK2_D_MARK, -}; -static const unsigned int scif2_data_e_pins[] = { - /* RXD, TXD */ - 20, 19, -}; -static const unsigned int scif2_data_e_mux[] = { - RX2_E_MARK, TX2_E_MARK, -}; -/* - SCIF3 ------------------------------------------------------------------ */ -static const unsigned int scif3_data_pins[] = { - /* RXD, TXD */ - 137, 136, -}; -static const unsigned int scif3_data_mux[] = { - RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK, -}; -static const unsigned int scif3_clk_pins[] = { - /* SCK */ - 135, -}; -static const unsigned int scif3_clk_mux[] = { - SCK3_MARK, -}; - -static const unsigned int scif3_data_b_pins[] = { - /* RXD, TXD */ - 64, 62, -}; -static const unsigned int scif3_data_b_mux[] = { - RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK, -}; -static const unsigned int scif3_data_c_pins[] = { - /* RXD, TXD */ - 15, 12, -}; -static const unsigned int scif3_data_c_mux[] = { - RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK, -}; -static const unsigned int scif3_data_d_pins[] = { - /* RXD, TXD */ - 30, 29, -}; -static const unsigned int scif3_data_d_mux[] = { - RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK, -}; -static const unsigned int scif3_data_e_pins[] = { - /* RXD, TXD */ - 35, 34, -}; -static const unsigned int scif3_data_e_mux[] = { - RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK, -}; -static const unsigned int scif3_clk_e_pins[] = { - /* SCK */ - 42, -}; -static const unsigned int scif3_clk_e_mux[] = { - SCK3_E_MARK, -}; -/* - SCIF4 ------------------------------------------------------------------ */ -static const unsigned int scif4_data_pins[] = { - /* RXD, TXD */ - 123, 122, -}; -static const unsigned int scif4_data_mux[] = { - RX4_MARK, TX4_MARK, -}; -static const unsigned int scif4_clk_pins[] = { - /* SCK */ - 121, -}; -static const unsigned int scif4_clk_mux[] = { - SCK4_MARK, -}; -static const unsigned int scif4_data_b_pins[] = { - /* RXD, TXD */ - 111, 110, -}; -static const unsigned int scif4_data_b_mux[] = { - RX4_B_MARK, TX4_B_MARK, -}; -static const unsigned int scif4_clk_b_pins[] = { - /* SCK */ - 112, -}; -static const unsigned int scif4_clk_b_mux[] = { - SCK4_B_MARK, -}; -static const unsigned int scif4_data_c_pins[] = { - /* RXD, TXD */ - 22, 21, -}; -static const unsigned int scif4_data_c_mux[] = { - RX4_C_MARK, TX4_C_MARK, -}; -static const unsigned int scif4_data_d_pins[] = { - /* RXD, TXD */ - 69, 68, -}; -static const unsigned int scif4_data_d_mux[] = { - RX4_D_MARK, TX4_D_MARK, -}; -/* - SCIF5 ------------------------------------------------------------------ */ -static const unsigned int scif5_data_pins[] = { - /* RXD, TXD */ - 51, 50, -}; -static const unsigned int scif5_data_mux[] = { - RX5_MARK, TX5_MARK, -}; -static const unsigned int scif5_clk_pins[] = { - /* SCK */ - 43, -}; -static const unsigned int scif5_clk_mux[] = { - SCK5_MARK, -}; -static const unsigned int scif5_data_b_pins[] = { - /* RXD, TXD */ - 18, 11, -}; -static const unsigned int scif5_data_b_mux[] = { - RX5_B_MARK, TX5_B_MARK, -}; -static const unsigned int scif5_clk_b_pins[] = { - /* SCK */ - 19, -}; -static const unsigned int scif5_clk_b_mux[] = { - SCK5_B_MARK, -}; -static const unsigned int scif5_data_c_pins[] = { - /* RXD, TXD */ - 24, 23, -}; -static const unsigned int scif5_data_c_mux[] = { - RX5_C_MARK, TX5_C_MARK, -}; -static const unsigned int scif5_clk_c_pins[] = { - /* SCK */ - 28, -}; -static const unsigned int scif5_clk_c_mux[] = { - SCK5_C_MARK, -}; -static const unsigned int scif5_data_d_pins[] = { - /* RXD, TXD */ - 8, 6, -}; -static const unsigned int scif5_data_d_mux[] = { - RX5_D_MARK, TX5_D_MARK, -}; -static const unsigned int scif5_clk_d_pins[] = { - /* SCK */ - 7, -}; -static const unsigned int scif5_clk_d_mux[] = { - SCK5_D_MARK, -}; -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 117, -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { - /* D[0:3] */ - 117, 118, 119, 120, -}; -static const unsigned int sdhi0_data4_mux[] = { - SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CMD, CLK */ - 114, 113, -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SD0_CMD_MARK, SD0_CLK_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - 115, -}; -static const unsigned int sdhi0_cd_mux[] = { - SD0_CD_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - 116, -}; -static const unsigned int sdhi0_wp_mux[] = { - SD0_WP_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 19, -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - 19, 20, 21, 2, -}; -static const unsigned int sdhi1_data4_mux[] = { - SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CMD, CLK */ - 18, 17, -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SD1_CMD_MARK, SD1_CLK_MARK, -}; -static const unsigned int sdhi1_cd_pins[] = { - /* CD */ - 10, -}; -static const unsigned int sdhi1_cd_mux[] = { - SD1_CD_MARK, -}; -static const unsigned int sdhi1_wp_pins[] = { - /* WP */ - 11, -}; -static const unsigned int sdhi1_wp_mux[] = { - SD1_WP_MARK, -}; -/* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 97, -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - 97, 98, 99, 100, -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CMD, CLK */ - 102, 101, -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SD2_CMD_MARK, SD2_CLK_MARK, -}; -static const unsigned int sdhi2_cd_pins[] = { - /* CD */ - 103, -}; -static const unsigned int sdhi2_cd_mux[] = { - SD2_CD_MARK, -}; -static const unsigned int sdhi2_wp_pins[] = { - /* WP */ - 104, -}; -static const unsigned int sdhi2_wp_mux[] = { - SD2_WP_MARK, -}; -/* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - 50, -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - 50, 51, 52, 53, -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_ctrl_pins[] = { - /* CMD, CLK */ - 35, 34, -}; -static const unsigned int sdhi3_ctrl_mux[] = { - SD3_CMD_MARK, SD3_CLK_MARK, -}; -static const unsigned int sdhi3_cd_pins[] = { - /* CD */ - 62, -}; -static const unsigned int sdhi3_cd_mux[] = { - SD3_CD_MARK, -}; -static const unsigned int sdhi3_wp_pins[] = { - /* WP */ - 64, -}; -static const unsigned int sdhi3_wp_mux[] = { - SD3_WP_MARK, -}; -/* - USB0 ------------------------------------------------------------------- */ -static const unsigned int usb0_pins[] = { - /* OVC */ - 150, 154, -}; -static const unsigned int usb0_mux[] = { - USB_OVC0_MARK, USB_PENC0_MARK, -}; -/* - USB1 ------------------------------------------------------------------- */ -static const unsigned int usb1_pins[] = { - /* OVC */ - 152, 155, -}; -static const unsigned int usb1_mux[] = { - USB_OVC1_MARK, USB_PENC1_MARK, -}; -/* - USB2 ------------------------------------------------------------------- */ -static const unsigned int usb2_pins[] = { - /* OVC, PENC */ - 125, 156, -}; -static const unsigned int usb2_mux[] = { - USB_OVC2_MARK, USB_PENC2_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(du0_rgb666), - SH_PFC_PIN_GROUP(du0_rgb888), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du0_clk_out_0), - SH_PFC_PIN_GROUP(du0_clk_out_1), - SH_PFC_PIN_GROUP(du0_sync_0), - SH_PFC_PIN_GROUP(du0_sync_1), - SH_PFC_PIN_GROUP(du0_oddf), - SH_PFC_PIN_GROUP(du0_cde), - SH_PFC_PIN_GROUP(du1_rgb666), - SH_PFC_PIN_GROUP(du1_rgb888), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du1_clk_out), - SH_PFC_PIN_GROUP(du1_sync_0), - SH_PFC_PIN_GROUP(du1_sync_1), - SH_PFC_PIN_GROUP(du1_oddf), - SH_PFC_PIN_GROUP(du1_cde), - SH_PFC_PIN_GROUP(hspi0), - SH_PFC_PIN_GROUP(hspi1), - SH_PFC_PIN_GROUP(hspi1_b), - SH_PFC_PIN_GROUP(hspi1_c), - SH_PFC_PIN_GROUP(hspi1_d), - SH_PFC_PIN_GROUP(hspi2), - SH_PFC_PIN_GROUP(hspi2_b), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq0_b), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq1_b), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq2_b), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(intc_irq3_b), - SH_PFC_PIN_GROUP(lbsc_cs0), - SH_PFC_PIN_GROUP(lbsc_cs1), - SH_PFC_PIN_GROUP(lbsc_ex_cs0), - SH_PFC_PIN_GROUP(lbsc_ex_cs1), - SH_PFC_PIN_GROUP(lbsc_ex_cs2), - SH_PFC_PIN_GROUP(lbsc_ex_cs3), - SH_PFC_PIN_GROUP(lbsc_ex_cs4), - SH_PFC_PIN_GROUP(lbsc_ex_cs5), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), - SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), - SH_PFC_PIN_GROUP(mmc1_ctrl), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif0_clk_b), - SH_PFC_PIN_GROUP(scif0_ctrl_b), - SH_PFC_PIN_GROUP(scif0_data_c), - SH_PFC_PIN_GROUP(scif0_clk_c), - SH_PFC_PIN_GROUP(scif0_ctrl_c), - SH_PFC_PIN_GROUP(scif0_data_d), - SH_PFC_PIN_GROUP(scif0_clk_d), - SH_PFC_PIN_GROUP(scif0_ctrl_d), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_clk_b), - SH_PFC_PIN_GROUP(scif1_ctrl_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_clk_c), - SH_PFC_PIN_GROUP(scif1_ctrl_c), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif2_clk_b), - SH_PFC_PIN_GROUP(scif2_data_c), - SH_PFC_PIN_GROUP(scif2_clk_c), - SH_PFC_PIN_GROUP(scif2_data_d), - SH_PFC_PIN_GROUP(scif2_clk_d), - SH_PFC_PIN_GROUP(scif2_data_e), - SH_PFC_PIN_GROUP(scif3_data), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif3_data_c), - SH_PFC_PIN_GROUP(scif3_data_d), - SH_PFC_PIN_GROUP(scif3_data_e), - SH_PFC_PIN_GROUP(scif3_clk_e), - SH_PFC_PIN_GROUP(scif4_data), - SH_PFC_PIN_GROUP(scif4_clk), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_clk_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif4_data_d), - SH_PFC_PIN_GROUP(scif5_data), - SH_PFC_PIN_GROUP(scif5_clk), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scif5_clk_b), - SH_PFC_PIN_GROUP(scif5_data_c), - SH_PFC_PIN_GROUP(scif5_clk_c), - SH_PFC_PIN_GROUP(scif5_data_d), - SH_PFC_PIN_GROUP(scif5_clk_d), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), -}; - -static const char * const du0_groups[] = { - "du0_rgb666", - "du0_rgb888", - "du0_clk_in", - "du0_clk_out_0", - "du0_clk_out_1", - "du0_sync_0", - "du0_sync_1", - "du0_oddf", - "du0_cde", -}; - -static const char * const du1_groups[] = { - "du1_rgb666", - "du1_rgb888", - "du1_clk_in", - "du1_clk_out", - "du1_sync_0", - "du1_sync_1", - "du1_oddf", - "du1_cde", -}; - -static const char * const hspi0_groups[] = { - "hspi0", -}; - -static const char * const hspi1_groups[] = { - "hspi1", - "hspi1_b", - "hspi1_c", - "hspi1_d", -}; - -static const char * const hspi2_groups[] = { - "hspi2", - "hspi2_b", -}; - -static const char * const intc_groups[] = { - "intc_irq0", - "intc_irq0_b", - "intc_irq1", - "intc_irq1_b", - "intc_irq2", - "intc_irq2_b", - "intc_irq3", - "intc_irq3_b", -}; - -static const char * const lbsc_groups[] = { - "lbsc_cs0", - "lbsc_cs1", - "lbsc_ex_cs0", - "lbsc_ex_cs1", - "lbsc_ex_cs2", - "lbsc_ex_cs3", - "lbsc_ex_cs4", - "lbsc_ex_cs5", -}; - -static const char * const mmc0_groups[] = { - "mmc0_data1", - "mmc0_data4", - "mmc0_data8", - "mmc0_ctrl", -}; - -static const char * const mmc1_groups[] = { - "mmc1_data1", - "mmc1_data4", - "mmc1_data8", - "mmc1_ctrl", -}; - -static const char * const scif0_groups[] = { - "scif0_data", - "scif0_clk", - "scif0_ctrl", - "scif0_data_b", - "scif0_clk_b", - "scif0_ctrl_b", - "scif0_data_c", - "scif0_clk_c", - "scif0_ctrl_c", - "scif0_data_d", - "scif0_clk_d", - "scif0_ctrl_d", -}; + GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), + GPIO_FN(A19), -static const char * const scif1_groups[] = { - "scif1_data", - "scif1_clk", - "scif1_ctrl", - "scif1_data_b", - "scif1_clk_b", - "scif1_ctrl_b", - "scif1_data_c", - "scif1_clk_c", - "scif1_ctrl_c", -}; - -static const char * const scif2_groups[] = { - "scif2_data", - "scif2_clk", - "scif2_data_b", - "scif2_clk_b", - "scif2_data_c", - "scif2_clk_c", - "scif2_data_d", - "scif2_clk_d", - "scif2_data_e", -}; + /* IPSR0 */ + GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), + GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), + GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), + GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), + GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), + GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), + GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), + GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), + GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), + GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), + GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), + GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), + GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), + GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), + GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), + GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), + GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), -static const char * const scif3_groups[] = { - "scif3_data", - "scif3_clk", - "scif3_data_b", - "scif3_data_c", - "scif3_data_d", - "scif3_data_e", - "scif3_clk_e", -}; + /* IPSR1 */ + GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), + GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), + GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), + GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), + GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), + GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), + GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), + GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), + GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), + GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), + GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), + GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), + GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), + GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), + GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), + GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), + GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), + GPIO_FN(CC5_STATE34), -static const char * const scif4_groups[] = { - "scif4_data", - "scif4_clk", - "scif4_data_b", - "scif4_clk_b", - "scif4_data_c", - "scif4_data_d", -}; + /* IPSR2 */ + GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), + GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), + GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), + GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), + GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), + GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), + GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), + GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), + GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), + GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), + GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), + GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), + GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), + GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), + GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), + GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), + GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), + GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), + GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), + GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), + GPIO_FN(AUDATA2), -static const char * const scif5_groups[] = { - "scif5_data", - "scif5_clk", - "scif5_data_b", - "scif5_clk_b", - "scif5_data_c", - "scif5_clk_c", - "scif5_data_d", - "scif5_clk_d", -}; + /* IPSR3 */ + GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), + GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), + GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), + GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), + GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), + GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), + GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), + GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), + GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), + GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), + GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20), + GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6), + GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23), + GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), + GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK), + GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), + GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), + GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS), + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), + GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), + GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; + /* IPSR4 */ + GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), + GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), + GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), + GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), + GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), + GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), + GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), + GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), + GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), + GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4), + GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0), + GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), + GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1), + GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), + GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2), + GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4), + GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6), + GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0), + GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), + GPIO_FN(TX5), GPIO_FN(SCK0_D), -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", - "sdhi1_cd", - "sdhi1_wp", -}; + /* IPSR5 */ + GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), + GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), + GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5), + GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7), + GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D), + GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), + GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD), + GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC), + GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC), + GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), + GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), + GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), + GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), + GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6), + GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), + GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), + GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), + GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), + GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D), + GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), + GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), + GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_ctrl", - "sdhi2_cd", - "sdhi2_wp", -}; + /* IPSR6 */ + GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1), + GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2), + GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5), + GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6), + GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34), + GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX), + GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7), + GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C), + GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8), + GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), + GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), + GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), + GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D), + GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), + GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6), + GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), -static const char * const sdhi3_groups[] = { - "sdhi3_data1", - "sdhi3_data4", - "sdhi3_ctrl", - "sdhi3_cd", - "sdhi3_wp", -}; + /* IPSR7 */ + GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), + GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), + GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), + GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C), + GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), + GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), + GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), + GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), + GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK), + GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11), + GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1), + GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1), + GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1), + GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1), + GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2), + GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2), + GPIO_FN(CTS1_B), -static const char * const usb0_groups[] = { - "usb0", -}; + /* IPSR8 */ + GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), + GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), + GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), + GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), + GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), + GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), + GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), + GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), + GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), + GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), + GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), + GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), + GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), + GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB), + GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), + GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), + GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), + GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B), + GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), + GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), -static const char * const usb1_groups[] = { - "usb1", -}; + /* IPSR9 */ + GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), + GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), + GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), + GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), + GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), + GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), + GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), + GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), + GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), + GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), + GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7), + GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), + GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6), + GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B), + GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), + GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), + GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9), -static const char * const usb2_groups[] = { - "usb2", -}; + /* IPSR10 */ + GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), + GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), + GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), + GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), + GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), + GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), + GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), + GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B), + GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), + GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), + GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), + GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), + GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), + GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), + GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B), + GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), + GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), + GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), + GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C), + GPIO_FN(SPV_TRST), GPIO_FN(SCL3), -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(hspi0), - SH_PFC_FUNCTION(hspi1), - SH_PFC_FUNCTION(hspi2), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(lbsc), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), -}; + /* IPSR11 */ + GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), + GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), + GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), + GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), + GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), + GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN), + GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), + GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), + GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), + GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), + GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), + GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), + GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), + GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), + GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), + GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), + GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), + GPIO_FN(HRTS0_B), -static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IPSR12 */ + GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), + GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), + GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), + GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), + GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), + GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), + GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), + GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), + GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), + GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { GP_0_31_FN, FN_IP3_31_29, GP_0_30_FN, FN_IP3_26_24, @@ -3407,7 +2412,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, /* IP11_26_24 [3] */ - FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1, + FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, /* IP11_23_21 [3] */ FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, @@ -3553,24 +2558,66 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C1 [2] */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } }, + { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } }, + { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_8_IN, GP_6_8_OUT, + GP_6_7_IN, GP_6_7_OUT, + GP_6_6_IN, GP_6_6_OUT, + GP_6_5_IN, GP_6_5_OUT, + GP_6_4_IN, GP_6_4_OUT, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, + { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA, + GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, + GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } + }, { }, }; -const struct sh_pfc_soc_info r8a7779_pinmux_info = { +struct sh_pfc_soc_info r8a7779_pinmux_info = { .name = "r8a7779_pfc", .unlock_reg = 0xfffc0000, /* PMMR */ + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_SCK4_B, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, .gpio_data = pinmux_data, .gpio_data_size = ARRAY_SIZE(pinmux_data), diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7203.c index f63d51dc3f4c..01b425dfd162 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7203.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7203.c @@ -272,7 +272,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PA */ PINMUX_DATA(PA7_DATA, PA7_IN), @@ -703,7 +703,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), @@ -815,269 +815,265 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PF2, PF2_DATA), PINMUX_GPIO(GPIO_PF1, PF1_DATA), PINMUX_GPIO(GPIO_PF0, PF0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - GPIO_FN(PINT7_PB), - GPIO_FN(PINT6_PB), - GPIO_FN(PINT5_PB), - GPIO_FN(PINT4_PB), - GPIO_FN(PINT3_PB), - GPIO_FN(PINT2_PB), - GPIO_FN(PINT1_PB), - GPIO_FN(PINT0_PB), - GPIO_FN(PINT7_PD), - GPIO_FN(PINT6_PD), - GPIO_FN(PINT5_PD), - GPIO_FN(PINT4_PD), - GPIO_FN(PINT3_PD), - GPIO_FN(PINT2_PD), - GPIO_FN(PINT1_PD), - GPIO_FN(PINT0_PD), - GPIO_FN(IRQ7_PB), - GPIO_FN(IRQ6_PB), - GPIO_FN(IRQ5_PB), - GPIO_FN(IRQ4_PB), - GPIO_FN(IRQ3_PB), - GPIO_FN(IRQ2_PB), - GPIO_FN(IRQ1_PB), - GPIO_FN(IRQ0_PB), - GPIO_FN(IRQ7_PD), - GPIO_FN(IRQ6_PD), - GPIO_FN(IRQ5_PD), - GPIO_FN(IRQ4_PD), - GPIO_FN(IRQ3_PD), - GPIO_FN(IRQ2_PD), - GPIO_FN(IRQ1_PD), - GPIO_FN(IRQ0_PD), - GPIO_FN(IRQ7_PE), - GPIO_FN(IRQ6_PE), - GPIO_FN(IRQ5_PE), - GPIO_FN(IRQ4_PE), - GPIO_FN(IRQ3_PE), - GPIO_FN(IRQ2_PE), - GPIO_FN(IRQ1_PE), - GPIO_FN(IRQ0_PE), - - GPIO_FN(WDTOVF), - GPIO_FN(IRQOUT), - GPIO_FN(REFOUT), - GPIO_FN(IRQOUT_REFOUT), - GPIO_FN(UBCTRG), + PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), /* CAN */ - GPIO_FN(CTX1), - GPIO_FN(CRX1), - GPIO_FN(CTX0), - GPIO_FN(CTX0_CTX1), - GPIO_FN(CRX0), - GPIO_FN(CRX0_CRX1), + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), /* IIC3 */ - GPIO_FN(SDA3), - GPIO_FN(SCL3), - GPIO_FN(SDA2), - GPIO_FN(SCL2), - GPIO_FN(SDA1), - GPIO_FN(SCL1), - GPIO_FN(SDA0), - GPIO_FN(SCL0), + PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), + PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), /* DMAC */ - GPIO_FN(TEND0_PD), - GPIO_FN(TEND0_PE), - GPIO_FN(DACK0_PD), - GPIO_FN(DACK0_PE), - GPIO_FN(DREQ0_PD), - GPIO_FN(DREQ0_PE), - GPIO_FN(TEND1_PD), - GPIO_FN(TEND1_PE), - GPIO_FN(DACK1_PD), - GPIO_FN(DACK1_PE), - GPIO_FN(DREQ1_PD), - GPIO_FN(DREQ1_PE), - GPIO_FN(DACK2), - GPIO_FN(DREQ2), - GPIO_FN(DACK3), - GPIO_FN(DREQ3), + PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), + PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), + PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), + PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), + PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), + PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), /* ADC */ - GPIO_FN(ADTRG_PD), - GPIO_FN(ADTRG_PE), + PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), /* BSC */ - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(A21), - GPIO_FN(CS4), - GPIO_FN(MRES), - GPIO_FN(BS), - GPIO_FN(IOIS16), - GPIO_FN(CS1), - GPIO_FN(CS6_CE1B), - GPIO_FN(CE2B), - GPIO_FN(CS5_CE1A), - GPIO_FN(CE2A), - GPIO_FN(FRAME), - GPIO_FN(WAIT), - GPIO_FN(RDWR), - GPIO_FN(CKE), - GPIO_FN(CASU), - GPIO_FN(BREQ), - GPIO_FN(RASU), - GPIO_FN(BACK), - GPIO_FN(CASL), - GPIO_FN(RASL), - GPIO_FN(WE3_DQMUU_AH_ICIO_WR), - GPIO_FN(WE2_DQMUL_ICIORD), - GPIO_FN(WE1_DQMLU_WE), - GPIO_FN(WE0_DQMLL), - GPIO_FN(CS3), - GPIO_FN(CS2), - GPIO_FN(A1), - GPIO_FN(A0), - GPIO_FN(CS7), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), + PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), + PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), + PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), + PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), + PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), /* TMU */ - GPIO_FN(TIOC4D), - GPIO_FN(TIOC4C), - GPIO_FN(TIOC4B), - GPIO_FN(TIOC4A), - GPIO_FN(TIOC3D), - GPIO_FN(TIOC3C), - GPIO_FN(TIOC3B), - GPIO_FN(TIOC3A), - GPIO_FN(TIOC2B), - GPIO_FN(TIOC1B), - GPIO_FN(TIOC2A), - GPIO_FN(TIOC1A), - GPIO_FN(TIOC0D), - GPIO_FN(TIOC0C), - GPIO_FN(TIOC0B), - GPIO_FN(TIOC0A), - GPIO_FN(TCLKD_PD), - GPIO_FN(TCLKC_PD), - GPIO_FN(TCLKB_PD), - GPIO_FN(TCLKA_PD), - GPIO_FN(TCLKD_PF), - GPIO_FN(TCLKC_PF), - GPIO_FN(TCLKB_PF), - GPIO_FN(TCLKA_PF), + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), /* SSU */ - GPIO_FN(SCS0_PD), - GPIO_FN(SSO0_PD), - GPIO_FN(SSI0_PD), - GPIO_FN(SSCK0_PD), - GPIO_FN(SCS0_PF), - GPIO_FN(SSO0_PF), - GPIO_FN(SSI0_PF), - GPIO_FN(SSCK0_PF), - GPIO_FN(SCS1_PD), - GPIO_FN(SSO1_PD), - GPIO_FN(SSI1_PD), - GPIO_FN(SSCK1_PD), - GPIO_FN(SCS1_PF), - GPIO_FN(SSO1_PF), - GPIO_FN(SSI1_PF), - GPIO_FN(SSCK1_PF), + PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), /* SCIF */ - GPIO_FN(TXD0), - GPIO_FN(RXD0), - GPIO_FN(SCK0), - GPIO_FN(TXD1), - GPIO_FN(RXD1), - GPIO_FN(SCK1), - GPIO_FN(TXD2), - GPIO_FN(RXD2), - GPIO_FN(SCK2), - GPIO_FN(RTS3), - GPIO_FN(CTS3), - GPIO_FN(TXD3), - GPIO_FN(RXD3), - GPIO_FN(SCK3), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), /* SSI */ - GPIO_FN(AUDIO_CLK), - GPIO_FN(SSIDATA3), - GPIO_FN(SSIWS3), - GPIO_FN(SSISCK3), - GPIO_FN(SSIDATA2), - GPIO_FN(SSIWS2), - GPIO_FN(SSISCK2), - GPIO_FN(SSIDATA1), - GPIO_FN(SSIWS1), - GPIO_FN(SSISCK1), - GPIO_FN(SSIDATA0), - GPIO_FN(SSIWS0), - GPIO_FN(SSISCK0), + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), /* FLCTL */ - GPIO_FN(FCE), - GPIO_FN(FRB), - GPIO_FN(NAF7), - GPIO_FN(NAF6), - GPIO_FN(NAF5), - GPIO_FN(NAF4), - GPIO_FN(NAF3), - GPIO_FN(NAF2), - GPIO_FN(NAF1), - GPIO_FN(NAF0), - GPIO_FN(FSC), - GPIO_FN(FOE), - GPIO_FN(FCDE), - GPIO_FN(FWE), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), /* LCDC */ - GPIO_FN(LCD_VEPWC), - GPIO_FN(LCD_VCPWC), - GPIO_FN(LCD_CLK), - GPIO_FN(LCD_FLM), - GPIO_FN(LCD_M_DISP), - GPIO_FN(LCD_CL2), - GPIO_FN(LCD_CL1), - GPIO_FN(LCD_DON), - GPIO_FN(LCD_DATA15), - GPIO_FN(LCD_DATA14), - GPIO_FN(LCD_DATA13), - GPIO_FN(LCD_DATA12), - GPIO_FN(LCD_DATA11), - GPIO_FN(LCD_DATA10), - GPIO_FN(LCD_DATA9), - GPIO_FN(LCD_DATA8), - GPIO_FN(LCD_DATA7), - GPIO_FN(LCD_DATA6), - GPIO_FN(LCD_DATA5), - GPIO_FN(LCD_DATA4), - GPIO_FN(LCD_DATA3), - GPIO_FN(LCD_DATA2), - GPIO_FN(LCD_DATA1), - GPIO_FN(LCD_DATA0), + PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 0, 0, 0, 0, @@ -1529,7 +1525,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 0, 0, 0, 0, 0, 0, 0, 0, @@ -1575,17 +1571,19 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7203_pinmux_info = { +struct sh_pfc_soc_info sh7203_pinmux_info = { .name = "sh7203_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_LCD_DATA0, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 284675249ed9..2ba5639dcf34 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -604,7 +604,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* Port A */ PINMUX_DATA(PA3_DATA, PA3_IN), @@ -1072,7 +1072,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD_D2_MARK, PK0MD_10), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* Port A */ PINMUX_GPIO(GPIO_PA3, PA3_DATA), @@ -1216,261 +1216,257 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PK2, PK2_DATA), PINMUX_GPIO(GPIO_PK1, PK1_DATA), PINMUX_GPIO(GPIO_PK0, PK0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - GPIO_FN(PINT7_PG), - GPIO_FN(PINT6_PG), - GPIO_FN(PINT5_PG), - GPIO_FN(PINT4_PG), - GPIO_FN(PINT3_PG), - GPIO_FN(PINT2_PG), - GPIO_FN(PINT1_PG), - - GPIO_FN(IRQ7_PC), - GPIO_FN(IRQ6_PC), - GPIO_FN(IRQ5_PC), - GPIO_FN(IRQ4_PC), - GPIO_FN(IRQ3_PG), - GPIO_FN(IRQ2_PG), - GPIO_FN(IRQ1_PJ), - GPIO_FN(IRQ0_PJ), - GPIO_FN(IRQ3_PE), - GPIO_FN(IRQ2_PE), - GPIO_FN(IRQ1_PE), - GPIO_FN(IRQ0_PE), + PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), + + PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), /* WDT */ - GPIO_FN(WDTOVF), + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), /* CAN */ - GPIO_FN(CTX1), - GPIO_FN(CRX1), - GPIO_FN(CTX0), - GPIO_FN(CRX0), - GPIO_FN(CRX0_CRX1), + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), /* DMAC */ - GPIO_FN(TEND0), - GPIO_FN(DACK0), - GPIO_FN(DREQ0), - GPIO_FN(TEND1), - GPIO_FN(DACK1), - GPIO_FN(DREQ1), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), /* ADC */ - GPIO_FN(ADTRG), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), /* BSCh */ - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(A21), - GPIO_FN(A20), - GPIO_FN(A19), - GPIO_FN(A18), - GPIO_FN(A17), - GPIO_FN(A16), - GPIO_FN(A15), - GPIO_FN(A14), - GPIO_FN(A13), - GPIO_FN(A12), - GPIO_FN(A11), - GPIO_FN(A10), - GPIO_FN(A9), - GPIO_FN(A8), - GPIO_FN(A7), - GPIO_FN(A6), - GPIO_FN(A5), - GPIO_FN(A4), - GPIO_FN(A3), - GPIO_FN(A2), - GPIO_FN(A1), - GPIO_FN(A0), - - GPIO_FN(D15), - GPIO_FN(D14), - GPIO_FN(D13), - GPIO_FN(D12), - GPIO_FN(D11), - GPIO_FN(D10), - GPIO_FN(D9), - GPIO_FN(D8), - GPIO_FN(D7), - GPIO_FN(D6), - GPIO_FN(D5), - GPIO_FN(D4), - GPIO_FN(D3), - GPIO_FN(D2), - GPIO_FN(D1), - GPIO_FN(D0), - - GPIO_FN(BS), - GPIO_FN(CS4), - GPIO_FN(CS3), - GPIO_FN(CS2), - GPIO_FN(CS1), - GPIO_FN(CS0), - GPIO_FN(CS6CE1B), - GPIO_FN(CS5CE1A), - GPIO_FN(CE2A), - GPIO_FN(CE2B), - GPIO_FN(RD), - GPIO_FN(RDWR), - GPIO_FN(ICIOWRAH), - GPIO_FN(ICIORD), - GPIO_FN(WE1DQMUWE), - GPIO_FN(WE0DQML), - GPIO_FN(RAS), - GPIO_FN(CAS), - GPIO_FN(CKE), - GPIO_FN(WAIT), - GPIO_FN(BREQ), - GPIO_FN(BACK), - GPIO_FN(IOIS16), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), + PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), + PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), + PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), /* TMU */ - GPIO_FN(TIOC4D), - GPIO_FN(TIOC4C), - GPIO_FN(TIOC4B), - GPIO_FN(TIOC4A), - GPIO_FN(TIOC3D), - GPIO_FN(TIOC3C), - GPIO_FN(TIOC3B), - GPIO_FN(TIOC3A), - GPIO_FN(TIOC2B), - GPIO_FN(TIOC1B), - GPIO_FN(TIOC2A), - GPIO_FN(TIOC1A), - GPIO_FN(TIOC0D), - GPIO_FN(TIOC0C), - GPIO_FN(TIOC0B), - GPIO_FN(TIOC0A), - GPIO_FN(TCLKD), - GPIO_FN(TCLKC), - GPIO_FN(TCLKB), - GPIO_FN(TCLKA), + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), /* SCIF */ - GPIO_FN(TXD0), - GPIO_FN(RXD0), - GPIO_FN(SCK0), - GPIO_FN(TXD1), - GPIO_FN(RXD1), - GPIO_FN(SCK1), - GPIO_FN(TXD2), - GPIO_FN(RXD2), - GPIO_FN(SCK2), - GPIO_FN(RTS3), - GPIO_FN(CTS3), - GPIO_FN(TXD3), - GPIO_FN(RXD3), - GPIO_FN(SCK3), - GPIO_FN(TXD4), - GPIO_FN(RXD4), - GPIO_FN(TXD5), - GPIO_FN(RXD5), - GPIO_FN(TXD6), - GPIO_FN(RXD6), - GPIO_FN(TXD7), - GPIO_FN(RXD7), - GPIO_FN(RTS1), - GPIO_FN(CTS1), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), + PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), + PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), + PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), + PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), + PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), + PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), + PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), /* RSPI */ - GPIO_FN(RSPCK0), - GPIO_FN(MOSI0), - GPIO_FN(MISO0_PF12), - GPIO_FN(MISO1), - GPIO_FN(SSL00), - GPIO_FN(RSPCK1), - GPIO_FN(MOSI1), - GPIO_FN(MISO1_PG19), - GPIO_FN(SSL10), + PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), + PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), + PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), + PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), + PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), + PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), /* IIC3 */ - GPIO_FN(SCL0), - GPIO_FN(SCL1), - GPIO_FN(SCL2), - GPIO_FN(SDA0), - GPIO_FN(SDA1), - GPIO_FN(SDA2), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), /* SSI */ - GPIO_FN(SSISCK0), - GPIO_FN(SSIWS0), - GPIO_FN(SSITXD0), - GPIO_FN(SSIRXD0), - GPIO_FN(SSIWS1), - GPIO_FN(SSIWS2), - GPIO_FN(SSIWS3), - GPIO_FN(SSISCK1), - GPIO_FN(SSISCK2), - GPIO_FN(SSISCK3), - GPIO_FN(SSIDATA1), - GPIO_FN(SSIDATA2), - GPIO_FN(SSIDATA3), - GPIO_FN(AUDIO_CLK), + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - GPIO_FN(SIOFTXD), - GPIO_FN(SIOFRXD), - GPIO_FN(SIOFSYNC), - GPIO_FN(SIOFSCK), + PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - GPIO_FN(SPDIF_IN), - GPIO_FN(SPDIF_OUT), + PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), + PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - GPIO_FN(FCE), - GPIO_FN(FRB), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), /* VDC3 */ - GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), - GPIO_FN(DV_HSYNC), - - GPIO_FN(DV_DATA7), - GPIO_FN(DV_DATA6), - GPIO_FN(DV_DATA5), - GPIO_FN(DV_DATA4), - GPIO_FN(DV_DATA3), - GPIO_FN(DV_DATA2), - GPIO_FN(DV_DATA1), - GPIO_FN(DV_DATA0), - - GPIO_FN(LCD_CLK), - GPIO_FN(LCD_EXTCLK), - GPIO_FN(LCD_VSYNC), - GPIO_FN(LCD_HSYNC), - GPIO_FN(LCD_DE), - - GPIO_FN(LCD_DATA15), - GPIO_FN(LCD_DATA14), - GPIO_FN(LCD_DATA13), - GPIO_FN(LCD_DATA12), - GPIO_FN(LCD_DATA11), - GPIO_FN(LCD_DATA10), - GPIO_FN(LCD_DATA9), - GPIO_FN(LCD_DATA8), - GPIO_FN(LCD_DATA7), - GPIO_FN(LCD_DATA6), - GPIO_FN(LCD_DATA5), - GPIO_FN(LCD_DATA4), - GPIO_FN(LCD_DATA3), - GPIO_FN(LCD_DATA2), - GPIO_FN(LCD_DATA1), - GPIO_FN(LCD_DATA0), - - GPIO_FN(LCD_M_DISP), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + + PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2036,7 +2032,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 0, 0, 0, 0, 0, 0, 0, PA2_DATA } @@ -2114,17 +2110,19 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { } }; -const struct sh_pfc_soc_info sh7264_pinmux_info = { +struct sh_pfc_soc_info sh7264_pinmux_info = { .name = "sh7264_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PA3, + .last_gpio = GPIO_FN_LCD_M_DISP, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 4c401a74acd5..b1b5d6d4ad76 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -781,7 +781,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* Port A */ PINMUX_DATA(PA1_DATA, PA1_IN), @@ -1452,7 +1452,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PWM1A_MARK, PJ0MD_100), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* Port A */ PINMUX_GPIO(GPIO_PA1, PA1_DATA), PINMUX_GPIO(GPIO_PA0, PA0_DATA), @@ -1613,343 +1613,339 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* INTC */ - GPIO_FN(IRQ7_PG), - GPIO_FN(IRQ6_PG), - GPIO_FN(IRQ5_PG), - GPIO_FN(IRQ4_PG), - GPIO_FN(IRQ3_PG), - GPIO_FN(IRQ2_PG), - GPIO_FN(IRQ1_PG), - GPIO_FN(IRQ0_PG), - GPIO_FN(IRQ7_PF), - GPIO_FN(IRQ6_PF), - GPIO_FN(IRQ5_PF), - GPIO_FN(IRQ4_PF), - GPIO_FN(IRQ3_PJ), - GPIO_FN(IRQ2_PJ), - GPIO_FN(IRQ1_PJ), - GPIO_FN(IRQ0_PJ), - GPIO_FN(IRQ1_PC), - GPIO_FN(IRQ0_PC), - - GPIO_FN(PINT7_PG), - GPIO_FN(PINT6_PG), - GPIO_FN(PINT5_PG), - GPIO_FN(PINT4_PG), - GPIO_FN(PINT3_PG), - GPIO_FN(PINT2_PG), - GPIO_FN(PINT1_PG), - GPIO_FN(PINT0_PG), - GPIO_FN(PINT7_PH), - GPIO_FN(PINT6_PH), - GPIO_FN(PINT5_PH), - GPIO_FN(PINT4_PH), - GPIO_FN(PINT3_PH), - GPIO_FN(PINT2_PH), - GPIO_FN(PINT1_PH), - GPIO_FN(PINT0_PH), - GPIO_FN(PINT7_PJ), - GPIO_FN(PINT6_PJ), - GPIO_FN(PINT5_PJ), - GPIO_FN(PINT4_PJ), - GPIO_FN(PINT3_PJ), - GPIO_FN(PINT2_PJ), - GPIO_FN(PINT1_PJ), - GPIO_FN(PINT0_PJ), + PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), + + PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), /* WDT */ - GPIO_FN(WDTOVF), + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), /* CAN */ - GPIO_FN(CTX1), - GPIO_FN(CRX1), - GPIO_FN(CTX0), - GPIO_FN(CRX0), - GPIO_FN(CRX0_CRX1), - GPIO_FN(CRX0_CRX1_CRX2), + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK), /* DMAC */ - GPIO_FN(TEND0), - GPIO_FN(DACK0), - GPIO_FN(DREQ0), - GPIO_FN(TEND1), - GPIO_FN(DACK1), - GPIO_FN(DREQ1), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), /* ADC */ - GPIO_FN(ADTRG), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), /* BSCh */ - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(A21), - GPIO_FN(A20), - GPIO_FN(A19), - GPIO_FN(A18), - GPIO_FN(A17), - GPIO_FN(A16), - GPIO_FN(A15), - GPIO_FN(A14), - GPIO_FN(A13), - GPIO_FN(A12), - GPIO_FN(A11), - GPIO_FN(A10), - GPIO_FN(A9), - GPIO_FN(A8), - GPIO_FN(A7), - GPIO_FN(A6), - GPIO_FN(A5), - GPIO_FN(A4), - GPIO_FN(A3), - GPIO_FN(A2), - GPIO_FN(A1), - GPIO_FN(A0), - - GPIO_FN(D15), - GPIO_FN(D14), - GPIO_FN(D13), - GPIO_FN(D12), - GPIO_FN(D11), - GPIO_FN(D10), - GPIO_FN(D9), - GPIO_FN(D8), - GPIO_FN(D7), - GPIO_FN(D6), - GPIO_FN(D5), - GPIO_FN(D4), - GPIO_FN(D3), - GPIO_FN(D2), - GPIO_FN(D1), - GPIO_FN(D0), - - GPIO_FN(BS), - GPIO_FN(CS4), - GPIO_FN(CS3), - GPIO_FN(CS2), - GPIO_FN(CS1), - GPIO_FN(CS0), - GPIO_FN(CS5CE1A), - GPIO_FN(CE2A), - GPIO_FN(CE2B), - GPIO_FN(RD), - GPIO_FN(RDWR), - GPIO_FN(WE3ICIOWRAHDQMUU), - GPIO_FN(WE2ICIORDDQMUL), - GPIO_FN(WE1DQMUWE), - GPIO_FN(WE0DQML), - GPIO_FN(RAS), - GPIO_FN(CAS), - GPIO_FN(CKE), - GPIO_FN(WAIT), - GPIO_FN(BREQ), - GPIO_FN(BACK), - GPIO_FN(IOIS16), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), + PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), + PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), + PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), /* TMU */ - GPIO_FN(TIOC4D), - GPIO_FN(TIOC4C), - GPIO_FN(TIOC4B), - GPIO_FN(TIOC4A), - GPIO_FN(TIOC3D), - GPIO_FN(TIOC3C), - GPIO_FN(TIOC3B), - GPIO_FN(TIOC3A), - GPIO_FN(TIOC2B), - GPIO_FN(TIOC1B), - GPIO_FN(TIOC2A), - GPIO_FN(TIOC1A), - GPIO_FN(TIOC0D), - GPIO_FN(TIOC0C), - GPIO_FN(TIOC0B), - GPIO_FN(TIOC0A), - GPIO_FN(TCLKD), - GPIO_FN(TCLKC), - GPIO_FN(TCLKB), - GPIO_FN(TCLKA), + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), /* SCIF */ - GPIO_FN(SCK0), - GPIO_FN(TXD0), - GPIO_FN(RXD0), - GPIO_FN(SCK1), - GPIO_FN(TXD1), - GPIO_FN(RXD1), - GPIO_FN(RTS1), - GPIO_FN(CTS1), - GPIO_FN(SCK2), - GPIO_FN(TXD2), - GPIO_FN(RXD2), - GPIO_FN(SCK3), - GPIO_FN(TXD3), - GPIO_FN(RXD3), - GPIO_FN(SCK4), - GPIO_FN(TXD4), - GPIO_FN(RXD4), - GPIO_FN(SCK5), - GPIO_FN(TXD5), - GPIO_FN(RXD5), - GPIO_FN(RTS5), - GPIO_FN(CTS5), - GPIO_FN(SCK6), - GPIO_FN(TXD6), - GPIO_FN(RXD6), - GPIO_FN(SCK7), - GPIO_FN(TXD7), - GPIO_FN(RXD7), - GPIO_FN(RTS7), - GPIO_FN(CTS7), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), + PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), + PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), + PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), + PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), + PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), + PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), + PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), + PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), + PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), + PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), + PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), + PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), + PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), /* RSPI */ - GPIO_FN(RSPCK0_PJ16), - GPIO_FN(SSL00_PJ17), - GPIO_FN(MOSI0_PJ18), - GPIO_FN(MISO0_PJ19), - GPIO_FN(RSPCK0_PB17), - GPIO_FN(SSL00_PB18), - GPIO_FN(MOSI0_PB19), - GPIO_FN(MISO0_PB20), - GPIO_FN(RSPCK1), - GPIO_FN(MOSI1), - GPIO_FN(MISO1), - GPIO_FN(SSL10), + PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), + PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), + PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), + PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), + PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), + PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), + PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), + PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), + PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), /* IIC3 */ - GPIO_FN(SCL0), - GPIO_FN(SCL1), - GPIO_FN(SCL2), - GPIO_FN(SDA0), - GPIO_FN(SDA1), - GPIO_FN(SDA2), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), /* SSI */ - GPIO_FN(SSISCK0), - GPIO_FN(SSIWS0), - GPIO_FN(SSITXD0), - GPIO_FN(SSIRXD0), - GPIO_FN(SSIWS1), - GPIO_FN(SSIWS2), - GPIO_FN(SSIWS3), - GPIO_FN(SSISCK1), - GPIO_FN(SSISCK2), - GPIO_FN(SSISCK3), - GPIO_FN(SSIDATA1), - GPIO_FN(SSIDATA2), - GPIO_FN(SSIDATA3), - GPIO_FN(AUDIO_CLK), - GPIO_FN(AUDIO_XOUT), + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ - GPIO_FN(SIOFTXD), - GPIO_FN(SIOFRXD), - GPIO_FN(SIOFSYNC), - GPIO_FN(SIOFSCK), + PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ - GPIO_FN(SPDIF_IN), - GPIO_FN(SPDIF_OUT), + PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), + PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ - GPIO_FN(FCE), - GPIO_FN(FRB), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), /* VDC3 */ - GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), - GPIO_FN(DV_HSYNC), - - GPIO_FN(DV_DATA23), - GPIO_FN(DV_DATA22), - GPIO_FN(DV_DATA21), - GPIO_FN(DV_DATA20), - GPIO_FN(DV_DATA19), - GPIO_FN(DV_DATA18), - GPIO_FN(DV_DATA17), - GPIO_FN(DV_DATA16), - GPIO_FN(DV_DATA15), - GPIO_FN(DV_DATA14), - GPIO_FN(DV_DATA13), - GPIO_FN(DV_DATA12), - GPIO_FN(DV_DATA11), - GPIO_FN(DV_DATA10), - GPIO_FN(DV_DATA9), - GPIO_FN(DV_DATA8), - GPIO_FN(DV_DATA7), - GPIO_FN(DV_DATA6), - GPIO_FN(DV_DATA5), - GPIO_FN(DV_DATA4), - GPIO_FN(DV_DATA3), - GPIO_FN(DV_DATA2), - GPIO_FN(DV_DATA1), - GPIO_FN(DV_DATA0), - - GPIO_FN(LCD_CLK), - GPIO_FN(LCD_EXTCLK), - GPIO_FN(LCD_VSYNC), - GPIO_FN(LCD_HSYNC), - GPIO_FN(LCD_DE), - - GPIO_FN(LCD_DATA23_PG23), - GPIO_FN(LCD_DATA22_PG22), - GPIO_FN(LCD_DATA21_PG21), - GPIO_FN(LCD_DATA20_PG20), - GPIO_FN(LCD_DATA19_PG19), - GPIO_FN(LCD_DATA18_PG18), - GPIO_FN(LCD_DATA17_PG17), - GPIO_FN(LCD_DATA16_PG16), - GPIO_FN(LCD_DATA15_PG15), - GPIO_FN(LCD_DATA14_PG14), - GPIO_FN(LCD_DATA13_PG13), - GPIO_FN(LCD_DATA12_PG12), - GPIO_FN(LCD_DATA11_PG11), - GPIO_FN(LCD_DATA10_PG10), - GPIO_FN(LCD_DATA9_PG9), - GPIO_FN(LCD_DATA8_PG8), - GPIO_FN(LCD_DATA7_PG7), - GPIO_FN(LCD_DATA6_PG6), - GPIO_FN(LCD_DATA5_PG5), - GPIO_FN(LCD_DATA4_PG4), - GPIO_FN(LCD_DATA3_PG3), - GPIO_FN(LCD_DATA2_PG2), - GPIO_FN(LCD_DATA1_PG1), - GPIO_FN(LCD_DATA0_PG0), - - GPIO_FN(LCD_DATA23_PJ23), - GPIO_FN(LCD_DATA22_PJ22), - GPIO_FN(LCD_DATA21_PJ21), - GPIO_FN(LCD_DATA20_PJ20), - GPIO_FN(LCD_DATA19_PJ19), - GPIO_FN(LCD_DATA18_PJ18), - GPIO_FN(LCD_DATA17_PJ17), - GPIO_FN(LCD_DATA16_PJ16), - GPIO_FN(LCD_DATA15_PJ15), - GPIO_FN(LCD_DATA14_PJ14), - GPIO_FN(LCD_DATA13_PJ13), - GPIO_FN(LCD_DATA12_PJ12), - GPIO_FN(LCD_DATA11_PJ11), - GPIO_FN(LCD_DATA10_PJ10), - GPIO_FN(LCD_DATA9_PJ9), - GPIO_FN(LCD_DATA8_PJ8), - GPIO_FN(LCD_DATA7_PJ7), - GPIO_FN(LCD_DATA6_PJ6), - GPIO_FN(LCD_DATA5_PJ5), - GPIO_FN(LCD_DATA4_PJ4), - GPIO_FN(LCD_DATA3_PJ3), - GPIO_FN(LCD_DATA2_PJ2), - GPIO_FN(LCD_DATA1_PJ1), - GPIO_FN(LCD_DATA0_PJ0), - - GPIO_FN(LCD_M_DISP), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + + PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK), + + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ /* where Field_Width is 1 for single mode registers or 4 for upto 16 @@ -2738,7 +2734,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 0, 0, 0, 0, 0, 0, 0, PA0_DATA } @@ -2817,17 +2813,19 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { } }; -const struct sh_pfc_soc_info sh7269_pinmux_info = { +struct sh_pfc_soc_info sh7269_pinmux_info = { .name = "sh7269_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PA1, + .last_gpio = GPIO_FN_LCD_M_DISP, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7372.c index df0ae21a5ac8..d44e7f02069b 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7372.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7372.c @@ -368,7 +368,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), @@ -929,214 +929,11 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), }; -static struct sh_pfc_pin pinmux_pins[] = { - GPIO_PORT_ALL(), -}; +static struct pinmux_gpio pinmux_gpios[] = { -/* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 84, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 84, 85, 86, 87, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { - /* D[0:7] */ - 84, 85, 86, 87, 88, 89, 90, 91, -}; -static const unsigned int mmc0_data8_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, - MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, -}; -static const unsigned int mmc0_ctrl_0_pins[] = { - /* CMD, CLK */ - 92, 99, -}; -static const unsigned int mmc0_ctrl_0_mux[] = { - MMCCMD0_MARK, MMCCLK0_MARK, -}; - -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 54, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 54, 55, 56, 57, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { - /* D[0:7] */ - 54, 55, 56, 57, 58, 59, 60, 61, -}; -static const unsigned int mmc0_data8_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, - MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, -}; -static const unsigned int mmc0_ctrl_1_pins[] = { - /* CMD, CLK */ - 67, 66, -}; -static const unsigned int mmc0_ctrl_1_mux[] = { - MMCCMD1_MARK, MMCCLK1_MARK, -}; -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 173, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { - /* D[0:3] */ - 173, 174, 175, 176, -}; -static const unsigned int sdhi0_data4_mux[] = { - SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CMD, CLK */ - 177, 171, -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SDHICMD0_MARK, SDHICLK0_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - 172, -}; -static const unsigned int sdhi0_cd_mux[] = { - SDHICD0_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - 178, -}; -static const unsigned int sdhi0_wp_mux[] = { - SDHIWP0_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 180, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - 180, 181, 182, 183, -}; -static const unsigned int sdhi1_data4_mux[] = { - SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CMD, CLK */ - 184, 179, -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SDHICMD1_MARK, SDHICLK1_MARK, -}; - -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 186, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - 186, 187, 188, 189, -}; -static const unsigned int sdhi2_data4_mux[] = { - SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CMD, CLK */ - 190, 185, -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SDHICMD2_MARK, SDHICLK2_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), - SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), - SH_PFC_PIN_GROUP(mmc0_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), -}; - -static const char * const mmc0_groups[] = { - "mmc0_data1_0", - "mmc0_data4_0", - "mmc0_data8_0", - "mmc0_ctrl_0", - "mmc0_data1_1", - "mmc0_data4_1", - "mmc0_data8_1", - "mmc0_ctrl_1", -}; - -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; - -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", -}; - -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_ctrl", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) + /* PORT */ + GPIO_PORT_ALL(), -static const struct pinmux_func pinmux_func_gpios[] = { /* IRQ */ GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), @@ -1277,6 +1074,18 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), + /* MMCIF(1) */ + GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5), + GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0), + GPIO_FN(MMCCLK0), + + /* MMCIF(2) */ + GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2), + GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5), + GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1), + GPIO_FN(MMCCMD1), + /* SPU2 */ GPIO_FN(VINT_I), @@ -1373,12 +1182,25 @@ static const struct pinmux_func pinmux_func_gpios[] = { /* HDMI */ GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), + /* SDHI0 */ + GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0), + GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3), + + /* SDHI1 */ + GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0), + GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3), + + /* SDHI2 */ + GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0), + GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3), + /* SDENC */ GPIO_FN(SDENC_CPG), GPIO_FN(SDENC_DV_CLKI), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xE6051000), /* PORT0CR */ PORTCR(1, 0xE6051001), /* PORT1CR */ PORTCR(2, 0xE6051002), /* PORT2CR */ @@ -1650,7 +1472,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, @@ -1775,59 +1597,56 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) -static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162), - PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12), - PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5), - PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16), - PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163), - PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18), - PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164), - PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167), - PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168), - PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169), - PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65), - PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67), - PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137), - PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145), - PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146), - PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147), - PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170), - PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85), - PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86), - PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87), - PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92), - PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93), - PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94), - PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95), - PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112), - PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119), - PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172), - PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180), - PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181), - PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182), - PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183), - PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184), +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), + PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), + PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), + PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), + PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), + PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), + PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), + PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), + PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), + PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), + PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), + PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), + PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), + PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), + PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), + PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), + PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), + PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), + PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), + PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), + PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), + PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), + PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), + PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), + PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), + PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), + PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), + PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), + PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), + PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), + PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), }; -const struct sh_pfc_soc_info sh7372_pinmux_info = { +struct sh_pfc_soc_info sh7372_pinmux_info = { .name = "sh7372_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_SDENC_DV_CLKI, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 587f7772abf2..709008e94124 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -18,18 +18,18 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include #include -#include - #include #include -#include "core.h" #include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \ + PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \ + PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \ + PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \ PORT_10(fn, pfx##10, sfx), \ PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ @@ -66,6 +66,14 @@ enum { PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ PINMUX_INPUT_END, + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + PINMUX_OUTPUT_BEGIN, PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ PINMUX_OUTPUT_END, @@ -460,15 +468,328 @@ enum { EDBGREQ_PD_MARK, EDBGREQ_PU_MARK, + /* Functions with pull-ups */ + KEYIN0_PU_MARK, + KEYIN1_PU_MARK, + KEYIN2_PU_MARK, + KEYIN3_PU_MARK, + KEYIN4_PU_MARK, + KEYIN5_PU_MARK, + KEYIN6_PU_MARK, + KEYIN7_PU_MARK, + SDHICD0_PU_MARK, + SDHID0_0_PU_MARK, + SDHID0_1_PU_MARK, + SDHID0_2_PU_MARK, + SDHID0_3_PU_MARK, + SDHICMD0_PU_MARK, + SDHIWP0_PU_MARK, + SDHID1_0_PU_MARK, + SDHID1_1_PU_MARK, + SDHID1_2_PU_MARK, + SDHID1_3_PU_MARK, + SDHICMD1_PU_MARK, + SDHID2_0_PU_MARK, + SDHID2_1_PU_MARK, + SDHID2_2_PU_MARK, + SDHID2_3_PU_MARK, + SDHICMD2_PU_MARK, + MMCCMD0_PU_MARK, + MMCCMD1_PU_MARK, + MMCD0_0_PU_MARK, + MMCD0_1_PU_MARK, + MMCD0_2_PU_MARK, + MMCD0_3_PU_MARK, + MMCD0_4_PU_MARK, + MMCD0_5_PU_MARK, + MMCD0_6_PU_MARK, + MMCD0_7_PU_MARK, + FSIBISLD_PU_MARK, + FSIACK_PU_MARK, + FSIAILR_PU_MARK, + FSIAIBT_PU_MARK, + FSIAISLD_PU_MARK, + PINMUX_MARK_END, }; -#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) - -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ - PINMUX_DATA_GP_ALL(), + + /* Table 25-1 (I/O and Pull U/D) */ + PORT_DATA_I_PD(0), + PORT_DATA_I_PU(1), + PORT_DATA_I_PU(2), + PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), + PORT_DATA_I_PU(5), + PORT_DATA_I_PU(6), + PORT_DATA_I_PU(7), + PORT_DATA_I_PU(8), + PORT_DATA_I_PD(9), + PORT_DATA_I_PD(10), + PORT_DATA_I_PU_PD(11), + PORT_DATA_IO_PU_PD(12), + PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PU_PD(14), + PORT_DATA_IO_PU_PD(15), + PORT_DATA_IO_PD(16), + PORT_DATA_IO_PD(17), + PORT_DATA_IO_PU(18), + PORT_DATA_IO_PU(19), + PORT_DATA_O(20), + PORT_DATA_O(21), + PORT_DATA_O(22), + PORT_DATA_O(23), + PORT_DATA_O(24), + PORT_DATA_I_PD(25), + PORT_DATA_I_PD(26), + PORT_DATA_IO_PU(27), + PORT_DATA_IO_PU(28), + PORT_DATA_IO_PD(29), + PORT_DATA_IO_PD(30), + PORT_DATA_IO_PU(31), + PORT_DATA_IO_PD(32), + PORT_DATA_I_PU_PD(33), + PORT_DATA_IO_PD(34), + PORT_DATA_I_PU_PD(35), + PORT_DATA_IO_PD(36), + PORT_DATA_IO(37), + PORT_DATA_O(38), + PORT_DATA_I_PU(39), + PORT_DATA_I_PU_PD(40), + PORT_DATA_O(41), + PORT_DATA_IO_PD(42), + PORT_DATA_IO_PU_PD(43), + PORT_DATA_IO_PU_PD(44), + PORT_DATA_IO_PD(45), + PORT_DATA_IO_PD(46), + PORT_DATA_IO_PD(47), + PORT_DATA_I_PD(48), + PORT_DATA_IO_PU_PD(49), + PORT_DATA_IO_PD(50), + + PORT_DATA_IO_PD(51), + PORT_DATA_O(52), + PORT_DATA_IO_PU_PD(53), + PORT_DATA_IO_PU_PD(54), + PORT_DATA_IO_PD(55), + PORT_DATA_I_PU_PD(56), + PORT_DATA_IO(57), + PORT_DATA_IO(58), + PORT_DATA_IO(59), + PORT_DATA_IO(60), + PORT_DATA_IO(61), + PORT_DATA_IO_PD(62), + PORT_DATA_IO_PD(63), + PORT_DATA_IO_PU_PD(64), + PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), + PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), + PORT_DATA_IO_PU_PD(69), + PORT_DATA_IO_PU_PD(70), + PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), + PORT_DATA_I_PU_PD(73), + PORT_DATA_IO_PU(74), + PORT_DATA_IO_PU(75), + PORT_DATA_IO_PU(76), + PORT_DATA_IO_PU(77), + PORT_DATA_IO_PU(78), + PORT_DATA_IO_PU(79), + PORT_DATA_IO_PU(80), + PORT_DATA_IO_PU(81), + PORT_DATA_IO_PU(82), + PORT_DATA_IO_PU(83), + PORT_DATA_IO_PU(84), + PORT_DATA_IO_PU(85), + PORT_DATA_IO_PU(86), + PORT_DATA_IO_PU(87), + PORT_DATA_IO_PU(88), + PORT_DATA_IO_PU(89), + PORT_DATA_O(90), + PORT_DATA_IO_PU(91), + PORT_DATA_O(92), + PORT_DATA_IO_PU(93), + PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO(96), + PORT_DATA_IO(97), + PORT_DATA_IO(98), + PORT_DATA_I_PU(99), + PORT_DATA_O(100), + PORT_DATA_O(101), + PORT_DATA_I_PU(102), + PORT_DATA_IO_PD(103), + PORT_DATA_I_PU_PD(104), + PORT_DATA_I_PD(105), + PORT_DATA_I_PD(106), + PORT_DATA_I_PU_PD(107), + PORT_DATA_I_PU_PD(108), + PORT_DATA_IO_PD(109), + PORT_DATA_IO_PD(110), + PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), + PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PD(114), + PORT_DATA_IO_PU(115), + PORT_DATA_IO_PU(116), + PORT_DATA_IO_PU_PD(117), + PORT_DATA_IO_PU_PD(118), + PORT_DATA_IO_PD(128), + + PORT_DATA_IO_PD(129), + PORT_DATA_IO_PU_PD(130), + PORT_DATA_IO_PD(131), + PORT_DATA_IO_PD(132), + PORT_DATA_IO_PD(133), + PORT_DATA_IO_PU_PD(134), + PORT_DATA_IO_PU_PD(135), + PORT_DATA_IO_PU_PD(136), + PORT_DATA_IO_PU_PD(137), + PORT_DATA_IO_PD(138), + PORT_DATA_IO_PD(139), + PORT_DATA_IO_PD(140), + PORT_DATA_IO_PD(141), + PORT_DATA_IO_PD(142), + PORT_DATA_IO_PD(143), + PORT_DATA_IO_PU_PD(144), + PORT_DATA_IO_PD(145), + PORT_DATA_IO_PU_PD(146), + PORT_DATA_IO_PU_PD(147), + PORT_DATA_IO_PU_PD(148), + PORT_DATA_IO_PU_PD(149), + PORT_DATA_I_PU_PD(150), + PORT_DATA_IO_PU_PD(151), + PORT_DATA_IO_PU_PD(152), + PORT_DATA_IO_PD(153), + PORT_DATA_IO_PD(154), + PORT_DATA_I_PU_PD(155), + PORT_DATA_IO_PU_PD(156), + PORT_DATA_I_PD(157), + PORT_DATA_IO_PD(158), + PORT_DATA_IO_PU_PD(159), + PORT_DATA_IO_PU_PD(160), + PORT_DATA_I_PU_PD(161), + PORT_DATA_I_PU_PD(162), + PORT_DATA_IO_PU_PD(163), + PORT_DATA_I_PU_PD(164), + PORT_DATA_IO_PD(192), + PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PD(194), + PORT_DATA_IO_PU_PD(195), + PORT_DATA_IO_PD(196), + PORT_DATA_IO_PD(197), + PORT_DATA_IO_PD(198), + PORT_DATA_IO_PD(199), + PORT_DATA_IO_PU_PD(200), + PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), + PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), + PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), + PORT_DATA_IO_PD(207), + PORT_DATA_IO_PD(208), + PORT_DATA_IO_PD(209), + PORT_DATA_IO_PD(210), + PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), + PORT_DATA_IO_PD(213), + PORT_DATA_IO_PU_PD(214), + PORT_DATA_IO_PU_PD(215), + PORT_DATA_IO_PD(216), + PORT_DATA_IO_PD(217), + PORT_DATA_O(218), + PORT_DATA_IO_PD(219), + PORT_DATA_IO_PD(220), + PORT_DATA_IO_PU_PD(221), + PORT_DATA_IO_PU_PD(222), + PORT_DATA_I_PU_PD(223), + PORT_DATA_I_PU_PD(224), + + PORT_DATA_IO_PU_PD(225), + PORT_DATA_O(226), + PORT_DATA_IO_PU_PD(227), + PORT_DATA_I_PU_PD(228), + PORT_DATA_I_PD(229), + PORT_DATA_IO(230), + PORT_DATA_IO_PU_PD(231), + PORT_DATA_IO_PU_PD(232), + PORT_DATA_I_PU_PD(233), + PORT_DATA_IO_PU_PD(234), + PORT_DATA_IO_PU_PD(235), + PORT_DATA_IO_PU_PD(236), + PORT_DATA_IO_PD(237), + PORT_DATA_IO_PU_PD(238), + PORT_DATA_IO_PU_PD(239), + PORT_DATA_IO_PU_PD(240), + PORT_DATA_O(241), + PORT_DATA_I_PD(242), + PORT_DATA_IO_PU_PD(243), + PORT_DATA_IO_PU_PD(244), + PORT_DATA_IO_PU_PD(245), + PORT_DATA_IO_PU_PD(246), + PORT_DATA_IO_PU_PD(247), + PORT_DATA_IO_PU_PD(248), + PORT_DATA_IO_PU_PD(249), + PORT_DATA_IO_PU_PD(250), + PORT_DATA_IO_PU_PD(251), + PORT_DATA_IO_PU_PD(252), + PORT_DATA_IO_PU_PD(253), + PORT_DATA_IO_PU_PD(254), + PORT_DATA_IO_PU_PD(255), + PORT_DATA_IO_PU_PD(256), + PORT_DATA_IO_PU_PD(257), + PORT_DATA_IO_PU_PD(258), + PORT_DATA_IO_PU_PD(259), + PORT_DATA_IO_PU_PD(260), + PORT_DATA_IO_PU_PD(261), + PORT_DATA_IO_PU_PD(262), + PORT_DATA_IO_PU_PD(263), + PORT_DATA_IO_PU_PD(264), + PORT_DATA_IO_PU_PD(265), + PORT_DATA_IO_PU_PD(266), + PORT_DATA_IO_PU_PD(267), + PORT_DATA_IO_PU_PD(268), + PORT_DATA_IO_PU_PD(269), + PORT_DATA_IO_PU_PD(270), + PORT_DATA_IO_PU_PD(271), + PORT_DATA_IO_PU_PD(272), + PORT_DATA_IO_PU_PD(273), + PORT_DATA_IO_PU_PD(274), + PORT_DATA_IO_PU_PD(275), + PORT_DATA_IO_PU_PD(276), + PORT_DATA_IO_PU_PD(277), + PORT_DATA_IO_PU_PD(278), + PORT_DATA_IO_PU_PD(279), + PORT_DATA_IO_PU_PD(280), + PORT_DATA_O(281), + PORT_DATA_O(282), + PORT_DATA_I_PU(288), + PORT_DATA_IO_PU_PD(289), + PORT_DATA_IO_PU_PD(290), + PORT_DATA_IO_PU_PD(291), + PORT_DATA_IO_PU_PD(292), + PORT_DATA_IO_PU_PD(293), + PORT_DATA_IO_PU_PD(294), + PORT_DATA_IO_PU_PD(295), + PORT_DATA_IO_PU_PD(296), + PORT_DATA_IO_PU_PD(297), + PORT_DATA_IO_PU_PD(298), + + PORT_DATA_IO_PU_PD(299), + PORT_DATA_IO_PU_PD(300), + PORT_DATA_IO_PU_PD(301), + PORT_DATA_IO_PU_PD(302), + PORT_DATA_IO_PU_PD(303), + PORT_DATA_IO_PU_PD(304), + PORT_DATA_IO_PU_PD(305), + PORT_DATA_O(306), + PORT_DATA_O(307), + PORT_DATA_I_PU(308), + PORT_DATA_O(309), /* Table 25-1 (Function 0-7) */ PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), @@ -1037,19 +1358,28 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, + MSEL4CR_MSEL15_0), \ PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), @@ -1155,1791 +1485,69 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), -}; - -#define SH73A0_PIN(pin, cfgs) \ - { \ - .name = __stringify(PORT##pin), \ - .enum_id = PORT##pin##_DATA, \ - .configs = cfgs, \ - } - -#define __I (SH_PFC_PIN_CFG_INPUT) -#define __O (SH_PFC_PIN_CFG_OUTPUT) -#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) -#define __PD (SH_PFC_PIN_CFG_PULL_DOWN) -#define __PU (SH_PFC_PIN_CFG_PULL_UP) -#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) - -#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD) -#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU) -#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD) -#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO) -#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD) -#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU) -#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD) -#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O) - -static struct sh_pfc_pin pinmux_pins[] = { - /* Table 25-1 (I/O and Pull U/D) */ - SH73A0_PIN_I_PD(0), - SH73A0_PIN_I_PU(1), - SH73A0_PIN_I_PU(2), - SH73A0_PIN_I_PU(3), - SH73A0_PIN_I_PU(4), - SH73A0_PIN_I_PU(5), - SH73A0_PIN_I_PU(6), - SH73A0_PIN_I_PU(7), - SH73A0_PIN_I_PU(8), - SH73A0_PIN_I_PD(9), - SH73A0_PIN_I_PD(10), - SH73A0_PIN_I_PU_PD(11), - SH73A0_PIN_IO_PU_PD(12), - SH73A0_PIN_IO_PU_PD(13), - SH73A0_PIN_IO_PU_PD(14), - SH73A0_PIN_IO_PU_PD(15), - SH73A0_PIN_IO_PD(16), - SH73A0_PIN_IO_PD(17), - SH73A0_PIN_IO_PU(18), - SH73A0_PIN_IO_PU(19), - SH73A0_PIN_O(20), - SH73A0_PIN_O(21), - SH73A0_PIN_O(22), - SH73A0_PIN_O(23), - SH73A0_PIN_O(24), - SH73A0_PIN_I_PD(25), - SH73A0_PIN_I_PD(26), - SH73A0_PIN_IO_PU(27), - SH73A0_PIN_IO_PU(28), - SH73A0_PIN_IO_PD(29), - SH73A0_PIN_IO_PD(30), - SH73A0_PIN_IO_PU(31), - SH73A0_PIN_IO_PD(32), - SH73A0_PIN_I_PU_PD(33), - SH73A0_PIN_IO_PD(34), - SH73A0_PIN_I_PU_PD(35), - SH73A0_PIN_IO_PD(36), - SH73A0_PIN_IO(37), - SH73A0_PIN_O(38), - SH73A0_PIN_I_PU(39), - SH73A0_PIN_I_PU_PD(40), - SH73A0_PIN_O(41), - SH73A0_PIN_IO_PD(42), - SH73A0_PIN_IO_PU_PD(43), - SH73A0_PIN_IO_PU_PD(44), - SH73A0_PIN_IO_PD(45), - SH73A0_PIN_IO_PD(46), - SH73A0_PIN_IO_PD(47), - SH73A0_PIN_I_PD(48), - SH73A0_PIN_IO_PU_PD(49), - SH73A0_PIN_IO_PD(50), - SH73A0_PIN_IO_PD(51), - SH73A0_PIN_O(52), - SH73A0_PIN_IO_PU_PD(53), - SH73A0_PIN_IO_PU_PD(54), - SH73A0_PIN_IO_PD(55), - SH73A0_PIN_I_PU_PD(56), - SH73A0_PIN_IO(57), - SH73A0_PIN_IO(58), - SH73A0_PIN_IO(59), - SH73A0_PIN_IO(60), - SH73A0_PIN_IO(61), - SH73A0_PIN_IO_PD(62), - SH73A0_PIN_IO_PD(63), - SH73A0_PIN_IO_PU_PD(64), - SH73A0_PIN_IO_PD(65), - SH73A0_PIN_IO_PU_PD(66), - SH73A0_PIN_IO_PU_PD(67), - SH73A0_PIN_IO_PU_PD(68), - SH73A0_PIN_IO_PU_PD(69), - SH73A0_PIN_IO_PU_PD(70), - SH73A0_PIN_IO_PU_PD(71), - SH73A0_PIN_IO_PU_PD(72), - SH73A0_PIN_I_PU_PD(73), - SH73A0_PIN_IO_PU(74), - SH73A0_PIN_IO_PU(75), - SH73A0_PIN_IO_PU(76), - SH73A0_PIN_IO_PU(77), - SH73A0_PIN_IO_PU(78), - SH73A0_PIN_IO_PU(79), - SH73A0_PIN_IO_PU(80), - SH73A0_PIN_IO_PU(81), - SH73A0_PIN_IO_PU(82), - SH73A0_PIN_IO_PU(83), - SH73A0_PIN_IO_PU(84), - SH73A0_PIN_IO_PU(85), - SH73A0_PIN_IO_PU(86), - SH73A0_PIN_IO_PU(87), - SH73A0_PIN_IO_PU(88), - SH73A0_PIN_IO_PU(89), - SH73A0_PIN_O(90), - SH73A0_PIN_IO_PU(91), - SH73A0_PIN_O(92), - SH73A0_PIN_IO_PU(93), - SH73A0_PIN_O(94), - SH73A0_PIN_I_PU_PD(95), - SH73A0_PIN_IO(96), - SH73A0_PIN_IO(97), - SH73A0_PIN_IO(98), - SH73A0_PIN_I_PU(99), - SH73A0_PIN_O(100), - SH73A0_PIN_O(101), - SH73A0_PIN_I_PU(102), - SH73A0_PIN_IO_PD(103), - SH73A0_PIN_I_PU_PD(104), - SH73A0_PIN_I_PD(105), - SH73A0_PIN_I_PD(106), - SH73A0_PIN_I_PU_PD(107), - SH73A0_PIN_I_PU_PD(108), - SH73A0_PIN_IO_PD(109), - SH73A0_PIN_IO_PD(110), - SH73A0_PIN_IO_PU_PD(111), - SH73A0_PIN_IO_PU_PD(112), - SH73A0_PIN_IO_PU_PD(113), - SH73A0_PIN_IO_PD(114), - SH73A0_PIN_IO_PU(115), - SH73A0_PIN_IO_PU(116), - SH73A0_PIN_IO_PU_PD(117), - SH73A0_PIN_IO_PU_PD(118), - SH73A0_PIN_IO_PD(128), - SH73A0_PIN_IO_PD(129), - SH73A0_PIN_IO_PU_PD(130), - SH73A0_PIN_IO_PD(131), - SH73A0_PIN_IO_PD(132), - SH73A0_PIN_IO_PD(133), - SH73A0_PIN_IO_PU_PD(134), - SH73A0_PIN_IO_PU_PD(135), - SH73A0_PIN_IO_PU_PD(136), - SH73A0_PIN_IO_PU_PD(137), - SH73A0_PIN_IO_PD(138), - SH73A0_PIN_IO_PD(139), - SH73A0_PIN_IO_PD(140), - SH73A0_PIN_IO_PD(141), - SH73A0_PIN_IO_PD(142), - SH73A0_PIN_IO_PD(143), - SH73A0_PIN_IO_PU_PD(144), - SH73A0_PIN_IO_PD(145), - SH73A0_PIN_IO_PU_PD(146), - SH73A0_PIN_IO_PU_PD(147), - SH73A0_PIN_IO_PU_PD(148), - SH73A0_PIN_IO_PU_PD(149), - SH73A0_PIN_I_PU_PD(150), - SH73A0_PIN_IO_PU_PD(151), - SH73A0_PIN_IO_PU_PD(152), - SH73A0_PIN_IO_PD(153), - SH73A0_PIN_IO_PD(154), - SH73A0_PIN_I_PU_PD(155), - SH73A0_PIN_IO_PU_PD(156), - SH73A0_PIN_I_PD(157), - SH73A0_PIN_IO_PD(158), - SH73A0_PIN_IO_PU_PD(159), - SH73A0_PIN_IO_PU_PD(160), - SH73A0_PIN_I_PU_PD(161), - SH73A0_PIN_I_PU_PD(162), - SH73A0_PIN_IO_PU_PD(163), - SH73A0_PIN_I_PU_PD(164), - SH73A0_PIN_IO_PD(192), - SH73A0_PIN_IO_PU_PD(193), - SH73A0_PIN_IO_PD(194), - SH73A0_PIN_IO_PU_PD(195), - SH73A0_PIN_IO_PD(196), - SH73A0_PIN_IO_PD(197), - SH73A0_PIN_IO_PD(198), - SH73A0_PIN_IO_PD(199), - SH73A0_PIN_IO_PU_PD(200), - SH73A0_PIN_IO_PU_PD(201), - SH73A0_PIN_IO_PU_PD(202), - SH73A0_PIN_IO_PU_PD(203), - SH73A0_PIN_IO_PU_PD(204), - SH73A0_PIN_IO_PU_PD(205), - SH73A0_PIN_IO_PU_PD(206), - SH73A0_PIN_IO_PD(207), - SH73A0_PIN_IO_PD(208), - SH73A0_PIN_IO_PD(209), - SH73A0_PIN_IO_PD(210), - SH73A0_PIN_IO_PD(211), - SH73A0_PIN_IO_PD(212), - SH73A0_PIN_IO_PD(213), - SH73A0_PIN_IO_PU_PD(214), - SH73A0_PIN_IO_PU_PD(215), - SH73A0_PIN_IO_PD(216), - SH73A0_PIN_IO_PD(217), - SH73A0_PIN_O(218), - SH73A0_PIN_IO_PD(219), - SH73A0_PIN_IO_PD(220), - SH73A0_PIN_IO_PU_PD(221), - SH73A0_PIN_IO_PU_PD(222), - SH73A0_PIN_I_PU_PD(223), - SH73A0_PIN_I_PU_PD(224), - SH73A0_PIN_IO_PU_PD(225), - SH73A0_PIN_O(226), - SH73A0_PIN_IO_PU_PD(227), - SH73A0_PIN_I_PU_PD(228), - SH73A0_PIN_I_PD(229), - SH73A0_PIN_IO(230), - SH73A0_PIN_IO_PU_PD(231), - SH73A0_PIN_IO_PU_PD(232), - SH73A0_PIN_I_PU_PD(233), - SH73A0_PIN_IO_PU_PD(234), - SH73A0_PIN_IO_PU_PD(235), - SH73A0_PIN_IO_PU_PD(236), - SH73A0_PIN_IO_PD(237), - SH73A0_PIN_IO_PU_PD(238), - SH73A0_PIN_IO_PU_PD(239), - SH73A0_PIN_IO_PU_PD(240), - SH73A0_PIN_O(241), - SH73A0_PIN_I_PD(242), - SH73A0_PIN_IO_PU_PD(243), - SH73A0_PIN_IO_PU_PD(244), - SH73A0_PIN_IO_PU_PD(245), - SH73A0_PIN_IO_PU_PD(246), - SH73A0_PIN_IO_PU_PD(247), - SH73A0_PIN_IO_PU_PD(248), - SH73A0_PIN_IO_PU_PD(249), - SH73A0_PIN_IO_PU_PD(250), - SH73A0_PIN_IO_PU_PD(251), - SH73A0_PIN_IO_PU_PD(252), - SH73A0_PIN_IO_PU_PD(253), - SH73A0_PIN_IO_PU_PD(254), - SH73A0_PIN_IO_PU_PD(255), - SH73A0_PIN_IO_PU_PD(256), - SH73A0_PIN_IO_PU_PD(257), - SH73A0_PIN_IO_PU_PD(258), - SH73A0_PIN_IO_PU_PD(259), - SH73A0_PIN_IO_PU_PD(260), - SH73A0_PIN_IO_PU_PD(261), - SH73A0_PIN_IO_PU_PD(262), - SH73A0_PIN_IO_PU_PD(263), - SH73A0_PIN_IO_PU_PD(264), - SH73A0_PIN_IO_PU_PD(265), - SH73A0_PIN_IO_PU_PD(266), - SH73A0_PIN_IO_PU_PD(267), - SH73A0_PIN_IO_PU_PD(268), - SH73A0_PIN_IO_PU_PD(269), - SH73A0_PIN_IO_PU_PD(270), - SH73A0_PIN_IO_PU_PD(271), - SH73A0_PIN_IO_PU_PD(272), - SH73A0_PIN_IO_PU_PD(273), - SH73A0_PIN_IO_PU_PD(274), - SH73A0_PIN_IO_PU_PD(275), - SH73A0_PIN_IO_PU_PD(276), - SH73A0_PIN_IO_PU_PD(277), - SH73A0_PIN_IO_PU_PD(278), - SH73A0_PIN_IO_PU_PD(279), - SH73A0_PIN_IO_PU_PD(280), - SH73A0_PIN_O(281), - SH73A0_PIN_O(282), - SH73A0_PIN_I_PU(288), - SH73A0_PIN_IO_PU_PD(289), - SH73A0_PIN_IO_PU_PD(290), - SH73A0_PIN_IO_PU_PD(291), - SH73A0_PIN_IO_PU_PD(292), - SH73A0_PIN_IO_PU_PD(293), - SH73A0_PIN_IO_PU_PD(294), - SH73A0_PIN_IO_PU_PD(295), - SH73A0_PIN_IO_PU_PD(296), - SH73A0_PIN_IO_PU_PD(297), - SH73A0_PIN_IO_PU_PD(298), - SH73A0_PIN_IO_PU_PD(299), - SH73A0_PIN_IO_PU_PD(300), - SH73A0_PIN_IO_PU_PD(301), - SH73A0_PIN_IO_PU_PD(302), - SH73A0_PIN_IO_PU_PD(303), - SH73A0_PIN_IO_PU_PD(304), - SH73A0_PIN_IO_PU_PD(305), - SH73A0_PIN_O(306), - SH73A0_PIN_O(307), - SH73A0_PIN_I_PU(308), - SH73A0_PIN_O(309), -}; - -static const struct pinmux_range pinmux_ranges[] = { - {.begin = 0, .end = 118,}, - {.begin = 128, .end = 164,}, - {.begin = 192, .end = 282,}, - {.begin = 288, .end = 309,}, -}; - -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. - */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) - -/* - BSC -------------------------------------------------------------------- */ -static const unsigned int bsc_data_0_7_pins[] = { - /* D[0:7] */ - 74, 75, 76, 77, 78, 79, 80, 81, -}; -static const unsigned int bsc_data_0_7_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, -}; -static const unsigned int bsc_data_8_15_pins[] = { - /* D[8:15] */ - 82, 83, 84, 85, 86, 87, 88, 89, -}; -static const unsigned int bsc_data_8_15_mux[] = { - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, -}; -static const unsigned int bsc_cs4_pins[] = { - /* CS */ - 90, -}; -static const unsigned int bsc_cs4_mux[] = { - CS4__MARK, -}; -static const unsigned int bsc_cs5_a_pins[] = { - /* CS */ - 91, -}; -static const unsigned int bsc_cs5_a_mux[] = { - CS5A__MARK, -}; -static const unsigned int bsc_cs5_b_pins[] = { - /* CS */ - 92, -}; -static const unsigned int bsc_cs5_b_mux[] = { - CS5B__MARK, -}; -static const unsigned int bsc_cs6_a_pins[] = { - /* CS */ - 94, -}; -static const unsigned int bsc_cs6_a_mux[] = { - CS6A__MARK, -}; -static const unsigned int bsc_cs6_b_pins[] = { - /* CS */ - 93, -}; -static const unsigned int bsc_cs6_b_mux[] = { - CS6B__MARK, -}; -static const unsigned int bsc_rd_pins[] = { - /* RD */ - 96, -}; -static const unsigned int bsc_rd_mux[] = { - RD__FSC_MARK, -}; -static const unsigned int bsc_rdwr_0_pins[] = { - /* RDWR */ - 91, -}; -static const unsigned int bsc_rdwr_0_mux[] = { - PORT91_RDWR_MARK, -}; -static const unsigned int bsc_rdwr_1_pins[] = { - /* RDWR */ - 97, -}; -static const unsigned int bsc_rdwr_1_mux[] = { - RDWR_FWE_MARK, -}; -static const unsigned int bsc_rdwr_2_pins[] = { - /* RDWR */ - 149, -}; -static const unsigned int bsc_rdwr_2_mux[] = { - PORT149_RDWR_MARK, -}; -static const unsigned int bsc_we0_pins[] = { - /* WE0 */ - 97, -}; -static const unsigned int bsc_we0_mux[] = { - WE0__FWE_MARK, -}; -static const unsigned int bsc_we1_pins[] = { - /* WE1 */ - 98, -}; -static const unsigned int bsc_we1_mux[] = { - WE1__MARK, -}; -/* - FSIA ------------------------------------------------------------------- */ -static const unsigned int fsia_mclk_in_pins[] = { - /* CK */ - 49, -}; -static const unsigned int fsia_mclk_in_mux[] = { - FSIACK_MARK, -}; -static const unsigned int fsia_mclk_out_pins[] = { - /* OMC */ - 49, -}; -static const unsigned int fsia_mclk_out_mux[] = { - FSIAOMC_MARK, -}; -static const unsigned int fsia_sclk_in_pins[] = { - /* ILR, IBT */ - 50, 51, -}; -static const unsigned int fsia_sclk_in_mux[] = { - FSIAILR_MARK, FSIAIBT_MARK, -}; -static const unsigned int fsia_sclk_out_pins[] = { - /* OLR, OBT */ - 50, 51, -}; -static const unsigned int fsia_sclk_out_mux[] = { - FSIAOLR_MARK, FSIAOBT_MARK, -}; -static const unsigned int fsia_data_in_pins[] = { - /* ISLD */ - 55, -}; -static const unsigned int fsia_data_in_mux[] = { - FSIAISLD_MARK, -}; -static const unsigned int fsia_data_out_pins[] = { - /* OSLD */ - 52, -}; -static const unsigned int fsia_data_out_mux[] = { - FSIAOSLD_MARK, -}; -static const unsigned int fsia_spdif_pins[] = { - /* SPDIF */ - 53, -}; -static const unsigned int fsia_spdif_mux[] = { - FSIASPDIF_MARK, -}; -/* - FSIB ------------------------------------------------------------------- */ -static const unsigned int fsib_mclk_in_pins[] = { - /* CK */ - 54, -}; -static const unsigned int fsib_mclk_in_mux[] = { - FSIBCK_MARK, -}; -static const unsigned int fsib_mclk_out_pins[] = { - /* OMC */ - 54, -}; -static const unsigned int fsib_mclk_out_mux[] = { - FSIBOMC_MARK, -}; -static const unsigned int fsib_sclk_in_pins[] = { - /* ILR, IBT */ - 37, 36, -}; -static const unsigned int fsib_sclk_in_mux[] = { - FSIBILR_MARK, FSIBIBT_MARK, -}; -static const unsigned int fsib_sclk_out_pins[] = { - /* OLR, OBT */ - 37, 36, -}; -static const unsigned int fsib_sclk_out_mux[] = { - FSIBOLR_MARK, FSIBOBT_MARK, -}; -static const unsigned int fsib_data_in_pins[] = { - /* ISLD */ - 39, -}; -static const unsigned int fsib_data_in_mux[] = { - FSIBISLD_MARK, -}; -static const unsigned int fsib_data_out_pins[] = { - /* OSLD */ - 38, -}; -static const unsigned int fsib_data_out_mux[] = { - FSIBOSLD_MARK, -}; -static const unsigned int fsib_spdif_pins[] = { - /* SPDIF */ - 53, -}; -static const unsigned int fsib_spdif_mux[] = { - FSIBSPDIF_MARK, -}; -/* - FSIC ------------------------------------------------------------------- */ -static const unsigned int fsic_mclk_in_pins[] = { - /* CK */ - 54, -}; -static const unsigned int fsic_mclk_in_mux[] = { - FSICCK_MARK, -}; -static const unsigned int fsic_mclk_out_pins[] = { - /* OMC */ - 54, -}; -static const unsigned int fsic_mclk_out_mux[] = { - FSICOMC_MARK, -}; -static const unsigned int fsic_sclk_in_pins[] = { - /* ILR, IBT */ - 46, 45, -}; -static const unsigned int fsic_sclk_in_mux[] = { - FSICILR_MARK, FSICIBT_MARK, -}; -static const unsigned int fsic_sclk_out_pins[] = { - /* OLR, OBT */ - 46, 45, -}; -static const unsigned int fsic_sclk_out_mux[] = { - FSICOLR_MARK, FSICOBT_MARK, -}; -static const unsigned int fsic_data_in_pins[] = { - /* ISLD */ - 48, -}; -static const unsigned int fsic_data_in_mux[] = { - FSICISLD_MARK, -}; -static const unsigned int fsic_data_out_pins[] = { - /* OSLD, OSLDT1, OSLDT2, OSLDT3 */ - 47, 44, 42, 16, -}; -static const unsigned int fsic_data_out_mux[] = { - FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK, -}; -static const unsigned int fsic_spdif_0_pins[] = { - /* SPDIF */ - 53, -}; -static const unsigned int fsic_spdif_0_mux[] = { - PORT53_FSICSPDIF_MARK, -}; -static const unsigned int fsic_spdif_1_pins[] = { - /* SPDIF */ - 47, -}; -static const unsigned int fsic_spdif_1_mux[] = { - PORT47_FSICSPDIF_MARK, -}; -/* - FSID ------------------------------------------------------------------- */ -static const unsigned int fsid_sclk_in_pins[] = { - /* ILR, IBT */ - 46, 45, -}; -static const unsigned int fsid_sclk_in_mux[] = { - FSIDILR_MARK, FSIDIBT_MARK, -}; -static const unsigned int fsid_sclk_out_pins[] = { - /* OLR, OBT */ - 46, 45, -}; -static const unsigned int fsid_sclk_out_mux[] = { - FSIDOLR_MARK, FSIDOBT_MARK, -}; -static const unsigned int fsid_data_in_pins[] = { - /* ISLD */ - 48, -}; -static const unsigned int fsid_data_in_mux[] = { - FSIDISLD_MARK, -}; -/* - I2C2 ------------------------------------------------------------------- */ -static const unsigned int i2c2_0_pins[] = { - /* SCL, SDA */ - 237, 236, -}; -static const unsigned int i2c2_0_mux[] = { - PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK, -}; -static const unsigned int i2c2_1_pins[] = { - /* SCL, SDA */ - 27, 28, -}; -static const unsigned int i2c2_1_mux[] = { - PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK, -}; -static const unsigned int i2c2_2_pins[] = { - /* SCL, SDA */ - 115, 116, -}; -static const unsigned int i2c2_2_mux[] = { - PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK, -}; -/* - I2C3 ------------------------------------------------------------------- */ -static const unsigned int i2c3_0_pins[] = { - /* SCL, SDA */ - 248, 249, -}; -static const unsigned int i2c3_0_mux[] = { - PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK, -}; -static const unsigned int i2c3_1_pins[] = { - /* SCL, SDA */ - 27, 28, -}; -static const unsigned int i2c3_1_mux[] = { - PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK, -}; -static const unsigned int i2c3_2_pins[] = { - /* SCL, SDA */ - 115, 116, -}; -static const unsigned int i2c3_2_mux[] = { - PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK, -}; -/* - IrDA ------------------------------------------------------------------- */ -static const unsigned int irda_0_pins[] = { - /* OUT, IN, FIRSEL */ - 241, 242, 243, -}; -static const unsigned int irda_0_mux[] = { - PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK, -}; -static const unsigned int irda_1_pins[] = { - /* OUT, IN, FIRSEL */ - 49, 53, 54, -}; -static const unsigned int irda_1_mux[] = { - PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, -}; -/* - KEYSC ------------------------------------------------------------------ */ -static const unsigned int keysc_in5_pins[] = { - /* KEYIN[0:4] */ - 66, 67, 68, 69, 70, -}; -static const unsigned int keysc_in5_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, -}; -static const unsigned int keysc_in6_pins[] = { - /* KEYIN[0:5] */ - 66, 67, 68, 69, 70, 71, -}; -static const unsigned int keysc_in6_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, -}; -static const unsigned int keysc_in7_pins[] = { - /* KEYIN[0:6] */ - 66, 67, 68, 69, 70, 71, 72, -}; -static const unsigned int keysc_in7_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, -}; -static const unsigned int keysc_in8_pins[] = { - /* KEYIN[0:7] */ - 66, 67, 68, 69, 70, 71, 72, 73, -}; -static const unsigned int keysc_in8_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, -}; -static const unsigned int keysc_out04_pins[] = { - /* KEYOUT[0:4] */ - 65, 64, 63, 62, 61, -}; -static const unsigned int keysc_out04_mux[] = { - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK, -}; -static const unsigned int keysc_out5_pins[] = { - /* KEYOUT5 */ - 60, -}; -static const unsigned int keysc_out5_mux[] = { - KEYOUT5_MARK, -}; -static const unsigned int keysc_out6_0_pins[] = { - /* KEYOUT6 */ - 59, -}; -static const unsigned int keysc_out6_0_mux[] = { - PORT59_KEYOUT6_MARK, -}; -static const unsigned int keysc_out6_1_pins[] = { - /* KEYOUT6 */ - 131, -}; -static const unsigned int keysc_out6_1_mux[] = { - PORT131_KEYOUT6_MARK, -}; -static const unsigned int keysc_out6_2_pins[] = { - /* KEYOUT6 */ - 143, -}; -static const unsigned int keysc_out6_2_mux[] = { - PORT143_KEYOUT6_MARK, -}; -static const unsigned int keysc_out7_0_pins[] = { - /* KEYOUT7 */ - 58, -}; -static const unsigned int keysc_out7_0_mux[] = { - PORT58_KEYOUT7_MARK, -}; -static const unsigned int keysc_out7_1_pins[] = { - /* KEYOUT7 */ - 132, -}; -static const unsigned int keysc_out7_1_mux[] = { - PORT132_KEYOUT7_MARK, -}; -static const unsigned int keysc_out7_2_pins[] = { - /* KEYOUT7 */ - 144, -}; -static const unsigned int keysc_out7_2_mux[] = { - PORT144_KEYOUT7_MARK, -}; -static const unsigned int keysc_out8_0_pins[] = { - /* KEYOUT8 */ - PIN_NUMBER(6, 26), -}; -static const unsigned int keysc_out8_0_mux[] = { - KEYOUT8_MARK, -}; -static const unsigned int keysc_out8_1_pins[] = { - /* KEYOUT8 */ - 136, -}; -static const unsigned int keysc_out8_1_mux[] = { - PORT136_KEYOUT8_MARK, -}; -static const unsigned int keysc_out8_2_pins[] = { - /* KEYOUT8 */ - 138, -}; -static const unsigned int keysc_out8_2_mux[] = { - PORT138_KEYOUT8_MARK, -}; -static const unsigned int keysc_out9_0_pins[] = { - /* KEYOUT9 */ - 137, -}; -static const unsigned int keysc_out9_0_mux[] = { - PORT137_KEYOUT9_MARK, -}; -static const unsigned int keysc_out9_1_pins[] = { - /* KEYOUT9 */ - 139, -}; -static const unsigned int keysc_out9_1_mux[] = { - PORT139_KEYOUT9_MARK, -}; -static const unsigned int keysc_out9_2_pins[] = { - /* KEYOUT9 */ - 149, -}; -static const unsigned int keysc_out9_2_mux[] = { - PORT149_KEYOUT9_MARK, -}; -static const unsigned int keysc_out10_0_pins[] = { - /* KEYOUT10 */ - 132, -}; -static const unsigned int keysc_out10_0_mux[] = { - PORT132_KEYOUT10_MARK, -}; -static const unsigned int keysc_out10_1_pins[] = { - /* KEYOUT10 */ - 142, -}; -static const unsigned int keysc_out10_1_mux[] = { - PORT142_KEYOUT10_MARK, -}; -static const unsigned int keysc_out11_0_pins[] = { - /* KEYOUT11 */ - 131, -}; -static const unsigned int keysc_out11_0_mux[] = { - PORT131_KEYOUT11_MARK, -}; -static const unsigned int keysc_out11_1_pins[] = { - /* KEYOUT11 */ - 143, -}; -static const unsigned int keysc_out11_1_mux[] = { - PORT143_KEYOUT11_MARK, -}; -/* - LCD -------------------------------------------------------------------- */ -static const unsigned int lcd_data8_pins[] = { - /* D[0:7] */ - 192, 193, 194, 195, 196, 197, 198, 199, -}; -static const unsigned int lcd_data8_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, -}; -static const unsigned int lcd_data9_pins[] = { - /* D[0:8] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, -}; -static const unsigned int lcd_data9_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, -}; -static const unsigned int lcd_data12_pins[] = { - /* D[0:11] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, -}; -static const unsigned int lcd_data12_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, -}; -static const unsigned int lcd_data16_pins[] = { - /* D[0:15] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, -}; -static const unsigned int lcd_data16_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, -}; -static const unsigned int lcd_data18_pins[] = { - /* D[0:17] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, -}; -static const unsigned int lcd_data18_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, -}; -static const unsigned int lcd_data24_pins[] = { - /* D[0:23] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, 210, 211, 212, 213, 214, 215 -}; -static const unsigned int lcd_data24_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK, - LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK, -}; -static const unsigned int lcd_display_pins[] = { - /* DON */ - 222, -}; -static const unsigned int lcd_display_mux[] = { - LCDDON_MARK, -}; -static const unsigned int lcd_lclk_pins[] = { - /* LCLK */ - 221, -}; -static const unsigned int lcd_lclk_mux[] = { - LCDLCLK_MARK, -}; -static const unsigned int lcd_sync_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 220, 218, 216, 219, -}; -static const unsigned int lcd_sync_mux[] = { - LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK, -}; -static const unsigned int lcd_sys_pins[] = { - /* CS, WR, RD, RS */ - 218, 216, 217, 219, -}; -static const unsigned int lcd_sys_mux[] = { - LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, -}; -/* - LCD2 ------------------------------------------------------------------- */ -static const unsigned int lcd2_data8_pins[] = { - /* D[0:7] */ - 128, 129, 142, 143, 144, 145, 138, 139, -}; -static const unsigned int lcd2_data8_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, -}; -static const unsigned int lcd2_data9_pins[] = { - /* D[0:8] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, -}; -static const unsigned int lcd2_data9_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, -}; -static const unsigned int lcd2_data12_pins[] = { - /* D[0:12] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, -}; -static const unsigned int lcd2_data12_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, -}; -static const unsigned int lcd2_data16_pins[] = { - /* D[0:15] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, -}; -static const unsigned int lcd2_data16_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, -}; -static const unsigned int lcd2_data18_pins[] = { - /* D[0:17] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, - 136, 137, -}; -static const unsigned int lcd2_data18_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, - LCD2D16_MARK, LCD2D17_MARK, -}; -static const unsigned int lcd2_data24_pins[] = { - /* D[0:23] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, - 136, 137, 146, 147, 234, 235, 238, 239 -}; -static const unsigned int lcd2_data24_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, - LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK, - LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK, -}; -static const unsigned int lcd2_sync_0_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 128, 129, 146, 145, -}; -static const unsigned int lcd2_sync_0_mux[] = { - PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK, - LCD2DCK_MARK, PORT145_LCD2DISP_MARK, -}; -static const unsigned int lcd2_sync_1_pins[] = { - /* VSYN, HSYN, DCK, DISP */ - 222, 221, 219, 217, -}; -static const unsigned int lcd2_sync_1_mux[] = { - PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK, - LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK, -}; -static const unsigned int lcd2_sys_0_pins[] = { - /* CS, WR, RD, RS */ - 129, 146, 147, 145, -}; -static const unsigned int lcd2_sys_0_mux[] = { - PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK, - LCD2RD__MARK, PORT145_LCD2RS_MARK, -}; -static const unsigned int lcd2_sys_1_pins[] = { - /* CS, WR, RD, RS */ - 221, 219, 147, 217, -}; -static const unsigned int lcd2_sys_1_mux[] = { - PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, - LCD2RD__MARK, PORT217_LCD2RS_MARK, -}; -/* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 271, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 271, 272, 273, 274, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { - /* D[0:7] */ - 271, 272, 273, 274, 275, 276, 277, 278, -}; -static const unsigned int mmc0_data8_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, - MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, -}; -static const unsigned int mmc0_ctrl_0_pins[] = { - /* CMD, CLK */ - 279, 270, -}; -static const unsigned int mmc0_ctrl_0_mux[] = { - MMCCMD0_MARK, MMCCLK0_MARK, -}; -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 305, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 305, 304, 303, 302, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { - /* D[0:7] */ - 305, 304, 303, 302, 301, 300, 299, 298, -}; -static const unsigned int mmc0_data8_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, - MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, -}; -static const unsigned int mmc0_ctrl_1_pins[] = { - /* CMD, CLK */ - 297, 289, -}; -static const unsigned int mmc0_ctrl_1_mux[] = { - MMCCMD1_MARK, MMCCLK1_MARK, -}; -/* - SCIFA0 ----------------------------------------------------------------- */ -static const unsigned int scifa0_data_pins[] = { - /* RXD, TXD */ - 43, 17, -}; -static const unsigned int scifa0_data_mux[] = { - SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, -}; -static const unsigned int scifa0_clk_pins[] = { - /* SCK */ - 16, -}; -static const unsigned int scifa0_clk_mux[] = { - SCIFA0_SCK_MARK, -}; -static const unsigned int scifa0_ctrl_pins[] = { - /* RTS, CTS */ - 42, 44, -}; -static const unsigned int scifa0_ctrl_mux[] = { - SCIFA0_RTS__MARK, SCIFA0_CTS__MARK, -}; -/* - SCIFA1 ----------------------------------------------------------------- */ -static const unsigned int scifa1_data_pins[] = { - /* RXD, TXD */ - 228, 225, -}; -static const unsigned int scifa1_data_mux[] = { - SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, -}; -static const unsigned int scifa1_clk_pins[] = { - /* SCK */ - 226, -}; -static const unsigned int scifa1_clk_mux[] = { - SCIFA1_SCK_MARK, -}; -static const unsigned int scifa1_ctrl_pins[] = { - /* RTS, CTS */ - 227, 229, -}; -static const unsigned int scifa1_ctrl_mux[] = { - SCIFA1_RTS__MARK, SCIFA1_CTS__MARK, -}; -/* - SCIFA2 ----------------------------------------------------------------- */ -static const unsigned int scifa2_data_0_pins[] = { - /* RXD, TXD */ - 155, 154, -}; -static const unsigned int scifa2_data_0_mux[] = { - SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK, -}; -static const unsigned int scifa2_clk_0_pins[] = { - /* SCK */ - 158, -}; -static const unsigned int scifa2_clk_0_mux[] = { - SCIFA2_SCK1_MARK, -}; -static const unsigned int scifa2_ctrl_0_pins[] = { - /* RTS, CTS */ - 156, 157, -}; -static const unsigned int scifa2_ctrl_0_mux[] = { - SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK, -}; -static const unsigned int scifa2_data_1_pins[] = { - /* RXD, TXD */ - 233, 230, -}; -static const unsigned int scifa2_data_1_mux[] = { - SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK, -}; -static const unsigned int scifa2_clk_1_pins[] = { - /* SCK */ - 232, -}; -static const unsigned int scifa2_clk_1_mux[] = { - SCIFA2_SCK2_MARK, -}; -static const unsigned int scifa2_ctrl_1_pins[] = { - /* RTS, CTS */ - 234, 231, -}; -static const unsigned int scifa2_ctrl_1_mux[] = { - SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK, -}; -/* - SCIFA3 ----------------------------------------------------------------- */ -static const unsigned int scifa3_data_pins[] = { - /* RXD, TXD */ - 108, 110, -}; -static const unsigned int scifa3_data_mux[] = { - SCIFA3_RXD_MARK, SCIFA3_TXD_MARK, -}; -static const unsigned int scifa3_ctrl_pins[] = { - /* RTS, CTS */ - 109, 107, -}; -static const unsigned int scifa3_ctrl_mux[] = { - SCIFA3_RTS__MARK, SCIFA3_CTS__MARK, -}; -/* - SCIFA4 ----------------------------------------------------------------- */ -static const unsigned int scifa4_data_pins[] = { - /* RXD, TXD */ - 33, 32, -}; -static const unsigned int scifa4_data_mux[] = { - SCIFA4_RXD_MARK, SCIFA4_TXD_MARK, -}; -static const unsigned int scifa4_ctrl_pins[] = { - /* RTS, CTS */ - 34, 35, -}; -static const unsigned int scifa4_ctrl_mux[] = { - SCIFA4_RTS__MARK, SCIFA4_CTS__MARK, -}; -/* - SCIFA5 ----------------------------------------------------------------- */ -static const unsigned int scifa5_data_0_pins[] = { - /* RXD, TXD */ - 246, 247, -}; -static const unsigned int scifa5_data_0_mux[] = { - PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK, -}; -static const unsigned int scifa5_clk_0_pins[] = { - /* SCK */ - 248, -}; -static const unsigned int scifa5_clk_0_mux[] = { - PORT248_SCIFA5_SCK_MARK, -}; -static const unsigned int scifa5_ctrl_0_pins[] = { - /* RTS, CTS */ - 245, 244, -}; -static const unsigned int scifa5_ctrl_0_mux[] = { - PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK, -}; -static const unsigned int scifa5_data_1_pins[] = { - /* RXD, TXD */ - 195, 196, -}; -static const unsigned int scifa5_data_1_mux[] = { - PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK, -}; -static const unsigned int scifa5_clk_1_pins[] = { - /* SCK */ - 197, -}; -static const unsigned int scifa5_clk_1_mux[] = { - PORT197_SCIFA5_SCK_MARK, -}; -static const unsigned int scifa5_ctrl_1_pins[] = { - /* RTS, CTS */ - 194, 193, -}; -static const unsigned int scifa5_ctrl_1_mux[] = { - PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK, -}; -static const unsigned int scifa5_data_2_pins[] = { - /* RXD, TXD */ - 162, 160, -}; -static const unsigned int scifa5_data_2_mux[] = { - PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK, -}; -static const unsigned int scifa5_clk_2_pins[] = { - /* SCK */ - 159, -}; -static const unsigned int scifa5_clk_2_mux[] = { - PORT159_SCIFA5_SCK_MARK, -}; -static const unsigned int scifa5_ctrl_2_pins[] = { - /* RTS, CTS */ - 163, 161, -}; -static const unsigned int scifa5_ctrl_2_mux[] = { - PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK, -}; -/* - SCIFA6 ----------------------------------------------------------------- */ -static const unsigned int scifa6_pins[] = { - /* TXD */ - 240, -}; -static const unsigned int scifa6_mux[] = { - SCIFA6_TXD_MARK, -}; -/* - SCIFA7 ----------------------------------------------------------------- */ -static const unsigned int scifa7_data_pins[] = { - /* RXD, TXD */ - 12, 18, -}; -static const unsigned int scifa7_data_mux[] = { - SCIFA7_RXD_MARK, SCIFA7_TXD_MARK, -}; -static const unsigned int scifa7_ctrl_pins[] = { - /* RTS, CTS */ - 19, 13, -}; -static const unsigned int scifa7_ctrl_mux[] = { - SCIFA7_RTS__MARK, SCIFA7_CTS__MARK, -}; -/* - SCIFB ------------------------------------------------------------------ */ -static const unsigned int scifb_data_0_pins[] = { - /* RXD, TXD */ - 162, 160, -}; -static const unsigned int scifb_data_0_mux[] = { - PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK, -}; -static const unsigned int scifb_clk_0_pins[] = { - /* SCK */ - 159, -}; -static const unsigned int scifb_clk_0_mux[] = { - PORT159_SCIFB_SCK_MARK, -}; -static const unsigned int scifb_ctrl_0_pins[] = { - /* RTS, CTS */ - 163, 161, -}; -static const unsigned int scifb_ctrl_0_mux[] = { - PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK, -}; -static const unsigned int scifb_data_1_pins[] = { - /* RXD, TXD */ - 246, 247, -}; -static const unsigned int scifb_data_1_mux[] = { - PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK, -}; -static const unsigned int scifb_clk_1_pins[] = { - /* SCK */ - 248, -}; -static const unsigned int scifb_clk_1_mux[] = { - PORT248_SCIFB_SCK_MARK, -}; -static const unsigned int scifb_ctrl_1_pins[] = { - /* RTS, CTS */ - 245, 244, -}; -static const unsigned int scifb_ctrl_1_mux[] = { - PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, -}; -/* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 252, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { - /* D[0:3] */ - 252, 253, 254, 255, -}; -static const unsigned int sdhi0_data4_mux[] = { - SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, -}; -static const unsigned int sdhi0_ctrl_pins[] = { - /* CMD, CLK */ - 256, 250, -}; -static const unsigned int sdhi0_ctrl_mux[] = { - SDHICMD0_MARK, SDHICLK0_MARK, -}; -static const unsigned int sdhi0_cd_pins[] = { - /* CD */ - 251, -}; -static const unsigned int sdhi0_cd_mux[] = { - SDHICD0_MARK, -}; -static const unsigned int sdhi0_wp_pins[] = { - /* WP */ - 257, -}; -static const unsigned int sdhi0_wp_mux[] = { - SDHIWP0_MARK, -}; -/* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 259, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - 259, 260, 261, 262, -}; -static const unsigned int sdhi1_data4_mux[] = { - SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CMD, CLK */ - 263, 258, -}; -static const unsigned int sdhi1_ctrl_mux[] = { - SDHICMD1_MARK, SDHICLK1_MARK, -}; -/* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 265, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - 265, 266, 267, 268, -}; -static const unsigned int sdhi2_data4_mux[] = { - SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, -}; -static const unsigned int sdhi2_ctrl_pins[] = { - /* CMD, CLK */ - 269, 264, -}; -static const unsigned int sdhi2_ctrl_mux[] = { - SDHICMD2_MARK, SDHICLK2_MARK, -}; -/* - USB -------------------------------------------------------------------- */ -static const unsigned int usb_vbus_pins[] = { - /* VBUS */ - 0, -}; -static const unsigned int usb_vbus_mux[] = { - VBUS_0_MARK, -}; - -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(bsc_data_0_7), - SH_PFC_PIN_GROUP(bsc_data_8_15), - SH_PFC_PIN_GROUP(bsc_cs4), - SH_PFC_PIN_GROUP(bsc_cs5_a), - SH_PFC_PIN_GROUP(bsc_cs5_b), - SH_PFC_PIN_GROUP(bsc_cs6_a), - SH_PFC_PIN_GROUP(bsc_cs6_b), - SH_PFC_PIN_GROUP(bsc_rd), - SH_PFC_PIN_GROUP(bsc_rdwr_0), - SH_PFC_PIN_GROUP(bsc_rdwr_1), - SH_PFC_PIN_GROUP(bsc_rdwr_2), - SH_PFC_PIN_GROUP(bsc_we0), - SH_PFC_PIN_GROUP(bsc_we1), - SH_PFC_PIN_GROUP(fsia_mclk_in), - SH_PFC_PIN_GROUP(fsia_mclk_out), - SH_PFC_PIN_GROUP(fsia_sclk_in), - SH_PFC_PIN_GROUP(fsia_sclk_out), - SH_PFC_PIN_GROUP(fsia_data_in), - SH_PFC_PIN_GROUP(fsia_data_out), - SH_PFC_PIN_GROUP(fsia_spdif), - SH_PFC_PIN_GROUP(fsib_mclk_in), - SH_PFC_PIN_GROUP(fsib_mclk_out), - SH_PFC_PIN_GROUP(fsib_sclk_in), - SH_PFC_PIN_GROUP(fsib_sclk_out), - SH_PFC_PIN_GROUP(fsib_data_in), - SH_PFC_PIN_GROUP(fsib_data_out), - SH_PFC_PIN_GROUP(fsib_spdif), - SH_PFC_PIN_GROUP(fsic_mclk_in), - SH_PFC_PIN_GROUP(fsic_mclk_out), - SH_PFC_PIN_GROUP(fsic_sclk_in), - SH_PFC_PIN_GROUP(fsic_sclk_out), - SH_PFC_PIN_GROUP(fsic_data_in), - SH_PFC_PIN_GROUP(fsic_data_out), - SH_PFC_PIN_GROUP(fsic_spdif_0), - SH_PFC_PIN_GROUP(fsic_spdif_1), - SH_PFC_PIN_GROUP(fsid_sclk_in), - SH_PFC_PIN_GROUP(fsid_sclk_out), - SH_PFC_PIN_GROUP(fsid_data_in), - SH_PFC_PIN_GROUP(i2c2_0), - SH_PFC_PIN_GROUP(i2c2_1), - SH_PFC_PIN_GROUP(i2c2_2), - SH_PFC_PIN_GROUP(i2c3_0), - SH_PFC_PIN_GROUP(i2c3_1), - SH_PFC_PIN_GROUP(i2c3_2), - SH_PFC_PIN_GROUP(irda_0), - SH_PFC_PIN_GROUP(irda_1), - SH_PFC_PIN_GROUP(keysc_in5), - SH_PFC_PIN_GROUP(keysc_in6), - SH_PFC_PIN_GROUP(keysc_in7), - SH_PFC_PIN_GROUP(keysc_in8), - SH_PFC_PIN_GROUP(keysc_out04), - SH_PFC_PIN_GROUP(keysc_out5), - SH_PFC_PIN_GROUP(keysc_out6_0), - SH_PFC_PIN_GROUP(keysc_out6_1), - SH_PFC_PIN_GROUP(keysc_out6_2), - SH_PFC_PIN_GROUP(keysc_out7_0), - SH_PFC_PIN_GROUP(keysc_out7_1), - SH_PFC_PIN_GROUP(keysc_out7_2), - SH_PFC_PIN_GROUP(keysc_out8_0), - SH_PFC_PIN_GROUP(keysc_out8_1), - SH_PFC_PIN_GROUP(keysc_out8_2), - SH_PFC_PIN_GROUP(keysc_out9_0), - SH_PFC_PIN_GROUP(keysc_out9_1), - SH_PFC_PIN_GROUP(keysc_out9_2), - SH_PFC_PIN_GROUP(keysc_out10_0), - SH_PFC_PIN_GROUP(keysc_out10_1), - SH_PFC_PIN_GROUP(keysc_out11_0), - SH_PFC_PIN_GROUP(keysc_out11_1), - SH_PFC_PIN_GROUP(lcd_data8), - SH_PFC_PIN_GROUP(lcd_data9), - SH_PFC_PIN_GROUP(lcd_data12), - SH_PFC_PIN_GROUP(lcd_data16), - SH_PFC_PIN_GROUP(lcd_data18), - SH_PFC_PIN_GROUP(lcd_data24), - SH_PFC_PIN_GROUP(lcd_display), - SH_PFC_PIN_GROUP(lcd_lclk), - SH_PFC_PIN_GROUP(lcd_sync), - SH_PFC_PIN_GROUP(lcd_sys), - SH_PFC_PIN_GROUP(lcd2_data8), - SH_PFC_PIN_GROUP(lcd2_data9), - SH_PFC_PIN_GROUP(lcd2_data12), - SH_PFC_PIN_GROUP(lcd2_data16), - SH_PFC_PIN_GROUP(lcd2_data18), - SH_PFC_PIN_GROUP(lcd2_data24), - SH_PFC_PIN_GROUP(lcd2_sync_0), - SH_PFC_PIN_GROUP(lcd2_sync_1), - SH_PFC_PIN_GROUP(lcd2_sys_0), - SH_PFC_PIN_GROUP(lcd2_sys_1), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), - SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), - SH_PFC_PIN_GROUP(mmc0_ctrl_1), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa2_data_0), - SH_PFC_PIN_GROUP(scifa2_clk_0), - SH_PFC_PIN_GROUP(scifa2_ctrl_0), - SH_PFC_PIN_GROUP(scifa2_data_1), - SH_PFC_PIN_GROUP(scifa2_clk_1), - SH_PFC_PIN_GROUP(scifa2_ctrl_1), - SH_PFC_PIN_GROUP(scifa3_data), - SH_PFC_PIN_GROUP(scifa3_ctrl), - SH_PFC_PIN_GROUP(scifa4_data), - SH_PFC_PIN_GROUP(scifa4_ctrl), - SH_PFC_PIN_GROUP(scifa5_data_0), - SH_PFC_PIN_GROUP(scifa5_clk_0), - SH_PFC_PIN_GROUP(scifa5_ctrl_0), - SH_PFC_PIN_GROUP(scifa5_data_1), - SH_PFC_PIN_GROUP(scifa5_clk_1), - SH_PFC_PIN_GROUP(scifa5_ctrl_1), - SH_PFC_PIN_GROUP(scifa5_data_2), - SH_PFC_PIN_GROUP(scifa5_clk_2), - SH_PFC_PIN_GROUP(scifa5_ctrl_2), - SH_PFC_PIN_GROUP(scifa6), - SH_PFC_PIN_GROUP(scifa7_data), - SH_PFC_PIN_GROUP(scifa7_ctrl), - SH_PFC_PIN_GROUP(scifb_data_0), - SH_PFC_PIN_GROUP(scifb_clk_0), - SH_PFC_PIN_GROUP(scifb_ctrl_0), - SH_PFC_PIN_GROUP(scifb_data_1), - SH_PFC_PIN_GROUP(scifb_clk_1), - SH_PFC_PIN_GROUP(scifb_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(usb_vbus), -}; - -static const char * const bsc_groups[] = { - "bsc_data_0_7", - "bsc_data_8_15", - "bsc_cs4", - "bsc_cs5_a", - "bsc_cs5_b", - "bsc_cs6_a", - "bsc_cs6_b", - "bsc_rd", - "bsc_rdwr_0", - "bsc_rdwr_1", - "bsc_rdwr_2", - "bsc_we0", - "bsc_we1", -}; - -static const char * const fsia_groups[] = { - "fsia_mclk_in", - "fsia_mclk_out", - "fsia_sclk_in", - "fsia_sclk_out", - "fsia_data_in", - "fsia_data_out", - "fsia_spdif", -}; - -static const char * const fsib_groups[] = { - "fsib_mclk_in", - "fsib_mclk_out", - "fsib_sclk_in", - "fsib_sclk_out", - "fsib_data_in", - "fsib_data_out", - "fsib_spdif", -}; - -static const char * const fsic_groups[] = { - "fsic_mclk_in", - "fsic_mclk_out", - "fsic_sclk_in", - "fsic_sclk_out", - "fsic_data_in", - "fsic_data_out", - "fsic_spdif", -}; - -static const char * const fsid_groups[] = { - "fsid_sclk_in", - "fsid_sclk_out", - "fsid_data_in", -}; - -static const char * const i2c2_groups[] = { - "i2c2_0", - "i2c2_1", - "i2c2_2", -}; - -static const char * const i2c3_groups[] = { - "i2c3_0", - "i2c3_1", - "i2c3_2", -}; - -static const char * const irda_groups[] = { - "irda_0", - "irda_1", -}; + /* Functions with pull-ups */ + PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), + PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), + PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), + PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), + PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), + PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), + PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), + PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), + + PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), + PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), + PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), + PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), + PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), + PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), + PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), + PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), + PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), + PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), + PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), + PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), + PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), + PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), + PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), + + PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, + MSEL4CR_MSEL15_1), + + PINMUX_DATA(MMCD0_0_PU_MARK, + PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_PU_MARK, + PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_PU_MARK, + PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_PU_MARK, + PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_PU_MARK, + PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_5_PU_MARK, + PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_6_PU_MARK, + PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_7_PU_MARK, + PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), + + PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), + PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), + PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), + PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), + PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + GPIO_PORT_ALL(), -static const char * const keysc_groups[] = { - "keysc_in5", - "keysc_in6", - "keysc_in7", - "keysc_in8", - "keysc_out04", - "keysc_out5", - "keysc_out6_0", - "keysc_out6_1", - "keysc_out6_2", - "keysc_out7_0", - "keysc_out7_1", - "keysc_out7_2", - "keysc_out8_0", - "keysc_out8_1", - "keysc_out8_2", - "keysc_out9_0", - "keysc_out9_1", - "keysc_out9_2", - "keysc_out10_0", - "keysc_out10_1", - "keysc_out11_0", - "keysc_out11_1", -}; - -static const char * const lcd_groups[] = { - "lcd_data8", - "lcd_data9", - "lcd_data12", - "lcd_data16", - "lcd_data18", - "lcd_data24", - "lcd_display", - "lcd_lclk", - "lcd_sync", - "lcd_sys", -}; - -static const char * const lcd2_groups[] = { - "lcd2_data8", - "lcd2_data9", - "lcd2_data12", - "lcd2_data16", - "lcd2_data18", - "lcd2_data24", - "lcd2_sync_0", - "lcd2_sync_1", - "lcd2_sys_0", - "lcd2_sys_1", -}; - -static const char * const mmc0_groups[] = { - "mmc0_data1_0", - "mmc0_data4_0", - "mmc0_data8_0", - "mmc0_ctrl_0", - "mmc0_data1_1", - "mmc0_data4_1", - "mmc0_data8_1", - "mmc0_ctrl_1", -}; - -static const char * const scifa0_groups[] = { - "scifa0_data", - "scifa0_clk", - "scifa0_ctrl", -}; - -static const char * const scifa1_groups[] = { - "scifa1_data", - "scifa1_clk", - "scifa1_ctrl", -}; - -static const char * const scifa2_groups[] = { - "scifa2_data_0", - "scifa2_clk_0", - "scifa2_ctrl_0", - "scifa2_data_1", - "scifa2_clk_1", - "scifa2_ctrl_1", -}; - -static const char * const scifa3_groups[] = { - "scifa3_data", - "scifa3_ctrl", -}; - -static const char * const scifa4_groups[] = { - "scifa4_data", - "scifa4_ctrl", -}; - -static const char * const scifa5_groups[] = { - "scifa5_data_0", - "scifa5_clk_0", - "scifa5_ctrl_0", - "scifa5_data_1", - "scifa5_clk_1", - "scifa5_ctrl_1", - "scifa5_data_2", - "scifa5_clk_2", - "scifa5_ctrl_2", -}; - -static const char * const scifa6_groups[] = { - "scifa6", -}; - -static const char * const scifa7_groups[] = { - "scifa7_data", - "scifa7_ctrl", -}; - -static const char * const scifb_groups[] = { - "scifb_data_0", - "scifb_clk_0", - "scifb_ctrl_0", - "scifb_data_1", - "scifb_clk_1", - "scifb_ctrl_1", -}; - -static const char * const sdhi0_groups[] = { - "sdhi0_data1", - "sdhi0_data4", - "sdhi0_ctrl", - "sdhi0_cd", - "sdhi0_wp", -}; - -static const char * const sdhi1_groups[] = { - "sdhi1_data1", - "sdhi1_data4", - "sdhi1_ctrl", -}; - -static const char * const sdhi2_groups[] = { - "sdhi2_data1", - "sdhi2_data4", - "sdhi2_ctrl", -}; - -static const char * const usb_groups[] = { - "usb_vbus", -}; - -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(bsc), - SH_PFC_FUNCTION(fsia), - SH_PFC_FUNCTION(fsib), - SH_PFC_FUNCTION(fsic), - SH_PFC_FUNCTION(fsid), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(irda), - SH_PFC_FUNCTION(keysc), - SH_PFC_FUNCTION(lcd), - SH_PFC_FUNCTION(lcd2), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifa3), - SH_PFC_FUNCTION(scifa4), - SH_PFC_FUNCTION(scifa5), - SH_PFC_FUNCTION(scifa6), - SH_PFC_FUNCTION(scifa7), - SH_PFC_FUNCTION(scifb), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(usb), -}; - -#define PINMUX_FN_BASE GPIO_FN_GPI0 - -static const struct pinmux_func pinmux_func_gpios[] = { /* Table 25-1 (Functions 0-7) */ + GPIO_FN(VBUS_0), GPIO_FN(GPI0), GPIO_FN(GPI1), GPIO_FN(GPI2), @@ -2948,12 +1556,19 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(GPI5), GPIO_FN(GPI6), GPIO_FN(GPI7), + GPIO_FN(SCIFA7_RXD), + GPIO_FN(SCIFA7_CTS_), GPIO_FN(GPO7), \ GPIO_FN(MFG0_OUT2), GPIO_FN(GPO6), \ GPIO_FN(MFG1_OUT2), GPIO_FN(GPO5), \ + GPIO_FN(SCIFA0_SCK), \ + GPIO_FN(FSICOSLDT3), \ GPIO_FN(PORT16_VIO_CKOR), + GPIO_FN(SCIFA0_TXD), + GPIO_FN(SCIFA7_TXD), + GPIO_FN(SCIFA7_RTS_), \ GPIO_FN(PORT19_VIO_CKO2), GPIO_FN(GPO0), GPIO_FN(GPO1), @@ -2966,9 +1581,13 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(VINT), GPIO_FN(TCKON), GPIO_FN(XDVFS1), \ + GPIO_FN(PORT27_I2C_SCL2), \ + GPIO_FN(PORT27_I2C_SCL3), \ GPIO_FN(MFG0_OUT1), \ GPIO_FN(PORT27_IROUT), GPIO_FN(XDVFS2), \ + GPIO_FN(PORT28_I2C_SDA2), \ + GPIO_FN(PORT28_I2C_SDA3), \ GPIO_FN(PORT28_TPU1TO1), GPIO_FN(SIM_RST), \ GPIO_FN(PORT29_TPU1TO1), @@ -2976,53 +1595,140 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(PORT30_VIO_CKOR), GPIO_FN(SIM_D), \ GPIO_FN(PORT31_IROUT), + GPIO_FN(SCIFA4_TXD), + GPIO_FN(SCIFA4_RXD), \ GPIO_FN(XWUP), + GPIO_FN(SCIFA4_RTS_), + GPIO_FN(SCIFA4_CTS_), + GPIO_FN(FSIBOBT), \ + GPIO_FN(FSIBIBT), + GPIO_FN(FSIBOLR), \ + GPIO_FN(FSIBILR), + GPIO_FN(FSIBOSLD), + GPIO_FN(FSIBISLD), GPIO_FN(VACK), GPIO_FN(XTAL1L), + GPIO_FN(SCIFA0_RTS_), \ + GPIO_FN(FSICOSLDT2), + GPIO_FN(SCIFA0_RXD), + GPIO_FN(SCIFA0_CTS_), \ + GPIO_FN(FSICOSLDT1), + GPIO_FN(FSICOBT), \ + GPIO_FN(FSICIBT), \ + GPIO_FN(FSIDOBT), \ + GPIO_FN(FSIDIBT), + GPIO_FN(FSICOLR), \ + GPIO_FN(FSICILR), \ + GPIO_FN(FSIDOLR), \ + GPIO_FN(FSIDILR), + GPIO_FN(FSICOSLD), \ + GPIO_FN(PORT47_FSICSPDIF), + GPIO_FN(FSICISLD), \ + GPIO_FN(FSIDISLD), + GPIO_FN(FSIACK), \ + GPIO_FN(PORT49_IRDA_OUT), \ GPIO_FN(PORT49_IROUT), \ + GPIO_FN(FSIAOMC), + GPIO_FN(FSIAOLR), \ GPIO_FN(BBIF2_TSYNC2), \ GPIO_FN(TPU2TO2), \ + GPIO_FN(FSIAILR), + GPIO_FN(FSIAOBT), \ GPIO_FN(BBIF2_TSCK2), \ GPIO_FN(TPU2TO3), \ + GPIO_FN(FSIAIBT), + GPIO_FN(FSIAOSLD), \ GPIO_FN(BBIF2_TXD2), + GPIO_FN(FSIASPDIF), \ + GPIO_FN(PORT53_IRDA_IN), \ GPIO_FN(TPU3TO3), \ + GPIO_FN(FSIBSPDIF), \ + GPIO_FN(PORT53_FSICSPDIF), + GPIO_FN(FSIBCK), \ + GPIO_FN(PORT54_IRDA_FIRSEL), \ GPIO_FN(TPU3TO2), \ + GPIO_FN(FSIBOMC), \ + GPIO_FN(FSICCK), \ + GPIO_FN(FSICOMC), + GPIO_FN(FSIAISLD), \ GPIO_FN(TPU0TO0), GPIO_FN(A0), \ GPIO_FN(BS_), GPIO_FN(A12), \ + GPIO_FN(PORT58_KEYOUT7), \ GPIO_FN(TPU4TO2), GPIO_FN(A13), \ + GPIO_FN(PORT59_KEYOUT6), \ GPIO_FN(TPU0TO1), GPIO_FN(A14), \ + GPIO_FN(KEYOUT5), GPIO_FN(A15), \ + GPIO_FN(KEYOUT4), GPIO_FN(A16), \ + GPIO_FN(KEYOUT3), \ GPIO_FN(MSIOF0_SS1), GPIO_FN(A17), \ + GPIO_FN(KEYOUT2), \ GPIO_FN(MSIOF0_TSYNC), GPIO_FN(A18), \ + GPIO_FN(KEYOUT1), \ GPIO_FN(MSIOF0_TSCK), GPIO_FN(A19), \ + GPIO_FN(KEYOUT0), \ GPIO_FN(MSIOF0_TXD), GPIO_FN(A20), \ + GPIO_FN(KEYIN0), \ GPIO_FN(MSIOF0_RSCK), GPIO_FN(A21), \ + GPIO_FN(KEYIN1), \ GPIO_FN(MSIOF0_RSYNC), GPIO_FN(A22), \ + GPIO_FN(KEYIN2), \ GPIO_FN(MSIOF0_MCK0), GPIO_FN(A23), \ + GPIO_FN(KEYIN3), \ GPIO_FN(MSIOF0_MCK1), GPIO_FN(A24), \ + GPIO_FN(KEYIN4), \ GPIO_FN(MSIOF0_RXD), GPIO_FN(A25), \ + GPIO_FN(KEYIN5), \ GPIO_FN(MSIOF0_SS2), GPIO_FN(A26), \ + GPIO_FN(KEYIN6), + GPIO_FN(KEYIN7), + GPIO_FN(D0_NAF0), + GPIO_FN(D1_NAF1), + GPIO_FN(D2_NAF2), + GPIO_FN(D3_NAF3), + GPIO_FN(D4_NAF4), + GPIO_FN(D5_NAF5), + GPIO_FN(D6_NAF6), + GPIO_FN(D7_NAF7), + GPIO_FN(D8_NAF8), + GPIO_FN(D9_NAF9), + GPIO_FN(D10_NAF10), + GPIO_FN(D11_NAF11), + GPIO_FN(D12_NAF12), + GPIO_FN(D13_NAF13), + GPIO_FN(D14_NAF14), + GPIO_FN(D15_NAF15), + GPIO_FN(CS4_), + GPIO_FN(CS5A_), \ + GPIO_FN(PORT91_RDWR), + GPIO_FN(CS5B_), \ GPIO_FN(FCE1_), + GPIO_FN(CS6B_), \ GPIO_FN(DACK0), GPIO_FN(FCE0_), \ + GPIO_FN(CS6A_), GPIO_FN(WAIT_), \ GPIO_FN(DREQ0), + GPIO_FN(RD__FSC), + GPIO_FN(WE0__FWE), \ + GPIO_FN(RDWR_FWE), + GPIO_FN(WE1_), GPIO_FN(FRB), GPIO_FN(CKO), GPIO_FN(NBRSTOUT_), @@ -3031,10 +1737,14 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF2_RXD), GPIO_FN(BBIF2_SYNC), GPIO_FN(BBIF2_SCK), + GPIO_FN(SCIFA3_CTS_), \ GPIO_FN(MFG3_IN2), + GPIO_FN(SCIFA3_RXD), \ GPIO_FN(MFG3_IN1), GPIO_FN(BBIF1_SS2), \ + GPIO_FN(SCIFA3_RTS_), \ GPIO_FN(MFG3_OUT1), + GPIO_FN(SCIFA3_TXD), GPIO_FN(HSI_RX_DATA), \ GPIO_FN(BBIF1_RXD), GPIO_FN(HSI_TX_WAKE), \ @@ -3045,57 +1755,103 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(BBIF1_TXD), GPIO_FN(HSI_RX_READY), \ GPIO_FN(BBIF1_RSCK), \ + GPIO_FN(PORT115_I2C_SCL2), \ + GPIO_FN(PORT115_I2C_SCL3), GPIO_FN(HSI_RX_WAKE), \ GPIO_FN(BBIF1_RSYNC), \ + GPIO_FN(PORT116_I2C_SDA2), \ + GPIO_FN(PORT116_I2C_SDA3), GPIO_FN(HSI_RX_FLAG), \ GPIO_FN(BBIF1_SS1), \ GPIO_FN(BBIF1_FLOW), GPIO_FN(HSI_TX_FLAG), GPIO_FN(VIO_VD), \ + GPIO_FN(PORT128_LCD2VSYN), \ GPIO_FN(VIO2_VD), \ + GPIO_FN(LCD2D0), GPIO_FN(VIO_HD), \ + GPIO_FN(PORT129_LCD2HSYN), \ + GPIO_FN(PORT129_LCD2CS_), \ GPIO_FN(VIO2_HD), \ + GPIO_FN(LCD2D1), GPIO_FN(VIO_D0), \ GPIO_FN(PORT130_MSIOF2_RXD), \ + GPIO_FN(LCD2D10), GPIO_FN(VIO_D1), \ + GPIO_FN(PORT131_KEYOUT6), \ GPIO_FN(PORT131_MSIOF2_SS1), \ + GPIO_FN(PORT131_KEYOUT11), \ + GPIO_FN(LCD2D11), GPIO_FN(VIO_D2), \ + GPIO_FN(PORT132_KEYOUT7), \ GPIO_FN(PORT132_MSIOF2_SS2), \ + GPIO_FN(PORT132_KEYOUT10), \ + GPIO_FN(LCD2D12), GPIO_FN(VIO_D3), \ GPIO_FN(MSIOF2_TSYNC), \ + GPIO_FN(LCD2D13), GPIO_FN(VIO_D4), \ GPIO_FN(MSIOF2_TXD), \ + GPIO_FN(LCD2D14), GPIO_FN(VIO_D5), \ GPIO_FN(MSIOF2_TSCK), \ + GPIO_FN(LCD2D15), GPIO_FN(VIO_D6), \ + GPIO_FN(PORT136_KEYOUT8), \ + GPIO_FN(LCD2D16), GPIO_FN(VIO_D7), \ + GPIO_FN(PORT137_KEYOUT9), \ + GPIO_FN(LCD2D17), GPIO_FN(VIO_D8), \ + GPIO_FN(PORT138_KEYOUT8), \ GPIO_FN(VIO2_D0), \ + GPIO_FN(LCD2D6), GPIO_FN(VIO_D9), \ + GPIO_FN(PORT139_KEYOUT9), \ GPIO_FN(VIO2_D1), \ + GPIO_FN(LCD2D7), GPIO_FN(VIO_D10), \ GPIO_FN(TPU0TO2), \ GPIO_FN(VIO2_D2), \ + GPIO_FN(LCD2D8), GPIO_FN(VIO_D11), \ GPIO_FN(TPU0TO3), \ GPIO_FN(VIO2_D3), \ + GPIO_FN(LCD2D9), GPIO_FN(VIO_D12), \ + GPIO_FN(PORT142_KEYOUT10), \ GPIO_FN(VIO2_D4), \ + GPIO_FN(LCD2D2), GPIO_FN(VIO_D13), \ + GPIO_FN(PORT143_KEYOUT11), \ + GPIO_FN(PORT143_KEYOUT6), \ GPIO_FN(VIO2_D5), \ + GPIO_FN(LCD2D3), GPIO_FN(VIO_D14), \ + GPIO_FN(PORT144_KEYOUT7), \ GPIO_FN(VIO2_D6), \ + GPIO_FN(LCD2D4), GPIO_FN(VIO_D15), \ GPIO_FN(TPU1TO3), \ + GPIO_FN(PORT145_LCD2DISP), \ + GPIO_FN(PORT145_LCD2RS), \ GPIO_FN(VIO2_D7), \ + GPIO_FN(LCD2D5), GPIO_FN(VIO_CLK), \ + GPIO_FN(LCD2DCK), \ + GPIO_FN(PORT146_LCD2WR_), \ GPIO_FN(VIO2_CLK), \ + GPIO_FN(LCD2D18), GPIO_FN(VIO_FIELD), \ + GPIO_FN(LCD2RD_), \ GPIO_FN(VIO2_FIELD), \ + GPIO_FN(LCD2D19), GPIO_FN(VIO_CKO), GPIO_FN(A27), \ + GPIO_FN(PORT149_RDWR), \ GPIO_FN(MFG0_IN1), \ + GPIO_FN(PORT149_KEYOUT9), GPIO_FN(MFG0_IN2), GPIO_FN(TS_SPSYNC3), \ GPIO_FN(MSIOF2_RSCK), @@ -3104,105 +1860,201 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(TPU1TO2), \ GPIO_FN(TS_SDEN3), \ GPIO_FN(PORT153_MSIOF2_SS1), + GPIO_FN(SCIFA2_TXD1), \ GPIO_FN(MSIOF2_MCK0), + GPIO_FN(SCIFA2_RXD1), \ GPIO_FN(MSIOF2_MCK1), + GPIO_FN(SCIFA2_RTS1_), \ GPIO_FN(PORT156_MSIOF2_SS2), + GPIO_FN(SCIFA2_CTS1_), \ GPIO_FN(PORT157_MSIOF2_RXD), GPIO_FN(DINT_), \ + GPIO_FN(SCIFA2_SCK1), \ GPIO_FN(TS_SCK3), + GPIO_FN(PORT159_SCIFB_SCK), \ + GPIO_FN(PORT159_SCIFA5_SCK), \ GPIO_FN(NMI), + GPIO_FN(PORT160_SCIFB_TXD), \ + GPIO_FN(PORT160_SCIFA5_TXD), + GPIO_FN(PORT161_SCIFB_CTS_), \ + GPIO_FN(PORT161_SCIFA5_CTS_), + GPIO_FN(PORT162_SCIFB_RXD), \ + GPIO_FN(PORT162_SCIFA5_RXD), + GPIO_FN(PORT163_SCIFB_RTS_), \ + GPIO_FN(PORT163_SCIFA5_RTS_), \ GPIO_FN(TPU3TO0), + GPIO_FN(LCDD0), + GPIO_FN(LCDD1), \ + GPIO_FN(PORT193_SCIFA5_CTS_), \ GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), \ + GPIO_FN(PORT194_SCIFA5_RTS_), \ GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), \ + GPIO_FN(PORT195_SCIFA5_RXD), \ GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), \ + GPIO_FN(PORT196_SCIFA5_TXD), + GPIO_FN(LCDD5), \ + GPIO_FN(PORT197_SCIFA5_SCK), \ GPIO_FN(MFG2_OUT2), \ GPIO_FN(TPU2TO1), + GPIO_FN(LCDD6), + GPIO_FN(LCDD7), \ GPIO_FN(TPU4TO1), \ GPIO_FN(MFG4_OUT2), + GPIO_FN(LCDD8), \ GPIO_FN(D16), + GPIO_FN(LCDD9), \ GPIO_FN(D17), + GPIO_FN(LCDD10), \ GPIO_FN(D18), + GPIO_FN(LCDD11), \ GPIO_FN(D19), + GPIO_FN(LCDD12), \ GPIO_FN(D20), + GPIO_FN(LCDD13), \ GPIO_FN(D21), + GPIO_FN(LCDD14), \ GPIO_FN(D22), + GPIO_FN(LCDD15), \ GPIO_FN(PORT207_MSIOF0L_SS1), \ GPIO_FN(D23), + GPIO_FN(LCDD16), \ GPIO_FN(PORT208_MSIOF0L_SS2), \ GPIO_FN(D24), + GPIO_FN(LCDD17), \ GPIO_FN(D25), + GPIO_FN(LCDD18), \ GPIO_FN(DREQ2), \ GPIO_FN(PORT210_MSIOF0L_SS1), \ GPIO_FN(D26), + GPIO_FN(LCDD19), \ GPIO_FN(PORT211_MSIOF0L_SS2), \ GPIO_FN(D27), + GPIO_FN(LCDD20), \ GPIO_FN(TS_SPSYNC1), \ GPIO_FN(MSIOF0L_MCK0), \ GPIO_FN(D28), + GPIO_FN(LCDD21), \ GPIO_FN(TS_SDAT1), \ GPIO_FN(MSIOF0L_MCK1), \ GPIO_FN(D29), + GPIO_FN(LCDD22), \ GPIO_FN(TS_SDEN1), \ GPIO_FN(MSIOF0L_RSCK), \ GPIO_FN(D30), + GPIO_FN(LCDD23), \ GPIO_FN(TS_SCK1), \ GPIO_FN(MSIOF0L_RSYNC), \ GPIO_FN(D31), + GPIO_FN(LCDDCK), \ + GPIO_FN(LCDWR_), + GPIO_FN(LCDRD_), \ GPIO_FN(DACK2), \ + GPIO_FN(PORT217_LCD2RS), \ GPIO_FN(MSIOF0L_TSYNC), \ GPIO_FN(VIO2_FIELD3), \ + GPIO_FN(PORT217_LCD2DISP), + GPIO_FN(LCDHSYN), \ + GPIO_FN(LCDCS_), \ + GPIO_FN(LCDCS2_), \ GPIO_FN(DACK3), \ GPIO_FN(PORT218_VIO_CKOR), + GPIO_FN(LCDDISP), \ + GPIO_FN(LCDRS), \ + GPIO_FN(PORT219_LCD2WR_), \ GPIO_FN(DREQ3), \ GPIO_FN(MSIOF0L_TSCK), \ GPIO_FN(VIO2_CLK3), \ + GPIO_FN(LCD2DCK_2), + GPIO_FN(LCDVSYN), \ + GPIO_FN(LCDVSYN2), + GPIO_FN(LCDLCLK), \ GPIO_FN(DREQ1), \ + GPIO_FN(PORT221_LCD2CS_), \ GPIO_FN(PWEN), \ GPIO_FN(MSIOF0L_RXD), \ GPIO_FN(VIO2_HD3), \ + GPIO_FN(PORT221_LCD2HSYN), + GPIO_FN(LCDDON), \ + GPIO_FN(LCDDON2), \ GPIO_FN(DACK1), \ GPIO_FN(OVCN), \ GPIO_FN(MSIOF0L_TXD), \ GPIO_FN(VIO2_VD3), \ + GPIO_FN(PORT222_LCD2VSYN), + GPIO_FN(SCIFA1_TXD), \ GPIO_FN(OVCN2), GPIO_FN(EXTLP), \ + GPIO_FN(SCIFA1_SCK), \ GPIO_FN(PORT226_VIO_CKO2), + GPIO_FN(SCIFA1_RTS_), \ GPIO_FN(IDIN), + GPIO_FN(SCIFA1_RXD), + GPIO_FN(SCIFA1_CTS_), \ GPIO_FN(MFG1_IN1), GPIO_FN(MSIOF1_TXD), \ + GPIO_FN(SCIFA2_TXD2), GPIO_FN(MSIOF1_TSYNC), \ + GPIO_FN(SCIFA2_CTS2_), GPIO_FN(MSIOF1_TSCK), \ + GPIO_FN(SCIFA2_SCK2), GPIO_FN(MSIOF1_RXD), \ + GPIO_FN(SCIFA2_RXD2), GPIO_FN(MSIOF1_RSCK), \ + GPIO_FN(SCIFA2_RTS2_), \ GPIO_FN(VIO2_CLK2), \ + GPIO_FN(LCD2D20), GPIO_FN(MSIOF1_RSYNC), \ GPIO_FN(MFG1_IN2), \ GPIO_FN(VIO2_VD2), \ + GPIO_FN(LCD2D21), GPIO_FN(MSIOF1_MCK0), \ + GPIO_FN(PORT236_I2C_SDA2), GPIO_FN(MSIOF1_MCK1), \ + GPIO_FN(PORT237_I2C_SCL2), GPIO_FN(MSIOF1_SS1), \ GPIO_FN(VIO2_FIELD2), \ + GPIO_FN(LCD2D22), GPIO_FN(MSIOF1_SS2), \ GPIO_FN(VIO2_HD2), \ + GPIO_FN(LCD2D23), + GPIO_FN(SCIFA6_TXD), + GPIO_FN(PORT241_IRDA_OUT), \ GPIO_FN(PORT241_IROUT), \ GPIO_FN(MFG4_OUT1), \ GPIO_FN(TPU4TO0), + GPIO_FN(PORT242_IRDA_IN), \ GPIO_FN(MFG4_IN2), + GPIO_FN(PORT243_IRDA_FIRSEL), \ GPIO_FN(PORT243_VIO_CKO2), + GPIO_FN(PORT244_SCIFA5_CTS_), \ GPIO_FN(MFG2_IN1), \ + GPIO_FN(PORT244_SCIFB_CTS_), \ GPIO_FN(MSIOF2R_RXD), + GPIO_FN(PORT245_SCIFA5_RTS_), \ GPIO_FN(MFG2_IN2), \ + GPIO_FN(PORT245_SCIFB_RTS_), \ GPIO_FN(MSIOF2R_TXD), + GPIO_FN(PORT246_SCIFA5_RXD), \ GPIO_FN(MFG1_OUT1), \ + GPIO_FN(PORT246_SCIFB_RXD), \ GPIO_FN(TPU1TO0), + GPIO_FN(PORT247_SCIFA5_TXD), \ GPIO_FN(MFG3_OUT2), \ + GPIO_FN(PORT247_SCIFB_TXD), \ GPIO_FN(TPU3TO1), + GPIO_FN(PORT248_SCIFA5_SCK), \ GPIO_FN(MFG2_OUT1), \ + GPIO_FN(PORT248_SCIFB_SCK), \ GPIO_FN(TPU2TO0), \ + GPIO_FN(PORT248_I2C_SCL3), \ GPIO_FN(MSIOF2R_TSCK), GPIO_FN(PORT249_IROUT), \ GPIO_FN(MFG4_IN1), \ + GPIO_FN(PORT249_I2C_SDA3), \ GPIO_FN(MSIOF2R_TSYNC), GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), @@ -3320,24 +2172,56 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(IRQ9_MEM_INT), GPIO_FN(IRQ9_MCP_INT), GPIO_FN(A11), + GPIO_FN(KEYOUT8), GPIO_FN(TPU4TO3), GPIO_FN(RESETA_N_PU_ON), GPIO_FN(RESETA_N_PU_OFF), GPIO_FN(EDBGREQ_PD), GPIO_FN(EDBGREQ_PU), -}; -#undef PORTCR -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ - _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 } \ - } -static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* Functions with pull-ups */ + GPIO_FN(KEYIN0_PU), + GPIO_FN(KEYIN1_PU), + GPIO_FN(KEYIN2_PU), + GPIO_FN(KEYIN3_PU), + GPIO_FN(KEYIN4_PU), + GPIO_FN(KEYIN5_PU), + GPIO_FN(KEYIN6_PU), + GPIO_FN(KEYIN7_PU), + GPIO_FN(SDHICD0_PU), + GPIO_FN(SDHID0_0_PU), + GPIO_FN(SDHID0_1_PU), + GPIO_FN(SDHID0_2_PU), + GPIO_FN(SDHID0_3_PU), + GPIO_FN(SDHICMD0_PU), + GPIO_FN(SDHIWP0_PU), + GPIO_FN(SDHID1_0_PU), + GPIO_FN(SDHID1_1_PU), + GPIO_FN(SDHID1_2_PU), + GPIO_FN(SDHID1_3_PU), + GPIO_FN(SDHICMD1_PU), + GPIO_FN(SDHID2_0_PU), + GPIO_FN(SDHID2_1_PU), + GPIO_FN(SDHID2_2_PU), + GPIO_FN(SDHID2_3_PU), + GPIO_FN(SDHICMD2_PU), + GPIO_FN(MMCCMD0_PU), + GPIO_FN(MMCCMD1_PU), + GPIO_FN(MMCD0_0_PU), + GPIO_FN(MMCD0_1_PU), + GPIO_FN(MMCD0_2_PU), + GPIO_FN(MMCD0_3_PU), + GPIO_FN(MMCD0_4_PU), + GPIO_FN(MMCD0_5_PU), + GPIO_FN(MMCD0_6_PU), + GPIO_FN(MMCD0_7_PU), + GPIO_FN(FSIACK_PU), + GPIO_FN(FSIAILR_PU), + GPIO_FN(FSIAIBT_PU), + GPIO_FN(FSIAISLD_PU), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(0, 0xe6050000), /* PORT0CR */ PORTCR(1, 0xe6050001), /* PORT1CR */ PORTCR(2, 0xe6050002), /* PORT2CR */ @@ -3745,7 +2629,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, @@ -3849,116 +2733,60 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -/* External IRQ pins mapped at IRQPIN_BASE */ -#define EXT_IRQ16L(n) irq_pin(n) -#define EXT_IRQ16H(n) irq_pin(n) - -static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), 9), - PINMUX_IRQ(EXT_IRQ16L(1), 10), - PINMUX_IRQ(EXT_IRQ16L(0), 11), - PINMUX_IRQ(EXT_IRQ16H(18), 13), - PINMUX_IRQ(EXT_IRQ16H(20), 14), - PINMUX_IRQ(EXT_IRQ16H(21), 15), - PINMUX_IRQ(EXT_IRQ16H(31), 26), - PINMUX_IRQ(EXT_IRQ16H(30), 27), - PINMUX_IRQ(EXT_IRQ16H(29), 28), - PINMUX_IRQ(EXT_IRQ16H(22), 40), - PINMUX_IRQ(EXT_IRQ16H(23), 53), - PINMUX_IRQ(EXT_IRQ16L(10), 54), - PINMUX_IRQ(EXT_IRQ16L(9), 56), - PINMUX_IRQ(EXT_IRQ16H(26), 115), - PINMUX_IRQ(EXT_IRQ16H(27), 116), - PINMUX_IRQ(EXT_IRQ16H(28), 117), - PINMUX_IRQ(EXT_IRQ16H(24), 118), - PINMUX_IRQ(EXT_IRQ16L(6), 147), - PINMUX_IRQ(EXT_IRQ16L(2), 149), - PINMUX_IRQ(EXT_IRQ16L(7), 150), - PINMUX_IRQ(EXT_IRQ16L(12), 156), - PINMUX_IRQ(EXT_IRQ16L(4), 159), - PINMUX_IRQ(EXT_IRQ16H(25), 164), - PINMUX_IRQ(EXT_IRQ16L(8), 223), - PINMUX_IRQ(EXT_IRQ16L(3), 224), - PINMUX_IRQ(EXT_IRQ16L(5), 227), - PINMUX_IRQ(EXT_IRQ16H(17), 234), - PINMUX_IRQ(EXT_IRQ16L(11), 238), - PINMUX_IRQ(EXT_IRQ16L(13), 239), - PINMUX_IRQ(EXT_IRQ16H(16), 249), - PINMUX_IRQ(EXT_IRQ16L(14), 251), - PINMUX_IRQ(EXT_IRQ16L(9), 308), -}; - -#define PORTnCR_PULMD_OFF (0 << 6) -#define PORTnCR_PULMD_DOWN (2 << 6) -#define PORTnCR_PULMD_UP (3 << 6) -#define PORTnCR_PULMD_MASK (3 << 6) - -static const unsigned int sh73a0_portcr_offsets[] = { - 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000, - 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, -}; - -static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) -{ - void __iomem *addr = pfc->window->virt - + sh73a0_portcr_offsets[pin >> 5] + pin; - u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; - - switch (value) { - case PORTnCR_PULMD_UP: - return PIN_CONFIG_BIAS_PULL_UP; - case PORTnCR_PULMD_DOWN: - return PIN_CONFIG_BIAS_PULL_DOWN; - case PORTnCR_PULMD_OFF: - default: - return PIN_CONFIG_BIAS_DISABLE; - } -} - -static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - void __iomem *addr = pfc->window->virt - + sh73a0_portcr_offsets[pin >> 5] + pin; - u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; - - switch (bias) { - case PIN_CONFIG_BIAS_PULL_UP: - value |= PORTnCR_PULMD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - value |= PORTnCR_PULMD_DOWN; - break; - } - - iowrite8(value, addr); -} - -static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { - .get_bias = sh73a0_pinmux_get_bias, - .set_bias = sh73a0_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info sh73a0_pinmux_info = { +/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ +#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) +#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) + +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), + PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), + PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), + PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), + PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), + PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), + PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), + PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), + PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), + PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), + PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), + PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), + PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), + PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), + PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), + PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), + PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), + PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), + PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), + PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), + PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), + PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), + PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), + PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), + PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), + PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), + PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), + PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), + PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), + PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), +}; + +struct sh_pfc_soc_info sh73a0_pinmux_info = { .name = "sh73a0_pfc", - .ops = &sh73a0_pinmux_ops, - + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .ranges = pinmux_ranges, - .nr_ranges = ARRAY_SIZE(pinmux_ranges), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), - - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_FSIAISLD_PU, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7720.c index 52e9f6be665f..10872ed688a6 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7720.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7720.c @@ -262,7 +262,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), @@ -606,7 +606,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -759,205 +759,202 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(IOIS16), - GPIO_FN(RAS), - GPIO_FN(CAS), - GPIO_FN(CKE), - GPIO_FN(CS5B_CE1A), - GPIO_FN(CS6B_CE1B), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(A21), - GPIO_FN(A20), - GPIO_FN(A19), - GPIO_FN(A0), - GPIO_FN(REFOUT), - GPIO_FN(IRQOUT), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), /* LCDC */ - GPIO_FN(LCD_DATA15), - GPIO_FN(LCD_DATA14), - GPIO_FN(LCD_DATA13), - GPIO_FN(LCD_DATA12), - GPIO_FN(LCD_DATA11), - GPIO_FN(LCD_DATA10), - GPIO_FN(LCD_DATA9), - GPIO_FN(LCD_DATA8), - GPIO_FN(LCD_DATA7), - GPIO_FN(LCD_DATA6), - GPIO_FN(LCD_DATA5), - GPIO_FN(LCD_DATA4), - GPIO_FN(LCD_DATA3), - GPIO_FN(LCD_DATA2), - GPIO_FN(LCD_DATA1), - GPIO_FN(LCD_DATA0), - GPIO_FN(LCD_M_DISP), - GPIO_FN(LCD_CL1), - GPIO_FN(LCD_CL2), - GPIO_FN(LCD_DON), - GPIO_FN(LCD_FLM), - GPIO_FN(LCD_VEPWC), - GPIO_FN(LCD_VCPWC), + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), + PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), /* AFEIF */ - GPIO_FN(AFE_RXIN), - GPIO_FN(AFE_RDET), - GPIO_FN(AFE_FS), - GPIO_FN(AFE_TXOUT), - GPIO_FN(AFE_SCLK), - GPIO_FN(AFE_RLYCNT), - GPIO_FN(AFE_HC1), + PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), + PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), + PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), + PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), + PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), + PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), + PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), /* IIC */ - GPIO_FN(IIC_SCL), - GPIO_FN(IIC_SDA), + PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), + PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), /* DAC */ - GPIO_FN(DA1), - GPIO_FN(DA0), + PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), + PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), /* ADC */ - GPIO_FN(AN3), - GPIO_FN(AN2), - GPIO_FN(AN1), - GPIO_FN(AN0), - GPIO_FN(ADTRG), + PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), + PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), + PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), + PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), /* USB */ - GPIO_FN(USB1D_RCV), - GPIO_FN(USB1D_TXSE0), - GPIO_FN(USB1D_TXDPLS), - GPIO_FN(USB1D_DMNS), - GPIO_FN(USB1D_DPLS), - GPIO_FN(USB1D_SPEED), - GPIO_FN(USB1D_TXENL), - - GPIO_FN(USB2_PWR_EN), - GPIO_FN(USB1_PWR_EN_USBF_UPLUP), - GPIO_FN(USB1D_SUSPEND), + PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), + + PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), + PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, + USB1_PWR_EN_USBF_UPLUP_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK), /* INTC */ - GPIO_FN(IRQ5), - GPIO_FN(IRQ4), - GPIO_FN(IRQ3_IRL3), - GPIO_FN(IRQ2_IRL2), - GPIO_FN(IRQ1_IRL1), - GPIO_FN(IRQ0_IRL0), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), /* PCC */ - GPIO_FN(PCC_REG), - GPIO_FN(PCC_DRV), - GPIO_FN(PCC_BVD2), - GPIO_FN(PCC_BVD1), - GPIO_FN(PCC_CD2), - GPIO_FN(PCC_CD1), - GPIO_FN(PCC_RESET), - GPIO_FN(PCC_RDY), - GPIO_FN(PCC_VS2), - GPIO_FN(PCC_VS1), + PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), + PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), + PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), + PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), + PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), + PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), + PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), /* HUDI */ - GPIO_FN(AUDATA3), - GPIO_FN(AUDATA2), - GPIO_FN(AUDATA1), - GPIO_FN(AUDATA0), - GPIO_FN(AUDCK), - GPIO_FN(AUDSYNC), - GPIO_FN(ASEBRKAK), - GPIO_FN(TRST), - GPIO_FN(TMS), - GPIO_FN(TDO), - GPIO_FN(TDI), - GPIO_FN(TCK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), + PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), + PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), + PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), + PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), + PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), /* DMAC */ - GPIO_FN(DACK1), - GPIO_FN(DREQ1), - GPIO_FN(DACK0), - GPIO_FN(DREQ0), - GPIO_FN(TEND1), - GPIO_FN(TEND0), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), /* SIOF0 */ - GPIO_FN(SIOF0_SYNC), - GPIO_FN(SIOF0_MCLK), - GPIO_FN(SIOF0_TXD), - GPIO_FN(SIOF0_RXD), - GPIO_FN(SIOF0_SCK), + PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), /* SIOF1 */ - GPIO_FN(SIOF1_SYNC), - GPIO_FN(SIOF1_MCLK), - GPIO_FN(SIOF1_TXD), - GPIO_FN(SIOF1_RXD), - GPIO_FN(SIOF1_SCK), + PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), /* SCIF0 */ - GPIO_FN(SCIF0_TXD), - GPIO_FN(SCIF0_RXD), - GPIO_FN(SCIF0_RTS), - GPIO_FN(SCIF0_CTS), - GPIO_FN(SCIF0_SCK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), /* SCIF1 */ - GPIO_FN(SCIF1_TXD), - GPIO_FN(SCIF1_RXD), - GPIO_FN(SCIF1_RTS), - GPIO_FN(SCIF1_CTS), - GPIO_FN(SCIF1_SCK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), /* TPU */ - GPIO_FN(TPU_TO1), - GPIO_FN(TPU_TO0), - GPIO_FN(TPU_TI3B), - GPIO_FN(TPU_TI3A), - GPIO_FN(TPU_TI2B), - GPIO_FN(TPU_TI2A), - GPIO_FN(TPU_TO3), - GPIO_FN(TPU_TO2), + PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), /* SIM */ - GPIO_FN(SIM_D), - GPIO_FN(SIM_CLK), - GPIO_FN(SIM_RST), + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), /* MMC */ - GPIO_FN(MMC_DAT), - GPIO_FN(MMC_CMD), - GPIO_FN(MMC_CLK), - GPIO_FN(MMC_VDDON), - GPIO_FN(MMC_ODMOD), + PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), + PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), + PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), /* SYSC */ - GPIO_FN(STATUS0), - GPIO_FN(STATUS1), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, @@ -1141,7 +1138,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1217,18 +1214,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7720_pinmux_info = { +struct sh_pfc_soc_info sh7720_pinmux_info = { .name = "sh7720_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_STATUS1, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 32034387477b..2de0929315e6 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -296,7 +296,7 @@ enum { PINMUX_FUNCTION_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PTA */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), @@ -787,7 +787,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -982,293 +982,289 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ - GPIO_FN(SCIF0_TXD), - GPIO_FN(SCIF0_RXD), - GPIO_FN(SCIF0_RTS), - GPIO_FN(SCIF0_CTS), - GPIO_FN(SCIF0_SCK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), /* SCIF1 */ - GPIO_FN(SCIF1_TXD), - GPIO_FN(SCIF1_RXD), - GPIO_FN(SCIF1_RTS), - GPIO_FN(SCIF1_CTS), - GPIO_FN(SCIF1_SCK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), /* SCIF2 */ - GPIO_FN(SCIF2_TXD), - GPIO_FN(SCIF2_RXD), - GPIO_FN(SCIF2_RTS), - GPIO_FN(SCIF2_CTS), - GPIO_FN(SCIF2_SCK), + PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), /* SIO */ - GPIO_FN(SIOTXD), - GPIO_FN(SIORXD), - GPIO_FN(SIOD), - GPIO_FN(SIOSTRB0), - GPIO_FN(SIOSTRB1), - GPIO_FN(SIOSCK), - GPIO_FN(SIOMCK), + PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), + PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), + PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), + PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), /* CEU */ - GPIO_FN(VIO_D15), - GPIO_FN(VIO_D14), - GPIO_FN(VIO_D13), - GPIO_FN(VIO_D12), - GPIO_FN(VIO_D11), - GPIO_FN(VIO_D10), - GPIO_FN(VIO_D9), - GPIO_FN(VIO_D8), - GPIO_FN(VIO_D7), - GPIO_FN(VIO_D6), - GPIO_FN(VIO_D5), - GPIO_FN(VIO_D4), - GPIO_FN(VIO_D3), - GPIO_FN(VIO_D2), - GPIO_FN(VIO_D1), - GPIO_FN(VIO_D0), - GPIO_FN(VIO_CLK), - GPIO_FN(VIO_VD), - GPIO_FN(VIO_HD), - GPIO_FN(VIO_FLD), - GPIO_FN(VIO_CKO), - GPIO_FN(VIO_STEX), - GPIO_FN(VIO_STEM), - GPIO_FN(VIO_VD2), - GPIO_FN(VIO_HD2), - GPIO_FN(VIO_CLK2), + PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), + PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), /* LCDC */ - GPIO_FN(LCDD23), - GPIO_FN(LCDD22), - GPIO_FN(LCDD21), - GPIO_FN(LCDD20), - GPIO_FN(LCDD19), - GPIO_FN(LCDD18), - GPIO_FN(LCDD17), - GPIO_FN(LCDD16), - GPIO_FN(LCDD15), - GPIO_FN(LCDD14), - GPIO_FN(LCDD13), - GPIO_FN(LCDD12), - GPIO_FN(LCDD11), - GPIO_FN(LCDD10), - GPIO_FN(LCDD9), - GPIO_FN(LCDD8), - GPIO_FN(LCDD7), - GPIO_FN(LCDD6), - GPIO_FN(LCDD5), - GPIO_FN(LCDD4), - GPIO_FN(LCDD3), - GPIO_FN(LCDD2), - GPIO_FN(LCDD1), - GPIO_FN(LCDD0), - GPIO_FN(LCDLCLK), + PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), + PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), + PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), + PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), + PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), + PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), + PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), + PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), + PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), + PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), + PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), + PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), + PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), + PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), + PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), + PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), + PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), + PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), + PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), + PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), + PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), + PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), + PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), + PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), /* Main LCD */ - GPIO_FN(LCDDON), - GPIO_FN(LCDVCPWC), - GPIO_FN(LCDVEPWC), - GPIO_FN(LCDVSYN), + PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), /* Main LCD - RGB Mode */ - GPIO_FN(LCDDCK), - GPIO_FN(LCDHSYN), - GPIO_FN(LCDDISP), + PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), + PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), /* Main LCD - SYS Mode */ - GPIO_FN(LCDRS), - GPIO_FN(LCDCS), - GPIO_FN(LCDWR), - GPIO_FN(LCDRD), + PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), + PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), + PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), /* Sub LCD - SYS Mode */ - GPIO_FN(LCDDON2), - GPIO_FN(LCDVCPWC2), - GPIO_FN(LCDVEPWC2), - GPIO_FN(LCDVSYN2), - GPIO_FN(LCDCS2), + PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), /* BSC */ - GPIO_FN(IOIS16), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(BS), - GPIO_FN(CS6B_CE1B), - GPIO_FN(WAIT), - GPIO_FN(CS6A_CE2B), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), /* SBSC */ - GPIO_FN(HPD63), - GPIO_FN(HPD62), - GPIO_FN(HPD61), - GPIO_FN(HPD60), - GPIO_FN(HPD59), - GPIO_FN(HPD58), - GPIO_FN(HPD57), - GPIO_FN(HPD56), - GPIO_FN(HPD55), - GPIO_FN(HPD54), - GPIO_FN(HPD53), - GPIO_FN(HPD52), - GPIO_FN(HPD51), - GPIO_FN(HPD50), - GPIO_FN(HPD49), - GPIO_FN(HPD48), - GPIO_FN(HPDQM7), - GPIO_FN(HPDQM6), - GPIO_FN(HPDQM5), - GPIO_FN(HPDQM4), + PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), + PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), + PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), + PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), + PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), + PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), + PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), + PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), + PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), + PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), + PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), + PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), + PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), + PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), + PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), + PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), /* IRQ */ - GPIO_FN(IRQ0), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2), - GPIO_FN(IRQ3), - GPIO_FN(IRQ4), - GPIO_FN(IRQ5), - GPIO_FN(IRQ6), - GPIO_FN(IRQ7), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), /* SDHI */ - GPIO_FN(SDHICD), - GPIO_FN(SDHIWP), - GPIO_FN(SDHID3), - GPIO_FN(SDHID2), - GPIO_FN(SDHID1), - GPIO_FN(SDHID0), - GPIO_FN(SDHICMD), - GPIO_FN(SDHICLK), + PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), + PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), + PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), + PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), + PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), + PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), + PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), /* SIU - Port A */ - GPIO_FN(SIUAOLR), - GPIO_FN(SIUAOBT), - GPIO_FN(SIUAISLD), - GPIO_FN(SIUAILR), - GPIO_FN(SIUAIBT), - GPIO_FN(SIUAOSLD), - GPIO_FN(SIUMCKA), - GPIO_FN(SIUFCKA), + PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), + PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), /* SIU - Port B */ - GPIO_FN(SIUBOLR), - GPIO_FN(SIUBOBT), - GPIO_FN(SIUBISLD), - GPIO_FN(SIUBILR), - GPIO_FN(SIUBIBT), - GPIO_FN(SIUBOSLD), - GPIO_FN(SIUMCKB), - GPIO_FN(SIUFCKB), + PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), + PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), /* AUD */ - GPIO_FN(AUDSYNC), - GPIO_FN(AUDATA3), - GPIO_FN(AUDATA2), - GPIO_FN(AUDATA1), - GPIO_FN(AUDATA0), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), /* DMAC */ - GPIO_FN(DACK), - GPIO_FN(DREQ0), + PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), /* VOU */ - GPIO_FN(DV_CLKI), - GPIO_FN(DV_CLK), - GPIO_FN(DV_HSYNC), - GPIO_FN(DV_VSYNC), - GPIO_FN(DV_D15), - GPIO_FN(DV_D14), - GPIO_FN(DV_D13), - GPIO_FN(DV_D12), - GPIO_FN(DV_D11), - GPIO_FN(DV_D10), - GPIO_FN(DV_D9), - GPIO_FN(DV_D8), - GPIO_FN(DV_D7), - GPIO_FN(DV_D6), - GPIO_FN(DV_D5), - GPIO_FN(DV_D4), - GPIO_FN(DV_D3), - GPIO_FN(DV_D2), - GPIO_FN(DV_D1), - GPIO_FN(DV_D0), + PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), + PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), + PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), + PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), + PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), + PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), + PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), + PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), + PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), + PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), + PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), + PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), + PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), + PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), + PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), + PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), /* CPG */ - GPIO_FN(STATUS0), - GPIO_FN(PDSTATUS), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), /* SIOF0 */ - GPIO_FN(SIOF0_MCK), - GPIO_FN(SIOF0_SCK), - GPIO_FN(SIOF0_SYNC), - GPIO_FN(SIOF0_SS1), - GPIO_FN(SIOF0_SS2), - GPIO_FN(SIOF0_TXD), - GPIO_FN(SIOF0_RXD), + PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), /* SIOF1 */ - GPIO_FN(SIOF1_MCK), - GPIO_FN(SIOF1_SCK), - GPIO_FN(SIOF1_SYNC), - GPIO_FN(SIOF1_SS1), - GPIO_FN(SIOF1_SS2), - GPIO_FN(SIOF1_TXD), - GPIO_FN(SIOF1_RXD), + PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), /* SIM */ - GPIO_FN(SIM_D), - GPIO_FN(SIM_CLK), - GPIO_FN(SIM_RST), + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), /* TSIF */ - GPIO_FN(TS_SDAT), - GPIO_FN(TS_SCK), - GPIO_FN(TS_SDEN), - GPIO_FN(TS_SPSYNC), + PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), + PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), + PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), /* IRDA */ - GPIO_FN(IRDA_IN), - GPIO_FN(IRDA_OUT), + PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), /* TPU */ - GPIO_FN(TPUTO), + PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), /* FLCTL */ - GPIO_FN(FCE), - GPIO_FN(NAF7), - GPIO_FN(NAF6), - GPIO_FN(NAF5), - GPIO_FN(NAF4), - GPIO_FN(NAF3), - GPIO_FN(NAF2), - GPIO_FN(NAF1), - GPIO_FN(NAF0), - GPIO_FN(FCDE), - GPIO_FN(FOE), - GPIO_FN(FSC), - GPIO_FN(FWE), - GPIO_FN(FRB), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), /* KEYSC */ - GPIO_FN(KEYIN0), - GPIO_FN(KEYIN1), - GPIO_FN(KEYIN2), - GPIO_FN(KEYIN3), - GPIO_FN(KEYIN4), - GPIO_FN(KEYOUT0), - GPIO_FN(KEYOUT1), - GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), - GPIO_FN(KEYOUT4_IN6), - GPIO_FN(KEYOUT5_IN5), + PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, @@ -1664,7 +1660,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1760,19 +1756,21 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7722_pinmux_info = { +struct sh_pfc_soc_info sh7722_pinmux_info = { .name = "sh7722_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_KEYOUT5_IN5, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7723.c index 07ad1d8d6c8b..609673d3d70e 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7723.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7723.c @@ -350,7 +350,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), @@ -923,7 +923,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1139,383 +1139,379 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* SCIF0 */ - GPIO_FN(SCIF0_PTT_TXD), - GPIO_FN(SCIF0_PTT_RXD), - GPIO_FN(SCIF0_PTT_SCK), - GPIO_FN(SCIF0_PTU_TXD), - GPIO_FN(SCIF0_PTU_RXD), - GPIO_FN(SCIF0_PTU_SCK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), /* SCIF1 */ - GPIO_FN(SCIF1_PTS_TXD), - GPIO_FN(SCIF1_PTS_RXD), - GPIO_FN(SCIF1_PTS_SCK), - GPIO_FN(SCIF1_PTV_TXD), - GPIO_FN(SCIF1_PTV_RXD), - GPIO_FN(SCIF1_PTV_SCK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), /* SCIF2 */ - GPIO_FN(SCIF2_PTT_TXD), - GPIO_FN(SCIF2_PTT_RXD), - GPIO_FN(SCIF2_PTT_SCK), - GPIO_FN(SCIF2_PTU_TXD), - GPIO_FN(SCIF2_PTU_RXD), - GPIO_FN(SCIF2_PTU_SCK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), /* SCIF3 */ - GPIO_FN(SCIF3_PTS_TXD), - GPIO_FN(SCIF3_PTS_RXD), - GPIO_FN(SCIF3_PTS_SCK), - GPIO_FN(SCIF3_PTS_RTS), - GPIO_FN(SCIF3_PTS_CTS), - GPIO_FN(SCIF3_PTV_TXD), - GPIO_FN(SCIF3_PTV_RXD), - GPIO_FN(SCIF3_PTV_SCK), - GPIO_FN(SCIF3_PTV_RTS), - GPIO_FN(SCIF3_PTV_CTS), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), /* SCIF4 */ - GPIO_FN(SCIF4_PTE_TXD), - GPIO_FN(SCIF4_PTE_RXD), - GPIO_FN(SCIF4_PTE_SCK), - GPIO_FN(SCIF4_PTN_TXD), - GPIO_FN(SCIF4_PTN_RXD), - GPIO_FN(SCIF4_PTN_SCK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), /* SCIF5 */ - GPIO_FN(SCIF5_PTE_TXD), - GPIO_FN(SCIF5_PTE_RXD), - GPIO_FN(SCIF5_PTE_SCK), - GPIO_FN(SCIF5_PTN_TXD), - GPIO_FN(SCIF5_PTN_RXD), - GPIO_FN(SCIF5_PTN_SCK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), /* CEU */ - GPIO_FN(VIO_D15), - GPIO_FN(VIO_D14), - GPIO_FN(VIO_D13), - GPIO_FN(VIO_D12), - GPIO_FN(VIO_D11), - GPIO_FN(VIO_D10), - GPIO_FN(VIO_D9), - GPIO_FN(VIO_D8), - GPIO_FN(VIO_D7), - GPIO_FN(VIO_D6), - GPIO_FN(VIO_D5), - GPIO_FN(VIO_D4), - GPIO_FN(VIO_D3), - GPIO_FN(VIO_D2), - GPIO_FN(VIO_D1), - GPIO_FN(VIO_D0), - GPIO_FN(VIO_CLK1), - GPIO_FN(VIO_VD1), - GPIO_FN(VIO_HD1), - GPIO_FN(VIO_FLD), - GPIO_FN(VIO_CKO), - GPIO_FN(VIO_VD2), - GPIO_FN(VIO_HD2), - GPIO_FN(VIO_CLK2), + PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), /* LCDC */ - GPIO_FN(LCDD23), - GPIO_FN(LCDD22), - GPIO_FN(LCDD21), - GPIO_FN(LCDD20), - GPIO_FN(LCDD19), - GPIO_FN(LCDD18), - GPIO_FN(LCDD17), - GPIO_FN(LCDD16), - GPIO_FN(LCDD15), - GPIO_FN(LCDD14), - GPIO_FN(LCDD13), - GPIO_FN(LCDD12), - GPIO_FN(LCDD11), - GPIO_FN(LCDD10), - GPIO_FN(LCDD9), - GPIO_FN(LCDD8), - GPIO_FN(LCDD7), - GPIO_FN(LCDD6), - GPIO_FN(LCDD5), - GPIO_FN(LCDD4), - GPIO_FN(LCDD3), - GPIO_FN(LCDD2), - GPIO_FN(LCDD1), - GPIO_FN(LCDD0), - GPIO_FN(LCDLCLK_PTR), - GPIO_FN(LCDLCLK_PTW), + PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), + PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), + PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), + PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), + PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), + PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), + PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), + PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), + PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), + PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), + PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), + PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), + PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), + PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), + PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), + PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), + PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), + PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), + PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), + PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), + PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), + PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), + PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), + PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), /* Main LCD */ - GPIO_FN(LCDDON), - GPIO_FN(LCDVCPWC), - GPIO_FN(LCDVEPWC), - GPIO_FN(LCDVSYN), + PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), /* Main LCD - RGB Mode */ - GPIO_FN(LCDDCK), - GPIO_FN(LCDHSYN), - GPIO_FN(LCDDISP), + PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), + PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), /* Main LCD - SYS Mode */ - GPIO_FN(LCDRS), - GPIO_FN(LCDCS), - GPIO_FN(LCDWR), - GPIO_FN(LCDRD), + PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), + PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), + PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), /* IRQ */ - GPIO_FN(IRQ0), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2), - GPIO_FN(IRQ3), - GPIO_FN(IRQ4), - GPIO_FN(IRQ5), - GPIO_FN(IRQ6), - GPIO_FN(IRQ7), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), /* AUD */ - GPIO_FN(AUDCK), - GPIO_FN(AUDSYNC), - GPIO_FN(AUDATA3), - GPIO_FN(AUDATA2), - GPIO_FN(AUDATA1), - GPIO_FN(AUDATA0), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), /* SDHI0 (PTD) */ - GPIO_FN(SDHI0CD_PTD), - GPIO_FN(SDHI0WP_PTD), - GPIO_FN(SDHI0D3_PTD), - GPIO_FN(SDHI0D2_PTD), - GPIO_FN(SDHI0D1_PTD), - GPIO_FN(SDHI0D0_PTD), - GPIO_FN(SDHI0CMD_PTD), - GPIO_FN(SDHI0CLK_PTD), + PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), /* SDHI0 (PTS) */ - GPIO_FN(SDHI0CD_PTS), - GPIO_FN(SDHI0WP_PTS), - GPIO_FN(SDHI0D3_PTS), - GPIO_FN(SDHI0D2_PTS), - GPIO_FN(SDHI0D1_PTS), - GPIO_FN(SDHI0D0_PTS), - GPIO_FN(SDHI0CMD_PTS), - GPIO_FN(SDHI0CLK_PTS), + PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), /* SDHI1 */ - GPIO_FN(SDHI1CD), - GPIO_FN(SDHI1WP), - GPIO_FN(SDHI1D3), - GPIO_FN(SDHI1D2), - GPIO_FN(SDHI1D1), - GPIO_FN(SDHI1D0), - GPIO_FN(SDHI1CMD), - GPIO_FN(SDHI1CLK), + PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), /* SIUA */ - GPIO_FN(SIUAFCK), - GPIO_FN(SIUAILR), - GPIO_FN(SIUAIBT), - GPIO_FN(SIUAISLD), - GPIO_FN(SIUAOLR), - GPIO_FN(SIUAOBT), - GPIO_FN(SIUAOSLD), - GPIO_FN(SIUAMCK), - GPIO_FN(SIUAISPD), - GPIO_FN(SIUAOSPD), + PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK), /* SIUB */ - GPIO_FN(SIUBFCK), - GPIO_FN(SIUBILR), - GPIO_FN(SIUBIBT), - GPIO_FN(SIUBISLD), - GPIO_FN(SIUBOLR), - GPIO_FN(SIUBOBT), - GPIO_FN(SIUBOSLD), - GPIO_FN(SIUBMCK), + PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), /* IRDA */ - GPIO_FN(IRDA_IN), - GPIO_FN(IRDA_OUT), + PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), /* VOU */ - GPIO_FN(DV_CLKI), - GPIO_FN(DV_CLK), - GPIO_FN(DV_HSYNC), - GPIO_FN(DV_VSYNC), - GPIO_FN(DV_D15), - GPIO_FN(DV_D14), - GPIO_FN(DV_D13), - GPIO_FN(DV_D12), - GPIO_FN(DV_D11), - GPIO_FN(DV_D10), - GPIO_FN(DV_D9), - GPIO_FN(DV_D8), - GPIO_FN(DV_D7), - GPIO_FN(DV_D6), - GPIO_FN(DV_D5), - GPIO_FN(DV_D4), - GPIO_FN(DV_D3), - GPIO_FN(DV_D2), - GPIO_FN(DV_D1), - GPIO_FN(DV_D0), + PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), + PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), + PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), + PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), + PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), + PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), + PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), + PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), + PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), + PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), + PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), + PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), + PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), + PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), + PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), + PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), /* KEYSC */ - GPIO_FN(KEYIN0), - GPIO_FN(KEYIN1), - GPIO_FN(KEYIN2), - GPIO_FN(KEYIN3), - GPIO_FN(KEYIN4), - GPIO_FN(KEYOUT0), - GPIO_FN(KEYOUT1), - GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), - GPIO_FN(KEYOUT4_IN6), - GPIO_FN(KEYOUT5_IN5), + PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), /* MSIOF0 (PTF) */ - GPIO_FN(MSIOF0_PTF_TXD), - GPIO_FN(MSIOF0_PTF_RXD), - GPIO_FN(MSIOF0_PTF_MCK), - GPIO_FN(MSIOF0_PTF_TSYNC), - GPIO_FN(MSIOF0_PTF_TSCK), - GPIO_FN(MSIOF0_PTF_RSYNC), - GPIO_FN(MSIOF0_PTF_RSCK), - GPIO_FN(MSIOF0_PTF_SS1), - GPIO_FN(MSIOF0_PTF_SS2), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), /* MSIOF0 (PTT+PTX) */ - GPIO_FN(MSIOF0_PTT_TXD), - GPIO_FN(MSIOF0_PTT_RXD), - GPIO_FN(MSIOF0_PTX_MCK), - GPIO_FN(MSIOF0_PTT_TSYNC), - GPIO_FN(MSIOF0_PTT_TSCK), - GPIO_FN(MSIOF0_PTT_RSYNC), - GPIO_FN(MSIOF0_PTT_RSCK), - GPIO_FN(MSIOF0_PTT_SS1), - GPIO_FN(MSIOF0_PTT_SS2), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), /* MSIOF1 */ - GPIO_FN(MSIOF1_TXD), - GPIO_FN(MSIOF1_RXD), - GPIO_FN(MSIOF1_MCK), - GPIO_FN(MSIOF1_TSYNC), - GPIO_FN(MSIOF1_TSCK), - GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_RSCK), - GPIO_FN(MSIOF1_SS1), - GPIO_FN(MSIOF1_SS2), + PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), /* TSIF */ - GPIO_FN(TS0_SDAT), - GPIO_FN(TS0_SCK), - GPIO_FN(TS0_SDEN), - GPIO_FN(TS0_SPSYNC), + PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), /* FLCTL */ - GPIO_FN(FCE), - GPIO_FN(NAF7), - GPIO_FN(NAF6), - GPIO_FN(NAF5), - GPIO_FN(NAF4), - GPIO_FN(NAF3), - GPIO_FN(NAF2), - GPIO_FN(NAF1), - GPIO_FN(NAF0), - GPIO_FN(FCDE), - GPIO_FN(FOE), - GPIO_FN(FSC), - GPIO_FN(FWE), - GPIO_FN(FRB), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), /* DMAC */ - GPIO_FN(DACK1), - GPIO_FN(DREQ1), - GPIO_FN(DACK0), - GPIO_FN(DREQ0), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), /* ADC */ - GPIO_FN(AN3), - GPIO_FN(AN2), - GPIO_FN(AN1), - GPIO_FN(AN0), - GPIO_FN(ADTRG), + PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), + PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), + PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), + PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), /* CPG */ - GPIO_FN(STATUS0), - GPIO_FN(PDSTATUS), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), /* TPU */ - GPIO_FN(TPUTO0), - GPIO_FN(TPUTO1), - GPIO_FN(TPUTO2), - GPIO_FN(TPUTO3), + PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), /* BSC */ - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(IOIS16), - GPIO_FN(WAIT), - GPIO_FN(BS), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(CS6B_CE1B), - GPIO_FN(CS6A_CE2B), - GPIO_FN(CS5B_CE1A), - GPIO_FN(CS5A_CE2A), - GPIO_FN(WE3_ICIOWR), - GPIO_FN(WE2_ICIORD), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), + PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), + PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), /* ATAPI */ - GPIO_FN(IDED15), - GPIO_FN(IDED14), - GPIO_FN(IDED13), - GPIO_FN(IDED12), - GPIO_FN(IDED11), - GPIO_FN(IDED10), - GPIO_FN(IDED9), - GPIO_FN(IDED8), - GPIO_FN(IDED7), - GPIO_FN(IDED6), - GPIO_FN(IDED5), - GPIO_FN(IDED4), - GPIO_FN(IDED3), - GPIO_FN(IDED2), - GPIO_FN(IDED1), - GPIO_FN(IDED0), - GPIO_FN(DIRECTION), - GPIO_FN(EXBUF_ENB), - GPIO_FN(IDERST), - GPIO_FN(IODACK), - GPIO_FN(IODREQ), - GPIO_FN(IDEIORDY), - GPIO_FN(IDEINT), - GPIO_FN(IDEIOWR), - GPIO_FN(IDEIORD), - GPIO_FN(IDECS1), - GPIO_FN(IDECS0), - GPIO_FN(IDEA2), - GPIO_FN(IDEA1), - GPIO_FN(IDEA0), + PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), + PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), + PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), + PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), + PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), + PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), + PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), + PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), + PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), + PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), + PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), + PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), + PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), + PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), + PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), + PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), + PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), + PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), + PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), + PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), + PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), + PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), + PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), + PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), + PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), + PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), + PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), + PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, 0, PTA7_IN, PTA6_FN, PTA6_OUT, 0, PTA6_IN, @@ -1789,7 +1785,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -1885,18 +1881,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7723_pinmux_info = { +struct sh_pfc_soc_info sh7723_pinmux_info = { .name = "sh7723_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_IDEA0, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7724.c index 35e551609805..233fbf750b39 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7724.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7724.c @@ -572,7 +572,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), @@ -1192,7 +1192,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1418,376 +1418,372 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* BSC */ - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(D15), - GPIO_FN(D14), - GPIO_FN(D13), - GPIO_FN(D12), - GPIO_FN(D11), - GPIO_FN(D10), - GPIO_FN(D9), - GPIO_FN(D8), - GPIO_FN(D7), - GPIO_FN(D6), - GPIO_FN(D5), - GPIO_FN(D4), - GPIO_FN(D3), - GPIO_FN(D2), - GPIO_FN(D1), - GPIO_FN(D0), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(CS6B_CE1B), - GPIO_FN(CS6A_CE2B), - GPIO_FN(CS5B_CE1A), - GPIO_FN(CS5A_CE2A), - GPIO_FN(WE3_ICIOWR), - GPIO_FN(WE2_ICIORD), - GPIO_FN(IOIS16), - GPIO_FN(WAIT), - GPIO_FN(BS), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), + PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), + PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), /* KEYSC */ - GPIO_FN(KEYOUT5_IN5), - GPIO_FN(KEYOUT4_IN6), - GPIO_FN(KEYIN4), - GPIO_FN(KEYIN3), - GPIO_FN(KEYIN2), - GPIO_FN(KEYIN1), - GPIO_FN(KEYIN0), - GPIO_FN(KEYOUT3), - GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT1), - GPIO_FN(KEYOUT0), + PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), /* ATAPI */ - GPIO_FN(IDED15), - GPIO_FN(IDED14), - GPIO_FN(IDED13), - GPIO_FN(IDED12), - GPIO_FN(IDED11), - GPIO_FN(IDED10), - GPIO_FN(IDED9), - GPIO_FN(IDED8), - GPIO_FN(IDED7), - GPIO_FN(IDED6), - GPIO_FN(IDED5), - GPIO_FN(IDED4), - GPIO_FN(IDED3), - GPIO_FN(IDED2), - GPIO_FN(IDED1), - GPIO_FN(IDED0), - GPIO_FN(IDEA2), - GPIO_FN(IDEA1), - GPIO_FN(IDEA0), - GPIO_FN(IDEIOWR), - GPIO_FN(IODREQ), - GPIO_FN(IDECS0), - GPIO_FN(IDECS1), - GPIO_FN(IDEIORD), - GPIO_FN(DIRECTION), - GPIO_FN(EXBUF_ENB), - GPIO_FN(IDERST), - GPIO_FN(IODACK), - GPIO_FN(IDEINT), - GPIO_FN(IDEIORDY), + PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), + PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), + PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), + PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), + PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), + PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), + PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), + PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), + PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), + PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), + PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), + PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), + PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), + PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), + PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), + PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), + PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), + PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), + PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), + PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), + PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), + PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), + PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), + PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), + PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), + PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), + PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), + PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), /* TPU */ - GPIO_FN(TPUTO3), - GPIO_FN(TPUTO2), - GPIO_FN(TPUTO1), - GPIO_FN(TPUTO0), - GPIO_FN(TPUTI3), - GPIO_FN(TPUTI2), + PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), + PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), + PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), /* LCDC */ - GPIO_FN(LCDD23), - GPIO_FN(LCDD22), - GPIO_FN(LCDD21), - GPIO_FN(LCDD20), - GPIO_FN(LCDD19), - GPIO_FN(LCDD18), - GPIO_FN(LCDD17), - GPIO_FN(LCDD16), - GPIO_FN(LCDD15), - GPIO_FN(LCDD14), - GPIO_FN(LCDD13), - GPIO_FN(LCDD12), - GPIO_FN(LCDD11), - GPIO_FN(LCDD10), - GPIO_FN(LCDD9), - GPIO_FN(LCDD8), - GPIO_FN(LCDD7), - GPIO_FN(LCDD6), - GPIO_FN(LCDD5), - GPIO_FN(LCDD4), - GPIO_FN(LCDD3), - GPIO_FN(LCDD2), - GPIO_FN(LCDD1), - GPIO_FN(LCDD0), - GPIO_FN(LCDVSYN), - GPIO_FN(LCDDISP), - GPIO_FN(LCDRS), - GPIO_FN(LCDHSYN), - GPIO_FN(LCDCS), - GPIO_FN(LCDDON), - GPIO_FN(LCDDCK), - GPIO_FN(LCDWR), - GPIO_FN(LCDVEPWC), - GPIO_FN(LCDVCPWC), - GPIO_FN(LCDRD), - GPIO_FN(LCDLCLK), + PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), + PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), + PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), + PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), + PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), + PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), + PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), + PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), + PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), + PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), + PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), + PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), + PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), + PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), + PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), + PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), + PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), + PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), + PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), + PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), + PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), + PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), + PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), + PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), + PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), + PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), + PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), + PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), /* SCIF0 */ - GPIO_FN(SCIF0_TXD), - GPIO_FN(SCIF0_RXD), - GPIO_FN(SCIF0_SCK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), /* SCIF1 */ - GPIO_FN(SCIF1_SCK), - GPIO_FN(SCIF1_RXD), - GPIO_FN(SCIF1_TXD), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), /* SCIF2 */ - GPIO_FN(SCIF2_L_TXD), - GPIO_FN(SCIF2_L_SCK), - GPIO_FN(SCIF2_L_RXD), - GPIO_FN(SCIF2_V_TXD), - GPIO_FN(SCIF2_V_SCK), - GPIO_FN(SCIF2_V_RXD), + PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), /* SCIF3 */ - GPIO_FN(SCIF3_V_SCK), - GPIO_FN(SCIF3_V_RXD), - GPIO_FN(SCIF3_V_TXD), - GPIO_FN(SCIF3_V_CTS), - GPIO_FN(SCIF3_V_RTS), - GPIO_FN(SCIF3_I_SCK), - GPIO_FN(SCIF3_I_RXD), - GPIO_FN(SCIF3_I_TXD), - GPIO_FN(SCIF3_I_CTS), - GPIO_FN(SCIF3_I_RTS), + PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), /* SCIF4 */ - GPIO_FN(SCIF4_SCK), - GPIO_FN(SCIF4_RXD), - GPIO_FN(SCIF4_TXD), + PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), /* SCIF5 */ - GPIO_FN(SCIF5_SCK), - GPIO_FN(SCIF5_RXD), - GPIO_FN(SCIF5_TXD), + PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), /* FSI */ - GPIO_FN(FSIMCKB), - GPIO_FN(FSIMCKA), - GPIO_FN(FSIOASD), - GPIO_FN(FSIIABCK), - GPIO_FN(FSIIALRCK), - GPIO_FN(FSIOABCK), - GPIO_FN(FSIOALRCK), - GPIO_FN(CLKAUDIOAO), - GPIO_FN(FSIIBSD), - GPIO_FN(FSIOBSD), - GPIO_FN(FSIIBBCK), - GPIO_FN(FSIIBLRCK), - GPIO_FN(FSIOBBCK), - GPIO_FN(FSIOBLRCK), - GPIO_FN(CLKAUDIOBO), - GPIO_FN(FSIIASD), + PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), + PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), + PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), + PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), + PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), + PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), + PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), + PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), + PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), + PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), + PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), /* AUD */ - GPIO_FN(AUDCK), - GPIO_FN(AUDSYNC), - GPIO_FN(AUDATA3), - GPIO_FN(AUDATA2), - GPIO_FN(AUDATA1), - GPIO_FN(AUDATA0), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), /* VIO */ - GPIO_FN(VIO_CKO), + PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), /* VIO0 */ - GPIO_FN(VIO0_D15), - GPIO_FN(VIO0_D14), - GPIO_FN(VIO0_D13), - GPIO_FN(VIO0_D12), - GPIO_FN(VIO0_D11), - GPIO_FN(VIO0_D10), - GPIO_FN(VIO0_D9), - GPIO_FN(VIO0_D8), - GPIO_FN(VIO0_D7), - GPIO_FN(VIO0_D6), - GPIO_FN(VIO0_D5), - GPIO_FN(VIO0_D4), - GPIO_FN(VIO0_D3), - GPIO_FN(VIO0_D2), - GPIO_FN(VIO0_D1), - GPIO_FN(VIO0_D0), - GPIO_FN(VIO0_VD), - GPIO_FN(VIO0_CLK), - GPIO_FN(VIO0_FLD), - GPIO_FN(VIO0_HD), + PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), /* VIO1 */ - GPIO_FN(VIO1_D7), - GPIO_FN(VIO1_D6), - GPIO_FN(VIO1_D5), - GPIO_FN(VIO1_D4), - GPIO_FN(VIO1_D3), - GPIO_FN(VIO1_D2), - GPIO_FN(VIO1_D1), - GPIO_FN(VIO1_D0), - GPIO_FN(VIO1_FLD), - GPIO_FN(VIO1_HD), - GPIO_FN(VIO1_VD), - GPIO_FN(VIO1_CLK), + PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), + PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), /* Eth */ - GPIO_FN(RMII_RXD0), - GPIO_FN(RMII_RXD1), - GPIO_FN(RMII_TXD0), - GPIO_FN(RMII_TXD1), - GPIO_FN(RMII_REF_CLK), - GPIO_FN(RMII_TX_EN), - GPIO_FN(RMII_RX_ER), - GPIO_FN(RMII_CRS_DV), - GPIO_FN(LNKSTA), - GPIO_FN(MDIO), - GPIO_FN(MDC), + PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), + PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), + PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), + PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), + PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), /* System */ - GPIO_FN(PDSTATUS), - GPIO_FN(STATUS2), - GPIO_FN(STATUS0), + PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), /* VOU */ - GPIO_FN(DV_D15), - GPIO_FN(DV_D14), - GPIO_FN(DV_D13), - GPIO_FN(DV_D12), - GPIO_FN(DV_D11), - GPIO_FN(DV_D10), - GPIO_FN(DV_D9), - GPIO_FN(DV_D8), - GPIO_FN(DV_D7), - GPIO_FN(DV_D6), - GPIO_FN(DV_D5), - GPIO_FN(DV_D4), - GPIO_FN(DV_D3), - GPIO_FN(DV_D2), - GPIO_FN(DV_D1), - GPIO_FN(DV_D0), - GPIO_FN(DV_CLKI), - GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), - GPIO_FN(DV_HSYNC), + PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), + PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), + PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), + PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), + PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), + PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), + PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), + PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), + PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), + PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), + PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), + PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), + PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), + PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), + PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), + PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), /* MSIOF0 */ - GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_TXD), - GPIO_FN(MSIOF0_MCK), - GPIO_FN(MSIOF0_TSCK), - GPIO_FN(MSIOF0_SS1), - GPIO_FN(MSIOF0_SS2), - GPIO_FN(MSIOF0_TSYNC), - GPIO_FN(MSIOF0_RSCK), - GPIO_FN(MSIOF0_RSYNC), + PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), /* MSIOF1 */ - GPIO_FN(MSIOF1_RXD), - GPIO_FN(MSIOF1_TXD), - GPIO_FN(MSIOF1_MCK), - GPIO_FN(MSIOF1_TSCK), - GPIO_FN(MSIOF1_SS1), - GPIO_FN(MSIOF1_SS2), - GPIO_FN(MSIOF1_TSYNC), - GPIO_FN(MSIOF1_RSCK), - GPIO_FN(MSIOF1_RSYNC), + PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), /* DMAC */ - GPIO_FN(DMAC_DACK0), - GPIO_FN(DMAC_DREQ0), - GPIO_FN(DMAC_DACK1), - GPIO_FN(DMAC_DREQ1), + PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), /* SDHI0 */ - GPIO_FN(SDHI0CD), - GPIO_FN(SDHI0WP), - GPIO_FN(SDHI0CMD), - GPIO_FN(SDHI0CLK), - GPIO_FN(SDHI0D3), - GPIO_FN(SDHI0D2), - GPIO_FN(SDHI0D1), - GPIO_FN(SDHI0D0), + PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), /* SDHI1 */ - GPIO_FN(SDHI1CD), - GPIO_FN(SDHI1WP), - GPIO_FN(SDHI1CMD), - GPIO_FN(SDHI1CLK), - GPIO_FN(SDHI1D3), - GPIO_FN(SDHI1D2), - GPIO_FN(SDHI1D1), - GPIO_FN(SDHI1D0), + PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), /* MMC */ - GPIO_FN(MMC_D7), - GPIO_FN(MMC_D6), - GPIO_FN(MMC_D5), - GPIO_FN(MMC_D4), - GPIO_FN(MMC_D3), - GPIO_FN(MMC_D2), - GPIO_FN(MMC_D1), - GPIO_FN(MMC_D0), - GPIO_FN(MMC_CLK), - GPIO_FN(MMC_CMD), + PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), + PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), /* IrDA */ - GPIO_FN(IRDA_OUT), - GPIO_FN(IRDA_IN), + PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), /* TSIF */ - GPIO_FN(TSIF_TS0_SDAT), - GPIO_FN(TSIF_TS0_SCK), - GPIO_FN(TSIF_TS0_SDEN), - GPIO_FN(TSIF_TS0_SPSYNC), + PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), + PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), + PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), /* IRQ */ - GPIO_FN(INTC_IRQ7), - GPIO_FN(INTC_IRQ6), - GPIO_FN(INTC_IRQ5), - GPIO_FN(INTC_IRQ4), - GPIO_FN(INTC_IRQ3), - GPIO_FN(INTC_IRQ2), - GPIO_FN(INTC_IRQ1), - GPIO_FN(INTC_IRQ0), + PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, @@ -2111,7 +2107,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2207,18 +2203,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7724_pinmux_info = { +struct sh_pfc_soc_info sh7724_pinmux_info = { .name = "sh7724_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_INTC_IRQ0, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7734.c index 2fd5b7d4cb94..23d76d262c32 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7734.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7734.c @@ -14,6 +14,11 @@ #include "sh_pfc.h" +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + #define CPU_32_PORT5(fn, pfx, sfx) \ PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ @@ -24,11 +29,11 @@ /* GPSR0 - GPSR5 */ #define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_32(fn, pfx##_0_, sfx), \ - PORT_32(fn, pfx##_1_, sfx), \ - PORT_32(fn, pfx##_2_, sfx), \ - PORT_32(fn, pfx##_3_, sfx), \ - PORT_32(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ CPU_32_PORT5(fn, pfx##_5_, sfx) #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) @@ -42,8 +47,20 @@ #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) -#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ @@ -592,7 +609,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), @@ -1367,13 +1384,9 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO_GP_ALL(), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), @@ -1652,7 +1665,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { GP_0_31_FN, FN_IP2_2_0, GP_0_30_FN, FN_IP1_31_29, @@ -2421,7 +2434,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { /* GPIO 0 - 5*/ { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, @@ -2438,20 +2451,22 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7734_pinmux_info = { +struct sh_pfc_soc_info sh7734_pinmux_info = { .name = "sh7734_pfc", .unlock_reg = 0xFFFC0000, + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_ST_CLKOUT, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7757.c index e074230e6243..5ed74cd0ba99 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7757.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7757.c @@ -526,7 +526,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PTA GPIO */ PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), @@ -1114,7 +1114,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PTA */ PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), @@ -1370,363 +1370,359 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* PTA (mobule: LBSC, RGMII) */ - GPIO_FN(BS), - GPIO_FN(RDWR), - GPIO_FN(WE1), - GPIO_FN(RDY), - GPIO_FN(ET0_MDC), - GPIO_FN(ET0_MDIO), - GPIO_FN(ET1_MDC), - GPIO_FN(ET1_MDIO), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), + PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), /* PTB (mobule: INTC, ONFI, TMU) */ - GPIO_FN(IRQ15), - GPIO_FN(IRQ14), - GPIO_FN(IRQ13), - GPIO_FN(IRQ12), - GPIO_FN(IRQ11), - GPIO_FN(IRQ10), - GPIO_FN(IRQ9), - GPIO_FN(IRQ8), - GPIO_FN(ON_NRE), - GPIO_FN(ON_NWE), - GPIO_FN(ON_NWP), - GPIO_FN(ON_NCE0), - GPIO_FN(ON_R_B0), - GPIO_FN(ON_ALE), - GPIO_FN(ON_CLE), - GPIO_FN(TCLK), + PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), + PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), + PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), + PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), + PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), + PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), + PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), + PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), + PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), + PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), + PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), + PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), /* PTC (mobule: IRQ, PWMU) */ - GPIO_FN(IRQ7), - GPIO_FN(IRQ6), - GPIO_FN(IRQ5), - GPIO_FN(IRQ4), - GPIO_FN(IRQ3), - GPIO_FN(IRQ2), - GPIO_FN(IRQ1), - GPIO_FN(IRQ0), - GPIO_FN(PWMU0), - GPIO_FN(PWMU1), - GPIO_FN(PWMU2), - GPIO_FN(PWMU3), - GPIO_FN(PWMU4), - GPIO_FN(PWMU5), + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), + PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), + PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), + PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), + PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), /* PTD (mobule: SPI0, DMAC) */ - GPIO_FN(SP0_MOSI), - GPIO_FN(SP0_MISO), - GPIO_FN(SP0_SCK), - GPIO_FN(SP0_SCK_FB), - GPIO_FN(SP0_SS0), - GPIO_FN(SP0_SS1), - GPIO_FN(SP0_SS2), - GPIO_FN(SP0_SS3), - GPIO_FN(DREQ0), - GPIO_FN(DACK0), - GPIO_FN(TEND0), + PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), /* PTE (mobule: RMII) */ - GPIO_FN(RMII0_CRS_DV), - GPIO_FN(RMII0_TXD1), - GPIO_FN(RMII0_TXD0), - GPIO_FN(RMII0_TXEN), - GPIO_FN(RMII0_REFCLK), - GPIO_FN(RMII0_RXD1), - GPIO_FN(RMII0_RXD0), - GPIO_FN(RMII0_RX_ER), + PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), /* PTF (mobule: RMII, SerMux) */ - GPIO_FN(RMII1_CRS_DV), - GPIO_FN(RMII1_TXD1), - GPIO_FN(RMII1_TXD0), - GPIO_FN(RMII1_TXEN), - GPIO_FN(RMII1_REFCLK), - GPIO_FN(RMII1_RXD1), - GPIO_FN(RMII1_RXD0), - GPIO_FN(RMII1_RX_ER), - GPIO_FN(RAC_RI), + PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ - GPIO_FN(BOOTFMS), - GPIO_FN(BOOTWP), - GPIO_FN(A25), - GPIO_FN(A24), - GPIO_FN(SERIRQ), - GPIO_FN(WDTOVF), - GPIO_FN(LPCPD), - GPIO_FN(LDRQ), - GPIO_FN(MMCCLK), - GPIO_FN(MMCCMD), + PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), + PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), + PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), + PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), + PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ - GPIO_FN(SP1_MOSI), - GPIO_FN(SP1_MISO), - GPIO_FN(SP1_SCK), - GPIO_FN(SP1_SCK_FB), - GPIO_FN(SP1_SS0), - GPIO_FN(SP1_SS1), - GPIO_FN(WP), - GPIO_FN(FMS0), - GPIO_FN(TEND1), - GPIO_FN(DREQ1), - GPIO_FN(DACK1), - GPIO_FN(ADTRG1), - GPIO_FN(ADTRG0), + PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), + PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_WP, WP_MARK), + PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), /* PTI (mobule: LBSC, SDHI) */ - GPIO_FN(D15), - GPIO_FN(D14), - GPIO_FN(D13), - GPIO_FN(D12), - GPIO_FN(D11), - GPIO_FN(D10), - GPIO_FN(D9), - GPIO_FN(D8), - GPIO_FN(SD_WP), - GPIO_FN(SD_CD), - GPIO_FN(SD_CLK), - GPIO_FN(SD_CMD), - GPIO_FN(SD_D3), - GPIO_FN(SD_D2), - GPIO_FN(SD_D1), - GPIO_FN(SD_D0), + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), + PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), + PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), + PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), + PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), + PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), + PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), /* PTJ (mobule: SCIF234, SERMUX) */ - GPIO_FN(RTS3), - GPIO_FN(CTS3), - GPIO_FN(TXD3), - GPIO_FN(RXD3), - GPIO_FN(RTS4), - GPIO_FN(RXD4), - GPIO_FN(TXD4), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), /* PTK (mobule: SERMUX, LBSC, SCIF) */ - GPIO_FN(COM2_TXD), - GPIO_FN(COM2_RXD), - GPIO_FN(COM2_RTS), - GPIO_FN(COM2_CTS), - GPIO_FN(COM2_DTR), - GPIO_FN(COM2_DSR), - GPIO_FN(COM2_DCD), - GPIO_FN(CLKOUT), - GPIO_FN(SCK2), - GPIO_FN(SCK4), - GPIO_FN(SCK3), + PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), + PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), + PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ - GPIO_FN(RAC_RXD), - GPIO_FN(RAC_RTS), - GPIO_FN(RAC_CTS), - GPIO_FN(RAC_DTR), - GPIO_FN(RAC_DSR), - GPIO_FN(RAC_DCD), - GPIO_FN(RAC_TXD), - GPIO_FN(RXD2), - GPIO_FN(CS5), - GPIO_FN(CS6), - GPIO_FN(AUDSYNC), - GPIO_FN(AUDCK), - GPIO_FN(TXD2), + PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), + PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), + PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), + PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), /* PTM (mobule: LBSC, IIC) */ - GPIO_FN(CS4), - GPIO_FN(RD), - GPIO_FN(WE0), - GPIO_FN(CS0), - GPIO_FN(SDA6), - GPIO_FN(SCL6), - GPIO_FN(SDA7), - GPIO_FN(SCL7), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), + PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), + PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), + PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), + PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), /* PTN (mobule: USB, JMC, SGPIO, WDT) */ - GPIO_FN(VBUS_EN), - GPIO_FN(VBUS_OC), - GPIO_FN(JMCTCK), - GPIO_FN(JMCTMS), - GPIO_FN(JMCTDO), - GPIO_FN(JMCTDI), - GPIO_FN(JMCTRST), - GPIO_FN(SGPIO1_CLK), - GPIO_FN(SGPIO1_LOAD), - GPIO_FN(SGPIO1_DI), - GPIO_FN(SGPIO1_DO), - GPIO_FN(SUB_CLKIN), + PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), + PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), + PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), + PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), + PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), /* PTO (mobule: SGPIO, SerMux) */ - GPIO_FN(SGPIO0_CLK), - GPIO_FN(SGPIO0_LOAD), - GPIO_FN(SGPIO0_DI), - GPIO_FN(SGPIO0_DO), - GPIO_FN(SGPIO2_CLK), - GPIO_FN(SGPIO2_LOAD), - GPIO_FN(SGPIO2_DI), - GPIO_FN(SGPIO2_DO), - GPIO_FN(COM1_TXD), - GPIO_FN(COM1_RXD), - GPIO_FN(COM1_RTS), - GPIO_FN(COM1_CTS), + PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), + PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), /* PTP (mobule: EVC, ADC) */ /* PTQ (mobule: LPC) */ - GPIO_FN(LAD3), - GPIO_FN(LAD2), - GPIO_FN(LAD1), - GPIO_FN(LAD0), - GPIO_FN(LFRAME), - GPIO_FN(LRESET), - GPIO_FN(LCLK), + PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), + PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), + PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), + PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), + PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), + PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), + PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), /* PTR (mobule: GRA, IIC) */ - GPIO_FN(DDC3), - GPIO_FN(DDC2), - GPIO_FN(SDA8), - GPIO_FN(SCL8), - GPIO_FN(SDA2), - GPIO_FN(SCL2), - GPIO_FN(SDA1), - GPIO_FN(SCL1), - GPIO_FN(SDA0), - GPIO_FN(SCL0), + PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), + PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), + PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), + PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), /* PTS (mobule: GRA, IIC) */ - GPIO_FN(DDC1), - GPIO_FN(DDC0), - GPIO_FN(SDA9), - GPIO_FN(SCL9), - GPIO_FN(SDA5), - GPIO_FN(SCL5), - GPIO_FN(SDA4), - GPIO_FN(SCL4), - GPIO_FN(SDA3), - GPIO_FN(SCL3), + PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), + PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), + PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), + PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), + PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), + PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), + PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), + PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), + PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), + PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), /* PTT (mobule: PWMX, AUD) */ - GPIO_FN(PWMX7), - GPIO_FN(PWMX6), - GPIO_FN(PWMX5), - GPIO_FN(PWMX4), - GPIO_FN(PWMX3), - GPIO_FN(PWMX2), - GPIO_FN(PWMX1), - GPIO_FN(PWMX0), - GPIO_FN(AUDATA3), - GPIO_FN(AUDATA2), - GPIO_FN(AUDATA1), - GPIO_FN(AUDATA0), - GPIO_FN(STATUS1), - GPIO_FN(STATUS0), + PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), + PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), + PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), + PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), + PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), + PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), + PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), + PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), /* PTU (mobule: LPC, APM) */ - GPIO_FN(LGPIO7), - GPIO_FN(LGPIO6), - GPIO_FN(LGPIO5), - GPIO_FN(LGPIO4), - GPIO_FN(LGPIO3), - GPIO_FN(LGPIO2), - GPIO_FN(LGPIO1), - GPIO_FN(LGPIO0), - GPIO_FN(APMONCTL_O), - GPIO_FN(APMPWBTOUT_O), - GPIO_FN(APMSCI_O), - GPIO_FN(APMVDDON), - GPIO_FN(APMSLPBTN), - GPIO_FN(APMPWRBTN), - GPIO_FN(APMS5N), - GPIO_FN(APMS3N), + PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), + PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), + PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), + PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), + PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), + PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), + PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ - GPIO_FN(A23), - GPIO_FN(A22), - GPIO_FN(A21), - GPIO_FN(A20), - GPIO_FN(A19), - GPIO_FN(A18), - GPIO_FN(A17), - GPIO_FN(A16), - GPIO_FN(COM2_RI), - GPIO_FN(R_SPI_MOSI), - GPIO_FN(R_SPI_MISO), - GPIO_FN(R_SPI_RSPCK), - GPIO_FN(R_SPI_SSL0), - GPIO_FN(R_SPI_SSL1), - GPIO_FN(EVENT7), - GPIO_FN(EVENT6), - GPIO_FN(VBIOS_DI), - GPIO_FN(VBIOS_DO), - GPIO_FN(VBIOS_CLK), - GPIO_FN(VBIOS_CS), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A18, A18_MARK), + PINMUX_GPIO(GPIO_FN_A17, A17_MARK), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), + PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), /* PTW (mobule: LBSC, EVC, SCIF) */ - GPIO_FN(A16), - GPIO_FN(A15), - GPIO_FN(A14), - GPIO_FN(A13), - GPIO_FN(A12), - GPIO_FN(A11), - GPIO_FN(A10), - GPIO_FN(A9), - GPIO_FN(A8), - GPIO_FN(EVENT5), - GPIO_FN(EVENT4), - GPIO_FN(EVENT3), - GPIO_FN(EVENT2), - GPIO_FN(EVENT1), - GPIO_FN(EVENT0), - GPIO_FN(CTS4), - GPIO_FN(CTS2), + PINMUX_GPIO(GPIO_FN_A16, A16_MARK), + PINMUX_GPIO(GPIO_FN_A15, A15_MARK), + PINMUX_GPIO(GPIO_FN_A14, A14_MARK), + PINMUX_GPIO(GPIO_FN_A13, A13_MARK), + PINMUX_GPIO(GPIO_FN_A12, A12_MARK), + PINMUX_GPIO(GPIO_FN_A11, A11_MARK), + PINMUX_GPIO(GPIO_FN_A10, A10_MARK), + PINMUX_GPIO(GPIO_FN_A9, A9_MARK), + PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), + PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), + PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), + PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), + PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), + PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), /* PTX (mobule: LBSC) */ - GPIO_FN(A7), - GPIO_FN(A6), - GPIO_FN(A5), - GPIO_FN(A4), - GPIO_FN(A3), - GPIO_FN(A2), - GPIO_FN(A1), - GPIO_FN(A0), - GPIO_FN(RTS2), - GPIO_FN(SIM_D), - GPIO_FN(SIM_CLK), - GPIO_FN(SIM_RST), + PINMUX_GPIO(GPIO_FN_A7, A7_MARK), + PINMUX_GPIO(GPIO_FN_A6, A6_MARK), + PINMUX_GPIO(GPIO_FN_A5, A5_MARK), + PINMUX_GPIO(GPIO_FN_A4, A4_MARK), + PINMUX_GPIO(GPIO_FN_A3, A3_MARK), + PINMUX_GPIO(GPIO_FN_A2, A2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), /* PTY (mobule: LBSC) */ - GPIO_FN(D7), - GPIO_FN(D6), - GPIO_FN(D5), - GPIO_FN(D4), - GPIO_FN(D3), - GPIO_FN(D2), - GPIO_FN(D1), - GPIO_FN(D0), + PINMUX_GPIO(GPIO_FN_D7, D7_MARK), + PINMUX_GPIO(GPIO_FN_D6, D6_MARK), + PINMUX_GPIO(GPIO_FN_D5, D5_MARK), + PINMUX_GPIO(GPIO_FN_D4, D4_MARK), + PINMUX_GPIO(GPIO_FN_D3, D3_MARK), + PINMUX_GPIO(GPIO_FN_D2, D2_MARK), + PINMUX_GPIO(GPIO_FN_D1, D1_MARK), + PINMUX_GPIO(GPIO_FN_D0, D0_MARK), /* PTZ (mobule: eMMC, ONFI) */ - GPIO_FN(MMCDAT7), - GPIO_FN(MMCDAT6), - GPIO_FN(MMCDAT5), - GPIO_FN(MMCDAT4), - GPIO_FN(MMCDAT3), - GPIO_FN(MMCDAT2), - GPIO_FN(MMCDAT1), - GPIO_FN(MMCDAT0), - GPIO_FN(ON_DQ7), - GPIO_FN(ON_DQ6), - GPIO_FN(ON_DQ5), - GPIO_FN(ON_DQ4), - GPIO_FN(ON_DQ3), - GPIO_FN(ON_DQ2), - GPIO_FN(ON_DQ1), - GPIO_FN(ON_DQ0), + PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, @@ -2156,7 +2152,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } @@ -2264,18 +2260,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7757_pinmux_info = { +struct sh_pfc_soc_info sh7757_pinmux_info = { .name = "sh7757_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PTA0, + .last_gpio = GPIO_FN_ON_DQ0, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7785.c index c176b794f240..3b1825d925bb 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7785.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7785.c @@ -355,7 +355,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -702,7 +702,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -845,180 +845,176 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PR2, PR2_DATA), PINMUX_GPIO(GPIO_PR1, PR1_DATA), PINMUX_GPIO(GPIO_PR0, PR0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ - GPIO_FN(D63_AD31), - GPIO_FN(D62_AD30), - GPIO_FN(D61_AD29), - GPIO_FN(D60_AD28), - GPIO_FN(D59_AD27), - GPIO_FN(D58_AD26), - GPIO_FN(D57_AD25), - GPIO_FN(D56_AD24), - GPIO_FN(D55_AD23), - GPIO_FN(D54_AD22), - GPIO_FN(D53_AD21), - GPIO_FN(D52_AD20), - GPIO_FN(D51_AD19), - GPIO_FN(D50_AD18), - GPIO_FN(D49_AD17_DB5), - GPIO_FN(D48_AD16_DB4), - GPIO_FN(D47_AD15_DB3), - GPIO_FN(D46_AD14_DB2), - GPIO_FN(D45_AD13_DB1), - GPIO_FN(D44_AD12_DB0), - GPIO_FN(D43_AD11_DG5), - GPIO_FN(D42_AD10_DG4), - GPIO_FN(D41_AD9_DG3), - GPIO_FN(D40_AD8_DG2), - GPIO_FN(D39_AD7_DG1), - GPIO_FN(D38_AD6_DG0), - GPIO_FN(D37_AD5_DR5), - GPIO_FN(D36_AD4_DR4), - GPIO_FN(D35_AD3_DR3), - GPIO_FN(D34_AD2_DR2), - GPIO_FN(D33_AD1_DR1), - GPIO_FN(D32_AD0_DR0), - GPIO_FN(REQ1), - GPIO_FN(REQ2), - GPIO_FN(REQ3), - GPIO_FN(GNT1), - GPIO_FN(GNT2), - GPIO_FN(GNT3), - GPIO_FN(MMCCLK), - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(SCIF1_SCK), - GPIO_FN(SCIF1_RXD), - GPIO_FN(SCIF1_TXD), - GPIO_FN(SCIF0_CTS), - GPIO_FN(INTD), - GPIO_FN(FCE), - GPIO_FN(SCIF0_RTS), - GPIO_FN(HSPI_CS), - GPIO_FN(FSE), - GPIO_FN(SCIF0_SCK), - GPIO_FN(HSPI_CLK), - GPIO_FN(FRE), - GPIO_FN(SCIF0_RXD), - GPIO_FN(HSPI_RX), - GPIO_FN(FRB), - GPIO_FN(SCIF0_TXD), - GPIO_FN(HSPI_TX), - GPIO_FN(FWE), - GPIO_FN(SCIF5_TXD), - GPIO_FN(HAC1_SYNC), - GPIO_FN(SSI1_WS), - GPIO_FN(SIOF_TXD_PJ), - GPIO_FN(HAC0_SDOUT), - GPIO_FN(SSI0_SDATA), - GPIO_FN(SIOF_RXD_PJ), - GPIO_FN(HAC0_SDIN), - GPIO_FN(SSI0_SCK), - GPIO_FN(SIOF_SYNC_PJ), - GPIO_FN(HAC0_SYNC), - GPIO_FN(SSI0_WS), - GPIO_FN(SIOF_MCLK_PJ), - GPIO_FN(HAC_RES), - GPIO_FN(SIOF_SCK_PJ), - GPIO_FN(HAC0_BITCLK), - GPIO_FN(SSI0_CLK), - GPIO_FN(HAC1_BITCLK), - GPIO_FN(SSI1_CLK), - GPIO_FN(TCLK), - GPIO_FN(IOIS16), - GPIO_FN(STATUS0), - GPIO_FN(DRAK0_PK3), - GPIO_FN(STATUS1), - GPIO_FN(DRAK1_PK2), - GPIO_FN(DACK2), - GPIO_FN(SCIF2_TXD), - GPIO_FN(MMCCMD), - GPIO_FN(SIOF_TXD_PK), - GPIO_FN(DACK3), - GPIO_FN(SCIF2_SCK), - GPIO_FN(MMCDAT), - GPIO_FN(SIOF_SCK_PK), - GPIO_FN(DREQ0), - GPIO_FN(DREQ1), - GPIO_FN(DRAK0_PK1), - GPIO_FN(DRAK1_PK0), - GPIO_FN(DREQ2), - GPIO_FN(INTB), - GPIO_FN(DREQ3), - GPIO_FN(INTC), - GPIO_FN(DRAK2), - GPIO_FN(CE2A), - GPIO_FN(IRL4), - GPIO_FN(FD4), - GPIO_FN(IRL5), - GPIO_FN(FD5), - GPIO_FN(IRL6), - GPIO_FN(FD6), - GPIO_FN(IRL7), - GPIO_FN(FD7), - GPIO_FN(DRAK3), - GPIO_FN(CE2B), - GPIO_FN(BREQ_BSACK), - GPIO_FN(BACK_BSREQ), - GPIO_FN(SCIF5_RXD), - GPIO_FN(HAC1_SDIN), - GPIO_FN(SSI1_SCK), - GPIO_FN(SCIF5_SCK), - GPIO_FN(HAC1_SDOUT), - GPIO_FN(SSI1_SDATA), - GPIO_FN(SCIF3_TXD), - GPIO_FN(FCLE), - GPIO_FN(SCIF3_RXD), - GPIO_FN(FALE), - GPIO_FN(SCIF3_SCK), - GPIO_FN(FD0), - GPIO_FN(SCIF4_TXD), - GPIO_FN(FD1), - GPIO_FN(SCIF4_RXD), - GPIO_FN(FD2), - GPIO_FN(SCIF4_SCK), - GPIO_FN(FD3), - GPIO_FN(DEVSEL_DCLKOUT), - GPIO_FN(STOP_CDE), - GPIO_FN(LOCK_ODDF), - GPIO_FN(TRDY_DISPL), - GPIO_FN(IRDY_HSYNC), - GPIO_FN(PCIFRAME_VSYNC), - GPIO_FN(INTA), - GPIO_FN(GNT0_GNTIN), - GPIO_FN(REQ0_REQOUT), - GPIO_FN(PERR), - GPIO_FN(SERR), - GPIO_FN(WE7_CBE3), - GPIO_FN(WE6_CBE2), - GPIO_FN(WE5_CBE1), - GPIO_FN(WE4_CBE0), - GPIO_FN(SCIF2_RXD), - GPIO_FN(SIOF_RXD), - GPIO_FN(MRESETOUT), - GPIO_FN(IRQOUT), + PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), + PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), + PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), + PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), + PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), + PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), + PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), + PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), + PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), + PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), + PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), + PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), + PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), + PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), + PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), + PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), + PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), + PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), + PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), + PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), + PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), + PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), + PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), + PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), + PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), + PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), + PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), + PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), + PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), + PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), + PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), + PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), + PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), + PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), + PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), + PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), + PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), + PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), + PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), + PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), + PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), + PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), + PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), + PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), + PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), + PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), + PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), + PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), + PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), + PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), + PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), + PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), + PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), + PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), + PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), + PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), + PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), + PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), + PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), + PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), + PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), + PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), + PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), + PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), + PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), + PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), + PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -1218,7 +1214,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -1286,18 +1282,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7785_pinmux_info = { +struct sh_pfc_soc_info sh7785_pinmux_info = { .name = "sh7785_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_IRQOUT, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7786.c index 8ae0e32844e9..1e18b58f9e5f 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-sh7786.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-sh7786.c @@ -191,7 +191,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t pinmux_data[] = { +static pinmux_enum_t pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -427,7 +427,7 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), }; -static struct sh_pfc_pin pinmux_pins[] = { +static struct pinmux_gpio pinmux_gpios[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -505,151 +505,147 @@ static struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) -static const struct pinmux_func pinmux_func_gpios[] = { /* FN */ - GPIO_FN(CDE), - GPIO_FN(ETH_MAGIC), - GPIO_FN(DISP), - GPIO_FN(ETH_LINK), - GPIO_FN(DR5), - GPIO_FN(ETH_TX_ER), - GPIO_FN(DR4), - GPIO_FN(ETH_TX_EN), - GPIO_FN(DR3), - GPIO_FN(ETH_TXD3), - GPIO_FN(DR2), - GPIO_FN(ETH_TXD2), - GPIO_FN(DR1), - GPIO_FN(ETH_TXD1), - GPIO_FN(DR0), - GPIO_FN(ETH_TXD0), - GPIO_FN(VSYNC), - GPIO_FN(HSPI_CLK), - GPIO_FN(ODDF), - GPIO_FN(HSPI_CS), - GPIO_FN(DG5), - GPIO_FN(ETH_MDIO), - GPIO_FN(DG4), - GPIO_FN(ETH_RX_CLK), - GPIO_FN(DG3), - GPIO_FN(ETH_MDC), - GPIO_FN(DG2), - GPIO_FN(ETH_COL), - GPIO_FN(DG1), - GPIO_FN(ETH_TX_CLK), - GPIO_FN(DG0), - GPIO_FN(ETH_CRS), - GPIO_FN(DCLKIN), - GPIO_FN(HSPI_RX), - GPIO_FN(HSYNC), - GPIO_FN(HSPI_TX), - GPIO_FN(DB5), - GPIO_FN(ETH_RXD3), - GPIO_FN(DB4), - GPIO_FN(ETH_RXD2), - GPIO_FN(DB3), - GPIO_FN(ETH_RXD1), - GPIO_FN(DB2), - GPIO_FN(ETH_RXD0), - GPIO_FN(DB1), - GPIO_FN(ETH_RX_DV), - GPIO_FN(DB0), - GPIO_FN(ETH_RX_ER), - GPIO_FN(DCLKOUT), - GPIO_FN(SCIF1_SCK), - GPIO_FN(SCIF1_RXD), - GPIO_FN(SCIF1_TXD), - GPIO_FN(DACK1), - GPIO_FN(BACK), - GPIO_FN(FALE), - GPIO_FN(DACK0), - GPIO_FN(FCLE), - GPIO_FN(DREQ1), - GPIO_FN(BREQ), - GPIO_FN(USB_OVC1), - GPIO_FN(DREQ0), - GPIO_FN(USB_OVC0), - GPIO_FN(USB_PENC1), - GPIO_FN(USB_PENC0), - GPIO_FN(HAC1_SDOUT), - GPIO_FN(SSI1_SDATA), - GPIO_FN(SDIF1CMD), - GPIO_FN(HAC1_SDIN), - GPIO_FN(SSI1_SCK), - GPIO_FN(SDIF1CD), - GPIO_FN(HAC1_SYNC), - GPIO_FN(SSI1_WS), - GPIO_FN(SDIF1WP), - GPIO_FN(HAC1_BITCLK), - GPIO_FN(SSI1_CLK), - GPIO_FN(SDIF1CLK), - GPIO_FN(HAC0_SDOUT), - GPIO_FN(SSI0_SDATA), - GPIO_FN(SDIF1D3), - GPIO_FN(HAC0_SDIN), - GPIO_FN(SSI0_SCK), - GPIO_FN(SDIF1D2), - GPIO_FN(HAC0_SYNC), - GPIO_FN(SSI0_WS), - GPIO_FN(SDIF1D1), - GPIO_FN(HAC0_BITCLK), - GPIO_FN(SSI0_CLK), - GPIO_FN(SDIF1D0), - GPIO_FN(SCIF3_SCK), - GPIO_FN(SSI2_SDATA), - GPIO_FN(SCIF3_RXD), - GPIO_FN(TCLK), - GPIO_FN(SSI2_SCK), - GPIO_FN(SCIF3_TXD), - GPIO_FN(HAC_RES), - GPIO_FN(SSI2_WS), - GPIO_FN(DACK3), - GPIO_FN(SDIF0CMD), - GPIO_FN(DACK2), - GPIO_FN(SDIF0CD), - GPIO_FN(DREQ3), - GPIO_FN(SDIF0WP), - GPIO_FN(SCIF0_CTS), - GPIO_FN(DREQ2), - GPIO_FN(SDIF0CLK), - GPIO_FN(SCIF0_RTS), - GPIO_FN(IRL7), - GPIO_FN(SDIF0D3), - GPIO_FN(SCIF0_SCK), - GPIO_FN(IRL6), - GPIO_FN(SDIF0D2), - GPIO_FN(SCIF0_RXD), - GPIO_FN(IRL5), - GPIO_FN(SDIF0D1), - GPIO_FN(SCIF0_TXD), - GPIO_FN(IRL4), - GPIO_FN(SDIF0D0), - GPIO_FN(SCIF5_SCK), - GPIO_FN(FRB), - GPIO_FN(SCIF5_RXD), - GPIO_FN(IOIS16), - GPIO_FN(SCIF5_TXD), - GPIO_FN(CE2B), - GPIO_FN(DRAK3), - GPIO_FN(CE2A), - GPIO_FN(SCIF4_SCK), - GPIO_FN(DRAK2), - GPIO_FN(SSI3_WS), - GPIO_FN(SCIF4_RXD), - GPIO_FN(DRAK1), - GPIO_FN(SSI3_SDATA), - GPIO_FN(FSTATUS), - GPIO_FN(SCIF4_TXD), - GPIO_FN(DRAK0), - GPIO_FN(SSI3_SCK), - GPIO_FN(FSE), + PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), + PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), + PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), + PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), + PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), + PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), + PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), + PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), + PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), + PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), + PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), + PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), + PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), + PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), + PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), + PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), + PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), + PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), + PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), + PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), + PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), + PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), + PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), + PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), + PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), + PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), + PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), + PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), + PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), + PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), + PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), + PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), + PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), + PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), + PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), }; -static const struct pinmux_cfg_reg pinmux_config_regs[] = { +static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -779,7 +775,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { {} }; -static const struct pinmux_data_reg pinmux_data_regs[] = { +static struct pinmux_data_reg pinmux_data_regs[] = { { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } @@ -819,18 +815,20 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info sh7786_pinmux_info = { +struct sh_pfc_soc_info sh7786_pinmux_info = { .name = "sh7786_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = pinmux_pins, - .nr_pins = ARRAY_SIZE(pinmux_pins), - .func_gpios = pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_IRL4, + .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, .data_regs = pinmux_data_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pfc-shx3.c b/trunk/drivers/pinctrl/sh-pfc/pfc-shx3.c index 6594c8c48747..ccf6918b03c6 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pfc-shx3.c +++ b/trunk/drivers/pinctrl/sh-pfc/pfc-shx3.c @@ -147,7 +147,7 @@ enum { PINMUX_MARK_END, }; -static const pinmux_enum_t shx3_pinmux_data[] = { +static pinmux_enum_t shx3_pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -306,7 +306,7 @@ static const pinmux_enum_t shx3_pinmux_data[] = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct sh_pfc_pin shx3_pinmux_pins[] = { +static struct pinmux_gpio shx3_pinmux_gpios[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -384,77 +384,73 @@ static struct sh_pfc_pin shx3_pinmux_pins[] = { PINMUX_GPIO(GPIO_PH2, PH2_DATA), PINMUX_GPIO(GPIO_PH1, PH1_DATA), PINMUX_GPIO(GPIO_PH0, PH0_DATA), -}; - -#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins) -static const struct pinmux_func shx3_pinmux_func_gpios[] = { /* FN */ - GPIO_FN(D31), - GPIO_FN(D30), - GPIO_FN(D29), - GPIO_FN(D28), - GPIO_FN(D27), - GPIO_FN(D26), - GPIO_FN(D25), - GPIO_FN(D24), - GPIO_FN(D23), - GPIO_FN(D22), - GPIO_FN(D21), - GPIO_FN(D20), - GPIO_FN(D19), - GPIO_FN(D18), - GPIO_FN(D17), - GPIO_FN(D16), - GPIO_FN(BACK), - GPIO_FN(BREQ), - GPIO_FN(WE3), - GPIO_FN(WE2), - GPIO_FN(CS6), - GPIO_FN(CS5), - GPIO_FN(CS4), - GPIO_FN(CLKOUTENB), - GPIO_FN(DACK3), - GPIO_FN(DACK2), - GPIO_FN(DACK1), - GPIO_FN(DACK0), - GPIO_FN(DREQ3), - GPIO_FN(DREQ2), - GPIO_FN(DREQ1), - GPIO_FN(DREQ0), - GPIO_FN(IRQ3), - GPIO_FN(IRQ2), - GPIO_FN(IRQ1), - GPIO_FN(IRQ0), - GPIO_FN(DRAK3), - GPIO_FN(DRAK2), - GPIO_FN(DRAK1), - GPIO_FN(DRAK0), - GPIO_FN(SCK3), - GPIO_FN(SCK2), - GPIO_FN(SCK1), - GPIO_FN(SCK0), - GPIO_FN(IRL3), - GPIO_FN(IRL2), - GPIO_FN(IRL1), - GPIO_FN(IRL0), - GPIO_FN(TXD3), - GPIO_FN(TXD2), - GPIO_FN(TXD1), - GPIO_FN(TXD0), - GPIO_FN(RXD3), - GPIO_FN(RXD2), - GPIO_FN(RXD1), - GPIO_FN(RXD0), - GPIO_FN(CE2B), - GPIO_FN(CE2A), - GPIO_FN(IOIS16), - GPIO_FN(STATUS1), - GPIO_FN(STATUS0), - GPIO_FN(IRQOUT), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), + PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), + PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), + PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), + PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), + PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), }; -static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { +static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -530,7 +526,7 @@ static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { { }, }; -static const struct pinmux_data_reg shx3_pinmux_data_regs[] = { +static struct pinmux_data_reg shx3_pinmux_data_regs[] = { { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 0, 0, 0, 0, 0, 0, 0, 0, PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, @@ -566,17 +562,19 @@ static const struct pinmux_data_reg shx3_pinmux_data_regs[] = { { }, }; -const struct sh_pfc_soc_info shx3_pinmux_info = { +struct sh_pfc_soc_info shx3_pinmux_info = { .name = "shx3_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .pins = shx3_pinmux_pins, - .nr_pins = ARRAY_SIZE(shx3_pinmux_pins), - .func_gpios = shx3_pinmux_func_gpios, - .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios), + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_STATUS0, + .gpios = shx3_pinmux_gpios, .gpio_data = shx3_pinmux_data, .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), .cfg_regs = shx3_pinmux_config_regs, diff --git a/trunk/drivers/pinctrl/sh-pfc/pinctrl.c b/trunk/drivers/pinctrl/sh-pfc/pinctrl.c index 3492ec9a33b7..11e0e1374d65 100644 --- a/trunk/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/trunk/drivers/pinctrl/sh-pfc/pinctrl.c @@ -9,6 +9,7 @@ */ #define DRV_NAME "sh-pfc" +#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt #include #include @@ -23,28 +24,25 @@ #include #include "core.h" -#include "../core.h" -#include "../pinconf.h" - -struct sh_pfc_pin_config { - u32 type; -}; struct sh_pfc_pinctrl { struct pinctrl_dev *pctl; - struct pinctrl_desc pctl_desc; - struct sh_pfc *pfc; - struct pinctrl_pin_desc *pins; - struct sh_pfc_pin_config *configs; + struct pinmux_gpio **functions; + unsigned int nr_functions; + + struct pinctrl_pin_desc *pads; + unsigned int nr_pads; + + spinlock_t lock; }; static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pfc->info->nr_groups; + return pmx->nr_pads; } static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, @@ -52,16 +50,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pfc->info->groups[selector].name; + return pmx->pads[selector].name; } -static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, +static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, const unsigned **pins, unsigned *num_pins) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *pins = pmx->pfc->info->groups[selector].pins; - *num_pins = pmx->pfc->info->groups[selector].nr_pins; + *pins = &pmx->pads[group].number; + *num_pins = 1; return 0; } @@ -72,7 +70,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "%s", DRV_NAME); } -static const struct pinctrl_ops sh_pfc_pinctrl_ops = { +static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_groups_count = sh_pfc_get_groups_count, .get_group_name = sh_pfc_get_group_name, .get_group_pins = sh_pfc_get_group_pins, @@ -83,7 +81,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pfc->info->nr_functions; + return pmx->nr_functions; } static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, @@ -91,113 +89,136 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->pfc->info->functions[selector].name; + return pmx->functions[selector]->name; } -static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, - unsigned selector, +static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, const char * const **groups, unsigned * const num_groups) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - *groups = pmx->pfc->info->functions[selector].groups; - *num_groups = pmx->pfc->info->functions[selector].nr_groups; + *groups = &pmx->functions[func]->name; + *num_groups = 1; return 0; } -static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, +static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, unsigned group) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; - unsigned long flags; - unsigned int i; - int ret = 0; - - spin_lock_irqsave(&pfc->lock, flags); + return 0; +} - for (i = 0; i < grp->nr_pins; ++i) { - int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; +static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, + unsigned group) +{ +} - if (cfg->type != PINMUX_TYPE_NONE) { - ret = -EBUSY; - goto done; - } - } +static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) +{ + if (sh_pfc_config_gpio(pfc, offset, + PINMUX_TYPE_FUNCTION, + GPIO_CFG_DRYRUN) != 0) + return -EINVAL; - for (i = 0; i < grp->nr_pins; ++i) { - ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); - if (ret < 0) - break; - } + if (sh_pfc_config_gpio(pfc, offset, + PINMUX_TYPE_FUNCTION, + GPIO_CFG_REQ) != 0) + return -EINVAL; -done: - spin_unlock_irqrestore(&pfc->lock, flags); - return ret; + return 0; } -static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) +static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, + int new_type) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; unsigned long flags; - unsigned int i; + int pinmux_type; + int ret = -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - for (i = 0; i < grp->nr_pins; ++i) { - int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; - cfg->type = PINMUX_TYPE_NONE; + /* + * See if the present config needs to first be de-configured. + */ + switch (pinmux_type) { + case PINMUX_TYPE_GPIO: + break; + case PINMUX_TYPE_OUTPUT: + case PINMUX_TYPE_INPUT: + case PINMUX_TYPE_INPUT_PULLUP: + case PINMUX_TYPE_INPUT_PULLDOWN: + sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + break; + default: + goto err; } + /* + * Dry run + */ + if (sh_pfc_config_gpio(pfc, offset, new_type, + GPIO_CFG_DRYRUN) != 0) + goto err; + + /* + * Request + */ + if (sh_pfc_config_gpio(pfc, offset, new_type, + GPIO_CFG_REQ) != 0) + goto err; + + pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; + pfc->info->gpios[offset].flags |= new_type; + + ret = 0; + +err: spin_unlock_irqrestore(&pfc->lock, flags); + + return ret; } + static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - int idx = sh_pfc_get_pin_index(pfc, offset); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; - int ret; + int ret, pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - if (cfg->type != PINMUX_TYPE_NONE) { - dev_err(pfc->dev, - "Pin %u is busy, can't configure it as GPIO.\n", - offset); - ret = -EBUSY; - goto done; - } + pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; - if (!pfc->gpio) { - /* If GPIOs are handled externally the pin mux type need to be - * set to GPIO here. - */ - const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + switch (pinmux_type) { + case PINMUX_TYPE_FUNCTION: + pr_notice_once("Use of GPIO API for function requests is " + "deprecated, convert to pinctrl\n"); + /* handle for now */ + ret = sh_pfc_config_function(pfc, offset); + if (unlikely(ret < 0)) + goto err; - ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); - if (ret < 0) - goto done; + break; + case PINMUX_TYPE_GPIO: + case PINMUX_TYPE_INPUT: + case PINMUX_TYPE_OUTPUT: + break; + default: + pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); + ret = -ENOTSUPP; + goto err; } - cfg->type = PINMUX_TYPE_GPIO; - ret = 0; -done: +err: spin_unlock_irqrestore(&pfc->lock, flags); return ret; @@ -209,12 +230,15 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); struct sh_pfc *pfc = pmx->pfc; - int idx = sh_pfc_get_pin_index(pfc, offset); - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; + int pinmux_type; spin_lock_irqsave(&pfc->lock, flags); - cfg->type = PINMUX_TYPE_NONE; + + pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; + + sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); + spin_unlock_irqrestore(&pfc->lock, flags); } @@ -223,242 +247,207 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned offset, bool input) { struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; - int idx = sh_pfc_get_pin_index(pfc, offset); - const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - unsigned long flags; - unsigned int dir; - int ret; - - /* Check if the requested direction is supported by the pin. Not all SoC - * provide pin config data, so perform the check conditionally. - */ - if (pin->configs) { - dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; - if (!(pin->configs & dir)) - return -EINVAL; - } - - spin_lock_irqsave(&pfc->lock, flags); - - ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); - if (ret < 0) - goto done; - - cfg->type = new_type; + int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; -done: - spin_unlock_irqrestore(&pfc->lock, flags); - return ret; + return sh_pfc_reconfig_pin(pmx->pfc, offset, type); } -static const struct pinmux_ops sh_pfc_pinmux_ops = { +static struct pinmux_ops sh_pfc_pinmux_ops = { .get_functions_count = sh_pfc_get_functions_count, .get_function_name = sh_pfc_get_function_name, .get_function_groups = sh_pfc_get_function_groups, - .enable = sh_pfc_func_enable, - .disable = sh_pfc_func_disable, + .enable = sh_pfc_noop_enable, + .disable = sh_pfc_noop_disable, .gpio_request_enable = sh_pfc_gpio_request_enable, .gpio_disable_free = sh_pfc_gpio_disable_free, .gpio_set_direction = sh_pfc_gpio_set_direction, }; -/* Check whether the requested parameter is supported for a pin. */ -static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, - enum pin_config_param param) +static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config) { - int idx = sh_pfc_get_pin_index(pfc, _pin); - const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + struct sh_pfc *pfc = pmx->pfc; - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - return true; + *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; - case PIN_CONFIG_BIAS_PULL_UP: - return pin->configs & SH_PFC_PIN_CFG_PULL_UP; + return 0; +} - case PIN_CONFIG_BIAS_PULL_DOWN: - return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; +static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long config) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - default: - return false; - } + /* Validate the new type */ + if (config >= PINMUX_FLAG_TYPE) + return -EINVAL; + + return sh_pfc_reconfig_pin(pmx->pfc, pin, config); } -static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, - unsigned long *config) +static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - enum pin_config_param param = pinconf_to_config_param(*config); - unsigned long flags; - unsigned int bias; + const char *pinmux_type_str[] = { + [PINMUX_TYPE_NONE] = "none", + [PINMUX_TYPE_FUNCTION] = "function", + [PINMUX_TYPE_GPIO] = "gpio", + [PINMUX_TYPE_OUTPUT] = "output", + [PINMUX_TYPE_INPUT] = "input", + [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up", + [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down", + }; + unsigned long config; + int rc; + + rc = sh_pfc_pinconf_get(pctldev, pin, &config); + if (unlikely(rc != 0)) + return; + + seq_printf(s, " %s", pinmux_type_str[config]); +} - if (!sh_pfc_pinconf_validate(pfc, _pin, param)) - return -ENOTSUPP; +static struct pinconf_ops sh_pfc_pinconf_ops = { + .pin_config_get = sh_pfc_pinconf_get, + .pin_config_set = sh_pfc_pinconf_set, + .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, +}; - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - if (!pfc->info->ops || !pfc->info->ops->get_bias) - return -ENOTSUPP; +static struct pinctrl_gpio_range sh_pfc_gpio_range = { + .name = DRV_NAME, + .id = 0, +}; - spin_lock_irqsave(&pfc->lock, flags); - bias = pfc->info->ops->get_bias(pfc, _pin); - spin_unlock_irqrestore(&pfc->lock, flags); +static struct pinctrl_desc sh_pfc_pinctrl_desc = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pctlops = &sh_pfc_pinctrl_ops, + .pmxops = &sh_pfc_pinmux_ops, + .confops = &sh_pfc_pinconf_ops, +}; - if (bias != param) - return -EINVAL; +static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, + struct pinmux_gpio *gpio, unsigned offset) +{ + struct pinmux_data_reg *dummy; + unsigned long flags; + int bit; - *config = 0; - break; + gpio->flags &= ~PINMUX_FLAG_TYPE; - default: - return -ENOTSUPP; - } + if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) + gpio->flags |= PINMUX_TYPE_GPIO; + else { + gpio->flags |= PINMUX_TYPE_FUNCTION; - return 0; + spin_lock_irqsave(&pmx->lock, flags); + pmx->nr_functions++; + spin_unlock_irqrestore(&pmx->lock, flags); + } } -static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, - unsigned long config) +/* pinmux ranges -> pinctrl pin descs */ +static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - struct sh_pfc *pfc = pmx->pfc; - enum pin_config_param param = pinconf_to_config_param(config); unsigned long flags; + int i; - if (!sh_pfc_pinconf_validate(pfc, _pin, param)) - return -ENOTSUPP; + pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; - switch (param) { - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_DISABLE: - if (!pfc->info->ops || !pfc->info->ops->set_bias) - return -ENOTSUPP; + pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, + GFP_KERNEL); + if (unlikely(!pmx->pads)) { + pmx->nr_pads = 0; + return -ENOMEM; + } - spin_lock_irqsave(&pfc->lock, flags); - pfc->info->ops->set_bias(pfc, _pin, param); - spin_unlock_irqrestore(&pfc->lock, flags); + spin_lock_irqsave(&pfc->lock, flags); - break; + /* + * We don't necessarily have a 1:1 mapping between pin and linux + * GPIO number, as the latter maps to the associated enum_id. + * Care needs to be taken to translate back to pin space when + * dealing with any pin configurations. + */ + for (i = 0; i < pmx->nr_pads; i++) { + struct pinctrl_pin_desc *pin = pmx->pads + i; + struct pinmux_gpio *gpio = pfc->info->gpios + i; - default: - return -ENOTSUPP; - } + pin->number = pfc->info->first_gpio + i; + pin->name = gpio->name; - return 0; -} + /* XXX */ + if (unlikely(!gpio->enum_id)) + continue; -static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, - unsigned long config) -{ - struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); - const unsigned int *pins; - unsigned int num_pins; - unsigned int i; + sh_pfc_map_one_gpio(pfc, pmx, gpio, i); + } - pins = pmx->pfc->info->groups[group].pins; - num_pins = pmx->pfc->info->groups[group].nr_pins; + spin_unlock_irqrestore(&pfc->lock, flags); - for (i = 0; i < num_pins; ++i) - sh_pfc_pinconf_set(pctldev, pins[i], config); + sh_pfc_pinctrl_desc.pins = pmx->pads; + sh_pfc_pinctrl_desc.npins = pmx->nr_pads; return 0; } -static const struct pinconf_ops sh_pfc_pinconf_ops = { - .is_generic = true, - .pin_config_get = sh_pfc_pinconf_get, - .pin_config_set = sh_pfc_pinconf_set, - .pin_config_group_set = sh_pfc_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -/* PFC ranges -> pinctrl pin descs */ -static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) +static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) { - const struct pinmux_range *ranges; - struct pinmux_range def_range; - unsigned int nr_ranges; - unsigned int nr_pins; - unsigned int i; - - if (pfc->info->ranges == NULL) { - def_range.begin = 0; - def_range.end = pfc->info->nr_pins - 1; - ranges = &def_range; - nr_ranges = 1; - } else { - ranges = pfc->info->ranges; - nr_ranges = pfc->info->nr_ranges; - } + unsigned long flags; + int i, fn; - pmx->pins = devm_kzalloc(pfc->dev, - sizeof(*pmx->pins) * pfc->info->nr_pins, - GFP_KERNEL); - if (unlikely(!pmx->pins)) + pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * + sizeof(*pmx->functions), GFP_KERNEL); + if (unlikely(!pmx->functions)) return -ENOMEM; - pmx->configs = devm_kzalloc(pfc->dev, - sizeof(*pmx->configs) * pfc->info->nr_pins, - GFP_KERNEL); - if (unlikely(!pmx->configs)) - return -ENOMEM; + spin_lock_irqsave(&pmx->lock, flags); - for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { - const struct pinmux_range *range = &ranges[i]; - unsigned int number; - - for (number = range->begin; number <= range->end; - number++, nr_pins++) { - struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; - struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; - const struct sh_pfc_pin *info = - &pfc->info->pins[nr_pins]; - - pin->number = number; - pin->name = info->name; - cfg->type = PINMUX_TYPE_NONE; - } + for (i = fn = 0; i < pmx->nr_pads; i++) { + struct pinmux_gpio *gpio = pfc->info->gpios + i; + + if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) + pmx->functions[fn++] = gpio; } - pfc->nr_pins = ranges[nr_ranges-1].end + 1; + spin_unlock_irqrestore(&pmx->lock, flags); - return nr_ranges; + return 0; } int sh_pfc_register_pinctrl(struct sh_pfc *pfc) { struct sh_pfc_pinctrl *pmx; - int nr_ranges; + int ret; pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); if (unlikely(!pmx)) return -ENOMEM; + spin_lock_init(&pmx->lock); + pmx->pfc = pfc; pfc->pinctrl = pmx; - nr_ranges = sh_pfc_map_pins(pfc, pmx); - if (unlikely(nr_ranges < 0)) - return nr_ranges; + ret = sh_pfc_map_gpios(pfc, pmx); + if (unlikely(ret != 0)) + return ret; - pmx->pctl_desc.name = DRV_NAME; - pmx->pctl_desc.owner = THIS_MODULE; - pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; - pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; - pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; - pmx->pctl_desc.pins = pmx->pins; - pmx->pctl_desc.npins = pfc->info->nr_pins; + ret = sh_pfc_map_functions(pfc, pmx); + if (unlikely(ret != 0)) + return ret; - pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); - if (pmx->pctl == NULL) - return -EINVAL; + pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); + if (IS_ERR(pmx->pctl)) + return PTR_ERR(pmx->pctl); + + sh_pfc_gpio_range.npins = pfc->info->last_gpio + - pfc->info->first_gpio + 1; + sh_pfc_gpio_range.base = pfc->info->first_gpio; + sh_pfc_gpio_range.pin_base = pfc->info->first_gpio; + + pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range); return 0; } diff --git a/trunk/drivers/pinctrl/sh-pfc/sh_pfc.h b/trunk/drivers/pinctrl/sh-pfc/sh_pfc.h index 3b785fc428d5..13049c4c8d30 100644 --- a/trunk/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/trunk/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -15,8 +15,7 @@ #include typedef unsigned short pinmux_enum_t; - -#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1) +typedef unsigned short pinmux_flag_t; enum { PINMUX_TYPE_NONE, @@ -31,81 +30,44 @@ enum { PINMUX_FLAG_TYPE, /* must be last */ }; -#define SH_PFC_PIN_CFG_INPUT (1 << 0) -#define SH_PFC_PIN_CFG_OUTPUT (1 << 1) -#define SH_PFC_PIN_CFG_PULL_UP (1 << 2) -#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) +#define PINMUX_FLAG_DBIT_SHIFT 5 +#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) +#define PINMUX_FLAG_DREG_SHIFT 10 +#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) -struct sh_pfc_pin { - const pinmux_enum_t enum_id; +struct pinmux_gpio { + pinmux_enum_t enum_id; + pinmux_flag_t flags; const char *name; - unsigned int configs; }; -#define SH_PFC_PIN_GROUP(n) \ - { \ - .name = #n, \ - .pins = n##_pins, \ - .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins), \ - } - -struct sh_pfc_pin_group { - const char *name; - const unsigned int *pins; - const unsigned int *mux; - unsigned int nr_pins; -}; - -#define SH_PFC_FUNCTION(n) \ - { \ - .name = #n, \ - .groups = n##_groups, \ - .nr_groups = ARRAY_SIZE(n##_groups), \ - } - -struct sh_pfc_function { - const char *name; - const char * const *groups; - unsigned int nr_groups; -}; - -struct pinmux_func { - const pinmux_enum_t enum_id; - const char *name; -}; - -#define PINMUX_GPIO(gpio, data_or_mark) \ - [gpio] = { \ - .name = __stringify(gpio), \ - .enum_id = data_or_mark, \ - } -#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ - [gpio - (base)] = { \ - .name = __stringify(gpio), \ - .enum_id = data_or_mark, \ - } +#define PINMUX_GPIO(gpio, data_or_mark) \ + [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 struct pinmux_cfg_reg { unsigned long reg, reg_width, field_width; - const pinmux_enum_t *enum_ids; - const unsigned long *var_field_width; + unsigned long *cnt; + pinmux_enum_t *enum_ids; + unsigned long *var_field_width; }; #define PINMUX_CFG_REG(name, r, r_width, f_width) \ .reg = r, .reg_width = r_width, .field_width = f_width, \ + .cnt = (unsigned long [r_width / f_width]) {}, \ .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ .reg = r, .reg_width = r_width, \ + .cnt = (unsigned long [r_width]) {}, \ .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ .enum_ids = (pinmux_enum_t []) struct pinmux_data_reg { - unsigned long reg, reg_width; - const pinmux_enum_t *enum_ids; + unsigned long reg, reg_width, reg_shadow; + pinmux_enum_t *enum_ids; + void __iomem *mapped_reg; }; #define PINMUX_DATA_REG(name, r, r_width) \ @@ -114,11 +76,11 @@ struct pinmux_data_reg { struct pinmux_irq { int irq; - unsigned short *gpios; + pinmux_enum_t *enum_ids; }; #define PINMUX_IRQ(irq_nr, ids...) \ - { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ + { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ struct pinmux_range { pinmux_enum_t begin; @@ -126,49 +88,33 @@ struct pinmux_range { pinmux_enum_t force; }; -struct sh_pfc; - -struct sh_pfc_soc_operations { - unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); - void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias); -}; - struct sh_pfc_soc_info { - const char *name; - const struct sh_pfc_soc_operations *ops; - + char *name; + pinmux_enum_t reserved_id; + struct pinmux_range data; struct pinmux_range input; struct pinmux_range input_pd; struct pinmux_range input_pu; struct pinmux_range output; + struct pinmux_range mark; struct pinmux_range function; - const struct sh_pfc_pin *pins; - unsigned int nr_pins; - const struct pinmux_range *ranges; - unsigned int nr_ranges; - const struct sh_pfc_pin_group *groups; - unsigned int nr_groups; - const struct sh_pfc_function *functions; - unsigned int nr_functions; - - const struct pinmux_func *func_gpios; - unsigned int nr_func_gpios; + unsigned first_gpio, last_gpio; - const struct pinmux_cfg_reg *cfg_regs; - const struct pinmux_data_reg *data_regs; + struct pinmux_gpio *gpios; + struct pinmux_cfg_reg *cfg_regs; + struct pinmux_data_reg *data_regs; - const pinmux_enum_t *gpio_data; + pinmux_enum_t *gpio_data; unsigned int gpio_data_size; - const struct pinmux_irq *gpio_irq; + struct pinmux_irq *gpio_irq; unsigned int gpio_irq_size; unsigned long unlock_reg; }; -enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; +enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; /* helper macro for port */ #define PORT_1(fn, pfx, sfx) fn(pfx, sfx) @@ -180,23 +126,6 @@ enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define PORT_32(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define PORT_32_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - #define PORT_90(fn, pfx, sfx) \ PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ @@ -208,7 +137,7 @@ enum { GPIO_CFG_REQ, GPIO_CFG_FREE }; #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) -#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) +#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) /* helper macro for pinmux_enum_t */ #define PORT_DATA_I(nr) \ diff --git a/trunk/drivers/pinctrl/spear/pinctrl-plgpio.c b/trunk/drivers/pinctrl/spear/pinctrl-plgpio.c index a4908ecd74fb..295b349a05cf 100644 --- a/trunk/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/trunk/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -15,12 +15,12 @@ #include #include #include -#include #include #include #include #include #include +#include #define MAX_GPIO_PER_REG 32 #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear.c b/trunk/drivers/pinctrl/spear/pinctrl-spear.c index 116da0412c4b..6a7dae70db08 100644 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear.c +++ b/trunk/drivers/pinctrl/spear/pinctrl-spear.c @@ -198,7 +198,7 @@ static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static const struct pinctrl_ops spear_pinctrl_ops = { +static struct pinctrl_ops spear_pinctrl_ops = { .get_groups_count = spear_pinctrl_get_groups_cnt, .get_group_name = spear_pinctrl_get_group_name, .get_group_pins = spear_pinctrl_get_group_pins, @@ -340,7 +340,7 @@ static void gpio_disable_free(struct pinctrl_dev *pctldev, gpio_request_endisable(pctldev, range, offset, false); } -static const struct pinmux_ops spear_pinmux_ops = { +static struct pinmux_ops spear_pinmux_ops = { .get_functions_count = spear_pinctrl_get_funcs_count, .get_function_name = spear_pinctrl_get_func_name, .get_function_groups = spear_pinctrl_get_func_groups, diff --git a/trunk/drivers/rtc/rtc-at91rm9200.c b/trunk/drivers/rtc/rtc-at91rm9200.c index 0a9f27e094ea..434ebc3a99dc 100644 --- a/trunk/drivers/rtc/rtc-at91rm9200.c +++ b/trunk/drivers/rtc/rtc-at91rm9200.c @@ -44,7 +44,6 @@ static DECLARE_COMPLETION(at91_rtc_updated); static unsigned int at91_alarm_year = AT91_RTC_EPOCH; static void __iomem *at91_rtc_regs; static int irq; -static u32 at91_rtc_imr; /* * Decode time/date into rtc_time structure @@ -109,11 +108,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) cr = at91_rtc_read(AT91_RTC_CR); at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM); - at91_rtc_imr |= AT91_RTC_ACKUPD; at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD); wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */ at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD); - at91_rtc_imr &= ~AT91_RTC_ACKUPD; at91_rtc_write(AT91_RTC_TIMR, bin2bcd(tm->tm_sec) << 0 @@ -145,7 +142,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); tm->tm_year = at91_alarm_year - 1900; - alrm->enabled = (at91_rtc_imr & AT91_RTC_ALARM) + alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM) ? 1 : 0; dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__, @@ -171,7 +168,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) tm.tm_sec = alrm->time.tm_sec; at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM); - at91_rtc_imr &= ~AT91_RTC_ALARM; at91_rtc_write(AT91_RTC_TIMALR, bin2bcd(tm.tm_sec) << 0 | bin2bcd(tm.tm_min) << 8 @@ -184,7 +180,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) if (alrm->enabled) { at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); - at91_rtc_imr |= AT91_RTC_ALARM; at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM); } @@ -201,12 +196,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) if (enabled) { at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); - at91_rtc_imr |= AT91_RTC_ALARM; at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM); - } else { + } else at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM); - at91_rtc_imr &= ~AT91_RTC_ALARM; - } return 0; } @@ -215,10 +207,12 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) */ static int at91_rtc_proc(struct device *dev, struct seq_file *seq) { + unsigned long imr = at91_rtc_read(AT91_RTC_IMR); + seq_printf(seq, "update_IRQ\t: %s\n", - (at91_rtc_imr & AT91_RTC_ACKUPD) ? "yes" : "no"); + (imr & AT91_RTC_ACKUPD) ? "yes" : "no"); seq_printf(seq, "periodic_IRQ\t: %s\n", - (at91_rtc_imr & AT91_RTC_SECEV) ? "yes" : "no"); + (imr & AT91_RTC_SECEV) ? "yes" : "no"); return 0; } @@ -233,7 +227,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id) unsigned int rtsr; unsigned long events = 0; - rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_imr; + rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR); if (rtsr) { /* this interrupt is shared! Is it ours? */ if (rtsr & AT91_RTC_ALARM) events |= (RTC_AF | RTC_IRQF); @@ -297,7 +291,6 @@ static int __init at91_rtc_probe(struct platform_device *pdev) at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM | AT91_RTC_SECEV | AT91_RTC_TIMEV | AT91_RTC_CALEV); - at91_rtc_imr = 0; ret = request_irq(irq, at91_rtc_interrupt, IRQF_SHARED, @@ -336,7 +329,6 @@ static int __exit at91_rtc_remove(struct platform_device *pdev) at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM | AT91_RTC_SECEV | AT91_RTC_TIMEV | AT91_RTC_CALEV); - at91_rtc_imr = 0; free_irq(irq, pdev); rtc_device_unregister(rtc); @@ -349,35 +341,31 @@ static int __exit at91_rtc_remove(struct platform_device *pdev) /* AT91RM9200 RTC Power management control */ -static u32 at91_rtc_bkpimr; - +static u32 at91_rtc_imr; static int at91_rtc_suspend(struct device *dev) { /* this IRQ is shared with DBGU and other hardware which isn't * necessarily doing PM like we are... */ - at91_rtc_bkpimr = at91_rtc_imr & (AT91_RTC_ALARM|AT91_RTC_SECEV); - if (at91_rtc_bkpimr) { - if (device_may_wakeup(dev)) { + at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR) + & (AT91_RTC_ALARM|AT91_RTC_SECEV); + if (at91_rtc_imr) { + if (device_may_wakeup(dev)) enable_irq_wake(irq); - } else { - at91_rtc_write(AT91_RTC_IDR, at91_rtc_bkpimr); - at91_rtc_imr &= ~at91_rtc_bkpimr; - } -} + else + at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr); + } return 0; } static int at91_rtc_resume(struct device *dev) { - if (at91_rtc_bkpimr) { - if (device_may_wakeup(dev)) { + if (at91_rtc_imr) { + if (device_may_wakeup(dev)) disable_irq_wake(irq); - } else { - at91_rtc_imr |= at91_rtc_bkpimr; - at91_rtc_write(AT91_RTC_IER, at91_rtc_bkpimr); - } + else + at91_rtc_write(AT91_RTC_IER, at91_rtc_imr); } return 0; } diff --git a/trunk/drivers/rtc/rtc-at91rm9200.h b/trunk/drivers/rtc/rtc-at91rm9200.h index 5f940b6844cb..da1945e5f714 100644 --- a/trunk/drivers/rtc/rtc-at91rm9200.h +++ b/trunk/drivers/rtc/rtc-at91rm9200.h @@ -64,6 +64,7 @@ #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */ #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */ #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ +#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ #define AT91_RTC_VER 0x2c /* Valid Entry Register */ #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ diff --git a/trunk/drivers/s390/block/scm_blk.c b/trunk/drivers/s390/block/scm_blk.c index 5ac9c935c151..e9b9c8392832 100644 --- a/trunk/drivers/s390/block/scm_blk.c +++ b/trunk/drivers/s390/block/scm_blk.c @@ -307,7 +307,7 @@ static void scm_blk_handle_error(struct scm_request *scmrq) case EQC_WR_PROHIBIT: spin_lock_irqsave(&bdev->lock, flags); if (bdev->state != SCM_WR_PROHIBIT) - pr_info("%lu: Write access to the SCM increment is suspended\n", + pr_info("%lx: Write access to the SCM increment is suspended\n", (unsigned long) bdev->scmdev->address); bdev->state = SCM_WR_PROHIBIT; spin_unlock_irqrestore(&bdev->lock, flags); @@ -445,7 +445,7 @@ void scm_blk_set_available(struct scm_blk_dev *bdev) spin_lock_irqsave(&bdev->lock, flags); if (bdev->state == SCM_WR_PROHIBIT) - pr_info("%lu: Write access to the SCM increment is restored\n", + pr_info("%lx: Write access to the SCM increment is restored\n", (unsigned long) bdev->scmdev->address); bdev->state = SCM_OPER; spin_unlock_irqrestore(&bdev->lock, flags); @@ -463,12 +463,15 @@ static int __init scm_blk_init(void) goto out; scm_major = ret; - if (scm_alloc_rqs(nr_requests)) + ret = scm_alloc_rqs(nr_requests); + if (ret) goto out_unreg; scm_debug = debug_register("scm_log", 16, 1, 16); - if (!scm_debug) + if (!scm_debug) { + ret = -ENOMEM; goto out_free; + } debug_register_view(scm_debug, &debug_hex_ascii_view); debug_set_level(scm_debug, 2); diff --git a/trunk/drivers/s390/block/scm_drv.c b/trunk/drivers/s390/block/scm_drv.c index 5f6180d6ff08..c98cf52d78d1 100644 --- a/trunk/drivers/s390/block/scm_drv.c +++ b/trunk/drivers/s390/block/scm_drv.c @@ -19,7 +19,7 @@ static void scm_notify(struct scm_device *scmdev, enum scm_event event) switch (event) { case SCM_CHANGE: - pr_info("%lu: The capabilities of the SCM increment changed\n", + pr_info("%lx: The capabilities of the SCM increment changed\n", (unsigned long) scmdev->address); SCM_LOG(2, "State changed"); SCM_LOG_STATE(2, scmdev); diff --git a/trunk/drivers/s390/char/tty3270.c b/trunk/drivers/s390/char/tty3270.c index b907dba24025..cee69dac3e18 100644 --- a/trunk/drivers/s390/char/tty3270.c +++ b/trunk/drivers/s390/char/tty3270.c @@ -915,7 +915,7 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty) int i, rc; /* Check if the tty3270 is already there. */ - view = raw3270_find_view(&tty3270_fn, tty->index); + view = raw3270_find_view(&tty3270_fn, tty->index + RAW3270_FIRSTMINOR); if (!IS_ERR(view)) { tp = container_of(view, struct tty3270, view); tty->driver_data = tp; @@ -927,15 +927,16 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty) tp->inattr = TF_INPUT; return tty_port_install(&tp->port, driver, tty); } - if (tty3270_max_index < tty->index) - tty3270_max_index = tty->index; + if (tty3270_max_index < tty->index + 1) + tty3270_max_index = tty->index + 1; /* Allocate tty3270 structure on first open. */ tp = tty3270_alloc_view(); if (IS_ERR(tp)) return PTR_ERR(tp); - rc = raw3270_add_view(&tp->view, &tty3270_fn, tty->index); + rc = raw3270_add_view(&tp->view, &tty3270_fn, + tty->index + RAW3270_FIRSTMINOR); if (rc) { tty3270_free_view(tp); return rc; @@ -1846,12 +1847,12 @@ static const struct tty_operations tty3270_ops = { void tty3270_create_cb(int minor) { - tty_register_device(tty3270_driver, minor, NULL); + tty_register_device(tty3270_driver, minor - RAW3270_FIRSTMINOR, NULL); } void tty3270_destroy_cb(int minor) { - tty_unregister_device(tty3270_driver, minor); + tty_unregister_device(tty3270_driver, minor - RAW3270_FIRSTMINOR); } struct raw3270_notifier tty3270_notifier = @@ -1884,7 +1885,8 @@ static int __init tty3270_init(void) driver->driver_name = "tty3270"; driver->name = "3270/tty"; driver->major = IBM_TTY3270_MAJOR; - driver->minor_start = 0; + driver->minor_start = RAW3270_FIRSTMINOR; + driver->name_base = RAW3270_FIRSTMINOR; driver->type = TTY_DRIVER_TYPE_SYSTEM; driver->subtype = SYSTEM_TYPE_TTY; driver->init_termios = tty_std_termios; diff --git a/trunk/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/trunk/drivers/scsi/bnx2fc/bnx2fc_fcoe.c index 2daf4b0da434..90bc7bd00966 100644 --- a/trunk/drivers/scsi/bnx2fc/bnx2fc_fcoe.c +++ b/trunk/drivers/scsi/bnx2fc/bnx2fc_fcoe.c @@ -940,6 +940,7 @@ static int bnx2fc_libfc_config(struct fc_lport *lport) fc_exch_init(lport); fc_rport_init(lport); fc_disc_init(lport); + fc_disc_config(lport, lport); return 0; } @@ -2133,6 +2134,7 @@ static int _bnx2fc_create(struct net_device *netdev, } ctlr = bnx2fc_to_ctlr(interface); + cdev = fcoe_ctlr_to_ctlr_dev(ctlr); interface->vlan_id = vlan_id; interface->timer_work_queue = @@ -2143,7 +2145,7 @@ static int _bnx2fc_create(struct net_device *netdev, goto ifput_err; } - lport = bnx2fc_if_create(interface, &interface->hba->pcidev->dev, 0); + lport = bnx2fc_if_create(interface, &cdev->dev, 0); if (!lport) { printk(KERN_ERR PFX "Failed to create interface (%s)\n", netdev->name); @@ -2159,8 +2161,6 @@ static int _bnx2fc_create(struct net_device *netdev, /* Make this master N_port */ ctlr->lp = lport; - cdev = fcoe_ctlr_to_ctlr_dev(ctlr); - if (link_state == BNX2FC_CREATE_LINK_UP) cdev->enabled = FCOE_CTLR_ENABLED; else diff --git a/trunk/drivers/scsi/fcoe/fcoe.c b/trunk/drivers/scsi/fcoe/fcoe.c index b5d92fc93c70..9bfdc9a3f897 100644 --- a/trunk/drivers/scsi/fcoe/fcoe.c +++ b/trunk/drivers/scsi/fcoe/fcoe.c @@ -490,7 +490,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe) { struct net_device *netdev = fcoe->netdev; struct fcoe_ctlr *fip = fcoe_to_ctlr(fcoe); - struct fcoe_ctlr_device *ctlr_dev = fcoe_ctlr_to_ctlr_dev(fip); rtnl_lock(); if (!fcoe->removed) @@ -501,7 +500,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe) /* tear-down the FCoE controller */ fcoe_ctlr_destroy(fip); scsi_host_put(fip->lp->host); - fcoe_ctlr_device_delete(ctlr_dev); dev_put(netdev); module_put(THIS_MODULE); } @@ -2194,6 +2192,8 @@ static int fcoe_destroy(struct net_device *netdev) */ static void fcoe_destroy_work(struct work_struct *work) { + struct fcoe_ctlr_device *cdev; + struct fcoe_ctlr *ctlr; struct fcoe_port *port; struct fcoe_interface *fcoe; struct Scsi_Host *shost; @@ -2224,10 +2224,15 @@ static void fcoe_destroy_work(struct work_struct *work) mutex_lock(&fcoe_config_mutex); fcoe = port->priv; + ctlr = fcoe_to_ctlr(fcoe); + cdev = fcoe_ctlr_to_ctlr_dev(ctlr); + fcoe_if_destroy(port->lport); fcoe_interface_cleanup(fcoe); mutex_unlock(&fcoe_config_mutex); + + fcoe_ctlr_device_delete(cdev); } /** @@ -2335,7 +2340,9 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode, rc = -EIO; rtnl_unlock(); fcoe_interface_cleanup(fcoe); - goto out_nortnl; + mutex_unlock(&fcoe_config_mutex); + fcoe_ctlr_device_delete(ctlr_dev); + goto out; } /* Make this the "master" N_Port */ @@ -2375,8 +2382,8 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode, out_nodev: rtnl_unlock(); -out_nortnl: mutex_unlock(&fcoe_config_mutex); +out: return rc; } diff --git a/trunk/drivers/scsi/fcoe/fcoe_ctlr.c b/trunk/drivers/scsi/fcoe/fcoe_ctlr.c index 08c3bc398da2..a76247201be5 100644 --- a/trunk/drivers/scsi/fcoe/fcoe_ctlr.c +++ b/trunk/drivers/scsi/fcoe/fcoe_ctlr.c @@ -2814,6 +2814,47 @@ static void fcoe_ctlr_vn_timeout(struct fcoe_ctlr *fip) fc_lport_set_local_id(fip->lp, new_port_id); } +/** + * fcoe_ctlr_mode_set() - Set or reset the ctlr's mode + * @lport: The local port to be (re)configured + * @fip: The FCoE controller whose mode is changing + * @fip_mode: The new fip mode + * + * Note that the we shouldn't be changing the libfc discovery settings + * (fc_disc_config) while an lport is going through the libfc state + * machine. The mode can only be changed when a fcoe_ctlr device is + * disabled, so that should ensure that this routine is only called + * when nothing is happening. + */ +void fcoe_ctlr_mode_set(struct fc_lport *lport, struct fcoe_ctlr *fip, + enum fip_state fip_mode) +{ + void *priv; + + WARN_ON(lport->state != LPORT_ST_RESET && + lport->state != LPORT_ST_DISABLED); + + if (fip_mode == FIP_MODE_VN2VN) { + lport->rport_priv_size = sizeof(struct fcoe_rport); + lport->point_to_multipoint = 1; + lport->tt.disc_recv_req = fcoe_ctlr_disc_recv; + lport->tt.disc_start = fcoe_ctlr_disc_start; + lport->tt.disc_stop = fcoe_ctlr_disc_stop; + lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final; + priv = fip; + } else { + lport->rport_priv_size = 0; + lport->point_to_multipoint = 0; + lport->tt.disc_recv_req = NULL; + lport->tt.disc_start = NULL; + lport->tt.disc_stop = NULL; + lport->tt.disc_stop_final = NULL; + priv = lport; + } + + fc_disc_config(lport, priv); +} + /** * fcoe_libfc_config() - Sets up libfc related properties for local port * @lport: The local port to configure libfc for @@ -2833,21 +2874,9 @@ int fcoe_libfc_config(struct fc_lport *lport, struct fcoe_ctlr *fip, fc_exch_init(lport); fc_elsct_init(lport); fc_lport_init(lport); - if (fip->mode == FIP_MODE_VN2VN) - lport->rport_priv_size = sizeof(struct fcoe_rport); fc_rport_init(lport); - if (fip->mode == FIP_MODE_VN2VN) { - lport->point_to_multipoint = 1; - lport->tt.disc_recv_req = fcoe_ctlr_disc_recv; - lport->tt.disc_start = fcoe_ctlr_disc_start; - lport->tt.disc_stop = fcoe_ctlr_disc_stop; - lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final; - mutex_init(&lport->disc.disc_mutex); - INIT_LIST_HEAD(&lport->disc.rports); - lport->disc.priv = fip; - } else { - fc_disc_init(lport); - } + fc_disc_init(lport); + fcoe_ctlr_mode_set(lport, fip, fip->mode); return 0; } EXPORT_SYMBOL_GPL(fcoe_libfc_config); @@ -2875,6 +2904,7 @@ EXPORT_SYMBOL(fcoe_fcf_get_selected); void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev) { struct fcoe_ctlr *ctlr = fcoe_ctlr_device_priv(ctlr_dev); + struct fc_lport *lport = ctlr->lp; mutex_lock(&ctlr->ctlr_mutex); switch (ctlr_dev->mode) { @@ -2888,5 +2918,7 @@ void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev) } mutex_unlock(&ctlr->ctlr_mutex); + + fcoe_ctlr_mode_set(lport, ctlr, ctlr->mode); } EXPORT_SYMBOL(fcoe_ctlr_set_fip_mode); diff --git a/trunk/drivers/scsi/libfc/fc_disc.c b/trunk/drivers/scsi/libfc/fc_disc.c index 8e561e6a557c..880a9068ca12 100644 --- a/trunk/drivers/scsi/libfc/fc_disc.c +++ b/trunk/drivers/scsi/libfc/fc_disc.c @@ -712,12 +712,13 @@ static void fc_disc_stop_final(struct fc_lport *lport) } /** - * fc_disc_init() - Initialize the discovery layer for a local port - * @lport: The local port that needs the discovery layer to be initialized + * fc_disc_config() - Configure the discovery layer for a local port + * @lport: The local port that needs the discovery layer to be configured + * @priv: Private data structre for users of the discovery layer */ -int fc_disc_init(struct fc_lport *lport) +void fc_disc_config(struct fc_lport *lport, void *priv) { - struct fc_disc *disc; + struct fc_disc *disc = &lport->disc; if (!lport->tt.disc_start) lport->tt.disc_start = fc_disc_start; @@ -732,12 +733,21 @@ int fc_disc_init(struct fc_lport *lport) lport->tt.disc_recv_req = fc_disc_recv_req; disc = &lport->disc; + + disc->priv = priv; +} +EXPORT_SYMBOL(fc_disc_config); + +/** + * fc_disc_init() - Initialize the discovery layer for a local port + * @lport: The local port that needs the discovery layer to be initialized + */ +void fc_disc_init(struct fc_lport *lport) +{ + struct fc_disc *disc = &lport->disc; + INIT_DELAYED_WORK(&disc->disc_work, fc_disc_timeout); mutex_init(&disc->disc_mutex); INIT_LIST_HEAD(&disc->rports); - - disc->priv = lport; - - return 0; } EXPORT_SYMBOL(fc_disc_init); diff --git a/trunk/drivers/spi/Kconfig b/trunk/drivers/spi/Kconfig index f80eee74a311..2be0de920d67 100644 --- a/trunk/drivers/spi/Kconfig +++ b/trunk/drivers/spi/Kconfig @@ -55,6 +55,7 @@ comment "SPI Master Controller Drivers" config SPI_ALTERA tristate "Altera SPI Controller" + depends on GENERIC_HARDIRQS select SPI_BITBANG help This is the driver for the Altera SPI Controller. @@ -310,7 +311,7 @@ config SPI_PXA2XX_DMA config SPI_PXA2XX tristate "PXA2xx SSP SPI master" - depends on ARCH_PXA || PCI || ACPI + depends on (ARCH_PXA || PCI || ACPI) && GENERIC_HARDIRQS select PXA_SSP if ARCH_PXA help This enables using a PXA2xx or Sodaville SSP port as a SPI master diff --git a/trunk/drivers/spi/spi-bcm63xx.c b/trunk/drivers/spi/spi-bcm63xx.c index 9578af782a77..d7df435d962e 100644 --- a/trunk/drivers/spi/spi-bcm63xx.c +++ b/trunk/drivers/spi/spi-bcm63xx.c @@ -152,7 +152,6 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi, static int bcm63xx_spi_setup(struct spi_device *spi) { struct bcm63xx_spi *bs; - int ret; bs = spi_master_get_devdata(spi->master); @@ -490,7 +489,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev) default: dev_err(dev, "unsupported MSG_CTL width: %d\n", bs->msg_ctl_width); - goto out_clk_disable; + goto out_err; } /* Initialize hardware */ diff --git a/trunk/drivers/spi/spi-mpc512x-psc.c b/trunk/drivers/spi/spi-mpc512x-psc.c index 89480b281d74..3e490ee7f275 100644 --- a/trunk/drivers/spi/spi-mpc512x-psc.c +++ b/trunk/drivers/spi/spi-mpc512x-psc.c @@ -164,7 +164,7 @@ static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, for (i = count; i > 0; i--) { data = tx_buf ? *tx_buf++ : 0; - if (len == EOFBYTE) + if (len == EOFBYTE && t->cs_change) setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF); out_8(&fifo->txdata_8, data); len--; diff --git a/trunk/drivers/spi/spi-pxa2xx.c b/trunk/drivers/spi/spi-pxa2xx.c index 90b27a3508a6..810413883c79 100644 --- a/trunk/drivers/spi/spi-pxa2xx.c +++ b/trunk/drivers/spi/spi-pxa2xx.c @@ -1168,7 +1168,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) master->dev.parent = &pdev->dev; master->dev.of_node = pdev->dev.of_node; - ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev)); /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; diff --git a/trunk/drivers/spi/spi-s3c64xx.c b/trunk/drivers/spi/spi-s3c64xx.c index e862ab8853aa..4188b2faac5c 100644 --- a/trunk/drivers/spi/spi-s3c64xx.c +++ b/trunk/drivers/spi/spi-s3c64xx.c @@ -994,25 +994,30 @@ static irqreturn_t s3c64xx_spi_irq(int irq, void *data) { struct s3c64xx_spi_driver_data *sdd = data; struct spi_master *spi = sdd->master; - unsigned int val; + unsigned int val, clr = 0; - val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR); + val = readl(sdd->regs + S3C64XX_SPI_STATUS); - val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR | - S3C64XX_SPI_PND_RX_UNDERRUN_CLR | - S3C64XX_SPI_PND_TX_OVERRUN_CLR | - S3C64XX_SPI_PND_TX_UNDERRUN_CLR; - - writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR); - - if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR) + if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { + clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; dev_err(&spi->dev, "RX overrun\n"); - if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR) + } + if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { + clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; dev_err(&spi->dev, "RX underrun\n"); - if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR) + } + if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { + clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; dev_err(&spi->dev, "TX overrun\n"); - if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR) + } + if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { + clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; dev_err(&spi->dev, "TX underrun\n"); + } + + /* Clear the pending irq by setting and then clearing it */ + writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); + writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); return IRQ_HANDLED; } @@ -1036,9 +1041,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) writel(0, regs + S3C64XX_SPI_MODE_CFG); writel(0, regs + S3C64XX_SPI_PACKET_CNT); - /* Clear any irq pending bits */ - writel(readl(regs + S3C64XX_SPI_PENDING_CLR), - regs + S3C64XX_SPI_PENDING_CLR); + /* Clear any irq pending bits, should set and clear the bits */ + val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | + S3C64XX_SPI_PND_RX_UNDERRUN_CLR | + S3C64XX_SPI_PND_TX_OVERRUN_CLR | + S3C64XX_SPI_PND_TX_UNDERRUN_CLR; + writel(val, regs + S3C64XX_SPI_PENDING_CLR); + writel(0, regs + S3C64XX_SPI_PENDING_CLR); writel(0, regs + S3C64XX_SPI_SWAP_CFG); diff --git a/trunk/drivers/spi/spi-tegra20-slink.c b/trunk/drivers/spi/spi-tegra20-slink.c index b8698b389ef3..a829563f4713 100644 --- a/trunk/drivers/spi/spi-tegra20-slink.c +++ b/trunk/drivers/spi/spi-tegra20-slink.c @@ -858,21 +858,6 @@ static int tegra_slink_setup(struct spi_device *spi) return 0; } -static int tegra_slink_prepare_transfer(struct spi_master *master) -{ - struct tegra_slink_data *tspi = spi_master_get_devdata(master); - - return pm_runtime_get_sync(tspi->dev); -} - -static int tegra_slink_unprepare_transfer(struct spi_master *master) -{ - struct tegra_slink_data *tspi = spi_master_get_devdata(master); - - pm_runtime_put(tspi->dev); - return 0; -} - static int tegra_slink_transfer_one_message(struct spi_master *master, struct spi_message *msg) { @@ -885,6 +870,12 @@ static int tegra_slink_transfer_one_message(struct spi_master *master, msg->status = 0; msg->actual_length = 0; + ret = pm_runtime_get_sync(tspi->dev); + if (ret < 0) { + dev_err(tspi->dev, "runtime get failed: %d\n", ret); + goto done; + } + single_xfer = list_is_singular(&msg->transfers); list_for_each_entry(xfer, &msg->transfers, transfer_list) { INIT_COMPLETION(tspi->xfer_completion); @@ -921,6 +912,8 @@ static int tegra_slink_transfer_one_message(struct spi_master *master, exit: tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); + pm_runtime_put(tspi->dev); +done: msg->status = ret; spi_finalize_current_message(master); return ret; @@ -1148,9 +1141,7 @@ static int tegra_slink_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; master->setup = tegra_slink_setup; - master->prepare_transfer_hardware = tegra_slink_prepare_transfer; master->transfer_one_message = tegra_slink_transfer_one_message; - master->unprepare_transfer_hardware = tegra_slink_unprepare_transfer; master->num_chipselect = MAX_CHIP_SELECT; master->bus_num = -1; diff --git a/trunk/drivers/spi/spi.c b/trunk/drivers/spi/spi.c index f996c600eb8c..004b10f184d4 100644 --- a/trunk/drivers/spi/spi.c +++ b/trunk/drivers/spi/spi.c @@ -543,17 +543,16 @@ static void spi_pump_messages(struct kthread_work *work) /* Lock queue and check for queue work */ spin_lock_irqsave(&master->queue_lock, flags); if (list_empty(&master->queue) || !master->running) { - if (master->busy && master->unprepare_transfer_hardware) { - ret = master->unprepare_transfer_hardware(master); - if (ret) { - spin_unlock_irqrestore(&master->queue_lock, flags); - dev_err(&master->dev, - "failed to unprepare transfer hardware\n"); - return; - } + if (!master->busy) { + spin_unlock_irqrestore(&master->queue_lock, flags); + return; } master->busy = false; spin_unlock_irqrestore(&master->queue_lock, flags); + if (master->unprepare_transfer_hardware && + master->unprepare_transfer_hardware(master)) + dev_err(&master->dev, + "failed to unprepare transfer hardware\n"); return; } @@ -984,7 +983,7 @@ static void acpi_register_spi_devices(struct spi_master *master) acpi_status status; acpi_handle handle; - handle = ACPI_HANDLE(&master->dev); + handle = ACPI_HANDLE(master->dev.parent); if (!handle) return; diff --git a/trunk/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/trunk/drivers/staging/imx-drm/ipu-v3/ipu-common.c index 6efe4e1b499f..366f259e3756 100644 --- a/trunk/drivers/staging/imx-drm/ipu-v3/ipu-common.c +++ b/trunk/drivers/staging/imx-drm/ipu-v3/ipu-common.c @@ -25,8 +25,8 @@ #include #include #include -#include #include +#include #include "imx-ipu-v3.h" #include "ipu-prv.h" diff --git a/trunk/drivers/usb/core/port.c b/trunk/drivers/usb/core/port.c index 797f9d514732..65d4e55552c6 100644 --- a/trunk/drivers/usb/core/port.c +++ b/trunk/drivers/usb/core/port.c @@ -67,7 +67,6 @@ static void usb_port_device_release(struct device *dev) { struct usb_port *port_dev = to_usb_port(dev); - dev_pm_qos_hide_flags(dev); kfree(port_dev); } diff --git a/trunk/drivers/video/fbmon.c b/trunk/drivers/video/fbmon.c index 94ad0f71383c..7f6709991a5c 100644 --- a/trunk/drivers/video/fbmon.c +++ b/trunk/drivers/video/fbmon.c @@ -1400,7 +1400,7 @@ int fb_videomode_from_videomode(const struct videomode *vm, fbmode->vmode = 0; if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH) fbmode->sync |= FB_SYNC_HOR_HIGH_ACT; - if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH) + if (vm->dmt_flags & VESA_DMT_VSYNC_HIGH) fbmode->sync |= FB_SYNC_VERT_HIGH_ACT; if (vm->data_flags & DISPLAY_FLAGS_INTERLACED) fbmode->vmode |= FB_VMODE_INTERLACED; diff --git a/trunk/drivers/video/sh_mobile_lcdcfb.c b/trunk/drivers/video/sh_mobile_lcdcfb.c index 63203acef812..0264704a52be 100644 --- a/trunk/drivers/video/sh_mobile_lcdcfb.c +++ b/trunk/drivers/video/sh_mobile_lcdcfb.c @@ -858,6 +858,7 @@ static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch) tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16) | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7); lcdc_write_chan(ch, LDHAJR, tmp); + lcdc_write_chan_mirror(ch, LDHAJR, tmp); } static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl) diff --git a/trunk/drivers/video/uvesafb.c b/trunk/drivers/video/uvesafb.c index b75db0186488..d4284458377e 100644 --- a/trunk/drivers/video/uvesafb.c +++ b/trunk/drivers/video/uvesafb.c @@ -1973,7 +1973,8 @@ static int uvesafb_init(void) err = -ENOMEM; if (err) { - platform_device_put(uvesafb_device); + if (uvesafb_device) + platform_device_put(uvesafb_device); platform_driver_unregister(&uvesafb_driver); cn_del_callback(&uvesafb_cn_id); return err; diff --git a/trunk/firmware/Makefile b/trunk/firmware/Makefile index 5d8ee1319b5c..cbb09ce9730a 100644 --- a/trunk/firmware/Makefile +++ b/trunk/firmware/Makefile @@ -82,7 +82,7 @@ fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \ fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \ qlogic/12160.bin fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin -fw-shipped-$(CONFIG_INFINIBAND_QIB) += intel/sd7220.fw +fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \ ess/maestro3_assp_minisrc.fw diff --git a/trunk/firmware/intel/sd7220.fw.ihex b/trunk/firmware/qlogic/sd7220.fw.ihex similarity index 100% rename from trunk/firmware/intel/sd7220.fw.ihex rename to trunk/firmware/qlogic/sd7220.fw.ihex diff --git a/trunk/fs/block_dev.c b/trunk/fs/block_dev.c index aea605c98ba6..aae187a7f94a 100644 --- a/trunk/fs/block_dev.c +++ b/trunk/fs/block_dev.c @@ -551,6 +551,7 @@ struct block_device *bdgrab(struct block_device *bdev) ihold(bdev->bd_inode); return bdev; } +EXPORT_SYMBOL(bdgrab); long nr_blockdev_pages(void) { diff --git a/trunk/fs/ext4/extents.c b/trunk/fs/ext4/extents.c index 56efcaadf848..9c6d06dcef8b 100644 --- a/trunk/fs/ext4/extents.c +++ b/trunk/fs/ext4/extents.c @@ -2999,20 +2999,23 @@ static int ext4_split_extent_at(handle_t *handle, if (split_flag & EXT4_EXT_DATA_VALID1) { err = ext4_ext_zeroout(inode, ex2); zero_ex.ee_block = ex2->ee_block; - zero_ex.ee_len = ext4_ext_get_actual_len(ex2); + zero_ex.ee_len = cpu_to_le16( + ext4_ext_get_actual_len(ex2)); ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(ex2)); } else { err = ext4_ext_zeroout(inode, ex); zero_ex.ee_block = ex->ee_block; - zero_ex.ee_len = ext4_ext_get_actual_len(ex); + zero_ex.ee_len = cpu_to_le16( + ext4_ext_get_actual_len(ex)); ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(ex)); } } else { err = ext4_ext_zeroout(inode, &orig_ex); zero_ex.ee_block = orig_ex.ee_block; - zero_ex.ee_len = ext4_ext_get_actual_len(&orig_ex); + zero_ex.ee_len = cpu_to_le16( + ext4_ext_get_actual_len(&orig_ex)); ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(&orig_ex)); } @@ -3272,7 +3275,7 @@ static int ext4_ext_convert_to_initialized(handle_t *handle, if (err) goto out; zero_ex.ee_block = ex->ee_block; - zero_ex.ee_len = ext4_ext_get_actual_len(ex); + zero_ex.ee_len = cpu_to_le16(ext4_ext_get_actual_len(ex)); ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(ex)); err = ext4_ext_get_access(handle, inode, path + depth); diff --git a/trunk/fs/ext4/indirect.c b/trunk/fs/ext4/indirect.c index b505a145a593..a04183127ef0 100644 --- a/trunk/fs/ext4/indirect.c +++ b/trunk/fs/ext4/indirect.c @@ -1539,9 +1539,9 @@ static int free_hole_blocks(handle_t *handle, struct inode *inode, blk = *i_data; if (level > 0) { ext4_lblk_t first2; - bh = sb_bread(inode->i_sb, blk); + bh = sb_bread(inode->i_sb, le32_to_cpu(blk)); if (!bh) { - EXT4_ERROR_INODE_BLOCK(inode, blk, + EXT4_ERROR_INODE_BLOCK(inode, le32_to_cpu(blk), "Read failure"); return -EIO; } diff --git a/trunk/fs/gfs2/file.c b/trunk/fs/gfs2/file.c index 019f45e45097..d79c2dadc536 100644 --- a/trunk/fs/gfs2/file.c +++ b/trunk/fs/gfs2/file.c @@ -923,8 +923,11 @@ static int gfs2_lock(struct file *file, int cmd, struct file_lock *fl) cmd = F_SETLK; fl->fl_type = F_UNLCK; } - if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags))) + if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags))) { + if (fl->fl_type == F_UNLCK) + posix_lock_file_wait(file, fl); return -EIO; + } if (IS_GETLK(cmd)) return dlm_posix_get(ls->ls_dlm, ip->i_no_addr, file, fl); else if (fl->fl_type == F_UNLCK) diff --git a/trunk/fs/gfs2/incore.h b/trunk/fs/gfs2/incore.h index 156e42ec84ea..5c29216e9cc1 100644 --- a/trunk/fs/gfs2/incore.h +++ b/trunk/fs/gfs2/incore.h @@ -588,6 +588,7 @@ struct lm_lockstruct { struct dlm_lksb ls_control_lksb; /* control_lock */ char ls_control_lvb[GDLM_LVB_SIZE]; /* control_lock lvb */ struct completion ls_sync_wait; /* {control,mounted}_{lock,unlock} */ + char *ls_lvb_bits; spinlock_t ls_recover_spin; /* protects following fields */ unsigned long ls_recover_flags; /* DFL_ */ diff --git a/trunk/fs/gfs2/lock_dlm.c b/trunk/fs/gfs2/lock_dlm.c index 9802de0f85e6..c8423d6de6c3 100644 --- a/trunk/fs/gfs2/lock_dlm.c +++ b/trunk/fs/gfs2/lock_dlm.c @@ -483,12 +483,8 @@ static void control_lvb_write(struct lm_lockstruct *ls, uint32_t lvb_gen, static int all_jid_bits_clear(char *lvb) { - int i; - for (i = JID_BITMAP_OFFSET; i < GDLM_LVB_SIZE; i++) { - if (lvb[i]) - return 0; - } - return 1; + return !memchr_inv(lvb + JID_BITMAP_OFFSET, 0, + GDLM_LVB_SIZE - JID_BITMAP_OFFSET); } static void sync_wait_cb(void *arg) @@ -580,7 +576,6 @@ static void gfs2_control_func(struct work_struct *work) { struct gfs2_sbd *sdp = container_of(work, struct gfs2_sbd, sd_control_work.work); struct lm_lockstruct *ls = &sdp->sd_lockstruct; - char lvb_bits[GDLM_LVB_SIZE]; uint32_t block_gen, start_gen, lvb_gen, flags; int recover_set = 0; int write_lvb = 0; @@ -634,7 +629,7 @@ static void gfs2_control_func(struct work_struct *work) return; } - control_lvb_read(ls, &lvb_gen, lvb_bits); + control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits); spin_lock(&ls->ls_recover_spin); if (block_gen != ls->ls_recover_block || @@ -664,10 +659,10 @@ static void gfs2_control_func(struct work_struct *work) ls->ls_recover_result[i] = 0; - if (!test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET)) + if (!test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET)) continue; - __clear_bit_le(i, lvb_bits + JID_BITMAP_OFFSET); + __clear_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET); write_lvb = 1; } } @@ -691,7 +686,7 @@ static void gfs2_control_func(struct work_struct *work) continue; if (ls->ls_recover_submit[i] < start_gen) { ls->ls_recover_submit[i] = 0; - __set_bit_le(i, lvb_bits + JID_BITMAP_OFFSET); + __set_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET); } } /* even if there are no bits to set, we need to write the @@ -705,7 +700,7 @@ static void gfs2_control_func(struct work_struct *work) spin_unlock(&ls->ls_recover_spin); if (write_lvb) { - control_lvb_write(ls, start_gen, lvb_bits); + control_lvb_write(ls, start_gen, ls->ls_lvb_bits); flags = DLM_LKF_CONVERT | DLM_LKF_VALBLK; } else { flags = DLM_LKF_CONVERT; @@ -725,7 +720,7 @@ static void gfs2_control_func(struct work_struct *work) */ for (i = 0; i < recover_size; i++) { - if (test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET)) { + if (test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET)) { fs_info(sdp, "recover generation %u jid %d\n", start_gen, i); gfs2_recover_set(sdp, i); @@ -758,7 +753,6 @@ static void gfs2_control_func(struct work_struct *work) static int control_mount(struct gfs2_sbd *sdp) { struct lm_lockstruct *ls = &sdp->sd_lockstruct; - char lvb_bits[GDLM_LVB_SIZE]; uint32_t start_gen, block_gen, mount_gen, lvb_gen; int mounted_mode; int retries = 0; @@ -857,7 +851,7 @@ static int control_mount(struct gfs2_sbd *sdp) * lvb_gen will be non-zero. */ - control_lvb_read(ls, &lvb_gen, lvb_bits); + control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits); if (lvb_gen == 0xFFFFFFFF) { /* special value to force mount attempts to fail */ @@ -887,7 +881,7 @@ static int control_mount(struct gfs2_sbd *sdp) * and all lvb bits to be clear (no pending journal recoveries.) */ - if (!all_jid_bits_clear(lvb_bits)) { + if (!all_jid_bits_clear(ls->ls_lvb_bits)) { /* journals need recovery, wait until all are clear */ fs_info(sdp, "control_mount wait for journal recovery\n"); goto restart; @@ -949,7 +943,6 @@ static int dlm_recovery_wait(void *word) static int control_first_done(struct gfs2_sbd *sdp) { struct lm_lockstruct *ls = &sdp->sd_lockstruct; - char lvb_bits[GDLM_LVB_SIZE]; uint32_t start_gen, block_gen; int error; @@ -991,8 +984,8 @@ static int control_first_done(struct gfs2_sbd *sdp) memset(ls->ls_recover_result, 0, ls->ls_recover_size*sizeof(uint32_t)); spin_unlock(&ls->ls_recover_spin); - memset(lvb_bits, 0, sizeof(lvb_bits)); - control_lvb_write(ls, start_gen, lvb_bits); + memset(ls->ls_lvb_bits, 0, GDLM_LVB_SIZE); + control_lvb_write(ls, start_gen, ls->ls_lvb_bits); error = mounted_lock(sdp, DLM_LOCK_PR, DLM_LKF_CONVERT); if (error) @@ -1022,6 +1015,12 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots, uint32_t old_size, new_size; int i, max_jid; + if (!ls->ls_lvb_bits) { + ls->ls_lvb_bits = kzalloc(GDLM_LVB_SIZE, GFP_NOFS); + if (!ls->ls_lvb_bits) + return -ENOMEM; + } + max_jid = 0; for (i = 0; i < num_slots; i++) { if (max_jid < slots[i].slot - 1) @@ -1057,6 +1056,7 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots, static void free_recover_size(struct lm_lockstruct *ls) { + kfree(ls->ls_lvb_bits); kfree(ls->ls_recover_submit); kfree(ls->ls_recover_result); ls->ls_recover_submit = NULL; @@ -1205,6 +1205,7 @@ static int gdlm_mount(struct gfs2_sbd *sdp, const char *table) ls->ls_recover_size = 0; ls->ls_recover_submit = NULL; ls->ls_recover_result = NULL; + ls->ls_lvb_bits = NULL; error = set_recover_size(sdp, NULL, 0); if (error) diff --git a/trunk/fs/gfs2/rgrp.c b/trunk/fs/gfs2/rgrp.c index d1f51fd73f86..5a51265a4341 100644 --- a/trunk/fs/gfs2/rgrp.c +++ b/trunk/fs/gfs2/rgrp.c @@ -576,7 +576,7 @@ int gfs2_rs_alloc(struct gfs2_inode *ip) RB_CLEAR_NODE(&ip->i_res->rs_node); out: up_write(&ip->i_rw_mutex); - return 0; + return error; } static void dump_rs(struct seq_file *seq, const struct gfs2_blkreserv *rs) @@ -1181,12 +1181,9 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset, const struct gfs2_bitmap *bi, unsigned minlen, u64 *ptrimmed) { struct super_block *sb = sdp->sd_vfs; - struct block_device *bdev = sb->s_bdev; - const unsigned int sects_per_blk = sdp->sd_sb.sb_bsize / - bdev_logical_block_size(sb->s_bdev); u64 blk; sector_t start = 0; - sector_t nr_sects = 0; + sector_t nr_blks = 0; int rv; unsigned int x; u32 trimmed = 0; @@ -1206,35 +1203,34 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset, if (diff == 0) continue; blk = offset + ((bi->bi_start + x) * GFS2_NBBY); - blk *= sects_per_blk; /* convert to sectors */ while(diff) { if (diff & 1) { - if (nr_sects == 0) + if (nr_blks == 0) goto start_new_extent; - if ((start + nr_sects) != blk) { - if (nr_sects >= minlen) { - rv = blkdev_issue_discard(bdev, - start, nr_sects, + if ((start + nr_blks) != blk) { + if (nr_blks >= minlen) { + rv = sb_issue_discard(sb, + start, nr_blks, GFP_NOFS, 0); if (rv) goto fail; - trimmed += nr_sects; + trimmed += nr_blks; } - nr_sects = 0; + nr_blks = 0; start_new_extent: start = blk; } - nr_sects += sects_per_blk; + nr_blks++; } diff >>= 2; - blk += sects_per_blk; + blk++; } } - if (nr_sects >= minlen) { - rv = blkdev_issue_discard(bdev, start, nr_sects, GFP_NOFS, 0); + if (nr_blks >= minlen) { + rv = sb_issue_discard(sb, start, nr_blks, GFP_NOFS, 0); if (rv) goto fail; - trimmed += nr_sects; + trimmed += nr_blks; } if (ptrimmed) *ptrimmed = trimmed; diff --git a/trunk/fs/nfsd/nfs4xdr.c b/trunk/fs/nfsd/nfs4xdr.c index 01168865dd37..a2720071f282 100644 --- a/trunk/fs/nfsd/nfs4xdr.c +++ b/trunk/fs/nfsd/nfs4xdr.c @@ -264,7 +264,7 @@ nfsd4_decode_fattr(struct nfsd4_compoundargs *argp, u32 *bmval, iattr->ia_valid |= ATTR_SIZE; } if (bmval[0] & FATTR4_WORD0_ACL) { - int nace; + u32 nace; struct nfs4_ace *ace; READ_BUF(4); len += 4; diff --git a/trunk/fs/reiserfs/xattr.c b/trunk/fs/reiserfs/xattr.c index c196369fe408..4cce1d9552fb 100644 --- a/trunk/fs/reiserfs/xattr.c +++ b/trunk/fs/reiserfs/xattr.c @@ -187,8 +187,8 @@ fill_with_dentries(void *buf, const char *name, int namelen, loff_t offset, if (dbuf->count == ARRAY_SIZE(dbuf->dentries)) return -ENOSPC; - if (name[0] == '.' && (name[1] == '\0' || - (name[1] == '.' && name[2] == '\0'))) + if (name[0] == '.' && (namelen < 2 || + (namelen == 2 && name[1] == '.'))) return 0; dentry = lookup_one_len(name, dbuf->xadir, namelen); diff --git a/trunk/fs/ubifs/super.c b/trunk/fs/ubifs/super.c index ac838b844936..f21acf0ef01f 100644 --- a/trunk/fs/ubifs/super.c +++ b/trunk/fs/ubifs/super.c @@ -1568,6 +1568,12 @@ static int ubifs_remount_rw(struct ubifs_info *c) c->remounting_rw = 1; c->ro_mount = 0; + if (c->space_fixup) { + err = ubifs_fixup_free_space(c); + if (err) + return err; + } + err = check_free_space(c); if (err) goto out; @@ -1684,12 +1690,6 @@ static int ubifs_remount_rw(struct ubifs_info *c) err = dbg_check_space_info(c); } - if (c->space_fixup) { - err = ubifs_fixup_free_space(c); - if (err) - goto out; - } - mutex_unlock(&c->umount_mutex); return err; diff --git a/trunk/include/linux/clocksource.h b/trunk/include/linux/clocksource.h index 192d6d1771ee..27cfda427dd9 100644 --- a/trunk/include/linux/clocksource.h +++ b/trunk/include/linux/clocksource.h @@ -332,23 +332,15 @@ extern int clocksource_mmio_init(void __iomem *, const char *, extern int clocksource_i8253_init(void); -struct device_node; -typedef void(*clocksource_of_init_fn)(struct device_node *); #ifdef CONFIG_CLKSRC_OF extern void clocksource_of_init(void); #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ static const struct of_device_id __clksrc_of_table_##name \ __used __section(__clksrc_of_table) \ - = { .compatible = compat, \ - .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } + = { .compatible = compat, .data = fn }; #else -static inline void clocksource_of_init(void) {} -#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ - static const struct of_device_id __clksrc_of_table_##name \ - __attribute__((unused)) \ - = { .compatible = compat, \ - .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } +#define CLOCKSOURCE_OF_DECLARE(name, compat, fn) #endif #endif /* _LINUX_CLOCKSOURCE_H */ diff --git a/trunk/include/linux/compat.h b/trunk/include/linux/compat.h index 76a87fb57ac2..377cd8c3395e 100644 --- a/trunk/include/linux/compat.h +++ b/trunk/include/linux/compat.h @@ -141,11 +141,11 @@ typedef struct { } compat_sigset_t; struct compat_sigaction { -#ifndef __ARCH_HAS_ODD_SIGACTION +#ifndef __ARCH_HAS_IRIX_SIGACTION compat_uptr_t sa_handler; compat_ulong_t sa_flags; #else - compat_ulong_t sa_flags; + compat_uint_t sa_flags; compat_uptr_t sa_handler; #endif #ifdef __ARCH_HAS_SA_RESTORER diff --git a/trunk/include/linux/devfreq.h b/trunk/include/linux/devfreq.h index e83ef39b3bea..fe8c4476f7e4 100644 --- a/trunk/include/linux/devfreq.h +++ b/trunk/include/linux/devfreq.h @@ -213,7 +213,7 @@ struct devfreq_simple_ondemand_data { #endif #else /* !CONFIG_PM_DEVFREQ */ -static struct devfreq *devfreq_add_device(struct device *dev, +static inline struct devfreq *devfreq_add_device(struct device *dev, struct devfreq_dev_profile *profile, const char *governor_name, void *data) @@ -221,34 +221,34 @@ static struct devfreq *devfreq_add_device(struct device *dev, return NULL; } -static int devfreq_remove_device(struct devfreq *devfreq) +static inline int devfreq_remove_device(struct devfreq *devfreq) { return 0; } -static int devfreq_suspend_device(struct devfreq *devfreq) +static inline int devfreq_suspend_device(struct devfreq *devfreq) { return 0; } -static int devfreq_resume_device(struct devfreq *devfreq) +static inline int devfreq_resume_device(struct devfreq *devfreq) { return 0; } -static struct opp *devfreq_recommended_opp(struct device *dev, +static inline struct opp *devfreq_recommended_opp(struct device *dev, unsigned long *freq, u32 flags) { - return -EINVAL; + return ERR_PTR(-EINVAL); } -static int devfreq_register_opp_notifier(struct device *dev, +static inline int devfreq_register_opp_notifier(struct device *dev, struct devfreq *devfreq) { return -EINVAL; } -static int devfreq_unregister_opp_notifier(struct device *dev, +static inline int devfreq_unregister_opp_notifier(struct device *dev, struct devfreq *devfreq) { return -EINVAL; diff --git a/trunk/include/linux/irqchip/arm-gic.h b/trunk/include/linux/irqchip/arm-gic.h index 3e203eb23cc7..3fd8e4290a1c 100644 --- a/trunk/include/linux/irqchip/arm-gic.h +++ b/trunk/include/linux/irqchip/arm-gic.h @@ -65,6 +65,7 @@ extern struct irq_chip gic_arch_extn; void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, u32 offset, struct device_node *); +void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); static inline void gic_init(unsigned int nr, int start, diff --git a/trunk/include/linux/irqchip/chained_irq.h b/trunk/include/linux/irqchip/chained_irq.h deleted file mode 100644 index adf4c30f3af6..000000000000 --- a/trunk/include/linux/irqchip/chained_irq.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Chained IRQ handlers support. - * - * Copyright (C) 2011 ARM Ltd. - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __IRQCHIP_CHAINED_IRQ_H -#define __IRQCHIP_CHAINED_IRQ_H - -#include - -/* - * Entry/exit functions for chained handlers where the primary IRQ chip - * may implement either fasteoi or level-trigger flow control. - */ -static inline void chained_irq_enter(struct irq_chip *chip, - struct irq_desc *desc) -{ - /* FastEOI controllers require no action on entry. */ - if (chip->irq_eoi) - return; - - if (chip->irq_mask_ack) { - chip->irq_mask_ack(&desc->irq_data); - } else { - chip->irq_mask(&desc->irq_data); - if (chip->irq_ack) - chip->irq_ack(&desc->irq_data); - } -} - -static inline void chained_irq_exit(struct irq_chip *chip, - struct irq_desc *desc) -{ - if (chip->irq_eoi) - chip->irq_eoi(&desc->irq_data); - else - chip->irq_unmask(&desc->irq_data); -} - -#endif /* __IRQCHIP_CHAINED_IRQ_H */ diff --git a/trunk/include/linux/kvm_host.h b/trunk/include/linux/kvm_host.h index cad77fe09d77..c13958251927 100644 --- a/trunk/include/linux/kvm_host.h +++ b/trunk/include/linux/kvm_host.h @@ -518,7 +518,7 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data, int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc, void *data, unsigned long len); int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc, - gpa_t gpa); + gpa_t gpa, unsigned long len); int kvm_clear_guest_page(struct kvm *kvm, gfn_t gfn, int offset, int len); int kvm_clear_guest(struct kvm *kvm, gpa_t gpa, unsigned long len); struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn); diff --git a/trunk/include/linux/kvm_types.h b/trunk/include/linux/kvm_types.h index fa7cc7244cbd..b0bcce0ddc95 100644 --- a/trunk/include/linux/kvm_types.h +++ b/trunk/include/linux/kvm_types.h @@ -71,6 +71,7 @@ struct gfn_to_hva_cache { u64 generation; gpa_t gpa; unsigned long hva; + unsigned long len; struct kvm_memory_slot *memslot; }; diff --git a/trunk/include/linux/netdevice.h b/trunk/include/linux/netdevice.h index b3d00fa4b314..6151e903eef0 100644 --- a/trunk/include/linux/netdevice.h +++ b/trunk/include/linux/netdevice.h @@ -210,9 +210,9 @@ struct netdev_hw_addr { #define NETDEV_HW_ADDR_T_SLAVE 3 #define NETDEV_HW_ADDR_T_UNICAST 4 #define NETDEV_HW_ADDR_T_MULTICAST 5 - bool synced; bool global_use; int refcount; + int synced; struct rcu_head rcu_head; }; @@ -895,7 +895,7 @@ struct netdev_fcoe_hbainfo { * * int (*ndo_bridge_setlink)(struct net_device *dev, struct nlmsghdr *nlh) * int (*ndo_bridge_getlink)(struct sk_buff *skb, u32 pid, u32 seq, - * struct net_device *dev) + * struct net_device *dev, u32 filter_mask) * * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier); * Called to change device carrier. Soft-devices (like dummy, team, etc) diff --git a/trunk/include/linux/pci.h b/trunk/include/linux/pci.h index 2461033a7987..710067f3618c 100644 --- a/trunk/include/linux/pci.h +++ b/trunk/include/linux/pci.h @@ -916,6 +916,7 @@ void pci_disable_rom(struct pci_dev *pdev); void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); +void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); /* Power management related routines */ int pci_save_state(struct pci_dev *dev); diff --git a/trunk/include/linux/pinctrl/pinctrl.h b/trunk/include/linux/pinctrl/pinctrl.h index 2c2a9e8d8578..778804df293f 100644 --- a/trunk/include/linux/pinctrl/pinctrl.h +++ b/trunk/include/linux/pinctrl/pinctrl.h @@ -118,9 +118,9 @@ struct pinctrl_desc { const char *name; struct pinctrl_pin_desc const *pins; unsigned int npins; - const struct pinctrl_ops *pctlops; - const struct pinmux_ops *pmxops; - const struct pinconf_ops *confops; + struct pinctrl_ops *pctlops; + struct pinmux_ops *pmxops; + struct pinconf_ops *confops; struct module *owner; }; diff --git a/trunk/include/linux/platform_data/gpio-rcar.h b/trunk/include/linux/platform_data/gpio-rcar.h deleted file mode 100644 index b253f77a7ddf..000000000000 --- a/trunk/include/linux/platform_data/gpio-rcar.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Renesas R-Car GPIO Support - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __GPIO_RCAR_H__ -#define __GPIO_RCAR_H__ - -struct gpio_rcar_config { - unsigned int gpio_base; - unsigned int irq_base; - unsigned int number_of_pins; - const char *pctl_name; -}; - -#endif /* __GPIO_RCAR_H__ */ diff --git a/trunk/include/linux/platform_data/irq-renesas-intc-irqpin.h b/trunk/include/linux/platform_data/irq-renesas-intc-irqpin.h deleted file mode 100644 index e4cb911066a6..000000000000 --- a/trunk/include/linux/platform_data/irq-renesas-intc-irqpin.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Renesas INTC External IRQ Pin Driver - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__ -#define __IRQ_RENESAS_INTC_IRQPIN_H__ - -struct renesas_intc_irqpin_config { - unsigned int sense_bitfield_width; - unsigned int irq_base; - bool control_parent; -}; - -#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */ diff --git a/trunk/include/linux/platform_data/irq-renesas-irqc.h b/trunk/include/linux/platform_data/irq-renesas-irqc.h deleted file mode 100644 index 3ae17b3e00ed..000000000000 --- a/trunk/include/linux/platform_data/irq-renesas-irqc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Renesas IRQC Driver - * - * Copyright (C) 2013 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __IRQ_RENESAS_IRQC_H__ -#define __IRQ_RENESAS_IRQC_H__ - -struct renesas_irqc_config { - unsigned int irq_base; -}; - -#endif /* __IRQ_RENESAS_IRQC_H__ */ diff --git a/trunk/include/linux/signal.h b/trunk/include/linux/signal.h index a2dcb94ea49d..9475c5cb28bc 100644 --- a/trunk/include/linux/signal.h +++ b/trunk/include/linux/signal.h @@ -250,11 +250,11 @@ extern int show_unhandled_signals; extern int sigsuspend(sigset_t *); struct sigaction { -#ifndef __ARCH_HAS_ODD_SIGACTION +#ifndef __ARCH_HAS_IRIX_SIGACTION __sighandler_t sa_handler; unsigned long sa_flags; #else - unsigned long sa_flags; + unsigned int sa_flags; __sighandler_t sa_handler; #endif #ifdef __ARCH_HAS_SA_RESTORER diff --git a/trunk/include/linux/skbuff.h b/trunk/include/linux/skbuff.h index 441f5bfdab8e..b8292d8cc9fa 100644 --- a/trunk/include/linux/skbuff.h +++ b/trunk/include/linux/skbuff.h @@ -2643,6 +2643,13 @@ static inline void nf_reset(struct sk_buff *skb) #endif } +static inline void nf_reset_trace(struct sk_buff *skb) +{ +#if IS_ENABLED(CONFIG_NETFILTER_XT_TARGET_TRACE) + skb->nf_trace = 0; +#endif +} + /* Note: This doesn't put any conntrack and bridge info in dst. */ static inline void __nf_copy(struct sk_buff *dst, const struct sk_buff *src) { diff --git a/trunk/include/scsi/libfc.h b/trunk/include/scsi/libfc.h index 399162b50a8d..e1379b4e8faf 100644 --- a/trunk/include/scsi/libfc.h +++ b/trunk/include/scsi/libfc.h @@ -1074,7 +1074,8 @@ void fc_rport_terminate_io(struct fc_rport *); /* * DISCOVERY LAYER *****************************/ -int fc_disc_init(struct fc_lport *); +void fc_disc_init(struct fc_lport *); +void fc_disc_config(struct fc_lport *, void *); static inline struct fc_lport *fc_disc_lport(struct fc_disc *disc) { diff --git a/trunk/include/sound/max98090.h b/trunk/include/sound/max98090.h old mode 100755 new mode 100644 diff --git a/trunk/include/sound/soc-dapm.h b/trunk/include/sound/soc-dapm.h index e1ef63d4a5c4..44a30b108683 100644 --- a/trunk/include/sound/soc-dapm.h +++ b/trunk/include/sound/soc-dapm.h @@ -488,6 +488,7 @@ struct snd_soc_dapm_path { /* status */ u32 connect:1; /* source and sink widgets are connected */ u32 walked:1; /* path has been walked */ + u32 walking:1; /* path is in the process of being walked */ u32 weak:1; /* path ignored for power management */ int (*connected)(struct snd_soc_dapm_widget *source, diff --git a/trunk/ipc/msg.c b/trunk/ipc/msg.c index 31cd1bf6af27..fede1d06ef30 100644 --- a/trunk/ipc/msg.c +++ b/trunk/ipc/msg.c @@ -872,6 +872,7 @@ long do_msgrcv(int msqid, void __user *buf, size_t bufsz, long msgtyp, goto out_unlock; break; } + msg = ERR_PTR(-EAGAIN); } else break; msg_counter++; diff --git a/trunk/mm/mmap.c b/trunk/mm/mmap.c index 6466699b16cb..0db0de1c2fbe 100644 --- a/trunk/mm/mmap.c +++ b/trunk/mm/mmap.c @@ -1940,7 +1940,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr) /* Check the cache first. */ /* (Cache hit rate is typically around 35%.) */ - vma = mm->mmap_cache; + vma = ACCESS_ONCE(mm->mmap_cache); if (!(vma && vma->vm_end > addr && vma->vm_start <= addr)) { struct rb_node *rb_node; diff --git a/trunk/mm/nommu.c b/trunk/mm/nommu.c index e19328087534..2f3ea749c318 100644 --- a/trunk/mm/nommu.c +++ b/trunk/mm/nommu.c @@ -821,7 +821,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr) struct vm_area_struct *vma; /* check the cache first */ - vma = mm->mmap_cache; + vma = ACCESS_ONCE(mm->mmap_cache); if (vma && vma->vm_start <= addr && vma->vm_end > addr) return vma; diff --git a/trunk/net/core/dev.c b/trunk/net/core/dev.c index b13e5c766c11..e7d68ed8aafe 100644 --- a/trunk/net/core/dev.c +++ b/trunk/net/core/dev.c @@ -1624,7 +1624,6 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb) } skb_orphan(skb); - nf_reset(skb); if (unlikely(!is_skb_forwardable(dev, skb))) { atomic_long_inc(&dev->rx_dropped); @@ -1640,6 +1639,7 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb) skb->mark = 0; secpath_reset(skb); nf_reset(skb); + nf_reset_trace(skb); return netif_rx(skb); } EXPORT_SYMBOL_GPL(dev_forward_skb); @@ -3314,6 +3314,7 @@ int netdev_rx_handler_register(struct net_device *dev, if (dev->rx_handler) return -EBUSY; + /* Note: rx_handler_data must be set before rx_handler */ rcu_assign_pointer(dev->rx_handler_data, rx_handler_data); rcu_assign_pointer(dev->rx_handler, rx_handler); @@ -3334,6 +3335,11 @@ void netdev_rx_handler_unregister(struct net_device *dev) ASSERT_RTNL(); RCU_INIT_POINTER(dev->rx_handler, NULL); + /* a reader seeing a non NULL rx_handler in a rcu_read_lock() + * section has a guarantee to see a non NULL rx_handler_data + * as well. + */ + synchronize_net(); RCU_INIT_POINTER(dev->rx_handler_data, NULL); } EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister); diff --git a/trunk/net/core/dev_addr_lists.c b/trunk/net/core/dev_addr_lists.c index bd2eb9d3e369..abdc9e6ef33e 100644 --- a/trunk/net/core/dev_addr_lists.c +++ b/trunk/net/core/dev_addr_lists.c @@ -37,7 +37,7 @@ static int __hw_addr_create_ex(struct netdev_hw_addr_list *list, ha->type = addr_type; ha->refcount = 1; ha->global_use = global; - ha->synced = false; + ha->synced = 0; list_add_tail_rcu(&ha->list, &list->list); list->count++; @@ -165,7 +165,7 @@ int __hw_addr_sync(struct netdev_hw_addr_list *to_list, addr_len, ha->type); if (err) break; - ha->synced = true; + ha->synced++; ha->refcount++; } else if (ha->refcount == 1) { __hw_addr_del(to_list, ha->addr, addr_len, ha->type); @@ -186,7 +186,7 @@ void __hw_addr_unsync(struct netdev_hw_addr_list *to_list, if (ha->synced) { __hw_addr_del(to_list, ha->addr, addr_len, ha->type); - ha->synced = false; + ha->synced--; __hw_addr_del(from_list, ha->addr, addr_len, ha->type); } diff --git a/trunk/net/core/flow.c b/trunk/net/core/flow.c index c56ea6f7f6c7..2bfd081c59f7 100644 --- a/trunk/net/core/flow.c +++ b/trunk/net/core/flow.c @@ -328,7 +328,7 @@ static void flow_cache_flush_per_cpu(void *data) struct flow_flush_info *info = data; struct tasklet_struct *tasklet; - tasklet = this_cpu_ptr(&info->cache->percpu->flush_tasklet); + tasklet = &this_cpu_ptr(info->cache->percpu)->flush_tasklet; tasklet->data = (unsigned long)info; tasklet_schedule(tasklet); } diff --git a/trunk/net/core/rtnetlink.c b/trunk/net/core/rtnetlink.c index 5fb8d7e47294..b65441da74ab 100644 --- a/trunk/net/core/rtnetlink.c +++ b/trunk/net/core/rtnetlink.c @@ -496,8 +496,10 @@ static int rtnl_link_fill(struct sk_buff *skb, const struct net_device *dev) } if (ops->fill_info) { data = nla_nest_start(skb, IFLA_INFO_DATA); - if (data == NULL) + if (data == NULL) { + err = -EMSGSIZE; goto err_cancel_link; + } err = ops->fill_info(skb, dev); if (err < 0) goto err_cancel_data; diff --git a/trunk/net/ipv4/devinet.c b/trunk/net/ipv4/devinet.c index f678507bc829..96083b7a436b 100644 --- a/trunk/net/ipv4/devinet.c +++ b/trunk/net/ipv4/devinet.c @@ -802,8 +802,10 @@ static int inet_rtm_newaddr(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg if (nlh->nlmsg_flags & NLM_F_EXCL || !(nlh->nlmsg_flags & NLM_F_REPLACE)) return -EEXIST; - - set_ifa_lifetime(ifa_existing, valid_lft, prefered_lft); + ifa = ifa_existing; + set_ifa_lifetime(ifa, valid_lft, prefered_lft); + rtmsg_ifa(RTM_NEWADDR, ifa, nlh, NETLINK_CB(skb).portid); + blocking_notifier_call_chain(&inetaddr_chain, NETDEV_UP, ifa); } return 0; } diff --git a/trunk/net/ipv6/addrconf.c b/trunk/net/ipv6/addrconf.c index 26512250e095..a459c4f5b769 100644 --- a/trunk/net/ipv6/addrconf.c +++ b/trunk/net/ipv6/addrconf.c @@ -2529,6 +2529,9 @@ static void sit_add_v4_addrs(struct inet6_dev *idev) static void init_loopback(struct net_device *dev) { struct inet6_dev *idev; + struct net_device *sp_dev; + struct inet6_ifaddr *sp_ifa; + struct rt6_info *sp_rt; /* ::1 */ @@ -2540,6 +2543,30 @@ static void init_loopback(struct net_device *dev) } add_addr(idev, &in6addr_loopback, 128, IFA_HOST); + + /* Add routes to other interface's IPv6 addresses */ + for_each_netdev(dev_net(dev), sp_dev) { + if (!strcmp(sp_dev->name, dev->name)) + continue; + + idev = __in6_dev_get(sp_dev); + if (!idev) + continue; + + read_lock_bh(&idev->lock); + list_for_each_entry(sp_ifa, &idev->addr_list, if_list) { + + if (sp_ifa->flags & (IFA_F_DADFAILED | IFA_F_TENTATIVE)) + continue; + + sp_rt = addrconf_dst_alloc(idev, &sp_ifa->addr, 0); + + /* Failure cases are ignored */ + if (!IS_ERR(sp_rt)) + ip6_ins_rt(sp_rt); + } + read_unlock_bh(&idev->lock); + } } static void addrconf_add_linklocal(struct inet6_dev *idev, const struct in6_addr *addr) diff --git a/trunk/net/ipv6/ip6_input.c b/trunk/net/ipv6/ip6_input.c index e33fe0ab2568..2bab2aa59745 100644 --- a/trunk/net/ipv6/ip6_input.c +++ b/trunk/net/ipv6/ip6_input.c @@ -118,6 +118,18 @@ int ipv6_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt ipv6_addr_loopback(&hdr->daddr)) goto err; + /* RFC4291 Errata ID: 3480 + * Interface-Local scope spans only a single interface on a + * node and is useful only for loopback transmission of + * multicast. Packets with interface-local scope received + * from another node must be discarded. + */ + if (!(skb->pkt_type == PACKET_LOOPBACK || + dev->flags & IFF_LOOPBACK) && + ipv6_addr_is_multicast(&hdr->daddr) && + IPV6_ADDR_MC_SCOPE(&hdr->daddr) == 1) + goto err; + /* RFC4291 2.7 * Nodes must not originate a packet to a multicast address whose scope * field contains the reserved value 0; if such a packet is received, it diff --git a/trunk/net/ipv6/netfilter/ip6t_NPT.c b/trunk/net/ipv6/netfilter/ip6t_NPT.c index 33608c610276..cb631143721c 100644 --- a/trunk/net/ipv6/netfilter/ip6t_NPT.c +++ b/trunk/net/ipv6/netfilter/ip6t_NPT.c @@ -57,7 +57,7 @@ static bool ip6t_npt_map_pfx(const struct ip6t_npt_tginfo *npt, if (pfx_len - i >= 32) mask = 0; else - mask = htonl(~((1 << (pfx_len - i)) - 1)); + mask = htonl((1 << (i - pfx_len + 32)) - 1); idx = i / 32; addr->s6_addr32[idx] &= mask; diff --git a/trunk/net/key/af_key.c b/trunk/net/key/af_key.c index 8555f331ea60..5b1e5af25713 100644 --- a/trunk/net/key/af_key.c +++ b/trunk/net/key/af_key.c @@ -2693,6 +2693,7 @@ static int key_notify_policy_flush(const struct km_event *c) hdr->sadb_msg_pid = c->portid; hdr->sadb_msg_version = PF_KEY_V2; hdr->sadb_msg_errno = (uint8_t) 0; + hdr->sadb_msg_satype = SADB_SATYPE_UNSPEC; hdr->sadb_msg_len = (sizeof(struct sadb_msg) / sizeof(uint64_t)); pfkey_broadcast(skb_out, GFP_ATOMIC, BROADCAST_ALL, NULL, c->net); return 0; diff --git a/trunk/net/mac80211/cfg.c b/trunk/net/mac80211/cfg.c index fb306814576a..a6893602f87a 100644 --- a/trunk/net/mac80211/cfg.c +++ b/trunk/net/mac80211/cfg.c @@ -2582,7 +2582,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local, list_del(&dep->list); mutex_unlock(&local->mtx); - ieee80211_roc_notify_destroy(dep); + ieee80211_roc_notify_destroy(dep, true); return 0; } @@ -2622,7 +2622,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local, ieee80211_start_next_roc(local); mutex_unlock(&local->mtx); - ieee80211_roc_notify_destroy(found); + ieee80211_roc_notify_destroy(found, true); } else { /* work may be pending so use it all the time */ found->abort = true; @@ -2632,6 +2632,8 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local, /* work will clean up etc */ flush_delayed_work(&found->work); + WARN_ON(!found->to_be_freed); + kfree(found); } return 0; diff --git a/trunk/net/mac80211/chan.c b/trunk/net/mac80211/chan.c index 78c0d90dd641..931be419ab5a 100644 --- a/trunk/net/mac80211/chan.c +++ b/trunk/net/mac80211/chan.c @@ -63,6 +63,7 @@ ieee80211_new_chanctx(struct ieee80211_local *local, enum ieee80211_chanctx_mode mode) { struct ieee80211_chanctx *ctx; + u32 changed; int err; lockdep_assert_held(&local->chanctx_mtx); @@ -76,6 +77,13 @@ ieee80211_new_chanctx(struct ieee80211_local *local, ctx->conf.rx_chains_dynamic = 1; ctx->mode = mode; + /* acquire mutex to prevent idle from changing */ + mutex_lock(&local->mtx); + /* turn idle off *before* setting channel -- some drivers need that */ + changed = ieee80211_idle_off(local); + if (changed) + ieee80211_hw_config(local, changed); + if (!local->use_chanctx) { local->_oper_channel_type = cfg80211_get_chandef_type(chandef); @@ -85,14 +93,17 @@ ieee80211_new_chanctx(struct ieee80211_local *local, err = drv_add_chanctx(local, ctx); if (err) { kfree(ctx); - return ERR_PTR(err); + ctx = ERR_PTR(err); + + ieee80211_recalc_idle(local); + goto out; } } + /* and keep the mutex held until the new chanctx is on the list */ list_add_rcu(&ctx->list, &local->chanctx_list); - mutex_lock(&local->mtx); - ieee80211_recalc_idle(local); + out: mutex_unlock(&local->mtx); return ctx; diff --git a/trunk/net/mac80211/ieee80211_i.h b/trunk/net/mac80211/ieee80211_i.h index 388580a1bada..5672533a0832 100644 --- a/trunk/net/mac80211/ieee80211_i.h +++ b/trunk/net/mac80211/ieee80211_i.h @@ -309,6 +309,7 @@ struct ieee80211_roc_work { struct ieee80211_channel *chan; bool started, abort, hw_begun, notified; + bool to_be_freed; unsigned long hw_start_time; @@ -1347,7 +1348,7 @@ void ieee80211_offchannel_return(struct ieee80211_local *local); void ieee80211_roc_setup(struct ieee80211_local *local); void ieee80211_start_next_roc(struct ieee80211_local *local); void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata); -void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc); +void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free); void ieee80211_sw_roc_work(struct work_struct *work); void ieee80211_handle_roc_started(struct ieee80211_roc_work *roc); @@ -1361,6 +1362,7 @@ int ieee80211_if_change_type(struct ieee80211_sub_if_data *sdata, enum nl80211_iftype type); void ieee80211_if_remove(struct ieee80211_sub_if_data *sdata); void ieee80211_remove_interfaces(struct ieee80211_local *local); +u32 ieee80211_idle_off(struct ieee80211_local *local); void ieee80211_recalc_idle(struct ieee80211_local *local); void ieee80211_adjust_monitor_flags(struct ieee80211_sub_if_data *sdata, const int offset); diff --git a/trunk/net/mac80211/iface.c b/trunk/net/mac80211/iface.c index baaa8608e52d..58150f877ec3 100644 --- a/trunk/net/mac80211/iface.c +++ b/trunk/net/mac80211/iface.c @@ -78,7 +78,7 @@ void ieee80211_recalc_txpower(struct ieee80211_sub_if_data *sdata) ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_TXPOWER); } -static u32 ieee80211_idle_off(struct ieee80211_local *local) +u32 ieee80211_idle_off(struct ieee80211_local *local) { if (!(local->hw.conf.flags & IEEE80211_CONF_IDLE)) return 0; @@ -349,21 +349,19 @@ static void ieee80211_set_default_queues(struct ieee80211_sub_if_data *sdata) static int ieee80211_add_virtual_monitor(struct ieee80211_local *local) { struct ieee80211_sub_if_data *sdata; - int ret = 0; + int ret; if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF)) return 0; - mutex_lock(&local->iflist_mtx); + ASSERT_RTNL(); if (local->monitor_sdata) - goto out_unlock; + return 0; sdata = kzalloc(sizeof(*sdata) + local->hw.vif_data_size, GFP_KERNEL); - if (!sdata) { - ret = -ENOMEM; - goto out_unlock; - } + if (!sdata) + return -ENOMEM; /* set up data */ sdata->local = local; @@ -377,13 +375,13 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local) if (WARN_ON(ret)) { /* ok .. stupid driver, it asked for this! */ kfree(sdata); - goto out_unlock; + return ret; } ret = ieee80211_check_queues(sdata); if (ret) { kfree(sdata); - goto out_unlock; + return ret; } ret = ieee80211_vif_use_channel(sdata, &local->monitor_chandef, @@ -391,13 +389,14 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local) if (ret) { drv_remove_interface(local, sdata); kfree(sdata); - goto out_unlock; + return ret; } + mutex_lock(&local->iflist_mtx); rcu_assign_pointer(local->monitor_sdata, sdata); - out_unlock: mutex_unlock(&local->iflist_mtx); - return ret; + + return 0; } static void ieee80211_del_virtual_monitor(struct ieee80211_local *local) @@ -407,14 +406,20 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local) if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF)) return; + ASSERT_RTNL(); + mutex_lock(&local->iflist_mtx); sdata = rcu_dereference_protected(local->monitor_sdata, lockdep_is_held(&local->iflist_mtx)); - if (!sdata) - goto out_unlock; + if (!sdata) { + mutex_unlock(&local->iflist_mtx); + return; + } rcu_assign_pointer(local->monitor_sdata, NULL); + mutex_unlock(&local->iflist_mtx); + synchronize_net(); ieee80211_vif_release_channel(sdata); @@ -422,8 +427,6 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local) drv_remove_interface(local, sdata); kfree(sdata); - out_unlock: - mutex_unlock(&local->iflist_mtx); } /* diff --git a/trunk/net/mac80211/mesh.c b/trunk/net/mac80211/mesh.c index 29ce2aa87e7b..4749b3858695 100644 --- a/trunk/net/mac80211/mesh.c +++ b/trunk/net/mac80211/mesh.c @@ -1060,7 +1060,8 @@ void ieee80211_mesh_notify_scan_completed(struct ieee80211_local *local) rcu_read_lock(); list_for_each_entry_rcu(sdata, &local->interfaces, list) - if (ieee80211_vif_is_mesh(&sdata->vif)) + if (ieee80211_vif_is_mesh(&sdata->vif) && + ieee80211_sdata_running(sdata)) ieee80211_queue_work(&local->hw, &sdata->work); rcu_read_unlock(); } diff --git a/trunk/net/mac80211/mlme.c b/trunk/net/mac80211/mlme.c index 141577412d84..82cc30318a86 100644 --- a/trunk/net/mac80211/mlme.c +++ b/trunk/net/mac80211/mlme.c @@ -3608,8 +3608,10 @@ void ieee80211_mlme_notify_scan_completed(struct ieee80211_local *local) /* Restart STA timers */ rcu_read_lock(); - list_for_each_entry_rcu(sdata, &local->interfaces, list) - ieee80211_restart_sta_timer(sdata); + list_for_each_entry_rcu(sdata, &local->interfaces, list) { + if (ieee80211_sdata_running(sdata)) + ieee80211_restart_sta_timer(sdata); + } rcu_read_unlock(); } diff --git a/trunk/net/mac80211/offchannel.c b/trunk/net/mac80211/offchannel.c index cc79b4a2e821..430bd254e496 100644 --- a/trunk/net/mac80211/offchannel.c +++ b/trunk/net/mac80211/offchannel.c @@ -297,10 +297,13 @@ void ieee80211_start_next_roc(struct ieee80211_local *local) } } -void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc) +void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free) { struct ieee80211_roc_work *dep, *tmp; + if (WARN_ON(roc->to_be_freed)) + return; + /* was never transmitted */ if (roc->frame) { cfg80211_mgmt_tx_status(&roc->sdata->wdev, @@ -316,9 +319,12 @@ void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc) GFP_KERNEL); list_for_each_entry_safe(dep, tmp, &roc->dependents, list) - ieee80211_roc_notify_destroy(dep); + ieee80211_roc_notify_destroy(dep, true); - kfree(roc); + if (free) + kfree(roc); + else + roc->to_be_freed = true; } void ieee80211_sw_roc_work(struct work_struct *work) @@ -331,6 +337,9 @@ void ieee80211_sw_roc_work(struct work_struct *work) mutex_lock(&local->mtx); + if (roc->to_be_freed) + goto out_unlock; + if (roc->abort) goto finish; @@ -370,7 +379,7 @@ void ieee80211_sw_roc_work(struct work_struct *work) finish: list_del(&roc->list); started = roc->started; - ieee80211_roc_notify_destroy(roc); + ieee80211_roc_notify_destroy(roc, !roc->abort); if (started) { drv_flush(local, false); @@ -410,7 +419,7 @@ static void ieee80211_hw_roc_done(struct work_struct *work) list_del(&roc->list); - ieee80211_roc_notify_destroy(roc); + ieee80211_roc_notify_destroy(roc, true); /* if there's another roc, start it now */ ieee80211_start_next_roc(local); @@ -460,12 +469,14 @@ void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata) list_for_each_entry_safe(roc, tmp, &tmp_list, list) { if (local->ops->remain_on_channel) { list_del(&roc->list); - ieee80211_roc_notify_destroy(roc); + ieee80211_roc_notify_destroy(roc, true); } else { ieee80211_queue_delayed_work(&local->hw, &roc->work, 0); /* work will clean up etc */ flush_delayed_work(&roc->work); + WARN_ON(!roc->to_be_freed); + kfree(roc); } } diff --git a/trunk/net/mac80211/rx.c b/trunk/net/mac80211/rx.c index bb73ed2d20b9..c6844ad080be 100644 --- a/trunk/net/mac80211/rx.c +++ b/trunk/net/mac80211/rx.c @@ -2675,7 +2675,19 @@ ieee80211_rx_h_action_return(struct ieee80211_rx_data *rx) memset(nskb->cb, 0, sizeof(nskb->cb)); - ieee80211_tx_skb(rx->sdata, nskb); + if (rx->sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE) { + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(nskb); + + info->flags = IEEE80211_TX_CTL_TX_OFFCHAN | + IEEE80211_TX_INTFL_OFFCHAN_TX_OK | + IEEE80211_TX_CTL_NO_CCK_RATE; + if (local->hw.flags & IEEE80211_HW_QUEUE_CONTROL) + info->hw_queue = + local->hw.offchannel_tx_hw_queue; + } + + __ieee80211_tx_skb_tid_band(rx->sdata, nskb, 7, + status->band); } dev_kfree_skb(rx->skb); return RX_QUEUED; diff --git a/trunk/net/mac80211/sta_info.c b/trunk/net/mac80211/sta_info.c index a79ce820cb50..238a0cca320e 100644 --- a/trunk/net/mac80211/sta_info.c +++ b/trunk/net/mac80211/sta_info.c @@ -766,6 +766,7 @@ int __must_check __sta_info_destroy(struct sta_info *sta) struct ieee80211_local *local; struct ieee80211_sub_if_data *sdata; int ret, i; + bool have_key = false; might_sleep(); @@ -793,12 +794,19 @@ int __must_check __sta_info_destroy(struct sta_info *sta) list_del_rcu(&sta->list); mutex_lock(&local->key_mtx); - for (i = 0; i < NUM_DEFAULT_KEYS; i++) + for (i = 0; i < NUM_DEFAULT_KEYS; i++) { __ieee80211_key_free(key_mtx_dereference(local, sta->gtk[i])); - if (sta->ptk) + have_key = true; + } + if (sta->ptk) { __ieee80211_key_free(key_mtx_dereference(local, sta->ptk)); + have_key = true; + } mutex_unlock(&local->key_mtx); + if (!have_key) + synchronize_net(); + sta->dead = true; local->num_sta--; diff --git a/trunk/net/netfilter/nf_conntrack_standalone.c b/trunk/net/netfilter/nf_conntrack_standalone.c index 6bcce401fd1c..fedee3943661 100644 --- a/trunk/net/netfilter/nf_conntrack_standalone.c +++ b/trunk/net/netfilter/nf_conntrack_standalone.c @@ -568,6 +568,7 @@ static int __init nf_conntrack_standalone_init(void) register_net_sysctl(&init_net, "net", nf_ct_netfilter_table); if (!nf_ct_netfilter_header) { pr_err("nf_conntrack: can't register to sysctl.\n"); + ret = -ENOMEM; goto out_sysctl; } #endif diff --git a/trunk/net/netfilter/nfnetlink_acct.c b/trunk/net/netfilter/nfnetlink_acct.c index 589d686f0b4c..dc3fd5d44464 100644 --- a/trunk/net/netfilter/nfnetlink_acct.c +++ b/trunk/net/netfilter/nfnetlink_acct.c @@ -49,6 +49,8 @@ nfnl_acct_new(struct sock *nfnl, struct sk_buff *skb, return -EINVAL; acct_name = nla_data(tb[NFACCT_NAME]); + if (strlen(acct_name) == 0) + return -EINVAL; list_for_each_entry(nfacct, &nfnl_acct_list, head) { if (strncmp(nfacct->name, acct_name, NFACCT_NAME_MAX) != 0) diff --git a/trunk/net/netfilter/nfnetlink_queue_core.c b/trunk/net/netfilter/nfnetlink_queue_core.c index 1cb48540f86a..42680b2baa11 100644 --- a/trunk/net/netfilter/nfnetlink_queue_core.c +++ b/trunk/net/netfilter/nfnetlink_queue_core.c @@ -1062,8 +1062,10 @@ static int __init nfnetlink_queue_init(void) #ifdef CONFIG_PROC_FS if (!proc_create("nfnetlink_queue", 0440, - proc_net_netfilter, &nfqnl_file_ops)) + proc_net_netfilter, &nfqnl_file_ops)) { + status = -ENOMEM; goto cleanup_subsys; + } #endif register_netdevice_notifier(&nfqnl_dev_notifier); diff --git a/trunk/net/nfc/llcp/llcp.c b/trunk/net/nfc/llcp/llcp.c index b530afadd76c..ee25f25f0cd6 100644 --- a/trunk/net/nfc/llcp/llcp.c +++ b/trunk/net/nfc/llcp/llcp.c @@ -107,8 +107,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen, accept_sk->sk_state_change(sk); bh_unlock_sock(accept_sk); - - sock_orphan(accept_sk); } if (listen == true) { @@ -134,8 +132,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen, bh_unlock_sock(sk); - sock_orphan(sk); - sk_del_node_init(sk); } @@ -164,8 +160,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen, bh_unlock_sock(sk); - sock_orphan(sk); - sk_del_node_init(sk); } @@ -827,7 +821,6 @@ static void nfc_llcp_recv_ui(struct nfc_llcp_local *local, skb_get(skb); } else { pr_err("Receive queue is full\n"); - kfree_skb(skb); } nfc_llcp_sock_put(llcp_sock); @@ -1028,7 +1021,6 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local, skb_get(skb); } else { pr_err("Receive queue is full\n"); - kfree_skb(skb); } } diff --git a/trunk/net/nfc/llcp/sock.c b/trunk/net/nfc/llcp/sock.c index 5c7cdf3f2a83..8f025746f337 100644 --- a/trunk/net/nfc/llcp/sock.c +++ b/trunk/net/nfc/llcp/sock.c @@ -270,7 +270,9 @@ struct sock *nfc_llcp_accept_dequeue(struct sock *parent, } if (sk->sk_state == LLCP_CONNECTED || !newsock) { - nfc_llcp_accept_unlink(sk); + list_del_init(&lsk->accept_queue); + sock_put(sk); + if (newsock) sock_graft(sk, newsock); @@ -464,8 +466,6 @@ static int llcp_sock_release(struct socket *sock) nfc_llcp_accept_unlink(accept_sk); release_sock(accept_sk); - - sock_orphan(accept_sk); } } diff --git a/trunk/net/sched/sch_cbq.c b/trunk/net/sched/sch_cbq.c index 13aa47aa2ffb..1bc210ffcba2 100644 --- a/trunk/net/sched/sch_cbq.c +++ b/trunk/net/sched/sch_cbq.c @@ -962,8 +962,11 @@ cbq_dequeue(struct Qdisc *sch) cbq_update(q); if ((incr -= incr2) < 0) incr = 0; + q->now += incr; + } else { + if (now > q->now) + q->now = now; } - q->now += incr; q->now_rt = now; for (;;) { diff --git a/trunk/net/sched/sch_fq_codel.c b/trunk/net/sched/sch_fq_codel.c index 4e606fcb2534..55786283a3df 100644 --- a/trunk/net/sched/sch_fq_codel.c +++ b/trunk/net/sched/sch_fq_codel.c @@ -195,7 +195,7 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch) flow->deficit = q->quantum; flow->dropped = 0; } - if (++sch->q.qlen < sch->limit) + if (++sch->q.qlen <= sch->limit) return NET_XMIT_SUCCESS; q->drop_overlimit++; diff --git a/trunk/net/sched/sch_generic.c b/trunk/net/sched/sch_generic.c index ffad48109a22..eac7e0ee23c1 100644 --- a/trunk/net/sched/sch_generic.c +++ b/trunk/net/sched/sch_generic.c @@ -904,7 +904,7 @@ void psched_ratecfg_precompute(struct psched_ratecfg *r, u32 rate) u64 mult; int shift; - r->rate_bps = rate << 3; + r->rate_bps = (u64)rate << 3; r->shift = 0; r->mult = 1; /* diff --git a/trunk/net/unix/af_unix.c b/trunk/net/unix/af_unix.c index 971282b6f6a3..2db702d82e7d 100644 --- a/trunk/net/unix/af_unix.c +++ b/trunk/net/unix/af_unix.c @@ -1412,8 +1412,8 @@ static void maybe_add_creds(struct sk_buff *skb, const struct socket *sock, if (UNIXCB(skb).cred) return; if (test_bit(SOCK_PASSCRED, &sock->flags) || - (other->sk_socket && - test_bit(SOCK_PASSCRED, &other->sk_socket->flags))) { + !other->sk_socket || + test_bit(SOCK_PASSCRED, &other->sk_socket->flags)) { UNIXCB(skb).pid = get_pid(task_tgid(current)); UNIXCB(skb).cred = get_current_cred(); } @@ -1993,7 +1993,7 @@ static int unix_stream_recvmsg(struct kiocb *iocb, struct socket *sock, if ((UNIXCB(skb).pid != siocb->scm->pid) || (UNIXCB(skb).cred != siocb->scm->cred)) break; - } else { + } else if (test_bit(SOCK_PASSCRED, &sock->flags)) { /* Copy credentials */ scm_set_cred(siocb->scm, UNIXCB(skb).pid, UNIXCB(skb).cred); check_creds = 1; diff --git a/trunk/net/vmw_vsock/af_vsock.c b/trunk/net/vmw_vsock/af_vsock.c index ca511c4f388a..d8079daf1bde 100644 --- a/trunk/net/vmw_vsock/af_vsock.c +++ b/trunk/net/vmw_vsock/af_vsock.c @@ -207,7 +207,7 @@ static struct sock *__vsock_find_bound_socket(struct sockaddr_vm *addr) struct vsock_sock *vsk; list_for_each_entry(vsk, vsock_bound_sockets(addr), bound_table) - if (vsock_addr_equals_addr_any(addr, &vsk->local_addr)) + if (addr->svm_port == vsk->local_addr.svm_port) return sk_vsock(vsk); return NULL; @@ -220,8 +220,8 @@ static struct sock *__vsock_find_connected_socket(struct sockaddr_vm *src, list_for_each_entry(vsk, vsock_connected_sockets(src, dst), connected_table) { - if (vsock_addr_equals_addr(src, &vsk->remote_addr) - && vsock_addr_equals_addr(dst, &vsk->local_addr)) { + if (vsock_addr_equals_addr(src, &vsk->remote_addr) && + dst->svm_port == vsk->local_addr.svm_port) { return sk_vsock(vsk); } } diff --git a/trunk/net/vmw_vsock/vmci_transport.c b/trunk/net/vmw_vsock/vmci_transport.c index a70ace83a153..1f6508e249ae 100644 --- a/trunk/net/vmw_vsock/vmci_transport.c +++ b/trunk/net/vmw_vsock/vmci_transport.c @@ -464,19 +464,16 @@ static struct sock *vmci_transport_get_pending( struct vsock_sock *vlistener; struct vsock_sock *vpending; struct sock *pending; + struct sockaddr_vm src; + + vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port); vlistener = vsock_sk(listener); list_for_each_entry(vpending, &vlistener->pending_links, pending_links) { - struct sockaddr_vm src; - struct sockaddr_vm dst; - - vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port); - vsock_addr_init(&dst, pkt->dg.dst.context, pkt->dst_port); - if (vsock_addr_equals_addr(&src, &vpending->remote_addr) && - vsock_addr_equals_addr(&dst, &vpending->local_addr)) { + pkt->dst_port == vpending->local_addr.svm_port) { pending = sk_vsock(vpending); sock_hold(pending); goto found; @@ -739,10 +736,15 @@ static int vmci_transport_recv_stream_cb(void *data, struct vmci_datagram *dg) */ bh_lock_sock(sk); - if (!sock_owned_by_user(sk) && sk->sk_state == SS_CONNECTED) - vmci_trans(vsk)->notify_ops->handle_notify_pkt( - sk, pkt, true, &dst, &src, - &bh_process_pkt); + if (!sock_owned_by_user(sk)) { + /* The local context ID may be out of date, update it. */ + vsk->local_addr.svm_cid = dst.svm_cid; + + if (sk->sk_state == SS_CONNECTED) + vmci_trans(vsk)->notify_ops->handle_notify_pkt( + sk, pkt, true, &dst, &src, + &bh_process_pkt); + } bh_unlock_sock(sk); @@ -902,6 +904,9 @@ static void vmci_transport_recv_pkt_work(struct work_struct *work) lock_sock(sk); + /* The local context ID may be out of date. */ + vsock_sk(sk)->local_addr.svm_cid = pkt->dg.dst.context; + switch (sk->sk_state) { case SS_LISTEN: vmci_transport_recv_listen(sk, pkt); @@ -958,6 +963,10 @@ static int vmci_transport_recv_listen(struct sock *sk, pending = vmci_transport_get_pending(sk, pkt); if (pending) { lock_sock(pending); + + /* The local context ID may be out of date. */ + vsock_sk(pending)->local_addr.svm_cid = pkt->dg.dst.context; + switch (pending->sk_state) { case SS_CONNECTING: err = vmci_transport_recv_connecting_server(sk, diff --git a/trunk/net/vmw_vsock/vsock_addr.c b/trunk/net/vmw_vsock/vsock_addr.c index b7df1aea7c59..ec2611b4ea0e 100644 --- a/trunk/net/vmw_vsock/vsock_addr.c +++ b/trunk/net/vmw_vsock/vsock_addr.c @@ -64,16 +64,6 @@ bool vsock_addr_equals_addr(const struct sockaddr_vm *addr, } EXPORT_SYMBOL_GPL(vsock_addr_equals_addr); -bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr, - const struct sockaddr_vm *other) -{ - return (addr->svm_cid == VMADDR_CID_ANY || - other->svm_cid == VMADDR_CID_ANY || - addr->svm_cid == other->svm_cid) && - addr->svm_port == other->svm_port; -} -EXPORT_SYMBOL_GPL(vsock_addr_equals_addr_any); - int vsock_addr_cast(const struct sockaddr *addr, size_t len, struct sockaddr_vm **out_addr) { diff --git a/trunk/net/vmw_vsock/vsock_addr.h b/trunk/net/vmw_vsock/vsock_addr.h index cdfbcefdf843..9ccd5316eac0 100644 --- a/trunk/net/vmw_vsock/vsock_addr.h +++ b/trunk/net/vmw_vsock/vsock_addr.h @@ -24,8 +24,6 @@ bool vsock_addr_bound(const struct sockaddr_vm *addr); void vsock_addr_unbind(struct sockaddr_vm *addr); bool vsock_addr_equals_addr(const struct sockaddr_vm *addr, const struct sockaddr_vm *other); -bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr, - const struct sockaddr_vm *other); int vsock_addr_cast(const struct sockaddr *addr, size_t len, struct sockaddr_vm **out_addr); diff --git a/trunk/net/wireless/core.c b/trunk/net/wireless/core.c index ea4155fe9733..6ddf74f0ae1e 100644 --- a/trunk/net/wireless/core.c +++ b/trunk/net/wireless/core.c @@ -212,6 +212,39 @@ static void cfg80211_rfkill_poll(struct rfkill *rfkill, void *data) rdev_rfkill_poll(rdev); } +void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev, + struct wireless_dev *wdev) +{ + lockdep_assert_held(&rdev->devlist_mtx); + lockdep_assert_held(&rdev->sched_scan_mtx); + + if (WARN_ON(wdev->iftype != NL80211_IFTYPE_P2P_DEVICE)) + return; + + if (!wdev->p2p_started) + return; + + rdev_stop_p2p_device(rdev, wdev); + wdev->p2p_started = false; + + rdev->opencount--; + + if (rdev->scan_req && rdev->scan_req->wdev == wdev) { + bool busy = work_busy(&rdev->scan_done_wk); + + /* + * If the work isn't pending or running (in which case it would + * be waiting for the lock we hold) the driver didn't properly + * cancel the scan when the interface was removed. In this case + * warn and leak the scan request object to not crash later. + */ + WARN_ON(!busy); + + rdev->scan_req->aborted = true; + ___cfg80211_scan_done(rdev, !busy); + } +} + static int cfg80211_rfkill_set_block(void *data, bool blocked) { struct cfg80211_registered_device *rdev = data; @@ -221,7 +254,8 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked) return 0; rtnl_lock(); - mutex_lock(&rdev->devlist_mtx); + + /* read-only iteration need not hold the devlist_mtx */ list_for_each_entry(wdev, &rdev->wdev_list, list) { if (wdev->netdev) { @@ -231,18 +265,18 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked) /* otherwise, check iftype */ switch (wdev->iftype) { case NL80211_IFTYPE_P2P_DEVICE: - if (!wdev->p2p_started) - break; - rdev_stop_p2p_device(rdev, wdev); - wdev->p2p_started = false; - rdev->opencount--; + /* but this requires it */ + mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); + cfg80211_stop_p2p_device(rdev, wdev); + mutex_unlock(&rdev->sched_scan_mtx); + mutex_unlock(&rdev->devlist_mtx); break; default: break; } } - mutex_unlock(&rdev->devlist_mtx); rtnl_unlock(); return 0; @@ -745,17 +779,13 @@ static void wdev_cleanup_work(struct work_struct *work) wdev = container_of(work, struct wireless_dev, cleanup_work); rdev = wiphy_to_dev(wdev->wiphy); - cfg80211_lock_rdev(rdev); + mutex_lock(&rdev->sched_scan_mtx); if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) { rdev->scan_req->aborted = true; ___cfg80211_scan_done(rdev, true); } - cfg80211_unlock_rdev(rdev); - - mutex_lock(&rdev->sched_scan_mtx); - if (WARN_ON(rdev->sched_scan_req && rdev->sched_scan_req->dev == wdev->netdev)) { __cfg80211_stop_sched_scan(rdev, false); @@ -781,21 +811,19 @@ void cfg80211_unregister_wdev(struct wireless_dev *wdev) return; mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); list_del_rcu(&wdev->list); rdev->devlist_generation++; switch (wdev->iftype) { case NL80211_IFTYPE_P2P_DEVICE: - if (!wdev->p2p_started) - break; - rdev_stop_p2p_device(rdev, wdev); - wdev->p2p_started = false; - rdev->opencount--; + cfg80211_stop_p2p_device(rdev, wdev); break; default: WARN_ON_ONCE(1); break; } + mutex_unlock(&rdev->sched_scan_mtx); mutex_unlock(&rdev->devlist_mtx); } EXPORT_SYMBOL(cfg80211_unregister_wdev); @@ -936,6 +964,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb, cfg80211_update_iface_num(rdev, wdev->iftype, 1); cfg80211_lock_rdev(rdev); mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); wdev_lock(wdev); switch (wdev->iftype) { #ifdef CONFIG_CFG80211_WEXT @@ -967,6 +996,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb, break; } wdev_unlock(wdev); + mutex_unlock(&rdev->sched_scan_mtx); rdev->opencount++; mutex_unlock(&rdev->devlist_mtx); cfg80211_unlock_rdev(rdev); diff --git a/trunk/net/wireless/core.h b/trunk/net/wireless/core.h index 3aec0e429d8a..5845c2b37aa8 100644 --- a/trunk/net/wireless/core.h +++ b/trunk/net/wireless/core.h @@ -503,6 +503,9 @@ int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, void cfg80211_update_iface_num(struct cfg80211_registered_device *rdev, enum nl80211_iftype iftype, int num); +void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev, + struct wireless_dev *wdev); + #define CFG80211_MAX_NUM_DIFFERENT_CHANNELS 10 #ifdef CONFIG_CFG80211_DEVELOPER_WARNINGS diff --git a/trunk/net/wireless/nl80211.c b/trunk/net/wireless/nl80211.c index d44ab216c0ec..58e13a8c95f9 100644 --- a/trunk/net/wireless/nl80211.c +++ b/trunk/net/wireless/nl80211.c @@ -4702,14 +4702,19 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info) if (!rdev->ops->scan) return -EOPNOTSUPP; - if (rdev->scan_req) - return -EBUSY; + mutex_lock(&rdev->sched_scan_mtx); + if (rdev->scan_req) { + err = -EBUSY; + goto unlock; + } if (info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]) { n_channels = validate_scan_freqs( info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]); - if (!n_channels) - return -EINVAL; + if (!n_channels) { + err = -EINVAL; + goto unlock; + } } else { enum ieee80211_band band; n_channels = 0; @@ -4723,23 +4728,29 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info) nla_for_each_nested(attr, info->attrs[NL80211_ATTR_SCAN_SSIDS], tmp) n_ssids++; - if (n_ssids > wiphy->max_scan_ssids) - return -EINVAL; + if (n_ssids > wiphy->max_scan_ssids) { + err = -EINVAL; + goto unlock; + } if (info->attrs[NL80211_ATTR_IE]) ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); else ie_len = 0; - if (ie_len > wiphy->max_scan_ie_len) - return -EINVAL; + if (ie_len > wiphy->max_scan_ie_len) { + err = -EINVAL; + goto unlock; + } request = kzalloc(sizeof(*request) + sizeof(*request->ssids) * n_ssids + sizeof(*request->channels) * n_channels + ie_len, GFP_KERNEL); - if (!request) - return -ENOMEM; + if (!request) { + err = -ENOMEM; + goto unlock; + } if (n_ssids) request->ssids = (void *)&request->channels[n_channels]; @@ -4876,6 +4887,8 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info) kfree(request); } + unlock: + mutex_unlock(&rdev->sched_scan_mtx); return err; } @@ -7749,20 +7762,9 @@ static int nl80211_stop_p2p_device(struct sk_buff *skb, struct genl_info *info) if (!rdev->ops->stop_p2p_device) return -EOPNOTSUPP; - if (!wdev->p2p_started) - return 0; - - rdev_stop_p2p_device(rdev, wdev); - wdev->p2p_started = false; - - mutex_lock(&rdev->devlist_mtx); - rdev->opencount--; - mutex_unlock(&rdev->devlist_mtx); - - if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) { - rdev->scan_req->aborted = true; - ___cfg80211_scan_done(rdev, true); - } + mutex_lock(&rdev->sched_scan_mtx); + cfg80211_stop_p2p_device(rdev, wdev); + mutex_unlock(&rdev->sched_scan_mtx); return 0; } @@ -8486,7 +8488,7 @@ static int nl80211_add_scan_req(struct sk_buff *msg, struct nlattr *nest; int i; - ASSERT_RDEV_LOCK(rdev); + lockdep_assert_held(&rdev->sched_scan_mtx); if (WARN_ON(!req)) return 0; diff --git a/trunk/net/wireless/scan.c b/trunk/net/wireless/scan.c index 674aadca0079..fd99ea495b7e 100644 --- a/trunk/net/wireless/scan.c +++ b/trunk/net/wireless/scan.c @@ -169,7 +169,7 @@ void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev, bool leak) union iwreq_data wrqu; #endif - ASSERT_RDEV_LOCK(rdev); + lockdep_assert_held(&rdev->sched_scan_mtx); request = rdev->scan_req; @@ -230,9 +230,9 @@ void __cfg80211_scan_done(struct work_struct *wk) rdev = container_of(wk, struct cfg80211_registered_device, scan_done_wk); - cfg80211_lock_rdev(rdev); + mutex_lock(&rdev->sched_scan_mtx); ___cfg80211_scan_done(rdev, false); - cfg80211_unlock_rdev(rdev); + mutex_unlock(&rdev->sched_scan_mtx); } void cfg80211_scan_done(struct cfg80211_scan_request *request, bool aborted) @@ -698,11 +698,6 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev, found = rb_find_bss(dev, tmp, BSS_CMP_REGULAR); if (found) { - found->pub.beacon_interval = tmp->pub.beacon_interval; - found->pub.signal = tmp->pub.signal; - found->pub.capability = tmp->pub.capability; - found->ts = tmp->ts; - /* Update IEs */ if (rcu_access_pointer(tmp->pub.proberesp_ies)) { const struct cfg80211_bss_ies *old; @@ -723,6 +718,8 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev, if (found->pub.hidden_beacon_bss && !list_empty(&found->hidden_list)) { + const struct cfg80211_bss_ies *f; + /* * The found BSS struct is one of the probe * response members of a group, but we're @@ -732,6 +729,10 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev, * SSID to showing it, which is confusing so * drop this information. */ + + f = rcu_access_pointer(tmp->pub.beacon_ies); + kfree_rcu((struct cfg80211_bss_ies *)f, + rcu_head); goto drop; } @@ -761,6 +762,11 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev, kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); } + + found->pub.beacon_interval = tmp->pub.beacon_interval; + found->pub.signal = tmp->pub.signal; + found->pub.capability = tmp->pub.capability; + found->ts = tmp->ts; } else { struct cfg80211_internal_bss *new; struct cfg80211_internal_bss *hidden; @@ -1056,6 +1062,7 @@ int cfg80211_wext_siwscan(struct net_device *dev, if (IS_ERR(rdev)) return PTR_ERR(rdev); + mutex_lock(&rdev->sched_scan_mtx); if (rdev->scan_req) { err = -EBUSY; goto out; @@ -1162,6 +1169,7 @@ int cfg80211_wext_siwscan(struct net_device *dev, dev_hold(dev); } out: + mutex_unlock(&rdev->sched_scan_mtx); kfree(creq); cfg80211_unlock_rdev(rdev); return err; diff --git a/trunk/net/wireless/sme.c b/trunk/net/wireless/sme.c index f432bd3755b1..09d994d192ff 100644 --- a/trunk/net/wireless/sme.c +++ b/trunk/net/wireless/sme.c @@ -85,6 +85,7 @@ static int cfg80211_conn_scan(struct wireless_dev *wdev) ASSERT_RTNL(); ASSERT_RDEV_LOCK(rdev); ASSERT_WDEV_LOCK(wdev); + lockdep_assert_held(&rdev->sched_scan_mtx); if (rdev->scan_req) return -EBUSY; @@ -320,11 +321,9 @@ void cfg80211_sme_scan_done(struct net_device *dev) { struct wireless_dev *wdev = dev->ieee80211_ptr; - mutex_lock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx); wdev_lock(wdev); __cfg80211_sme_scan_done(dev); wdev_unlock(wdev); - mutex_unlock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx); } void cfg80211_sme_rx_auth(struct net_device *dev, @@ -924,9 +923,12 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev, int err; mutex_lock(&rdev->devlist_mtx); + /* might request scan - scan_mtx -> wdev_mtx dependency */ + mutex_lock(&rdev->sched_scan_mtx); wdev_lock(dev->ieee80211_ptr); err = __cfg80211_connect(rdev, dev, connect, connkeys, NULL); wdev_unlock(dev->ieee80211_ptr); + mutex_unlock(&rdev->sched_scan_mtx); mutex_unlock(&rdev->devlist_mtx); return err; diff --git a/trunk/net/wireless/trace.h b/trunk/net/wireless/trace.h index b7a531380e19..7586de77a2f8 100644 --- a/trunk/net/wireless/trace.h +++ b/trunk/net/wireless/trace.h @@ -27,7 +27,8 @@ #define WIPHY_PR_ARG __entry->wiphy_name #define WDEV_ENTRY __field(u32, id) -#define WDEV_ASSIGN (__entry->id) = (wdev ? wdev->identifier : 0) +#define WDEV_ASSIGN (__entry->id) = (!IS_ERR_OR_NULL(wdev) \ + ? wdev->identifier : 0) #define WDEV_PR_FMT "wdev(%u)" #define WDEV_PR_ARG (__entry->id) @@ -1778,7 +1779,7 @@ TRACE_EVENT(rdev_set_mac_acl, ), TP_fast_assign( WIPHY_ASSIGN; - WIPHY_ASSIGN; + NETDEV_ASSIGN; __entry->acl_policy = params->acl_policy; ), TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", acl policy: %d", diff --git a/trunk/net/wireless/wext-sme.c b/trunk/net/wireless/wext-sme.c index fb9622f6d99c..e79cb5c0655a 100644 --- a/trunk/net/wireless/wext-sme.c +++ b/trunk/net/wireless/wext-sme.c @@ -89,6 +89,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev, cfg80211_lock_rdev(rdev); mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); wdev_lock(wdev); if (wdev->sme_state != CFG80211_SME_IDLE) { @@ -135,6 +136,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev, err = cfg80211_mgd_wext_connect(rdev, wdev); out: wdev_unlock(wdev); + mutex_unlock(&rdev->sched_scan_mtx); mutex_unlock(&rdev->devlist_mtx); cfg80211_unlock_rdev(rdev); return err; @@ -190,6 +192,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev, cfg80211_lock_rdev(rdev); mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); wdev_lock(wdev); err = 0; @@ -223,6 +226,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev, err = cfg80211_mgd_wext_connect(rdev, wdev); out: wdev_unlock(wdev); + mutex_unlock(&rdev->sched_scan_mtx); mutex_unlock(&rdev->devlist_mtx); cfg80211_unlock_rdev(rdev); return err; @@ -285,6 +289,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev, cfg80211_lock_rdev(rdev); mutex_lock(&rdev->devlist_mtx); + mutex_lock(&rdev->sched_scan_mtx); wdev_lock(wdev); if (wdev->sme_state != CFG80211_SME_IDLE) { @@ -313,6 +318,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev, err = cfg80211_mgd_wext_connect(rdev, wdev); out: wdev_unlock(wdev); + mutex_unlock(&rdev->sched_scan_mtx); mutex_unlock(&rdev->devlist_mtx); cfg80211_unlock_rdev(rdev); return err; diff --git a/trunk/net/xfrm/xfrm_replay.c b/trunk/net/xfrm/xfrm_replay.c index 35754cc8a9e5..8dafe6d3c6e4 100644 --- a/trunk/net/xfrm/xfrm_replay.c +++ b/trunk/net/xfrm/xfrm_replay.c @@ -334,6 +334,70 @@ static void xfrm_replay_notify_bmp(struct xfrm_state *x, int event) x->xflags &= ~XFRM_TIME_DEFER; } +static void xfrm_replay_notify_esn(struct xfrm_state *x, int event) +{ + u32 seq_diff, oseq_diff; + struct km_event c; + struct xfrm_replay_state_esn *replay_esn = x->replay_esn; + struct xfrm_replay_state_esn *preplay_esn = x->preplay_esn; + + /* we send notify messages in case + * 1. we updated on of the sequence numbers, and the seqno difference + * is at least x->replay_maxdiff, in this case we also update the + * timeout of our timer function + * 2. if x->replay_maxage has elapsed since last update, + * and there were changes + * + * The state structure must be locked! + */ + + switch (event) { + case XFRM_REPLAY_UPDATE: + if (!x->replay_maxdiff) + break; + + if (replay_esn->seq_hi == preplay_esn->seq_hi) + seq_diff = replay_esn->seq - preplay_esn->seq; + else + seq_diff = ~preplay_esn->seq + replay_esn->seq + 1; + + if (replay_esn->oseq_hi == preplay_esn->oseq_hi) + oseq_diff = replay_esn->oseq - preplay_esn->oseq; + else + oseq_diff = ~preplay_esn->oseq + replay_esn->oseq + 1; + + if (seq_diff < x->replay_maxdiff && + oseq_diff < x->replay_maxdiff) { + + if (x->xflags & XFRM_TIME_DEFER) + event = XFRM_REPLAY_TIMEOUT; + else + return; + } + + break; + + case XFRM_REPLAY_TIMEOUT: + if (memcmp(x->replay_esn, x->preplay_esn, + xfrm_replay_state_esn_len(replay_esn)) == 0) { + x->xflags |= XFRM_TIME_DEFER; + return; + } + + break; + } + + memcpy(x->preplay_esn, x->replay_esn, + xfrm_replay_state_esn_len(replay_esn)); + c.event = XFRM_MSG_NEWAE; + c.data.aevent = event; + km_state_notify(x, &c); + + if (x->replay_maxage && + !mod_timer(&x->rtimer, jiffies + x->replay_maxage)) + x->xflags &= ~XFRM_TIME_DEFER; +} + static int xfrm_replay_overflow_esn(struct xfrm_state *x, struct sk_buff *skb) { int err = 0; @@ -510,7 +574,7 @@ static struct xfrm_replay xfrm_replay_esn = { .advance = xfrm_replay_advance_esn, .check = xfrm_replay_check_esn, .recheck = xfrm_replay_recheck_esn, - .notify = xfrm_replay_notify_bmp, + .notify = xfrm_replay_notify_esn, .overflow = xfrm_replay_overflow_esn, }; diff --git a/trunk/sound/pci/hda/hda_codec.c b/trunk/sound/pci/hda/hda_codec.c index ecdf30eb5879..4aba7646dd9c 100644 --- a/trunk/sound/pci/hda/hda_codec.c +++ b/trunk/sound/pci/hda/hda_codec.c @@ -173,7 +173,7 @@ const char *snd_hda_get_jack_type(u32 cfg) "Line Out", "Speaker", "HP Out", "CD", "SPDIF Out", "Digital Out", "Modem Line", "Modem Hand", "Line In", "Aux", "Mic", "Telephony", - "SPDIF In", "Digitial In", "Reserved", "Other" + "SPDIF In", "Digital In", "Reserved", "Other" }; return jack_types[(cfg & AC_DEFCFG_DEVICE) diff --git a/trunk/sound/pci/hda/hda_eld.c b/trunk/sound/pci/hda/hda_eld.c index 7dd846380a50..d0d7ac1e99d2 100644 --- a/trunk/sound/pci/hda/hda_eld.c +++ b/trunk/sound/pci/hda/hda_eld.c @@ -320,7 +320,7 @@ int snd_hdmi_get_eld(struct hda_codec *codec, hda_nid_t nid, unsigned char *buf, int *eld_size) { int i; - int ret; + int ret = 0; int size; /* diff --git a/trunk/sound/pci/hda/hda_generic.c b/trunk/sound/pci/hda/hda_generic.c index 43c2ea539561..2dbe767be16b 100644 --- a/trunk/sound/pci/hda/hda_generic.c +++ b/trunk/sound/pci/hda/hda_generic.c @@ -740,7 +740,7 @@ EXPORT_SYMBOL_HDA(snd_hda_activate_path); static void path_power_down_sync(struct hda_codec *codec, struct nid_path *path) { struct hda_gen_spec *spec = codec->spec; - bool changed; + bool changed = false; int i; if (!spec->power_down_unused || path->active) diff --git a/trunk/sound/pci/hda/hda_intel.c b/trunk/sound/pci/hda/hda_intel.c index 418bfc0eb0a3..bcd40ee488e3 100644 --- a/trunk/sound/pci/hda/hda_intel.c +++ b/trunk/sound/pci/hda/hda_intel.c @@ -134,8 +134,8 @@ MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " * this may give more power-saving, but will take longer time to * wake up. */ -static int power_save_controller = -1; -module_param(power_save_controller, bint, 0644); +static bool power_save_controller = 1; +module_param(power_save_controller, bool, 0644); MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); #endif /* CONFIG_PM */ @@ -2931,8 +2931,6 @@ static int azx_runtime_idle(struct device *dev) struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; - if (power_save_controller > 0) - return 0; if (!power_save_controller || !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) return -EBUSY; diff --git a/trunk/sound/pci/hda/patch_hdmi.c b/trunk/sound/pci/hda/patch_hdmi.c index 78e1827d0a95..de8ac5c07fd0 100644 --- a/trunk/sound/pci/hda/patch_hdmi.c +++ b/trunk/sound/pci/hda/patch_hdmi.c @@ -1196,7 +1196,7 @@ static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) _snd_printd(SND_PR_VERBOSE, "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", - codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); + codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid); if (eld->eld_valid) { if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer, diff --git a/trunk/sound/pci/hda/patch_realtek.c b/trunk/sound/pci/hda/patch_realtek.c index 563c24df4d6f..f15c36bde540 100644 --- a/trunk/sound/pci/hda/patch_realtek.c +++ b/trunk/sound/pci/hda/patch_realtek.c @@ -3440,7 +3440,8 @@ static int alc662_parse_auto_config(struct hda_codec *codec) const hda_nid_t *ssids; if (codec->vendor_id == 0x10ec0272 || codec->vendor_id == 0x10ec0663 || - codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670) + codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670 || + codec->vendor_id == 0x10ec0671) ssids = alc663_ssids; else ssids = alc662_ssids; @@ -3894,6 +3895,7 @@ static const struct hda_codec_preset snd_hda_preset_realtek[] = { { .id = 0x10ec0665, .name = "ALC665", .patch = patch_alc662 }, { .id = 0x10ec0668, .name = "ALC668", .patch = patch_alc662 }, { .id = 0x10ec0670, .name = "ALC670", .patch = patch_alc662 }, + { .id = 0x10ec0671, .name = "ALC671", .patch = patch_alc662 }, { .id = 0x10ec0680, .name = "ALC680", .patch = patch_alc680 }, { .id = 0x10ec0880, .name = "ALC880", .patch = patch_alc880 }, { .id = 0x10ec0882, .name = "ALC882", .patch = patch_alc882 }, diff --git a/trunk/sound/soc/codecs/max98090.c b/trunk/sound/soc/codecs/max98090.c old mode 100755 new mode 100644 diff --git a/trunk/sound/soc/codecs/max98090.h b/trunk/sound/soc/codecs/max98090.h old mode 100755 new mode 100644 diff --git a/trunk/sound/soc/codecs/si476x.c b/trunk/sound/soc/codecs/si476x.c index f2d61a187830..566ea3256e2d 100644 --- a/trunk/sound/soc/codecs/si476x.c +++ b/trunk/sound/soc/codecs/si476x.c @@ -159,6 +159,7 @@ static int si476x_codec_hw_params(struct snd_pcm_substream *substream, switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: width = SI476X_PCM_FORMAT_S8; + break; case SNDRV_PCM_FORMAT_S16_LE: width = SI476X_PCM_FORMAT_S16_LE; break; diff --git a/trunk/sound/soc/codecs/wm_adsp.c b/trunk/sound/soc/codecs/wm_adsp.c index f3f7e75f8628..9af1bddc4c62 100644 --- a/trunk/sound/soc/codecs/wm_adsp.c +++ b/trunk/sound/soc/codecs/wm_adsp.c @@ -828,7 +828,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) &buf_list); if (!buf) { adsp_err(dsp, "Out of memory\n"); - return -ENOMEM; + ret = -ENOMEM; + goto out_fw; } adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", @@ -865,7 +866,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) wm_adsp_buf_free(&buf_list); out: kfree(file); - return 0; + return ret; } int wm_adsp1_init(struct wm_adsp *adsp) diff --git a/trunk/sound/soc/fsl/imx-ssi.c b/trunk/sound/soc/fsl/imx-ssi.c index 55464a5b0706..810c7eeb7b03 100644 --- a/trunk/sound/soc/fsl/imx-ssi.c +++ b/trunk/sound/soc/fsl/imx-ssi.c @@ -496,6 +496,8 @@ static void imx_ssi_ac97_reset(struct snd_ac97 *ac97) if (imx_ssi->ac97_reset) imx_ssi->ac97_reset(ac97); + /* First read sometimes fails, do a dummy read */ + imx_ssi_ac97_read(ac97, 0); } static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97) @@ -504,6 +506,9 @@ static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97) if (imx_ssi->ac97_warm_reset) imx_ssi->ac97_warm_reset(ac97); + + /* First read sometimes fails, do a dummy read */ + imx_ssi_ac97_read(ac97, 0); } struct snd_ac97_bus_ops soc_ac97_ops = { diff --git a/trunk/sound/soc/fsl/pcm030-audio-fabric.c b/trunk/sound/soc/fsl/pcm030-audio-fabric.c index 8e52c1485df3..eb4373840bb6 100644 --- a/trunk/sound/soc/fsl/pcm030-audio-fabric.c +++ b/trunk/sound/soc/fsl/pcm030-audio-fabric.c @@ -51,7 +51,7 @@ static struct snd_soc_card pcm030_card = { .num_links = ARRAY_SIZE(pcm030_fabric_dai), }; -static int __init pcm030_fabric_probe(struct platform_device *op) +static int pcm030_fabric_probe(struct platform_device *op) { struct device_node *np = op->dev.of_node; struct device_node *platform_np; diff --git a/trunk/sound/soc/sh/dma-sh7760.c b/trunk/sound/soc/sh/dma-sh7760.c index 19eff8fc4fdd..1a8b03e4b41b 100644 --- a/trunk/sound/soc/sh/dma-sh7760.c +++ b/trunk/sound/soc/sh/dma-sh7760.c @@ -342,8 +342,8 @@ static int camelot_pcm_new(struct snd_soc_pcm_runtime *rtd) return 0; } -static struct snd_soc_platform sh7760_soc_platform = { - .pcm_ops = &camelot_pcm_ops, +static struct snd_soc_platform_driver sh7760_soc_platform = { + .ops = &camelot_pcm_ops, .pcm_new = camelot_pcm_new, .pcm_free = camelot_pcm_free, }; diff --git a/trunk/sound/soc/soc-core.c b/trunk/sound/soc/soc-core.c index b7e84a7cd9ee..507d251916af 100644 --- a/trunk/sound/soc/soc-core.c +++ b/trunk/sound/soc/soc-core.c @@ -3140,7 +3140,7 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, if (params->mask) { ret = regmap_read(codec->control_data, params->base, &val); if (ret != 0) - return ret; + goto out; val &= params->mask; @@ -3158,13 +3158,15 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, ((u32 *)data)[0] |= cpu_to_be32(val); break; default: - return -EINVAL; + ret = -EINVAL; + goto out; } } ret = regmap_raw_write(codec->control_data, params->base, data, len); +out: kfree(data); return ret; @@ -4197,7 +4199,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, dev_err(card->dev, "ASoC: Property '%s' index %d could not be read: %d\n", propname, 2 * i, ret); - kfree(routes); return -EINVAL; } ret = of_property_read_string_index(np, propname, @@ -4206,7 +4207,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, dev_err(card->dev, "ASoC: Property '%s' index %d could not be read: %d\n", propname, (2 * i) + 1, ret); - kfree(routes); return -EINVAL; } } diff --git a/trunk/sound/soc/soc-dapm.c b/trunk/sound/soc/soc-dapm.c index 1d6a9b3ceb27..d6d9ba2e6916 100644 --- a/trunk/sound/soc/soc-dapm.c +++ b/trunk/sound/soc/soc-dapm.c @@ -831,6 +831,9 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget, if (path->weak) continue; + if (path->walking) + return 1; + if (path->walked) continue; @@ -838,6 +841,7 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget, if (path->sink && path->connect) { path->walked = 1; + path->walking = 1; /* do we need to add this widget to the list ? */ if (list) { @@ -847,11 +851,14 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget, dev_err(widget->dapm->dev, "ASoC: could not add widget %s\n", widget->name); + path->walking = 0; return con; } } con += is_connected_output_ep(path->sink, list); + + path->walking = 0; } } @@ -931,6 +938,9 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget, if (path->weak) continue; + if (path->walking) + return 1; + if (path->walked) continue; @@ -938,6 +948,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget, if (path->source && path->connect) { path->walked = 1; + path->walking = 1; /* do we need to add this widget to the list ? */ if (list) { @@ -947,11 +958,14 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget, dev_err(widget->dapm->dev, "ASoC: could not add widget %s\n", widget->name); + path->walking = 0; return con; } } con += is_connected_input_ep(path->source, list); + + path->walking = 0; } } diff --git a/trunk/sound/soc/spear/spear_pcm.c b/trunk/sound/soc/spear/spear_pcm.c index 9b76cc5a1148..5e7aebe1e664 100644 --- a/trunk/sound/soc/spear/spear_pcm.c +++ b/trunk/sound/soc/spear/spear_pcm.c @@ -149,9 +149,9 @@ static void spear_pcm_free(struct snd_pcm *pcm) static u64 spear_pcm_dmamask = DMA_BIT_MASK(32); -static int spear_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, struct snd_pcm *pcm) +static int spear_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; int ret; if (!card->dev->dma_mask) @@ -159,16 +159,16 @@ static int spear_pcm_new(struct snd_card *card, if (!card->dev->coherent_dma_mask) card->dev->coherent_dma_mask = DMA_BIT_MASK(32); - if (dai->driver->playback.channels_min) { - ret = spear_pcm_preallocate_dma_buffer(pcm, + if (rtd->cpu_dai->driver->playback.channels_min) { + ret = spear_pcm_preallocate_dma_buffer(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK, spear_pcm_hardware.buffer_bytes_max); if (ret) return ret; } - if (dai->driver->capture.channels_min) { - ret = spear_pcm_preallocate_dma_buffer(pcm, + if (rtd->cpu_dai->driver->capture.channels_min) { + ret = spear_pcm_preallocate_dma_buffer(rtd->pcm, SNDRV_PCM_STREAM_CAPTURE, spear_pcm_hardware.buffer_bytes_max); if (ret) diff --git a/trunk/sound/usb/clock.c b/trunk/sound/usb/clock.c index 5e634a2eb282..9e2703a25156 100644 --- a/trunk/sound/usb/clock.c +++ b/trunk/sound/usb/clock.c @@ -253,7 +253,7 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, { struct usb_device *dev = chip->dev; unsigned char data[4]; - int err, crate; + int err, cur_rate, prev_rate; int clock = snd_usb_clock_find_source(chip, fmt->clock); if (clock < 0) @@ -266,6 +266,19 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, return -ENXIO; } + err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR, + USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN, + UAC2_CS_CONTROL_SAM_FREQ << 8, + snd_usb_ctrl_intf(chip) | (clock << 8), + data, sizeof(data)); + if (err < 0) { + snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n", + dev->devnum, iface, fmt->altsetting); + prev_rate = 0; + } else { + prev_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); + } + data[0] = rate; data[1] = rate >> 8; data[2] = rate >> 16; @@ -280,19 +293,31 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface, return err; } - if ((err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR, - USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN, - UAC2_CS_CONTROL_SAM_FREQ << 8, - snd_usb_ctrl_intf(chip) | (clock << 8), - data, sizeof(data))) < 0) { + err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR, + USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN, + UAC2_CS_CONTROL_SAM_FREQ << 8, + snd_usb_ctrl_intf(chip) | (clock << 8), + data, sizeof(data)); + if (err < 0) { snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n", dev->devnum, iface, fmt->altsetting); - return err; + cur_rate = 0; + } else { + cur_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); } - crate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); - if (crate != rate) - snd_printd(KERN_WARNING "current rate %d is different from the runtime rate %d\n", crate, rate); + if (cur_rate != rate) { + snd_printd(KERN_WARNING + "current rate %d is different from the runtime rate %d\n", + cur_rate, rate); + } + + /* Some devices doesn't respond to sample rate changes while the + * interface is active. */ + if (rate != prev_rate) { + usb_set_interface(dev, iface, 0); + usb_set_interface(dev, iface, fmt->altsetting); + } return 0; } diff --git a/trunk/virt/kvm/kvm_main.c b/trunk/virt/kvm/kvm_main.c index adc68feb5c5a..f18013f09e68 100644 --- a/trunk/virt/kvm/kvm_main.c +++ b/trunk/virt/kvm/kvm_main.c @@ -1541,21 +1541,38 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data, } int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc, - gpa_t gpa) + gpa_t gpa, unsigned long len) { struct kvm_memslots *slots = kvm_memslots(kvm); int offset = offset_in_page(gpa); - gfn_t gfn = gpa >> PAGE_SHIFT; + gfn_t start_gfn = gpa >> PAGE_SHIFT; + gfn_t end_gfn = (gpa + len - 1) >> PAGE_SHIFT; + gfn_t nr_pages_needed = end_gfn - start_gfn + 1; + gfn_t nr_pages_avail; ghc->gpa = gpa; ghc->generation = slots->generation; - ghc->memslot = gfn_to_memslot(kvm, gfn); - ghc->hva = gfn_to_hva_many(ghc->memslot, gfn, NULL); - if (!kvm_is_error_hva(ghc->hva)) + ghc->len = len; + ghc->memslot = gfn_to_memslot(kvm, start_gfn); + ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn, &nr_pages_avail); + if (!kvm_is_error_hva(ghc->hva) && nr_pages_avail >= nr_pages_needed) { ghc->hva += offset; - else - return -EFAULT; - + } else { + /* + * If the requested region crosses two memslots, we still + * verify that the entire region is valid here. + */ + while (start_gfn <= end_gfn) { + ghc->memslot = gfn_to_memslot(kvm, start_gfn); + ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn, + &nr_pages_avail); + if (kvm_is_error_hva(ghc->hva)) + return -EFAULT; + start_gfn += nr_pages_avail; + } + /* Use the slow path for cross page reads and writes. */ + ghc->memslot = NULL; + } return 0; } EXPORT_SYMBOL_GPL(kvm_gfn_to_hva_cache_init); @@ -1566,8 +1583,13 @@ int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc, struct kvm_memslots *slots = kvm_memslots(kvm); int r; + BUG_ON(len > ghc->len); + if (slots->generation != ghc->generation) - kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa); + kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len); + + if (unlikely(!ghc->memslot)) + return kvm_write_guest(kvm, ghc->gpa, data, len); if (kvm_is_error_hva(ghc->hva)) return -EFAULT; @@ -1587,8 +1609,13 @@ int kvm_read_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc, struct kvm_memslots *slots = kvm_memslots(kvm); int r; + BUG_ON(len > ghc->len); + if (slots->generation != ghc->generation) - kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa); + kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len); + + if (unlikely(!ghc->memslot)) + return kvm_read_guest(kvm, ghc->gpa, data, len); if (kvm_is_error_hva(ghc->hva)) return -EFAULT;