From dc30f8deb5dd049348ddc6cb999c70fdab2c685b Mon Sep 17 00:00:00 2001
From: Matt Carlson <mcarlson@broadcom.com>
Date: Mon, 12 Apr 2010 06:58:24 +0000
Subject: [PATCH] --- yaml --- r: 194023 b: refs/heads/master c:
 cea46462681d61a65a208d17206d38739c1ea1b1 h: refs/heads/master i:   194021:
 69fdc7ae2e75378d23aa6d3ec6fe84023c01f74b   194019:
 0b8c9254016d268e7b3df7402adaa5787a1c5a58   194015:
 480f7c20171ae70edc3938b6747a446e63e845ee v: v3

---
 [refs]                  |  2 +-
 trunk/drivers/net/tg3.c | 14 ++++++++++++++
 trunk/drivers/net/tg3.h |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 847e681d5e7e..31d02ee5cb7a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b6c6712a42ca3f9fa7f4a3d7c40e3a9dd1fd9e03
+refs/heads/master: cea46462681d61a65a208d17206d38739c1ea1b1
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index 460a0c22b318..4ae01b3799f4 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -7642,6 +7642,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 		tw32(GRC_MODE, grc_mode);
 	}
 
+	if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+		u32 grc_mode = tr32(GRC_MODE);
+
+		/* Access the lower 1K of PL PCIE block registers. */
+		val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+		tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+
+		val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
+		tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
+		     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
+
+		tw32(GRC_MODE, grc_mode);
+	}
+
 	/* This works around an issue with Athlon chipsets on
 	 * B3 tigon3 silicon.  This bit has no effect on any
 	 * other revision.  But do not set this on PCI Express
diff --git a/trunk/drivers/net/tg3.h b/trunk/drivers/net/tg3.h
index 5d7f72a2ea01..8a6012ab23ff 100644
--- a/trunk/drivers/net/tg3.h
+++ b/trunk/drivers/net/tg3.h
@@ -1854,6 +1854,8 @@
 #define TG3_PCIE_TLDLPL_PORT		0x00007c00
 #define TG3_PCIE_PL_LO_PHYCTL1		 0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN	  0x00001000
+#define TG3_PCIE_PL_LO_PHYCTL5		 0x00000014
+#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ	  0x80000000
 
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK		0x000000e0