From dc46b326496dba87d910c9358c562b1f4cfbf7d2 Mon Sep 17 00:00:00 2001
From: Yaniv Rosner <yanivr@broadcom.com>
Date: Tue, 2 Aug 2011 23:00:00 +0000
Subject: [PATCH] --- yaml --- r: 262462 b: refs/heads/master c:
 d2059a061164120a1e44a0ca46fe08044d6d7c2d h: refs/heads/master v: v3

---
 [refs]                               |  2 +-
 trunk/drivers/net/bnx2x/bnx2x_link.c | 11 +++++++++--
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 01fa0f8e208d..fa76e13863b8 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fd38f73eb936f9d9f28e4f7ff598cc0780e09424
+refs/heads/master: d2059a061164120a1e44a0ca46fe08044d6d7c2d
diff --git a/trunk/drivers/net/bnx2x/bnx2x_link.c b/trunk/drivers/net/bnx2x/bnx2x_link.c
index cf8b8d13ab6c..5e6f3513862c 100644
--- a/trunk/drivers/net/bnx2x/bnx2x_link.c
+++ b/trunk/drivers/net/bnx2x/bnx2x_link.c
@@ -10219,8 +10219,15 @@ static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
 	u32 cfg_pin;
 	u8 port;
 
-	/* This works with E3 only, no need to check the chip
-	   before determining the port. */
+	/*
+	 * In case of no EPIO routed to reset the GPHY, put it
+	 * in low power mode.
+	 */
+	bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
+	/*
+	 * This works with E3 only, no need to check the chip
+	 * before determining the port.
+	 */
 	port = params->port;
 	cfg_pin = (REG_RD(bp, params->shmem_base +
 			offsetof(struct shmem_region,