From dd4817bdaf7ca2b0983d7c65f903996568700f3e Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Thu, 3 Feb 2005 23:06:29 +0000 Subject: [PATCH] --- yaml --- r: 10974 b: refs/heads/master c: 925ddb04c5eee5668e7229c71580d458ed61eb9b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/kernel/irq_cpu.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index fcd63f37a773..5228e5de1ff7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 38b18f72587422450bd01695b471b3ae2ff4b169 +refs/heads/master: 925ddb04c5eee5668e7229c71580d458ed61eb9b diff --git a/trunk/arch/mips/kernel/irq_cpu.c b/trunk/arch/mips/kernel/irq_cpu.c index 2b936cf1ef70..8f8c15fa748d 100644 --- a/trunk/arch/mips/kernel/irq_cpu.c +++ b/trunk/arch/mips/kernel/irq_cpu.c @@ -3,6 +3,8 @@ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * * Copyright (C) 2001 Ralf Baechle + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Author: Maciej W. Rozycki * * This file define the irq handler for MIPS CPU interrupts. * @@ -37,7 +39,6 @@ static int mips_cpu_irq_base; static inline void unmask_mips_irq(unsigned int irq) { - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); set_c0_status(0x100 << (irq - mips_cpu_irq_base)); } @@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base) { int i; + /* Mask interrupts. */ + clear_c0_status(ST0_IM); + clear_c0_cause(CAUSEF_IP); + for (i = irq_base; i < irq_base + 8; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = NULL;