From dde54b4f725624f23d3d98308be863b7c7e0f941 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 13 Feb 2008 16:39:21 +0100 Subject: [PATCH] --- yaml --- r: 91209 b: refs/heads/master c: dcc88a170ce9f90e4b819c67feebb16e8a123f79 h: refs/heads/master i: 91207: 1ad0c73da0c18206ee6646db9fde4d382e5aa40a v: v3 --- [refs] | 2 +- trunk/arch/arm/Kconfig | 11 +- trunk/arch/arm/Makefile | 3 +- .../{orion5x_defconfig => orion_defconfig} | 2 +- .../arm/{mach-orion5x => mach-orion}/Kconfig | 10 +- .../arm/{mach-orion5x => mach-orion}/Makefile | 3 +- .../Makefile.boot | 0 trunk/arch/arm/mach-orion/addr-map.c | 490 +++++++++++++++ .../arm/{mach-orion5x => mach-orion}/common.c | 220 ++++--- trunk/arch/arm/mach-orion/common.h | 92 +++ .../db88f5281-setup.c | 55 +- .../dns323-setup.c | 45 +- .../arm/{mach-orion5x => mach-orion}/gpio.c | 77 ++- .../arm/{mach-orion5x => mach-orion}/irq.c | 132 +++-- .../kurobox_pro-setup.c | 80 ++- trunk/arch/arm/mach-orion/pci.c | 557 +++++++++++++++++ .../rd88f5182-setup.c | 53 +- trunk/arch/arm/mach-orion/time.c | 181 ++++++ .../ts209-setup.c | 145 +---- trunk/arch/arm/mach-orion5x/addr-map.c | 240 -------- trunk/arch/arm/mach-orion5x/common.h | 72 --- trunk/arch/arm/mach-orion5x/pci.c | 559 ------------------ trunk/arch/arm/mach-pxa/pxa3xx.c | 22 + trunk/arch/arm/mm/Kconfig | 2 +- trunk/arch/arm/plat-orion/Makefile | 8 - trunk/arch/arm/plat-orion/irq.c | 64 -- trunk/arch/arm/plat-orion/pcie.c | 245 -------- trunk/arch/arm/plat-orion/time.c | 203 ------- trunk/arch/arm/tools/mach-types | 117 +++- trunk/drivers/ata/sata_mv.c | 31 - trunk/drivers/i2c/busses/Kconfig | 2 +- trunk/drivers/mtd/nand/Kconfig | 2 +- trunk/drivers/mtd/nand/orion_nand.c | 2 +- trunk/drivers/net/Kconfig | 2 +- trunk/drivers/usb/host/ehci-hcd.c | 2 +- trunk/drivers/usb/host/ehci-orion.c | 37 +- .../debug-macro.S | 8 +- .../{arch-orion5x => arch-orion}/dma.h | 0 .../entry-macro.S | 4 +- .../{arch-orion5x => arch-orion}/gpio.h | 8 +- .../{arch-orion5x => arch-orion}/hardware.h | 10 +- trunk/include/asm-arm/arch-orion/io.h | 27 + trunk/include/asm-arm/arch-orion/irqs.h | 61 ++ .../{arch-orion5x => arch-orion}/memory.h | 7 +- trunk/include/asm-arm/arch-orion/orion.h | 165 ++++++ .../orion_nand.h => arch-orion/platform.h} | 11 +- .../{arch-orion5x => arch-orion}/system.h | 13 +- trunk/include/asm-arm/arch-orion/timex.h | 12 + .../{arch-orion5x => arch-orion}/uncompress.h | 8 +- .../{arch-orion5x => arch-orion}/vmalloc.h | 2 +- trunk/include/asm-arm/arch-orion5x/io.h | 68 --- trunk/include/asm-arm/arch-orion5x/irqs.h | 62 -- trunk/include/asm-arm/arch-orion5x/orion5x.h | 159 ----- trunk/include/asm-arm/arch-orion5x/timex.h | 13 - trunk/include/asm-arm/arch-pxa/pxa3xx-regs.h | 9 + trunk/include/asm-arm/plat-orion/ehci-orion.h | 19 - trunk/include/asm-arm/plat-orion/irq.h | 17 - trunk/include/asm-arm/plat-orion/pcie.h | 31 - trunk/include/asm-arm/plat-orion/time.h | 17 - trunk/include/linux/ata_platform.h | 3 - trunk/include/linux/mbus.h | 36 -- 61 files changed, 2146 insertions(+), 2392 deletions(-) rename trunk/arch/arm/configs/{orion5x_defconfig => orion_defconfig} (99%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/Kconfig (77%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/Makefile (68%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/Makefile.boot (100%) create mode 100644 trunk/arch/arm/mach-orion/addr-map.c rename trunk/arch/arm/{mach-orion5x => mach-orion}/common.c (52%) create mode 100644 trunk/arch/arm/mach-orion/common.h rename trunk/arch/arm/{mach-orion5x => mach-orion}/db88f5281-setup.c (88%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/dns323-setup.c (89%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/gpio.c (68%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/irq.c (55%) rename trunk/arch/arm/{mach-orion5x => mach-orion}/kurobox_pro-setup.c (75%) create mode 100644 trunk/arch/arm/mach-orion/pci.c rename trunk/arch/arm/{mach-orion5x => mach-orion}/rd88f5182-setup.c (85%) create mode 100644 trunk/arch/arm/mach-orion/time.c rename trunk/arch/arm/{mach-orion5x => mach-orion}/ts209-setup.c (76%) delete mode 100644 trunk/arch/arm/mach-orion5x/addr-map.c delete mode 100644 trunk/arch/arm/mach-orion5x/common.h delete mode 100644 trunk/arch/arm/mach-orion5x/pci.c delete mode 100644 trunk/arch/arm/plat-orion/Makefile delete mode 100644 trunk/arch/arm/plat-orion/irq.c delete mode 100644 trunk/arch/arm/plat-orion/pcie.c delete mode 100644 trunk/arch/arm/plat-orion/time.c rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/debug-macro.S (73%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/dma.h (100%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/entry-macro.S (90%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/gpio.h (79%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/hardware.h (64%) create mode 100644 trunk/include/asm-arm/arch-orion/io.h create mode 100644 trunk/include/asm-arm/arch-orion/irqs.h rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/memory.h (64%) create mode 100644 trunk/include/asm-arm/arch-orion/orion.h rename trunk/include/asm-arm/{plat-orion/orion_nand.h => arch-orion/platform.h} (64%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/system.h (54%) create mode 100644 trunk/include/asm-arm/arch-orion/timex.h rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/uncompress.h (71%) rename trunk/include/asm-arm/{arch-orion5x => arch-orion}/vmalloc.h (51%) delete mode 100644 trunk/include/asm-arm/arch-orion5x/io.h delete mode 100644 trunk/include/asm-arm/arch-orion5x/irqs.h delete mode 100644 trunk/include/asm-arm/arch-orion5x/orion5x.h delete mode 100644 trunk/include/asm-arm/arch-orion5x/timex.h delete mode 100644 trunk/include/asm-arm/plat-orion/ehci-orion.h delete mode 100644 trunk/include/asm-arm/plat-orion/irq.h delete mode 100644 trunk/include/asm-arm/plat-orion/pcie.h delete mode 100644 trunk/include/asm-arm/plat-orion/time.h delete mode 100644 trunk/include/linux/mbus.h diff --git a/[refs] b/[refs] index 833cf3df8bb8..d5255851dc12 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 875492511a4afce7880c9dd0ca71462c299b40e6 +refs/heads/master: dcc88a170ce9f90e4b819c67feebb16e8a123f79 diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 2f4fb773f3e8..4039a133006e 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -377,17 +377,15 @@ config ARCH_MXC help Support for Freescale MXC/iMX-based family of processors -config ARCH_ORION5X +config ARCH_ORION bool "Marvell Orion" depends on MMU select PCI select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS - select PLAT_ORION help - Support for the following Marvell Orion 5x series SoCs: - Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) + Support for Marvell Orion System on Chip family. config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" @@ -518,7 +516,7 @@ source "arch/arm/mach-omap1/Kconfig" source "arch/arm/mach-omap2/Kconfig" -source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-orion/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" @@ -565,9 +563,6 @@ config ARCH_ACORN config PLAT_IOP bool -config PLAT_ORION - bool - source arch/arm/mm/Kconfig config IWMMXT diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 6f9975053759..1a4649667ec8 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -139,7 +139,7 @@ endif machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_ORION5X) := orion5x + machine-$(CONFIG_ARCH_ORION) := orion machine-$(CONFIG_ARCH_MSM7X00A) := msm ifeq ($(CONFIG_ARCH_EBSA110),y) @@ -185,7 +185,6 @@ core-$(CONFIG_VFP) += arch/arm/vfp/ # If we have a common platform directory, then include it in the build. core-$(CONFIG_PLAT_IOP) += arch/arm/plat-iop/ -core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/ core-$(CONFIG_ARCH_OMAP) += arch/arm/plat-omap/ core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/ core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ diff --git a/trunk/arch/arm/configs/orion5x_defconfig b/trunk/arch/arm/configs/orion_defconfig similarity index 99% rename from trunk/arch/arm/configs/orion5x_defconfig rename to trunk/arch/arm/configs/orion_defconfig index 52cd99bd52fb..1e5aaa645fcd 100644 --- a/trunk/arch/arm/configs/orion5x_defconfig +++ b/trunk/arch/arm/configs/orion_defconfig @@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set -CONFIG_ARCH_ORION5X=y +CONFIG_ARCH_ORION=y # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set diff --git a/trunk/arch/arm/mach-orion5x/Kconfig b/trunk/arch/arm/mach-orion/Kconfig similarity index 77% rename from trunk/arch/arm/mach-orion5x/Kconfig rename to trunk/arch/arm/mach-orion/Kconfig index 93debf336155..1dcbb6ac5a30 100644 --- a/trunk/arch/arm/mach-orion5x/Kconfig +++ b/trunk/arch/arm/mach-orion/Kconfig @@ -1,4 +1,4 @@ -if ARCH_ORION5X +if ARCH_ORION menu "Orion Implementations" @@ -36,14 +36,6 @@ config MACH_TS209 Say 'Y' here if you want your kernel to support the QNAP TS-109/TS-209 platform. -config MACH_LINKSTATION_PRO - bool "Buffalo Linkstation Pro/Live" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - Buffalo Linkstation Pro/Live platform. Both v1 and - v2 devices are supported. - endmenu endif diff --git a/trunk/arch/arm/mach-orion5x/Makefile b/trunk/arch/arm/mach-orion/Makefile similarity index 68% rename from trunk/arch/arm/mach-orion5x/Makefile rename to trunk/arch/arm/mach-orion/Makefile index 9301bf55910b..f91d937a73e8 100644 --- a/trunk/arch/arm/mach-orion5x/Makefile +++ b/trunk/arch/arm/mach-orion/Makefile @@ -1,7 +1,6 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o +obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o -obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o diff --git a/trunk/arch/arm/mach-orion5x/Makefile.boot b/trunk/arch/arm/mach-orion/Makefile.boot similarity index 100% rename from trunk/arch/arm/mach-orion5x/Makefile.boot rename to trunk/arch/arm/mach-orion/Makefile.boot diff --git a/trunk/arch/arm/mach-orion/addr-map.c b/trunk/arch/arm/mach-orion/addr-map.c new file mode 100644 index 000000000000..58cc3c0333b6 --- /dev/null +++ b/trunk/arch/arm/mach-orion/addr-map.c @@ -0,0 +1,490 @@ +/* + * arch/arm/mach-orion/addr-map.c + * + * Address map functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include "common.h" + +/* + * The Orion has fully programable address map. There's a separate address + * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, + * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own + * address decode windows that allow it to access any of the Orion resources. + * + * CPU address decoding -- + * Linux assumes that it is the boot loader that already setup the access to + * DDR and internal registers. + * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. + * Setup access to various devices located on the device bus interface (e.g. + * flashes, RTC, etc) should be issued by machine-setup.c according to + * specific board population (by using orion_setup_cpu_win()). + * + * Non-CPU Masters address decoding -- + * Unlike the CPU, we setup the access from Orion's master interfaces to DDR + * banks only (the typical use case). + * Setup access for each master to DDR is issued by common.c. + * + * Note: although orion_setbits() and orion_clrbits() are not atomic + * no locking is necessary here since code in this file is only called + * at boot time when there is no concurrency issues. + */ + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_PCI 3 +#define TARGET_PCIE 4 +#define TARGET_DEV_BUS 1 +#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ + ((n) == 1) ? 0xd : \ + ((n) == 2) ? 0xb : \ + ((n) == 3) ? 0x7 : 0xf) +#define ATTR_PCIE_MEM 0x59 +#define ATTR_PCIE_IO 0x51 +#define ATTR_PCI_MEM 0x59 +#define ATTR_PCI_IO 0x51 +#define ATTR_DEV_CS0 0x1e +#define ATTR_DEV_CS1 0x1d +#define ATTR_DEV_CS2 0x1b +#define ATTR_DEV_BOOT 0xf +#define WIN_EN 1 + +/* + * Helpers to get DDR banks info + */ +#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) +#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) +#define DDR_MAX_CS 4 +#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) +#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) +#define DDR_BANK_EN 1 + +/* + * CPU Address Decode Windows registers + */ +#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) +#define CPU_MAX_WIN 8 + +/* + * Use this CPU address decode windows allocation + */ +#define CPU_WIN_PCIE_IO 0 +#define CPU_WIN_PCI_IO 1 +#define CPU_WIN_PCIE_MEM 2 +#define CPU_WIN_PCI_MEM 3 +#define CPU_WIN_DEV_BOOT 4 +#define CPU_WIN_DEV_CS0 5 +#define CPU_WIN_DEV_CS1 6 +#define CPU_WIN_DEV_CS2 7 + +/* + * PCIE Address Decode Windows registers + */ +#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4)) +#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8)) +#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8)) +#define PCIE_WIN_CTRL(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1820 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1880)) +#define PCIE_WIN_BASE(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x1824 + ((n) << 4)) : \ + ORION_PCIE_REG(0x1884)) +#define PCIE_WIN_REMAP(n) (((n) < 5) ? \ + ORION_PCIE_REG(0x182c + ((n) << 4)) : \ + ORION_PCIE_REG(0x188c)) +#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0) +#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0) +#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4) +#define PCIE_MAX_BARS 3 +#define PCIE_MAX_WINS 6 + +/* + * Use PCIE BAR '1' for all DDR banks + */ +#define PCIE_DRAM_BAR 1 + +/* + * PCI Address Decode Windows registers + */ +#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ + ((n) == 1) ? ORION_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) +#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) +#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4)) +#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4)) +#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4)) +#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) + +/* + * PCI configuration heleprs for BAR settings + */ +#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) +#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) +#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) + +/* + * Gigabit Ethernet Address Decode Windows registers + */ +#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) +#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) +#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) +#define ETH_WIN_EN ORION_ETH_REG(0x290) +#define ETH_WIN_PROT ORION_ETH_REG(0x294) +#define ETH_MAX_WIN 6 +#define ETH_MAX_REMAP_WIN 4 + +/* + * USB Address Decode Windows registers + */ +#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \ + : ORION_USB1_REG(0x320 + ((w) << 4))) +#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \ + : ORION_USB1_REG(0x324 + ((w) << 4))) +#define USB_MAX_WIN 4 + +/* + * SATA Address Decode Windows registers + */ +#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10)) +#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10)) +#define SATA_MAX_WIN 4 + +static int __init orion_cpu_win_can_remap(u32 win) +{ + u32 dev, rev; + + orion_pcie_id(&dev, &rev); + if ((dev == MV88F5281_DEV_ID && win < 4) + || (dev == MV88F5182_DEV_ID && win < 2) + || (dev == MV88F5181_DEV_ID && win < 2)) + return 1; + + return 0; +} + +void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) +{ + u32 win, attr, ctrl; + + switch (target) { + case ORION_PCIE_IO: + target = TARGET_PCIE; + attr = ATTR_PCIE_IO; + win = CPU_WIN_PCIE_IO; + break; + case ORION_PCI_IO: + target = TARGET_PCI; + attr = ATTR_PCI_IO; + win = CPU_WIN_PCI_IO; + break; + case ORION_PCIE_MEM: + target = TARGET_PCIE; + attr = ATTR_PCIE_MEM; + win = CPU_WIN_PCIE_MEM; + break; + case ORION_PCI_MEM: + target = TARGET_PCI; + attr = ATTR_PCI_MEM; + win = CPU_WIN_PCI_MEM; + break; + case ORION_DEV_BOOT: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_BOOT; + win = CPU_WIN_DEV_BOOT; + break; + case ORION_DEV0: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS0; + win = CPU_WIN_DEV_CS0; + break; + case ORION_DEV1: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS1; + win = CPU_WIN_DEV_CS1; + break; + case ORION_DEV2: + target = TARGET_DEV_BUS; + attr = ATTR_DEV_CS2; + win = CPU_WIN_DEV_CS2; + break; + case ORION_DDR: + case ORION_REGS: + /* + * Must be mapped by bootloader. + */ + default: + target = attr = win = -1; + BUG(); + } + + base &= 0xffff0000; + ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | + (target << 4) | WIN_EN); + + orion_write(CPU_WIN_BASE(win), base); + orion_write(CPU_WIN_CTRL(win), ctrl); + + if (orion_cpu_win_can_remap(win)) { + if (remap >= 0) { + orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); + orion_write(CPU_WIN_REMAP_HI(win), 0); + } else { + orion_write(CPU_WIN_REMAP_LO(win), base); + orion_write(CPU_WIN_REMAP_HI(win), 0); + } + } +} + +void __init orion_setup_cpu_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < CPU_MAX_WIN; i++) { + orion_write(CPU_WIN_BASE(i), 0); + orion_write(CPU_WIN_CTRL(i), 0); + if (orion_cpu_win_can_remap(i)) { + orion_write(CPU_WIN_REMAP_LO(i), 0); + orion_write(CPU_WIN_REMAP_HI(i), 0); + } + } + + /* + * Setup windows for PCI+PCIe IO+MEM space. + */ + orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, + ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); + orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, + ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); + orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, + ORION_PCIE_MEM_SIZE, -1); + orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, + ORION_PCI_MEM_SIZE, -1); +} + +/* + * Setup PCIE BARs and Address Decode Wins: + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks + * WIN[0-3] -> DRAM bank[0-3] + */ +void __init orion_setup_pcie_wins(void) +{ + u32 base, size, i; + + /* + * First, disable and clear BARs and windows + */ + for (i = 1; i < PCIE_MAX_BARS; i++) { + orion_write(PCIE_BAR_CTRL(i), 0); + orion_write(PCIE_BAR_LO(i), 0); + orion_write(PCIE_BAR_HI(i), 0); + } + + for (i = 0; i < PCIE_MAX_WINS; i++) { + orion_write(PCIE_WIN_CTRL(i), 0); + orion_write(PCIE_WIN_BASE(i), 0); + orion_write(PCIE_WIN_REMAP(i), 0); + } + + /* + * Setup windows for DDR banks. Count total DDR size on the fly. + */ + base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0))); + size = 0; + for (i = 0; i < DDR_MAX_CS; i++) { + u32 bank_base, bank_size; + bank_size = orion_read(DDR_SIZE_CS(i)); + bank_base = orion_read(DDR_BASE_CS(i)); + if (bank_size & DDR_BANK_EN) { + bank_size = DDR_REG_TO_SIZE(bank_size); + bank_base = DDR_REG_TO_BASE(bank_base); + orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000); + orion_write(PCIE_WIN_REMAP(i), 0); + orion_write(PCIE_WIN_CTRL(i), + ((bank_size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | + (PCIE_DRAM_BAR << 1) | WIN_EN); + size += bank_size; + } + } + + /* + * Setup BAR[1] to all DRAM banks + */ + orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000); + orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0); + orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR), + ((size - 1) & 0xffff0000) | WIN_EN); +} + +void __init orion_setup_pci_wins(void) +{ + u32 base, size, i; + + /* + * First, disable windows + */ + orion_write(PCI_BAR_ENABLE, 0xffffffff); + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + base = orion_read(DDR_BASE_CS(i)); + size = orion_read(DDR_SIZE_CS(i)); + if (size & DDR_BANK_EN) { + u32 bus, dev, func, reg, val; + size = DDR_REG_TO_SIZE(size); + base = DDR_REG_TO_BASE(base); + bus = orion_pci_local_bus_nr(); + dev = orion_pci_local_dev_nr(); + func = PCI_CONF_FUNC_BAR_CS(i); + reg = PCI_CONF_REG_BAR_LO_CS(i); + orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, + (base & 0xfffff000) | (val & 0xfff)); + reg = PCI_CONF_REG_BAR_HI_CS(i); + orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0); + orion_write(PCI_BAR_SIZE_DDR_CS(i), + (size - 1) & 0xfffff000); + orion_write(PCI_BAR_REMAP_DDR_CS(i), + base & 0xfffff000); + orion_clrbits(PCI_BAR_ENABLE, (1 << i)); + } + } + + /* + * Disable automatic update of address remaping when writing to BARs + */ + orion_setbits(PCI_ADDR_DECODE_CTRL, 1); +} + +void __init orion_setup_usb_wins(void) +{ + int i; + u32 usb_if, dev, rev; + u32 max_usb_if = 1; + + orion_pcie_id(&dev, &rev); + if (dev == MV88F5182_DEV_ID) + max_usb_if = 2; + + for (usb_if = 0; usb_if < max_usb_if; usb_if++) { + /* + * First, disable and clear windows + */ + for (i = 0; i < USB_MAX_WIN; i++) { + orion_write(USB_WIN_BASE(usb_if, i), 0); + orion_write(USB_WIN_CTRL(usb_if, i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(USB_WIN_CTRL(usb_if, i), + ((size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | WIN_EN); + orion_write(USB_WIN_BASE(usb_if, i), + base & 0xffff0000); + } + } + } +} + +void __init orion_setup_eth_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < ETH_MAX_WIN; i++) { + orion_write(ETH_WIN_BASE(i), 0); + orion_write(ETH_WIN_SIZE(i), 0); + orion_setbits(ETH_WIN_EN, 1 << i); + orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); + if (i < ETH_MAX_REMAP_WIN) + orion_write(ETH_WIN_REMAP(i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); + orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + TARGET_DDR); + orion_clrbits(ETH_WIN_EN, 1 << i); + orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); + } + } +} + +void __init orion_setup_sata_wins(void) +{ + int i; + + /* + * First, disable and clear windows + */ + for (i = 0; i < SATA_MAX_WIN; i++) { + orion_write(SATA_WIN_BASE(i), 0); + orion_write(SATA_WIN_CTRL(i), 0); + } + + /* + * Setup windows for DDR banks. + */ + for (i = 0; i < DDR_MAX_CS; i++) { + u32 base, size; + size = orion_read(DDR_SIZE_CS(i)); + base = orion_read(DDR_BASE_CS(i)); + if (size & DDR_BANK_EN) { + base = DDR_REG_TO_BASE(base); + size = DDR_REG_TO_SIZE(size); + orion_write(SATA_WIN_CTRL(i), + ((size-1) & 0xffff0000) | + (ATTR_DDR_CS(i) << 8) | + (TARGET_DDR << 4) | WIN_EN); + orion_write(SATA_WIN_BASE(i), + base & 0xffff0000); + } + } +} diff --git a/trunk/arch/arm/mach-orion5x/common.c b/trunk/arch/arm/mach-orion/common.c similarity index 52% rename from trunk/arch/arm/mach-orion5x/common.c rename to trunk/arch/arm/mach-orion/common.c index 439c7784af02..bbc2b4ec932c 100644 --- a/trunk/arch/arm/mach-orion5x/common.c +++ b/trunk/arch/arm/mach-orion/common.c @@ -1,12 +1,12 @@ /* - * arch/arm/mach-orion5x/common.c + * arch/arm/mach-orion/common.c * - * Core functions for Marvell Orion 5x SoCs + * Core functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -14,71 +14,64 @@ #include #include #include -#include #include #include -#include #include #include #include #include #include -#include #include -#include -#include -#include -#include #include "common.h" /***************************************************************************** * I/O Address Mapping ****************************************************************************/ -static struct map_desc orion5x_io_desc[] __initdata = { +static struct map_desc orion_io_desc[] __initdata = { { - .virtual = ORION5X_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), - .length = ORION5X_REGS_SIZE, + .virtual = ORION_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), + .length = ORION_REGS_SIZE, .type = MT_DEVICE }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), - .length = ORION5X_PCIE_IO_SIZE, + .virtual = ORION_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), + .length = ORION_PCIE_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), - .length = ORION5X_PCI_IO_SIZE, + .virtual = ORION_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), + .length = ORION_PCI_IO_SIZE, .type = MT_DEVICE }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, - .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), - .length = ORION5X_PCIE_WA_SIZE, + .virtual = ORION_PCIE_WA_VIRT_BASE, + .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), + .length = ORION_PCIE_WA_SIZE, .type = MT_DEVICE }, }; -void __init orion5x_map_io(void) +void __init orion_map_io(void) { - iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); + iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); } /***************************************************************************** * UART ****************************************************************************/ -static struct resource orion5x_uart_resources[] = { +static struct resource orion_uart_resources[] = { { .start = UART0_PHYS_BASE, .end = UART0_PHYS_BASE + 0xff, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION5X_UART0, - .end = IRQ_ORION5X_UART0, + .start = IRQ_ORION_UART0, + .end = IRQ_ORION_UART0, .flags = IORESOURCE_IRQ, }, { @@ -87,102 +80,96 @@ static struct resource orion5x_uart_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION5X_UART1, - .end = IRQ_ORION5X_UART1, + .start = IRQ_ORION_UART1, + .end = IRQ_ORION_UART1, .flags = IORESOURCE_IRQ, }, }; -static struct plat_serial8250_port orion5x_uart_data[] = { +static struct plat_serial8250_port orion_uart_data[] = { { .mapbase = UART0_PHYS_BASE, .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION5X_UART0, + .irq = IRQ_ORION_UART0, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION5X_TCLK, + .uartclk = ORION_TCLK, }, { .mapbase = UART1_PHYS_BASE, .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION5X_UART1, + .irq = IRQ_ORION_UART1, .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, - .uartclk = ORION5X_TCLK, + .uartclk = ORION_TCLK, }, { }, }; -static struct platform_device orion5x_uart = { +static struct platform_device orion_uart = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, .dev = { - .platform_data = orion5x_uart_data, + .platform_data = orion_uart_data, }, - .resource = orion5x_uart_resources, - .num_resources = ARRAY_SIZE(orion5x_uart_resources), + .resource = orion_uart_resources, + .num_resources = ARRAY_SIZE(orion_uart_resources), }; /******************************************************************************* * USB Controller - 2 interfaces ******************************************************************************/ -static struct resource orion5x_ehci0_resources[] = { +static struct resource orion_ehci0_resources[] = { { - .start = ORION5X_USB0_PHYS_BASE, - .end = ORION5X_USB0_PHYS_BASE + SZ_4K, + .start = ORION_USB0_PHYS_BASE, + .end = ORION_USB0_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION5X_USB0_CTRL, - .end = IRQ_ORION5X_USB0_CTRL, + .start = IRQ_ORION_USB0_CTRL, + .end = IRQ_ORION_USB0_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct resource orion5x_ehci1_resources[] = { +static struct resource orion_ehci1_resources[] = { { - .start = ORION5X_USB1_PHYS_BASE, - .end = ORION5X_USB1_PHYS_BASE + SZ_4K, + .start = ORION_USB1_PHYS_BASE, + .end = ORION_USB1_PHYS_BASE + SZ_4K, .flags = IORESOURCE_MEM, }, { - .start = IRQ_ORION5X_USB1_CTRL, - .end = IRQ_ORION5X_USB1_CTRL, + .start = IRQ_ORION_USB1_CTRL, + .end = IRQ_ORION_USB1_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct orion_ehci_data orion5x_ehci_data = { - .dram = &orion5x_mbus_dram_info, -}; - static u64 ehci_dmamask = 0xffffffffUL; -static struct platform_device orion5x_ehci0 = { +static struct platform_device orion_ehci0 = { .name = "orion-ehci", .id = 0, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion5x_ehci_data, }, - .resource = orion5x_ehci0_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), + .resource = orion_ehci0_resources, + .num_resources = ARRAY_SIZE(orion_ehci0_resources), }; -static struct platform_device orion5x_ehci1 = { +static struct platform_device orion_ehci1 = { .name = "orion-ehci", .id = 1, .dev = { .dma_mask = &ehci_dmamask, .coherent_dma_mask = 0xffffffff, - .platform_data = &orion5x_ehci_data, }, - .resource = orion5x_ehci1_resources, - .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), + .resource = orion_ehci1_resources, + .num_resources = ARRAY_SIZE(orion_ehci1_resources), }; /***************************************************************************** @@ -190,42 +177,42 @@ static struct platform_device orion5x_ehci1 = { * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) ****************************************************************************/ -static struct resource orion5x_eth_shared_resources[] = { +static struct resource orion_eth_shared_resources[] = { { - .start = ORION5X_ETH_PHYS_BASE + 0x2000, - .end = ORION5X_ETH_PHYS_BASE + 0x3fff, + .start = ORION_ETH_PHYS_BASE + 0x2000, + .end = ORION_ETH_PHYS_BASE + 0x3fff, .flags = IORESOURCE_MEM, }, }; -static struct platform_device orion5x_eth_shared = { +static struct platform_device orion_eth_shared = { .name = MV643XX_ETH_SHARED_NAME, .id = 0, .num_resources = 1, - .resource = orion5x_eth_shared_resources, + .resource = orion_eth_shared_resources, }; -static struct resource orion5x_eth_resources[] = { +static struct resource orion_eth_resources[] = { { .name = "eth irq", - .start = IRQ_ORION5X_ETH_SUM, - .end = IRQ_ORION5X_ETH_SUM, + .start = IRQ_ORION_ETH_SUM, + .end = IRQ_ORION_ETH_SUM, .flags = IORESOURCE_IRQ, } }; -static struct platform_device orion5x_eth = { +static struct platform_device orion_eth = { .name = MV643XX_ETH_NAME, .id = 0, .num_resources = 1, - .resource = orion5x_eth_resources, + .resource = orion_eth_resources, }; -void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) +void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion5x_eth.dev.platform_data = eth_data; - platform_device_register(&orion5x_eth_shared); - platform_device_register(&orion5x_eth); + orion_eth.dev.platform_data = eth_data; + platform_device_register(&orion_eth_shared); + platform_device_register(&orion_eth); } /***************************************************************************** @@ -233,13 +220,13 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) * (The Orion and Discovery (MV643xx) families share the same I2C controller) ****************************************************************************/ -static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { +static struct mv64xxx_i2c_pdata orion_i2c_pdata = { .freq_m = 8, /* assumes 166 MHz TCLK */ .freq_n = 3, .timeout = 1000, /* Default timeout of 1 second */ }; -static struct resource orion5x_i2c_resources[] = { +static struct resource orion_i2c_resources[] = { { .name = "i2c base", .start = I2C_PHYS_BASE, @@ -248,70 +235,56 @@ static struct resource orion5x_i2c_resources[] = { }, { .name = "i2c irq", - .start = IRQ_ORION5X_I2C, - .end = IRQ_ORION5X_I2C, + .start = IRQ_ORION_I2C, + .end = IRQ_ORION_I2C, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion5x_i2c = { +static struct platform_device orion_i2c = { .name = MV64XXX_I2C_CTLR_NAME, .id = 0, - .num_resources = ARRAY_SIZE(orion5x_i2c_resources), - .resource = orion5x_i2c_resources, + .num_resources = ARRAY_SIZE(orion_i2c_resources), + .resource = orion_i2c_resources, .dev = { - .platform_data = &orion5x_i2c_pdata, + .platform_data = &orion_i2c_pdata, }, }; /***************************************************************************** * Sata port ****************************************************************************/ -static struct resource orion5x_sata_resources[] = { +static struct resource orion_sata_resources[] = { { .name = "sata base", - .start = ORION5X_SATA_PHYS_BASE, - .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, + .start = ORION_SATA_PHYS_BASE, + .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, .flags = IORESOURCE_MEM, }, { .name = "sata irq", - .start = IRQ_ORION5X_SATA, - .end = IRQ_ORION5X_SATA, + .start = IRQ_ORION_SATA, + .end = IRQ_ORION_SATA, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion5x_sata = { +static struct platform_device orion_sata = { .name = "sata_mv", .id = 0, .dev = { .coherent_dma_mask = 0xffffffff, }, - .num_resources = ARRAY_SIZE(orion5x_sata_resources), - .resource = orion5x_sata_resources, + .num_resources = ARRAY_SIZE(orion_sata_resources), + .resource = orion_sata_resources, }; -void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) +void __init orion_sata_init(struct mv_sata_platform_data *sata_data) { - sata_data->dram = &orion5x_mbus_dram_info; - orion5x_sata.dev.platform_data = sata_data; - platform_device_register(&orion5x_sata); + orion_sata.dev.platform_data = sata_data; + platform_device_register(&orion_sata); } -/***************************************************************************** - * Time handling - ****************************************************************************/ - -static void orion5x_timer_init(void) -{ - orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); -} - -struct sys_timer orion5x_timer = { - .init = orion5x_timer_init, -}; - /***************************************************************************** * General ****************************************************************************/ @@ -319,9 +292,9 @@ struct sys_timer orion5x_timer = { /* * Identify device ID and rev from PCIE configuration header space '0'. */ -static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) +static void orion_id(u32 *dev, u32 *rev, char **dev_name) { - orion5x_pcie_id(dev, rev); + orion_pcie_id(dev, rev); if (*dev == MV88F5281_DEV_ID) { if (*rev == MV88F5281_REV_D2) { @@ -348,28 +321,33 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) } } -void __init orion5x_init(void) +void __init orion_init(void) { char *dev_name; u32 dev, rev; - orion5x_id(&dev, &rev, &dev_name); - printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); + orion_id(&dev, &rev, &dev_name); + printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); /* * Setup Orion address map */ - orion5x_setup_cpu_mbus_bridge(); - orion5x_setup_eth_wins(); + orion_setup_cpu_wins(); + orion_setup_usb_wins(); + orion_setup_eth_wins(); + orion_setup_pci_wins(); + orion_setup_pcie_wins(); + if (dev == MV88F5182_DEV_ID) + orion_setup_sata_wins(); /* - * Register devices. + * REgister devices */ - platform_device_register(&orion5x_uart); - platform_device_register(&orion5x_ehci0); + platform_device_register(&orion_uart); + platform_device_register(&orion_ehci0); if (dev == MV88F5182_DEV_ID) - platform_device_register(&orion5x_ehci1); - platform_device_register(&orion5x_i2c); + platform_device_register(&orion_ehci1); + platform_device_register(&orion_i2c); } /* diff --git a/trunk/arch/arm/mach-orion/common.h b/trunk/arch/arm/mach-orion/common.h new file mode 100644 index 000000000000..501497cc2c4d --- /dev/null +++ b/trunk/arch/arm/mach-orion/common.h @@ -0,0 +1,92 @@ +#ifndef __ARCH_ORION_COMMON_H__ +#define __ARCH_ORION_COMMON_H__ + +/* + * Basic Orion init functions used early by machine-setup. + */ + +void __init orion_map_io(void); +void __init orion_init_irq(void); +void __init orion_init(void); + +/* + * Enumerations and functions for Orion windows mapping. Used by Orion core + * functions to map its interfaces and by the machine-setup to map its on- + * board devices. Details in /mach-orion/addr-map.c + */ + +enum orion_target { + ORION_DEV_BOOT = 0, + ORION_DEV0, + ORION_DEV1, + ORION_DEV2, + ORION_PCIE_MEM, + ORION_PCIE_IO, + ORION_PCI_MEM, + ORION_PCI_IO, + ORION_DDR, + ORION_REGS, + ORION_MAX_TARGETS +}; + +void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); +void orion_setup_cpu_wins(void); +void orion_setup_eth_wins(void); +void orion_setup_usb_wins(void); +void orion_setup_pci_wins(void); +void orion_setup_pcie_wins(void); +void orion_setup_sata_wins(void); + +/* + * Shared code used internally by other Orion core functions. + * (/mach-orion/pci.c) + */ + +struct pci_sys_data; +struct pci_bus; + +void orion_pcie_id(u32 *dev, u32 *rev); +u32 orion_pcie_local_bus_nr(void); +u32 orion_pci_local_bus_nr(void); +u32 orion_pci_local_dev_nr(void); +int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); +int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val); +int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val); + +/* + * Valid GPIO pins according to MPP setup, used by machine-setup. + * (/mach-orion/gpio.c). + */ + +void __init orion_gpio_set_valid_pins(u32 pins); +void gpio_display(void); /* debug */ + +/* + * Orion system timer (clocksource + clockevnt, /mach-orion/time.c) + */ +extern struct sys_timer orion_timer; + +/* + * Pull in Orion Ethernet platform_data, used by machine-setup + */ + +struct mv643xx_eth_platform_data; + +void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data); + +/* + * Orion Sata platform_data, used by machine-setup + */ + +struct mv_sata_platform_data; + +void __init orion_sata_init(struct mv_sata_platform_data *sata_data); + +struct machine_desc; +struct meminfo; +struct tag; +extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, + char **, struct meminfo *); + +#endif /* __ARCH_ORION_COMMON_H__ */ diff --git a/trunk/arch/arm/mach-orion5x/db88f5281-setup.c b/trunk/arch/arm/mach-orion/db88f5281-setup.c similarity index 88% rename from trunk/arch/arm/mach-orion5x/db88f5281-setup.c rename to trunk/arch/arm/mach-orion/db88f5281-setup.c index 872aed372327..5ef44e1a2d36 100644 --- a/trunk/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/trunk/arch/arm/mach-orion/db88f5281-setup.c @@ -1,12 +1,12 @@ /* - * arch/arm/mach-orion5x/db88f5281-setup.c + * arch/arm/mach-orion/db88f5281-setup.c * * Marvell Orion-2 Development Board Setup * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -24,8 +24,8 @@ #include #include #include -#include -#include +#include +#include #include "common.h" /***************************************************************************** @@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = { .nr_controllers = 2, .preinit = db88f5281_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, .map_irq = db88f5281_pci_map_irq, }; @@ -312,16 +312,19 @@ static void __init db88f5281_init(void) /* * Basic Orion setup. Need to be called early. */ - orion5x_init(); + orion_init(); /* * Setup the CPU address decode windows for our on-board devices */ - orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); - orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); - orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); - orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, + DB88F5281_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, + DB88F5281_7SEG_SIZE, -1); + orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, + DB88F5281_NOR_SIZE, -1); + orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, + DB88F5281_NAND_SIZE, -1); /* * Setup Multiplexing Pins: @@ -337,25 +340,25 @@ static void __init db88f5281_init(void) * MPP18: UART1_CTS MPP19: UART1_RTS * MPP-DEV: DEV_D[16:31] */ - orion5x_write(MPP_0_7_CTRL, 0x00222203); - orion5x_write(MPP_8_15_CTRL, 0x44000000); - orion5x_write(MPP_16_19_CTRL, 0); - orion5x_write(MPP_DEV_CTRL, 0); + orion_write(MPP_0_7_CTRL, 0x00222203); + orion_write(MPP_8_15_CTRL, 0x44000000); + orion_write(MPP_16_19_CTRL, 0); + orion_write(MPP_DEV_CTRL, 0); - orion5x_gpio_set_valid_pins(0x00003fc3); + orion_gpio_set_valid_pins(0x00003fc3); platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); - orion5x_eth_init(&db88f5281_eth_data); + orion_eth_init(&db88f5281_eth_data); } MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") /* Maintainer: Tzachi Perelstein */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, + .phys_io = ORION_REGS_PHYS_BASE, + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, .boot_params = 0x00000100, .init_machine = db88f5281_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-orion5x/dns323-setup.c b/trunk/arch/arm/mach-orion/dns323-setup.c similarity index 89% rename from trunk/arch/arm/mach-orion5x/dns323-setup.c rename to trunk/arch/arm/mach-orion/dns323-setup.c index d67790ef236e..076e155ad510 100644 --- a/trunk/arch/arm/mach-orion5x/dns323-setup.c +++ b/trunk/arch/arm/mach-orion/dns323-setup.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-orion5x/dns323-setup.c + * arch/arm/mach-orion/dns323-setup.c * * Copyright (C) 2007 Herbert Valerio Riedel * @@ -25,7 +25,8 @@ #include #include #include -#include +#include +#include #include "common.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 @@ -44,8 +45,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { /* PCI-E */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; pr_err("%s: requested mapping for unknown bus\n", __func__); @@ -55,8 +56,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci dns323_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, .map_irq = dns323_pci_map_irq, }; @@ -246,25 +247,27 @@ static void dns323_power_off(void) static void __init dns323_init(void) { /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); + orion_init(); /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ - orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, + DNS323_NOR_BOOT_SIZE, -1); /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE * * Open a special address decode windows for the PCIE WA. */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); + orion_write(ORION_REGS_VIRT_BASE | 0x20070, + (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ - orion5x_write(MPP_0_7_CTRL, 0); - orion5x_write(MPP_8_15_CTRL, 0); - orion5x_write(MPP_16_19_CTRL, 0); - orion5x_write(MPP_DEV_CTRL, 0); + orion_write(MPP_0_7_CTRL, 0); + orion_write(MPP_8_15_CTRL, 0); + orion_write(MPP_16_19_CTRL, 0); + orion_write(MPP_DEV_CTRL, 0); /* Define used GPIO pins @@ -287,7 +290,7 @@ static void __init dns323_init(void) | 14 | Out | //unknown// | 15 | Out | //unknown// */ - orion5x_gpio_set_valid_pins(0x07f6); + orion_gpio_set_valid_pins(0x07f6); /* register dns323 specific power-off method */ if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) @@ -303,18 +306,18 @@ static void __init dns323_init(void) i2c_register_board_info(0, dns323_i2c_devices, ARRAY_SIZE(dns323_i2c_devices)); - orion5x_eth_init(&dns323_eth_data); + orion_eth_init(&dns323_eth_data); } /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ MACHINE_START(DNS323, "D-Link DNS-323") /* Maintainer: Herbert Valerio Riedel */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION_REGS_PHYS_BASE, + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = dns323_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/trunk/arch/arm/mach-orion5x/gpio.c b/trunk/arch/arm/mach-orion/gpio.c similarity index 68% rename from trunk/arch/arm/mach-orion5x/gpio.c rename to trunk/arch/arm/mach-orion/gpio.c index 8108c316c426..f713818c66a3 100644 --- a/trunk/arch/arm/mach-orion5x/gpio.c +++ b/trunk/arch/arm/mach-orion/gpio.c @@ -1,12 +1,12 @@ /* - * arch/arm/mach-orion5x/gpio.c + * arch/arm/mach-orion/gpio.c * * GPIO functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -16,15 +16,14 @@ #include #include #include -#include -#include +#include #include "common.h" static DEFINE_SPINLOCK(gpio_lock); static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ -void __init orion5x_gpio_set_valid_pins(u32 pins) +void __init orion_gpio_set_valid_pins(u32 pins) { gpio_valid[0] = pins; } @@ -50,7 +49,7 @@ int gpio_direction_input(unsigned pin) if (!gpio_label[pin]) gpio_label[pin] = "?"; - orion5x_setbits(GPIO_IO_CONF, 1 << pin); + orion_setbits(GPIO_IO_CONF, 1 << pin); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -77,12 +76,12 @@ int gpio_direction_output(unsigned pin, int value) gpio_label[pin] = "?"; mask = 1 << pin; - orion5x_clrbits(GPIO_BLINK_EN, mask); + orion_clrbits(GPIO_BLINK_EN, mask); if (value) - orion5x_setbits(GPIO_OUT, mask); + orion_setbits(GPIO_OUT, mask); else - orion5x_clrbits(GPIO_OUT, mask); - orion5x_clrbits(GPIO_IO_CONF, mask); + orion_clrbits(GPIO_OUT, mask); + orion_clrbits(GPIO_IO_CONF, mask); spin_unlock_irqrestore(&gpio_lock, flags); return 0; @@ -93,10 +92,10 @@ int gpio_get_value(unsigned pin) { int val, mask = 1 << pin; - if (orion5x_read(GPIO_IO_CONF) & mask) - val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); + if (orion_read(GPIO_IO_CONF) & mask) + val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); else - val = orion5x_read(GPIO_OUT); + val = orion_read(GPIO_OUT); return val & mask; } @@ -109,32 +108,32 @@ void gpio_set_value(unsigned pin, int value) spin_lock_irqsave(&gpio_lock, flags); - orion5x_clrbits(GPIO_BLINK_EN, mask); + orion_clrbits(GPIO_BLINK_EN, mask); if (value) - orion5x_setbits(GPIO_OUT, mask); + orion_setbits(GPIO_OUT, mask); else - orion5x_clrbits(GPIO_OUT, mask); + orion_clrbits(GPIO_OUT, mask); spin_unlock_irqrestore(&gpio_lock, flags); } EXPORT_SYMBOL(gpio_set_value); -void orion5x_gpio_set_blink(unsigned pin, int blink) +void orion_gpio_set_blink(unsigned pin, int blink) { unsigned long flags; int mask = 1 << pin; spin_lock_irqsave(&gpio_lock, flags); - orion5x_clrbits(GPIO_OUT, mask); + orion_clrbits(GPIO_OUT, mask); if (blink) - orion5x_setbits(GPIO_BLINK_EN, mask); + orion_setbits(GPIO_BLINK_EN, mask); else - orion5x_clrbits(GPIO_BLINK_EN, mask); + orion_clrbits(GPIO_BLINK_EN, mask); spin_unlock_irqrestore(&gpio_lock, flags); } -EXPORT_SYMBOL(orion5x_gpio_set_blink); +EXPORT_SYMBOL(orion_gpio_set_blink); int gpio_request(unsigned pin, const char *label) { @@ -188,39 +187,39 @@ void gpio_display(void) printk("GPIO, free\n"); } else { printk("GPIO, used by %s, ", gpio_label[i]); - if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { + if (orion_read(GPIO_IO_CONF) & (1 << i)) { printk("input, active %s, level %s, edge %s\n", - ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); } else { - printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); + printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); } } } printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); + MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); + MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); + MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); + MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, orion5x_read(GPIO_OUT)); + GPIO_OUT, orion_read(GPIO_OUT)); printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); + GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); + GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); + GPIO_IN_POL, orion_read(GPIO_IN_POL)); printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); + GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); + GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); + GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); + GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); } diff --git a/trunk/arch/arm/mach-orion5x/irq.c b/trunk/arch/arm/mach-orion/irq.c similarity index 55% rename from trunk/arch/arm/mach-orion5x/irq.c rename to trunk/arch/arm/mach-orion/irq.c index dd21f38c5d37..df7e12ad378b 100644 --- a/trunk/arch/arm/mach-orion5x/irq.c +++ b/trunk/arch/arm/mach-orion/irq.c @@ -1,12 +1,12 @@ /* - * arch/arm/mach-orion5x/irq.c + * arch/arm/mach-orion/irq.c * * Core IRQ functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -14,9 +14,7 @@ #include #include #include -#include -#include -#include +#include #include "common.h" /***************************************************************************** @@ -44,46 +42,46 @@ * polarity LEVEL mask * ****************************************************************************/ -static void orion5x_gpio_irq_ack(u32 irq) +static void orion_gpio_irq_ack(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) /* * Mask bit for level interrupt */ - orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); else /* * Clear casue bit for egde interrupt */ - orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); + orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); } -static void orion5x_gpio_irq_mask(u32 irq) +static void orion_gpio_irq_mask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); + orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); else - orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); + orion_clrbits(GPIO_EDGE_MASK, 1 << pin); } -static void orion5x_gpio_irq_unmask(u32 irq) +static void orion_gpio_irq_unmask(u32 irq) { int pin = irq_to_gpio(irq); if (irq_desc[irq].status & IRQ_LEVEL) - orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); + orion_setbits(GPIO_LEVEL_MASK, 1 << pin); else - orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); + orion_setbits(GPIO_EDGE_MASK, 1 << pin); } -static int orion5x_gpio_set_irq_type(u32 irq, u32 type) +static int orion_gpio_set_irq_type(u32 irq, u32 type) { int pin = irq_to_gpio(irq); struct irq_desc *desc; - if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { - printk(KERN_ERR "orion5x_gpio_set_irq_type failed " + if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + printk(KERN_ERR "orion_gpio_set_irq_type failed " "(irq %d, pin %d).\n", irq, pin); return -EINVAL; } @@ -94,22 +92,22 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) case IRQT_HIGH: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); + orion_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_LOW: desc->handle_irq = handle_level_irq; desc->status |= IRQ_LEVEL; - orion5x_setbits(GPIO_IN_POL, (1 << pin)); + orion_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_RISING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); + orion_clrbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_FALLING: desc->handle_irq = handle_edge_irq; desc->status &= ~IRQ_LEVEL; - orion5x_setbits(GPIO_IN_POL, (1 << pin)); + orion_setbits(GPIO_IN_POL, (1 << pin)); break; case IRQT_BOTHEDGE: desc->handle_irq = handle_edge_irq; @@ -117,11 +115,11 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) /* * set initial polarity based on current input level */ - if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) + if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) & (1 << pin)) - orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ + orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ else - orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ + orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ break; default: @@ -135,22 +133,22 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) return 0; } -static struct irq_chip orion5x_gpio_irq_chip = { +static struct irq_chip orion_gpio_irq_chip = { .name = "Orion-IRQ-GPIO", - .ack = orion5x_gpio_irq_ack, - .mask = orion5x_gpio_irq_mask, - .unmask = orion5x_gpio_irq_unmask, - .set_type = orion5x_gpio_set_irq_type, + .ack = orion_gpio_irq_ack, + .mask = orion_gpio_irq_mask, + .unmask = orion_gpio_irq_unmask, + .set_type = orion_gpio_set_irq_type, }; -static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) { u32 cause, offs, pin; - BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); - offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; - cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | - (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); + BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); + offs = (irq - IRQ_ORION_GPIO_0_7) * 8; + cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | + (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); for (pin = offs; pin < offs + 8; pin++) { if (cause & (1 << pin)) { @@ -158,16 +156,16 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc = irq_desc + irq; if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { /* Swap polarity (race with GPIO line) */ - u32 polarity = orion5x_read(GPIO_IN_POL); + u32 polarity = orion_read(GPIO_IN_POL); polarity ^= 1 << pin; - orion5x_write(GPIO_IN_POL, polarity); + orion_write(GPIO_IN_POL, polarity); } desc_handle_irq(irq, desc); } } } -static void __init orion5x_init_gpio_irq(void) +static void __init orion_init_gpio_irq(void) { int i; struct irq_desc *desc; @@ -175,37 +173,69 @@ static void __init orion5x_init_gpio_irq(void) /* * Mask and clear GPIO IRQ interrupts */ - orion5x_write(GPIO_LEVEL_MASK, 0x0); - orion5x_write(GPIO_EDGE_MASK, 0x0); - orion5x_write(GPIO_EDGE_CAUSE, 0x0); + orion_write(GPIO_LEVEL_MASK, 0x0); + orion_write(GPIO_EDGE_MASK, 0x0); + orion_write(GPIO_EDGE_CAUSE, 0x0); /* * Register chained level handlers for GPIO IRQs by default. * User can use set_type() if he wants to use edge types handlers. */ - for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { - set_irq_chip(i, &orion5x_gpio_irq_chip); + for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion_gpio_irq_chip); set_irq_handler(i, handle_level_irq); desc = irq_desc + i; desc->status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } - set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); - set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); + set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); } /***************************************************************************** * Orion Main IRQ ****************************************************************************/ -static void __init orion5x_init_main_irq(void) +static void orion_main_irq_mask(u32 irq) { - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); + orion_clrbits(MAIN_IRQ_MASK, 1 << irq); } -void __init orion5x_init_irq(void) +static void orion_main_irq_unmask(u32 irq) { - orion5x_init_main_irq(); - orion5x_init_gpio_irq(); + orion_setbits(MAIN_IRQ_MASK, 1 << irq); +} + +static struct irq_chip orion_main_irq_chip = { + .name = "Orion-IRQ-Main", + .ack = orion_main_irq_mask, + .mask = orion_main_irq_mask, + .unmask = orion_main_irq_unmask, +}; + +static void __init orion_init_main_irq(void) +{ + int i; + + /* + * Mask and clear Main IRQ interrupts + */ + orion_write(MAIN_IRQ_MASK, 0x0); + orion_write(MAIN_IRQ_CAUSE, 0x0); + + /* + * Register level handler for Main IRQs + */ + for (i = 0; i < IRQ_ORION_GPIO_START; i++) { + set_irq_chip(i, &orion_main_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } +} + +void __init orion_init_irq(void) +{ + orion_init_main_irq(); + orion_init_gpio_irq(); } diff --git a/trunk/arch/arm/mach-orion5x/kurobox_pro-setup.c b/trunk/arch/arm/mach-orion/kurobox_pro-setup.c similarity index 75% rename from trunk/arch/arm/mach-orion5x/kurobox_pro-setup.c rename to trunk/arch/arm/mach-orion/kurobox_pro-setup.c index 91413455beba..785a07bdf1e2 100644 --- a/trunk/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/trunk/arch/arm/mach-orion/kurobox_pro-setup.c @@ -1,10 +1,10 @@ /* - * arch/arm/mach-orion5x/kurobox_pro-setup.c + * arch/arm/mach-orion/kurobox_pro-setup.c * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -22,8 +22,8 @@ #include #include #include -#include -#include +#include +#include #include "common.h" /***************************************************************************** @@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI isn't used on the Kuro */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; else printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); @@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) static struct hw_pci kurobox_pro_pci __initdata = { .nr_controllers = 1, .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, .map_irq = kurobox_pro_pci_map_irq, }; @@ -178,25 +178,31 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = { * General Setup ****************************************************************************/ +static struct platform_device *kurobox_pro_devices[] __initdata = { + &kurobox_pro_nor_flash, + &kurobox_pro_nand_flash, +}; + static void __init kurobox_pro_init(void) { /* * Setup basic Orion functions. Need to be called early. */ - orion5x_init(); + orion_init(); /* * Setup the CPU address decode windows for our devices */ - orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); - orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); - + orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE, -1); /* * Open a special address decode windows for the PCIE WA. */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); /* * Setup Multiplexing Pins -- @@ -213,44 +219,26 @@ static void __init kurobox_pro_init(void) * MPP[15] SATA 1 active indication * MPP[16-19] Not used */ - orion5x_write(MPP_0_7_CTRL, 0x44220003); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x0); + orion_write(MPP_0_7_CTRL, 0x44220003); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x0); - orion5x_gpio_set_valid_pins(0x0000000c); + orion_gpio_set_valid_pins(0x0000000c); - platform_device_register(&kurobox_pro_nor_flash); - if (machine_is_kurobox_pro()) - platform_device_register(&kurobox_pro_nand_flash); + platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); - orion5x_eth_init(&kurobox_pro_eth_data); - orion5x_sata_init(&kurobox_pro_sata_data); + orion_eth_init(&kurobox_pro_eth_data); + orion_sata_init(&kurobox_pro_sata_data); } -#ifdef CONFIG_MACH_KUROBOX_PRO MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, - .boot_params = 0x00000100, - .init_machine = kurobox_pro_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, - .fixup = tag_fixup_mem32, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_LINKSTATION_PRO -MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") - /* Maintainer: Byron Bradley */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION_REGS_PHYS_BASE, + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = kurobox_pro_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, .fixup = tag_fixup_mem32, MACHINE_END -#endif diff --git a/trunk/arch/arm/mach-orion/pci.c b/trunk/arch/arm/mach-orion/pci.c new file mode 100644 index 000000000000..b109bb46681e --- /dev/null +++ b/trunk/arch/arm/mach-orion/pci.c @@ -0,0 +1,557 @@ +/* + * arch/arm/mach-orion/pci.c + * + * PCI and PCIE functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Orion has one PCIE controller and one PCI controller. + * + * Note1: The local PCIE bus number is '0'. The local PCI bus number + * follows the scanned PCIE bridged busses, if any. + * + * Note2: It is possible for PCI/PCIE agents to access many subsystem's + * space, by configuring BARs and Address Decode Windows, e.g. flashes on + * device bus, Orion registers, etc. However this code only enable the + * access to DDR banks. + ****************************************************************************/ + + +/***************************************************************************** + * PCIE controller + ****************************************************************************/ +#define PCIE_CTRL ORION_PCIE_REG(0x1a00) +#define PCIE_STAT ORION_PCIE_REG(0x1a04) +#define PCIE_DEV_ID ORION_PCIE_REG(0x0000) +#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004) +#define PCIE_DEV_REV ORION_PCIE_REG(0x0008) +#define PCIE_MASK ORION_PCIE_REG(0x1910) +#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8) +#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc) + +/* + * PCIE_STAT bits + */ +#define PCIE_STAT_LINK_DOWN 1 +#define PCIE_STAT_BUS_OFFS 8 +#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS) +#define PCIE_STAT_DEV_OFFS 20 +#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS) + +/* + * PCIE_CONF_ADDR bits + */ +#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc)) +#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) +#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) +#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) +#define PCIE_CONF_ADDR_EN (1 << 31) + +/* + * PCIE config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pcie_lock); + +void orion_pcie_id(u32 *dev, u32 *rev) +{ + *dev = orion_read(PCIE_DEV_ID) >> 16; + *rev = orion_read(PCIE_DEV_REV) & 0xff; +} + +u32 orion_pcie_local_bus_nr(void) +{ + u32 stat = orion_read(PCIE_STAT); + return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS); +} + +static u32 orion_pcie_local_dev_nr(void) +{ + u32 stat = orion_read(PCIE_STAT); + return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS); +} + +static u32 orion_pcie_no_link(void) +{ + u32 stat = orion_read(PCIE_STAT); + return(stat & PCIE_STAT_LINK_DOWN); +} + +static void orion_pcie_set_bus_nr(int nr) +{ + orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK); + orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS); +} + +static void orion_pcie_master_slave_enable(void) +{ + orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER | + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY); +} + +static void orion_pcie_enable_interrupts(void) +{ + /* + * Enable interrupts lines + * INTA[24] INTB[25] INTC[26] INTD[27] + */ + orion_setbits(PCIE_MASK, 0xf<<24); +} + +static int orion_pcie_valid_config(u32 bus, u32 dev) +{ + /* + * Don't go out when trying to access -- + * 1. our own device + * 2. where there's no device connected (no link) + * 3. nonexisting devices on local bus + */ + + if ((orion_pcie_local_bus_nr() == bus) && + (orion_pcie_local_dev_nr() == dev)) + return 0; + + if (orion_pcie_no_link()) + return 0; + + if (bus == orion_pcie_local_bus_nr()) + if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) || + ((orion_pcie_local_dev_nr() != 0) && (dev != 0))) + return 0; + + return 1; +} + +static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + unsigned int dev, rev, pcie_addr; + + if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&orion_pcie_lock, flags); + + orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + + orion_pcie_id(&dev, &rev); + if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { + /* extended register space */ + pcie_addr = ORION_PCIE_WA_VIRT_BASE; + pcie_addr |= PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where); + *val = orion_read(pcie_addr); + } else + *val = orion_read(PCIE_CONF_DATA); + + if (size == 1) + *val = (*val >> (8*(where & 0x3))) & 0xff; + else if (size == 2) + *val = (*val >> (8*(where & 0x3))) & 0xffff; + + spin_unlock_irqrestore(&orion_pcie_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + + +static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + unsigned long flags; + int ret; + + if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&orion_pcie_lock, flags); + + ret = PCIBIOS_SUCCESSFUL; + + orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) | + PCIE_CONF_DEV(PCI_SLOT(devfn)) | + PCIE_CONF_FUNC(PCI_FUNC(devfn)) | + PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN); + + if (size == 4) { + __raw_writel(val, PCIE_CONF_DATA); + } else if (size == 2) { + __raw_writew(val, PCIE_CONF_DATA + (where & 0x3)); + } else if (size == 1) { + __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&orion_pcie_lock, flags); + + return ret; +} + +struct pci_ops orion_pcie_ops = { + .read = orion_pcie_rd_conf, + .write = orion_pcie_wr_conf, +}; + + +static int orion_pcie_setup(struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Master + Slave enable + */ + orion_pcie_master_slave_enable(); + + /* + * Enable interrupts lines A-D + */ + orion_pcie_enable_interrupts(); + + /* + * Request resource + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("orion_pci_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCI-EX I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION_PCIE_IO_BUS_BASE; + res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIE IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCI-EX Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIE Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + +/***************************************************************************** + * PCI controller + ****************************************************************************/ +#define PCI_MODE ORION_PCI_REG(0xd00) +#define PCI_CMD ORION_PCI_REG(0xc00) +#define PCI_P2P_CONF ORION_PCI_REG(0x1d14) +#define PCI_CONF_ADDR ORION_PCI_REG(0xc78) +#define PCI_CONF_DATA ORION_PCI_REG(0xc7c) + +/* + * PCI_MODE bits + */ +#define PCI_MODE_64BIT (1 << 2) +#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) + +/* + * PCI_CMD bits + */ +#define PCI_CMD_HOST_REORDER (1 << 29) + +/* + * PCI_P2P_CONF bits + */ +#define PCI_P2P_BUS_OFFS 16 +#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) +#define PCI_P2P_DEV_OFFS 24 +#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) + +/* + * PCI_CONF_ADDR bits + */ +#define PCI_CONF_REG(reg) ((reg) & 0xfc) +#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) +#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) +#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) +#define PCI_CONF_ADDR_EN (1 << 31) + +/* + * Internal configuration space + */ +#define PCI_CONF_FUNC_STAT_CMD 0 +#define PCI_CONF_REG_STAT_CMD 4 +#define PCIX_STAT 0x64 +#define PCIX_STAT_BUS_OFFS 8 +#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) + +/* + * PCI config cycles are done by programming the PCI_CONF_ADDR register + * and then reading the PCI_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(orion_pci_lock); + +u32 orion_pci_local_bus_nr(void) +{ + u32 conf = orion_read(PCI_P2P_CONF); + return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); +} + +u32 orion_pci_local_dev_nr(void) +{ + u32 conf = orion_read(PCI_P2P_CONF); + return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS); +} + +int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, + u32 where, u32 size, u32 *val) +{ + unsigned long flags; + spin_lock_irqsave(&orion_pci_lock, flags); + + orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + *val = orion_read(PCI_CONF_DATA); + + if (size == 1) + *val = (*val >> (8*(where & 0x3))) & 0xff; + else if (size == 2) + *val = (*val >> (8*(where & 0x3))) & 0xffff; + + spin_unlock_irqrestore(&orion_pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, + u32 where, u32 size, u32 val) +{ + unsigned long flags; + int ret = PCIBIOS_SUCCESSFUL; + + spin_lock_irqsave(&orion_pci_lock, flags); + + orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + + if (size == 4) { + __raw_writel(val, PCI_CONF_DATA); + } else if (size == 2) { + __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); + } else if (size == 1) { + __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); + } else { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&orion_pci_lock, flags); + + return ret; +} + +static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) +{ + /* + * Don't go out for local device + */ + if ((orion_pci_local_bus_nr() == bus->number) && + (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + /* + * Don't go out for local device + */ + if ((orion_pci_local_bus_nr() == bus->number) && + (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) + return PCIBIOS_DEVICE_NOT_FOUND; + + return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where, size, val); +} + +struct pci_ops orion_pci_ops = { + .read = orion_pci_rd_conf, + .write = orion_pci_wr_conf, +}; + +static void orion_pci_set_bus_nr(int nr) +{ + u32 p2p = orion_read(PCI_P2P_CONF); + + if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { + /* + * PCI-X mode + */ + u32 pcix_status, bus, dev; + bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; + dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; + orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + pcix_status &= ~PCIX_STAT_BUS_MASK; + pcix_status |= (nr << PCIX_STAT_BUS_OFFS); + orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + } else { + /* + * PCI Conventional mode + */ + p2p &= ~PCI_P2P_BUS_MASK; + p2p |= (nr << PCI_P2P_BUS_OFFS); + orion_write(PCI_P2P_CONF, p2p); + } +} + +static void orion_pci_master_slave_enable(void) +{ + u32 bus_nr, dev_nr, func, reg, val; + + bus_nr = orion_pci_local_bus_nr(); + dev_nr = orion_pci_local_dev_nr(); + func = PCI_CONF_FUNC_STAT_CMD; + reg = PCI_CONF_REG_STAT_CMD; + orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val); + val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7); +} + +static int orion_pci_setup(struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Master + Slave enable + */ + orion_pci_master_slave_enable(); + + /* + * Force ordering + */ + orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); + + /* + * Request resources + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("orion_pci_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCI I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = ORION_PCI_IO_BUS_BASE; + res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCI IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = ORION_PCI_MEM_PHYS_BASE; + res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCI Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + + +/***************************************************************************** + * General PCIE + PCI + ****************************************************************************/ +int orion_pci_sys_setup(int nr, struct pci_sys_data *sys) +{ + int ret = 0; + + if (nr == 0) { + /* + * PCIE setup + */ + orion_pcie_set_bus_nr(0); + ret = orion_pcie_setup(sys); + } else if (nr == 1) { + /* + * PCI setup + */ + ret = orion_pci_setup(sys); + } + + return ret; +} + +struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_ops *ops; + struct pci_bus *bus; + + + if (nr == 0) { + u32 pci_bus; + /* + * PCIE scan + */ + ops = &orion_pcie_ops; + bus = pci_scan_bus(sys->busnr, ops, sys); + /* + * Set local PCI bus number to follow PCIE bridges (if any) + */ + pci_bus = bus->number + bus->subordinate - bus->secondary + 1; + orion_pci_set_bus_nr(pci_bus); + } else if (nr == 1) { + /* + * PCI scan + */ + ops = &orion_pci_ops; + bus = pci_scan_bus(sys->busnr, ops, sys); + } else { + BUG(); + bus = NULL; + } + + return bus; +} diff --git a/trunk/arch/arm/mach-orion5x/rd88f5182-setup.c b/trunk/arch/arm/mach-orion/rd88f5182-setup.c similarity index 85% rename from trunk/arch/arm/mach-orion5x/rd88f5182-setup.c rename to trunk/arch/arm/mach-orion/rd88f5182-setup.c index 37e8b2dc3ed5..e851b8ca5ac6 100644 --- a/trunk/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/trunk/arch/arm/mach-orion/rd88f5182-setup.c @@ -1,12 +1,12 @@ /* - * arch/arm/mach-orion5x/rd88f5182-setup.c + * arch/arm/mach-orion/rd88f5182-setup.c * * Marvell Orion-NAS Reference Design Setup * * Maintainer: Ronen Shitrit * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -24,7 +24,8 @@ #include #include #include -#include +#include +#include #include "common.h" /***************************************************************************** @@ -175,8 +176,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI-E isn't used on the RD2 */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -196,8 +197,8 @@ static struct hw_pci rd88f5182_pci __initdata = { .nr_controllers = 2, .preinit = rd88f5182_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, .map_irq = rd88f5182_pci_map_irq, }; @@ -249,20 +250,22 @@ static void __init rd88f5182_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion5x_init(); + orion_init(); /* * Setup the CPU address decode windows for our devices */ - orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE, -1); + orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, + RD88F5182_NOR_SIZE, -1); /* * Open a special address decode windows for the PCIE WA. */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); /* * Setup Multiplexing Pins -- @@ -288,25 +291,25 @@ static void __init rd88f5182_init(void) * MPP[25] USB 0 over current enable */ - orion5x_write(MPP_0_7_CTRL, 0x00000003); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x5555); + orion_write(MPP_0_7_CTRL, 0x00000003); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x5555); - orion5x_gpio_set_valid_pins(0x000000fb); + orion_gpio_set_valid_pins(0x000000fb); platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); - orion5x_eth_init(&rd88f5182_eth_data); - orion5x_sata_init(&rd88f5182_sata_data); + orion_eth_init(&rd88f5182_eth_data); + orion_sata_init(&rd88f5182_sata_data); } MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") /* Maintainer: Ronen Shitrit */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION_REGS_PHYS_BASE, + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = rd88f5182_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, MACHINE_END diff --git a/trunk/arch/arm/mach-orion/time.c b/trunk/arch/arm/mach-orion/time.c new file mode 100644 index 000000000000..bd4262da4f40 --- /dev/null +++ b/trunk/arch/arm/mach-orion/time.c @@ -0,0 +1,181 @@ +/* + * arch/arm/mach-orion/time.c + * + * Core time functions for Marvell Orion System On Chip + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Timer0: clock_event_device, Tick. + * Timer1: clocksource, Free running. + * WatchDog: Not used. + * + * Timers are counting down. + */ +#define CLOCKEVENT 0 +#define CLOCKSOURCE 1 + +/* + * Timers bits + */ +#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1)) +#define TIMER_EN(x) (1 << ((x) * 2)) +#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1)) +#define BRIDGE_INT_TIMER_WD (1 << 3) +#define TIMER_WD_EN (1 << 4) +#define TIMER_WD_RELOAD_EN (1 << 5) + +static cycle_t orion_clksrc_read(void) +{ + return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE))); +} + +static struct clocksource orion_clksrc = { + .name = "orion_clocksource", + .shift = 20, + .rating = 300, + .read = orion_clksrc_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int +orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + + if (delta == 0) + return -ETIME; + + local_irq_save(flags); + + /* + * Clear and enable timer interrupt bit + */ + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + + /* + * Setup new timer value + */ + orion_write(TIMER_VAL(CLOCKEVENT), delta); + + /* + * Disable auto reload and kickoff the timer + */ + orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT)); + orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT)); + + local_irq_restore(flags); + + return 0; +} + +static void +orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + unsigned long flags; + + local_irq_save(flags); + + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* + * Setup latch cycles in timer and enable reload interrupt. + */ + orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH); + orion_write(TIMER_VAL(CLOCKEVENT), LATCH); + orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | + TIMER_EN(CLOCKEVENT)); + } else { + /* + * Disable timer and interrupt + */ + orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) | + TIMER_EN(CLOCKEVENT)); + } + + local_irq_restore(flags); +} + +static struct clock_event_device orion_clkevt = { + .name = "orion_tick", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 300, + .cpumask = CPU_MASK_CPU0, + .set_next_event = orion_clkevt_next_event, + .set_mode = orion_clkevt_mode, +}; + +static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) +{ + /* + * Clear cause bit and do event + */ + orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT)); + orion_clkevt.event_handler(&orion_clkevt); + return IRQ_HANDLED; +} + +static struct irqaction orion_timer_irq = { + .name = "orion_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = orion_timer_interrupt +}; + +static void orion_timer_init(void) +{ + /* + * Setup clocksource free running timer (no interrupt on reload) + */ + orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff); + orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff); + orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE)); + orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) | + TIMER_EN(CLOCKSOURCE)); + + /* + * Register clocksource + */ + orion_clksrc.mult = + clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift); + + clocksource_register(&orion_clksrc); + + /* + * Connect and enable tick handler + */ + setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq); + + /* + * Register clockevent + */ + orion_clkevt.mult = + div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift); + orion_clkevt.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &orion_clkevt); + orion_clkevt.min_delta_ns = + clockevent_delta2ns(1, &orion_clkevt); + + clockevents_register_device(&orion_clkevt); +} + +struct sys_timer orion_timer = { + .init = orion_timer_init, +}; diff --git a/trunk/arch/arm/mach-orion5x/ts209-setup.c b/trunk/arch/arm/mach-orion/ts209-setup.c similarity index 76% rename from trunk/arch/arm/mach-orion5x/ts209-setup.c rename to trunk/arch/arm/mach-orion/ts209-setup.c index fd43863a86f6..45764dad16d0 100644 --- a/trunk/arch/arm/mach-orion5x/ts209-setup.c +++ b/trunk/arch/arm/mach-orion/ts209-setup.c @@ -26,7 +26,8 @@ #include #include #include -#include +#include +#include #include "common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 @@ -144,8 +145,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCIE IRQ is connected internally (not GPIO) */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + if (dev->bus->number == orion_pcie_local_bus_nr()) + return IRQ_ORION_PCIE0_INT; /* * PCI IRQs are connected via GPIOs @@ -164,8 +165,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { .nr_controllers = 2, .preinit = qnap_ts209_pci_preinit, .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, + .setup = orion_pci_sys_setup, + .scan = orion_pci_sys_scan_bus, .map_irq = qnap_ts209_pci_map_irq, }; @@ -188,87 +189,6 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { .force_phy_addr = 1, }; -static int __init parse_hex_nibble(char n) -{ - if (n >= '0' && n <= '9') - return n - '0'; - - if (n >= 'A' && n <= 'F') - return n - 'A' + 10; - - if (n >= 'a' && n <= 'f') - return n - 'a' + 10; - - return -1; -} - -static int __init parse_hex_byte(const char *b) -{ - int hi; - int lo; - - hi = parse_hex_nibble(b[0]); - lo = parse_hex_nibble(b[1]); - - if (hi < 0 || lo < 0) - return -1; - - return (hi << 4) | lo; -} - -static int __init check_mac_addr(const char *addr_str) -{ - u_int8_t addr[6]; - int i; - - for (i = 0; i < 6; i++) { - int byte; - - /* - * Enforce "xx:xx:xx:xx:xx:xx\n" format. - */ - if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) - return -1; - - byte = parse_hex_byte(addr_str + (i * 3)); - if (byte < 0) - return -1; - addr[i] = byte; - } - - printk(KERN_INFO "ts209: found ethernet mac address "); - for (i = 0; i < 6; i++) - printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); - - memcpy(qnap_ts209_eth_data.mac_addr, addr, 6); - - return 0; -} - -/* - * The 'NAS Config' flash partition has an ext2 filesystem which - * contains a file that has the ethernet MAC address in plain text - * (format "xx:xx:xx:xx:xx:xx\n".) - */ -static void __init ts209_find_mac_addr(void) -{ - unsigned long addr; - - for (addr = 0x00700000; addr < 0x00760000; addr += 1024) { - char *nor_page; - int ret = 0; - - nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024); - if (nor_page != NULL) { - ret = check_mac_addr(nor_page); - iounmap(nor_page); - } - - if (ret == 0) - break; - } -} - /***************************************************************************** * RTC S35390A on I2C bus ****************************************************************************/ @@ -342,21 +262,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { static void qnap_ts209_power_off(void) { /* 19200 baud divisor */ - const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); + const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); pr_info("%s: triggering power-off...\n", __func__); /* hijack uart1 and reset into sane state (19200,8n1) */ - orion5x_write(UART1_REG(LCR), 0x83); - orion5x_write(UART1_REG(DLL), divisor & 0xff); - orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); - orion5x_write(UART1_REG(LCR), 0x03); - orion5x_write(UART1_REG(IER), 0x00); - orion5x_write(UART1_REG(FCR), 0x00); - orion5x_write(UART1_REG(MCR), 0x00); + orion_write(UART1_REG(LCR), 0x83); + orion_write(UART1_REG(DLL), divisor & 0xff); + orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); + orion_write(UART1_REG(LCR), 0x03); + orion_write(UART1_REG(IER), 0x00); + orion_write(UART1_REG(FCR), 0x00); + orion_write(UART1_REG(MCR), 0x00); /* send the power-off command 'A' to PIC */ - orion5x_write(UART1_REG(TX), 'A'); + orion_write(UART1_REG(TX), 'A'); } static void __init qnap_ts209_init(void) @@ -364,19 +284,20 @@ static void __init qnap_ts209_init(void) /* * Setup basic Orion functions. Need to be called early. */ - orion5x_init(); + orion_init(); /* * Setup flash mapping */ - orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); + orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE, -1); /* * Open a special address decode windows for the PCIE WA. */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); + orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | + (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); /* * Setup Multiplexing Pins -- @@ -401,10 +322,10 @@ static void __init qnap_ts209_init(void) * MPP[22] USB 0 over current * MPP[23-25] Reserved */ - orion5x_write(MPP_0_7_CTRL, 0x3); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x5500); - orion5x_gpio_set_valid_pins(0x3cc0fff); + orion_write(MPP_0_7_CTRL, 0x3); + orion_write(MPP_8_15_CTRL, 0x55550000); + orion_write(MPP_16_19_CTRL, 0x5500); + orion_gpio_set_valid_pins(0x3cc0fff); /* register ts209 specific power-off method */ pm_power_off = qnap_ts209_power_off; @@ -423,20 +344,18 @@ static void __init qnap_ts209_init(void) pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - ts209_find_mac_addr(); - orion5x_eth_init(&qnap_ts209_eth_data); - - orion5x_sata_init(&qnap_ts209_sata_data); + orion_eth_init(&qnap_ts209_eth_data); + orion_sata_init(&qnap_ts209_sata_data); } MACHINE_START(TS209, "QNAP TS-109/TS-209") /* Maintainer: Byron Bradley */ - .phys_io = ORION5X_REGS_PHYS_BASE, - .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .phys_io = ORION_REGS_PHYS_BASE, + .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, .init_machine = qnap_ts209_init, - .map_io = orion5x_map_io, - .init_irq = orion5x_init_irq, - .timer = &orion5x_timer, + .map_io = orion_map_io, + .init_irq = orion_init_irq, + .timer = &orion_timer, .fixup = tag_fixup_mem32, MACHINE_END diff --git a/trunk/arch/arm/mach-orion5x/addr-map.c b/trunk/arch/arm/mach-orion5x/addr-map.c deleted file mode 100644 index 6b179371e0a2..000000000000 --- a/trunk/arch/arm/mach-orion5x/addr-map.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * arch/arm/mach-orion5x/addr-map.c - * - * Address map functions for Marvell Orion 5x SoCs - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "common.h" - -/* - * The Orion has fully programable address map. There's a separate address - * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, - * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own - * address decode windows that allow it to access any of the Orion resources. - * - * CPU address decoding -- - * Linux assumes that it is the boot loader that already setup the access to - * DDR and internal registers. - * Setup access to PCI and PCI-E IO/MEM space is issued by this file. - * Setup access to various devices located on the device bus interface (e.g. - * flashes, RTC, etc) should be issued by machine-setup.c according to - * specific board population (by using orion5x_setup_*_win()). - * - * Non-CPU Masters address decoding -- - * Unlike the CPU, we setup the access from Orion's master interfaces to DDR - * banks only (the typical use case). - * Setup access for each master to DDR is issued by common.c. - * - * Note: although orion_setbits() and orion_clrbits() are not atomic - * no locking is necessary here since code in this file is only called - * at boot time when there is no concurrency issues. - */ - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DDR 0 -#define TARGET_DEV_BUS 1 -#define TARGET_PCI 3 -#define TARGET_PCIE 4 -#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \ - ((n) == 1) ? 0xd : \ - ((n) == 2) ? 0xb : \ - ((n) == 3) ? 0x7 : 0xf) -#define ATTR_PCIE_MEM 0x59 -#define ATTR_PCIE_IO 0x51 -#define ATTR_PCIE_WA 0x79 -#define ATTR_PCI_MEM 0x59 -#define ATTR_PCI_IO 0x51 -#define ATTR_DEV_CS0 0x1e -#define ATTR_DEV_CS1 0x1d -#define ATTR_DEV_CS2 0x1b -#define ATTR_DEV_BOOT 0xf -#define WIN_EN 1 - -/* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) -#define DDR_MAX_CS 4 -#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) -#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) -#define DDR_BANK_EN 1 - -/* - * CPU Address Decode Windows registers - */ -#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) - -/* - * Gigabit Ethernet Address Decode Windows registers - */ -#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) -#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) -#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) -#define ETH_WIN_EN ORION5X_ETH_REG(0x290) -#define ETH_WIN_PROT ORION5X_ETH_REG(0x294) -#define ETH_MAX_WIN 6 -#define ETH_MAX_REMAP_WIN 4 - - -struct mbus_dram_target_info orion5x_mbus_dram_info; - -static int __init orion5x_cpu_win_can_remap(int win) -{ - u32 dev, rev; - - orion5x_pcie_id(&dev, &rev); - if ((dev == MV88F5281_DEV_ID && win < 4) - || (dev == MV88F5182_DEV_ID && win < 2) - || (dev == MV88F5181_DEV_ID && win < 2)) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); - orion5x_write(CPU_WIN_CTRL(win), - ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion5x_write(CPU_WIN_REMAP_HI(win), 0); - } -} - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; - - /* - * First, disable and clear windows. - */ - for (i = 0; i < 8; i++) { - orion5x_write(CPU_WIN_BASE(i), 0); - orion5x_write(CPU_WIN_CTRL(i), 0); - if (orion5x_cpu_win_can_remap(i)) { - orion5x_write(CPU_WIN_REMAP_LO(i), 0); - orion5x_write(CPU_WIN_REMAP_HI(i), 0); - } - } - - /* - * Setup windows for PCI+PCIe IO+MEM space. - */ - setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); - - /* - * Setup MBUS dram target info. - */ - orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xff000000; - w->size = (size | 0x00ffffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; -} - -void __init orion5x_setup_dev_boot_win(u32 base, u32 size) -{ - setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); -} - -void __init orion5x_setup_dev0_win(u32 base, u32 size) -{ - setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); -} - -void __init orion5x_setup_dev1_win(u32 base, u32 size) -{ - setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); -} - -void __init orion5x_setup_dev2_win(u32 base, u32 size) -{ - setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); -} - -void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) -{ - setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); -} - -void __init orion5x_setup_eth_wins(void) -{ - int i; - - /* - * First, disable and clear windows - */ - for (i = 0; i < ETH_MAX_WIN; i++) { - orion5x_write(ETH_WIN_BASE(i), 0); - orion5x_write(ETH_WIN_SIZE(i), 0); - orion5x_setbits(ETH_WIN_EN, 1 << i); - orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); - if (i < ETH_MAX_REMAP_WIN) - orion5x_write(ETH_WIN_REMAP(i), 0); - } - - /* - * Setup windows for DDR banks. - */ - for (i = 0; i < DDR_MAX_CS; i++) { - u32 base, size; - size = orion5x_read(DDR_SIZE_CS(i)); - base = orion5x_read(DDR_BASE_CS(i)); - if (size & DDR_BANK_EN) { - base = DDR_REG_TO_BASE(base); - size = DDR_REG_TO_SIZE(size); - orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); - orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | - (ATTR_DDR_CS(i) << 8) | - TARGET_DDR); - orion5x_clrbits(ETH_WIN_EN, 1 << i); - orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); - } - } -} diff --git a/trunk/arch/arm/mach-orion5x/common.h b/trunk/arch/arm/mach-orion5x/common.h deleted file mode 100644 index f4c4c9a72a7c..000000000000 --- a/trunk/arch/arm/mach-orion5x/common.h +++ /dev/null @@ -1,72 +0,0 @@ -#ifndef __ARCH_ORION5X_COMMON_H -#define __ARCH_ORION5X_COMMON_H - -/* - * Basic Orion init functions used early by machine-setup. - */ - -void orion5x_map_io(void); -void orion5x_init_irq(void); -void orion5x_init(void); -extern struct sys_timer orion5x_timer; - -/* - * Enumerations and functions for Orion windows mapping. Used by Orion core - * functions to map its interfaces and by the machine-setup to map its on- - * board devices. Details in /mach-orion/addr-map.c - */ -extern struct mbus_dram_target_info orion5x_mbus_dram_info; -void orion5x_setup_cpu_mbus_bridge(void); -void orion5x_setup_dev_boot_win(u32 base, u32 size); -void orion5x_setup_dev0_win(u32 base, u32 size); -void orion5x_setup_dev1_win(u32 base, u32 size); -void orion5x_setup_dev2_win(u32 base, u32 size); -void orion5x_setup_pcie_wa_win(u32 base, u32 size); -void orion5x_setup_eth_wins(void); - -/* - * Shared code used internally by other Orion core functions. - * (/mach-orion/pci.c) - */ - -struct pci_sys_data; -struct pci_bus; - -void orion5x_pcie_id(u32 *dev, u32 *rev); -int orion5x_pcie_local_bus_nr(void); -int orion5x_pci_local_bus_nr(void); -int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); -struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); - -/* - * Valid GPIO pins according to MPP setup, used by machine-setup. - * (/mach-orion/gpio.c). - */ - -void orion5x_gpio_set_valid_pins(u32 pins); -void gpio_display(void); /* debug */ - -/* - * Pull in Orion Ethernet platform_data, used by machine-setup - */ - -struct mv643xx_eth_platform_data; - -void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); - -/* - * Orion Sata platform_data, used by machine-setup - */ - -struct mv_sata_platform_data; - -void orion5x_sata_init(struct mv_sata_platform_data *sata_data); - -struct machine_desc; -struct meminfo; -struct tag; -extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, - char **, struct meminfo *); - - -#endif diff --git a/trunk/arch/arm/mach-orion5x/pci.c b/trunk/arch/arm/mach-orion5x/pci.c deleted file mode 100644 index fdf99fca85b3..000000000000 --- a/trunk/arch/arm/mach-orion5x/pci.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - * arch/arm/mach-orion5x/pci.c - * - * PCI and PCIe functions for Marvell Orion System On Chip - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "common.h" - -/***************************************************************************** - * Orion has one PCIe controller and one PCI controller. - * - * Note1: The local PCIe bus number is '0'. The local PCI bus number - * follows the scanned PCIe bridged busses, if any. - * - * Note2: It is possible for PCI/PCIe agents to access many subsystem's - * space, by configuring BARs and Address Decode Windows, e.g. flashes on - * device bus, Orion registers, etc. However this code only enable the - * access to DDR banks. - ****************************************************************************/ - - -/***************************************************************************** - * PCIe controller - ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) - -void __init orion5x_pcie_id(u32 *dev, u32 *rev) -{ - *dev = orion_pcie_dev_id(PCIE_BASE); - *rev = orion_pcie_rev(PCIE_BASE); -} - -int __init orion5x_pcie_local_bus_nr(void) -{ - return orion_pcie_get_local_bus_nr(PCIE_BASE); -} - -static int pcie_valid_config(int bus, int dev) -{ - /* - * Don't go out when trying to access -- - * 1. nonexisting device on local bus - * 2. where there's no device connected (no link) - */ - if (bus == 0 && dev == 0) - return 1; - - if (!orion_pcie_link_up(PCIE_BASE)) - return 0; - - if (bus == 0 && dev != 1) - return 0; - - return 1; -} - - -/* - * PCIe config cycles are done by programming the PCIE_CONF_ADDR register - * and then reading the PCIE_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion5x_pcie_lock); - -static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) -{ - unsigned long flags; - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - spin_lock_irqsave(&orion5x_pcie_lock, flags); - ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion5x_pcie_lock, flags); - - return ret; -} - -static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, - int where, int size, u32 *val) -{ - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - /* - * We only support access to the non-extended configuration - * space when using the WA access method (or we would have to - * sacrifice 256M of CPU virtual address space.) - */ - if (where >= 0x100) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, - bus, devfn, where, size, val); - - return ret; -} - -static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - unsigned long flags; - int ret; - - if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - spin_lock_irqsave(&orion5x_pcie_lock, flags); - ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); - spin_unlock_irqrestore(&orion5x_pcie_lock, flags); - - return ret; -} - -static struct pci_ops pcie_ops = { - .read = pcie_rd_conf, - .write = pcie_wr_conf, -}; - - -static int __init pcie_setup(struct pci_sys_data *sys) -{ - struct resource *res; - int dev; - - /* - * Generic PCIe unit setup. - */ - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); - - /* - * Check whether to apply Orion-1/Orion-NAS PCIe config - * read transaction workaround. - */ - dev = orion_pcie_dev_id(PCIE_BASE); - if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { - printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " - "read transaction workaround\n"); - pcie_ops.read = pcie_rd_conf_wa; - } - - /* - * Request resources. - */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("pcie_setup unable to alloc resources"); - - /* - * IORESOURCE_IO - */ - res[0].name = "PCIe I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCIE_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCIe IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* - * IORESOURCE_MEM - */ - res[1].name = "PCIe Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) - panic("Request PCIe Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; - - return 1; -} - -/***************************************************************************** - * PCI controller - ****************************************************************************/ -#define PCI_MODE ORION5X_PCI_REG(0xd00) -#define PCI_CMD ORION5X_PCI_REG(0xc00) -#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) -#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) -#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) - -/* - * PCI_MODE bits - */ -#define PCI_MODE_64BIT (1 << 2) -#define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) - -/* - * PCI_CMD bits - */ -#define PCI_CMD_HOST_REORDER (1 << 29) - -/* - * PCI_P2P_CONF bits - */ -#define PCI_P2P_BUS_OFFS 16 -#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) -#define PCI_P2P_DEV_OFFS 24 -#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) - -/* - * PCI_CONF_ADDR bits - */ -#define PCI_CONF_REG(reg) ((reg) & 0xfc) -#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) -#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) -#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) -#define PCI_CONF_ADDR_EN (1 << 31) - -/* - * Internal configuration space - */ -#define PCI_CONF_FUNC_STAT_CMD 0 -#define PCI_CONF_REG_STAT_CMD 4 -#define PCIX_STAT 0x64 -#define PCIX_STAT_BUS_OFFS 8 -#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) - -/* - * PCI Address Decode Windows registers - */ -#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) -#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) -#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) - -/* - * PCI configuration helpers for BAR settings - */ -#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) -#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) -#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) - -/* - * PCI config cycles are done by programming the PCI_CONF_ADDR register - * and then reading the PCI_CONF_DATA register. Need to make sure these - * transactions are atomic. - */ -static DEFINE_SPINLOCK(orion5x_pci_lock); - -int orion5x_pci_local_bus_nr(void) -{ - u32 conf = orion5x_read(PCI_P2P_CONF); - return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); -} - -static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 *val) -{ - unsigned long flags; - spin_lock_irqsave(&orion5x_pci_lock, flags); - - orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - - *val = orion5x_read(PCI_CONF_DATA); - - if (size == 1) - *val = (*val >> (8*(where & 0x3))) & 0xff; - else if (size == 2) - *val = (*val >> (8*(where & 0x3))) & 0xffff; - - spin_unlock_irqrestore(&orion5x_pci_lock, flags); - - return PCIBIOS_SUCCESSFUL; -} - -static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 val) -{ - unsigned long flags; - int ret = PCIBIOS_SUCCESSFUL; - - spin_lock_irqsave(&orion5x_pci_lock, flags); - - orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); - - if (size == 4) { - __raw_writel(val, PCI_CONF_DATA); - } else if (size == 2) { - __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); - } else if (size == 1) { - __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); - } else { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - } - - spin_unlock_irqrestore(&orion5x_pci_lock, flags); - - return ret; -} - -static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 *val) -{ - /* - * Don't go out for local device - */ - if (bus->number == orion5x_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); -} - -static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - if (bus->number == orion5x_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); -} - -static struct pci_ops pci_ops = { - .read = orion5x_pci_rd_conf, - .write = orion5x_pci_wr_conf, -}; - -static void __init orion5x_pci_set_bus_nr(int nr) -{ - u32 p2p = orion5x_read(PCI_P2P_CONF); - - if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { - /* - * PCI-X mode - */ - u32 pcix_status, bus, dev; - bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; - dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); - pcix_status &= ~PCIX_STAT_BUS_MASK; - pcix_status |= (nr << PCIX_STAT_BUS_OFFS); - orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); - } else { - /* - * PCI Conventional mode - */ - p2p &= ~PCI_P2P_BUS_MASK; - p2p |= (nr << PCI_P2P_BUS_OFFS); - orion5x_write(PCI_P2P_CONF, p2p); - } -} - -static void __init orion5x_pci_master_slave_enable(void) -{ - int bus_nr, func, reg; - u32 val; - - bus_nr = orion5x_pci_local_bus_nr(); - func = PCI_CONF_FUNC_STAT_CMD; - reg = PCI_CONF_REG_STAT_CMD; - orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); - val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); -} - -static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) -{ - u32 win_enable; - int bus; - int i; - - /* - * First, disable windows. - */ - win_enable = 0xffffffff; - orion5x_write(PCI_BAR_ENABLE, win_enable); - - /* - * Setup windows for DDR banks. - */ - bus = orion5x_pci_local_bus_nr(); - - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); - u32 reg; - u32 val; - - /* - * Write DRAM bank base address register. - */ - reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); - val = (cs->base & 0xfffff000) | (val & 0xfff); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); - - /* - * Write DRAM bank size register. - */ - reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); - orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), - (cs->size - 1) & 0xfffff000); - orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), - cs->base & 0xfffff000); - - /* - * Enable decode window for this chip select. - */ - win_enable &= ~(1 << cs->cs_index); - } - - /* - * Re-enable decode windows. - */ - orion5x_write(PCI_BAR_ENABLE, win_enable); - - /* - * Disable automatic update of address remaping when writing to BARs. - */ - orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); -} - -static int __init pci_setup(struct pci_sys_data *sys) -{ - struct resource *res; - - /* - * Point PCI unit MBUS decode windows to DRAM space. - */ - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); - - /* - * Master + Slave enable - */ - orion5x_pci_master_slave_enable(); - - /* - * Force ordering - */ - orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); - - /* - * Request resources - */ - res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); - if (!res) - panic("pci_setup unable to alloc resources"); - - /* - * IORESOURCE_IO - */ - res[0].name = "PCI I/O Space"; - res[0].flags = IORESOURCE_IO; - res[0].start = ORION5X_PCI_IO_BUS_BASE; - res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; - if (request_resource(&ioport_resource, &res[0])) - panic("Request PCI IO resource failed\n"); - sys->resource[0] = &res[0]; - - /* - * IORESOURCE_MEM - */ - res[1].name = "PCI Memory Space"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ORION5X_PCI_MEM_PHYS_BASE; - res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; - if (request_resource(&iomem_resource, &res[1])) - panic("Request PCI Memory resource failed\n"); - sys->resource[1] = &res[1]; - - sys->resource[2] = NULL; - sys->io_offset = 0; - - return 1; -} - - -/***************************************************************************** - * General PCIe + PCI - ****************************************************************************/ -static void __devinit rc_pci_fixup(struct pci_dev *dev) -{ - /* - * Prevent enumeration of root complex. - */ - if (dev->bus->parent == NULL && dev->devfn == 0) { - int i; - - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); - -int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) -{ - int ret = 0; - - if (nr == 0) { - orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); - ret = pcie_setup(sys); - } else if (nr == 1) { - orion5x_pci_set_bus_nr(sys->busnr); - ret = pci_setup(sys); - } - - return ret; -} - -struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - - if (nr == 0) { - bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); - } else if (nr == 1) { - bus = pci_scan_bus(sys->busnr, &pci_ops, sys); - } else { - bus = NULL; - BUG(); - } - - return bus; -} diff --git a/trunk/arch/arm/mach-pxa/pxa3xx.c b/trunk/arch/arm/mach-pxa/pxa3xx.c index 35f25fdaeba3..54c9e8371a21 100644 --- a/trunk/arch/arm/mach-pxa/pxa3xx.c +++ b/trunk/arch/arm/mach-pxa/pxa3xx.c @@ -156,6 +156,21 @@ static const struct clkops clk_pxa3xx_hsio_ops = { .getrate = clk_pxa3xx_hsio_getrate, }; +static void clk_pout_enable(struct clk *clk) +{ + OSCC |= OSCC_PEN; +} + +static void clk_pout_disable(struct clk *clk) +{ + OSCC &= ~OSCC_PEN; +} + +static const struct clkops clk_pout_ops = { + .enable = clk_pout_enable, + .disable = clk_pout_disable, +}; + #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ { \ .name = _name, \ @@ -175,6 +190,13 @@ static const struct clkops clk_pxa3xx_hsio_ops = { } static struct clk pxa3xx_clks[] = { + { + .name = "CLK_POUT", + .ops = &clk_pout_ops, + .rate = 13000000, + .delay = 70, + }, + PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig index 64d09244df46..76348f060f27 100644 --- a/trunk/arch/arm/mm/Kconfig +++ b/trunk/arch/arm/mm/Kconfig @@ -345,7 +345,7 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION5X + depends on ARCH_ORION default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/trunk/arch/arm/plat-orion/Makefile b/trunk/arch/arm/plat-orion/Makefile deleted file mode 100644 index 198f3dde2be3..000000000000 --- a/trunk/arch/arm/plat-orion/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := irq.o pcie.o time.o -obj-m := -obj-n := -obj- := diff --git a/trunk/arch/arm/plat-orion/irq.c b/trunk/arch/arm/plat-orion/irq.c deleted file mode 100644 index c5b669d234bc..000000000000 --- a/trunk/arch/arm/plat-orion/irq.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * arch/arm/plat-orion/irq.c - * - * Marvell Orion SoC IRQ handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - -static void orion_irq_mask(u32 irq) -{ - void __iomem *maskaddr = get_irq_chip_data(irq); - u32 mask; - - mask = readl(maskaddr); - mask &= ~(1 << (irq & 31)); - writel(mask, maskaddr); -} - -static void orion_irq_unmask(u32 irq) -{ - void __iomem *maskaddr = get_irq_chip_data(irq); - u32 mask; - - mask = readl(maskaddr); - mask |= 1 << (irq & 31); - writel(mask, maskaddr); -} - -static struct irq_chip orion_irq_chip = { - .name = "orion_irq", - .ack = orion_irq_mask, - .mask = orion_irq_mask, - .unmask = orion_irq_unmask, -}; - -void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) -{ - unsigned int i; - - /* - * Mask all interrupts initially. - */ - writel(0, maskaddr); - - /* - * Register IRQ sources. - */ - for (i = 0; i < 32; i++) { - unsigned int irq = irq_start + i; - - set_irq_chip(irq, &orion_irq_chip); - set_irq_chip_data(irq, maskaddr); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } -} diff --git a/trunk/arch/arm/plat-orion/pcie.c b/trunk/arch/arm/plat-orion/pcie.c deleted file mode 100644 index abfda53f1800..000000000000 --- a/trunk/arch/arm/plat-orion/pcie.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * arch/arm/plat-orion/pcie.c - * - * Marvell Orion SoC PCIe handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - -/* - * PCIe unit register offsets. - */ -#define PCIE_DEV_ID_OFF 0x0000 -#define PCIE_CMD_OFF 0x0004 -#define PCIE_DEV_REV_OFF 0x0008 -#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) -#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) -#define PCIE_HEADER_LOG_4_OFF 0x0128 -#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) -#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) -#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) -#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) -#define PCIE_WIN5_CTRL_OFF 0x1880 -#define PCIE_WIN5_BASE_OFF 0x1884 -#define PCIE_WIN5_REMAP_OFF 0x188c -#define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN 0x80000000 -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8) -#define PCIE_CONF_DATA_OFF 0x18fc -#define PCIE_MASK_OFF 0x1910 -#define PCIE_CTRL_OFF 0x1a00 -#define PCIE_STAT_OFF 0x1a04 -#define PCIE_STAT_DEV_OFFS 20 -#define PCIE_STAT_DEV_MASK 0x1f -#define PCIE_STAT_BUS_OFFS 8 -#define PCIE_STAT_BUS_MASK 0xff -#define PCIE_STAT_LINK_DOWN 1 - - -u32 __init orion_pcie_dev_id(void __iomem *base) -{ - return readl(base + PCIE_DEV_ID_OFF) >> 16; -} - -u32 __init orion_pcie_rev(void __iomem *base) -{ - return readl(base + PCIE_DEV_REV_OFF) & 0xff; -} - -int orion_pcie_link_up(void __iomem *base) -{ - return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); -} - -int orion_pcie_get_local_bus_nr(void __iomem *base) -{ - u32 stat = readl(base + PCIE_STAT_OFF); - - return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; -} - -void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) -{ - u32 stat; - - stat = readl(base + PCIE_STAT_OFF); - stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); - stat |= nr << PCIE_STAT_BUS_OFFS; - writel(stat, base + PCIE_STAT_OFF); -} - -/* - * Setup PCIE BARs and Address Decode Wins: - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks - * WIN[0-3] -> DRAM bank[0-3] - */ -static void __init orion_pcie_setup_wins(void __iomem *base, - struct mbus_dram_target_info *dram) -{ - u32 size; - int i; - - /* - * First, disable and clear BARs and windows. - */ - for (i = 1; i <= 2; i++) { - writel(0, base + PCIE_BAR_CTRL_OFF(i)); - writel(0, base + PCIE_BAR_LO_OFF(i)); - writel(0, base + PCIE_BAR_HI_OFF(i)); - } - - for (i = 0; i < 5; i++) { - writel(0, base + PCIE_WIN04_CTRL_OFF(i)); - writel(0, base + PCIE_WIN04_BASE_OFF(i)); - writel(0, base + PCIE_WIN04_REMAP_OFF(i)); - } - - writel(0, base + PCIE_WIN5_CTRL_OFF); - writel(0, base + PCIE_WIN5_BASE_OFF); - writel(0, base + PCIE_WIN5_REMAP_OFF); - - /* - * Setup windows for DDR banks. Count total DDR size on the fly. - */ - size = 0; - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - - writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); - writel(0, base + PCIE_WIN04_REMAP_OFF(i)); - writel(((cs->size - 1) & 0xffff0000) | - (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1, - base + PCIE_WIN04_CTRL_OFF(i)); - - size += cs->size; - } - - /* - * Setup BAR[1] to all DRAM banks. - */ - writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); - writel(0, base + PCIE_BAR_HI_OFF(1)); - writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); -} - -void __init orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram) -{ - u16 cmd; - u32 mask; - - /* - * Point PCIe unit MBUS decode windows to DRAM space. - */ - orion_pcie_setup_wins(base, dram); - - /* - * Master + slave enable. - */ - cmd = readw(base + PCIE_CMD_OFF); - cmd |= PCI_COMMAND_IO; - cmd |= PCI_COMMAND_MEMORY; - cmd |= PCI_COMMAND_MASTER; - writew(cmd, base + PCIE_CMD_OFF); - - /* - * Enable interrupt lines A-D. - */ - mask = readl(base + PCIE_MASK_OFF); - mask |= 0x0f000000; - writel(mask, base + PCIE_MASK_OFF); -} - -int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - writel(PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, - base + PCIE_CONF_ADDR_OFF); - - *val = readl(base + PCIE_CONF_DATA_OFF); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xff; - else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xffff; - - return PCIBIOS_SUCCESSFUL; -} - -int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - writel(PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, - base + PCIE_CONF_ADDR_OFF); - - *val = readl(base + PCIE_CONF_DATA_OFF); - - if (bus->number != orion_pcie_get_local_bus_nr(base) || - PCI_FUNC(devfn) != 0) - *val = readl(base + PCIE_HEADER_LOG_4_OFF); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xff; - else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xffff; - - return PCIBIOS_SUCCESSFUL; -} - -int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where))); - - if (size == 1) - *val = (*val >> (8 * (where & 3))) & 0xff; - else if (size == 2) - *val = (*val >> (8 * (where & 3))) & 0xffff; - - return PCIBIOS_SUCCESSFUL; -} - -int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) -{ - int ret = PCIBIOS_SUCCESSFUL; - - writel(PCIE_CONF_BUS(bus->number) | - PCIE_CONF_DEV(PCI_SLOT(devfn)) | - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | - PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, - base + PCIE_CONF_ADDR_OFF); - - if (size == 4) { - writel(val, base + PCIE_CONF_DATA_OFF); - } else if (size == 2) { - writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); - } else if (size == 1) { - writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); - } else { - ret = PCIBIOS_BAD_REGISTER_NUMBER; - } - - return ret; -} diff --git a/trunk/arch/arm/plat-orion/time.c b/trunk/arch/arm/plat-orion/time.c deleted file mode 100644 index 28b5285446e8..000000000000 --- a/trunk/arch/arm/plat-orion/time.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * arch/arm/plat-orion/time.c - * - * Marvell Orion SoC timer handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Timer 0 is used as free-running clocksource, while timer 1 is - * used as clock_event_device. - */ - -#include -#include -#include -#include -#include -#include - -/* - * Number of timer ticks per jiffy. - */ -static u32 ticks_per_jiffy; - - -/* - * Timer block registers. - */ -#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) -#define TIMER0_EN 0x0001 -#define TIMER0_RELOAD_EN 0x0002 -#define TIMER1_EN 0x0004 -#define TIMER1_RELOAD_EN 0x0008 -#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) -#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) -#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) -#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) - - -/* - * Clocksource handling. - */ -static cycle_t orion_clksrc_read(void) -{ - return 0xffffffff - readl(TIMER0_VAL); -} - -static struct clocksource orion_clksrc = { - .name = "orion_clocksource", - .shift = 20, - .rating = 300, - .read = orion_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - - -/* - * Clockevent handling. - */ -static int -orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) -{ - unsigned long flags; - u32 u; - - if (delta == 0) - return -ETIME; - - local_irq_save(flags); - - /* - * Clear and enable clockevent timer interrupt. - */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); - - u = readl(BRIDGE_MASK); - u |= BRIDGE_INT_TIMER1; - writel(u, BRIDGE_MASK); - - /* - * Setup new clockevent timer value. - */ - writel(delta, TIMER1_VAL); - - /* - * Enable the timer. - */ - u = readl(TIMER_CTRL); - u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; - writel(u, TIMER_CTRL); - - local_irq_restore(flags); - - return 0; -} - -static void -orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) -{ - unsigned long flags; - u32 u; - - local_irq_save(flags); - if (mode == CLOCK_EVT_MODE_PERIODIC) { - /* - * Setup timer to fire at 1/HZ intervals. - */ - writel(ticks_per_jiffy - 1, TIMER1_RELOAD); - writel(ticks_per_jiffy - 1, TIMER1_VAL); - - /* - * Enable timer interrupt. - */ - u = readl(BRIDGE_MASK); - writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); - - /* - * Enable timer. - */ - u = readl(TIMER_CTRL); - writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); - } else { - /* - * Disable timer. - */ - u = readl(TIMER_CTRL); - writel(u & ~TIMER1_EN, TIMER_CTRL); - - /* - * Disable timer interrupt. - */ - u = readl(BRIDGE_MASK); - writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); - - /* - * ACK pending timer interrupt. - */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); - - } - local_irq_restore(flags); -} - -static struct clock_event_device orion_clkevt = { - .name = "orion_tick", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .shift = 32, - .rating = 300, - .cpumask = CPU_MASK_CPU0, - .set_next_event = orion_clkevt_next_event, - .set_mode = orion_clkevt_mode, -}; - -static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) -{ - /* - * ACK timer interrupt and call event handler. - */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); - orion_clkevt.event_handler(&orion_clkevt); - - return IRQ_HANDLED; -} - -static struct irqaction orion_timer_irq = { - .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = orion_timer_interrupt -}; - -void __init orion_time_init(unsigned int irq, unsigned int tclk) -{ - u32 u; - - ticks_per_jiffy = (tclk + HZ/2) / HZ; - - - /* - * Setup free-running clocksource timer (interrupts - * disabled.) - */ - writel(0xffffffff, TIMER0_VAL); - writel(0xffffffff, TIMER0_RELOAD); - u = readl(BRIDGE_MASK); - writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); - u = readl(TIMER_CTRL); - writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); - orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); - clocksource_register(&orion_clksrc); - - - /* - * Setup clockevent timer (interrupt-driven.) - */ - setup_irq(irq, &orion_timer_irq); - orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); - orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); - orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); - clockevents_register_device(&orion_clkevt); -} diff --git a/trunk/arch/arm/tools/mach-types b/trunk/arch/arm/tools/mach-types index 7ed58c0c24c2..207a8b5a0c4a 100644 --- a/trunk/arch/arm/tools/mach-types +++ b/trunk/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Sat Jan 26 14:45:34 2008 +# Last update: Sat Apr 19 11:23:38 2008 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -381,13 +381,13 @@ ks8695p ARCH_KS8695P KS8695P 363 se4000 ARCH_SE4000 SE4000 364 quadriceps ARCH_QUADRICEPS QUADRICEPS 365 bronco ARCH_BRONCO BRONCO 366 -esl_wireless_tab ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET 367 +esl_wireless_tab ARCH_ESL_WIRELESS_TAB ESL_WIRELESS_TAB 367 esl_sofcomp ARCH_ESL_SOFCOMP ESL_SOFCOMP 368 s5c7375 ARCH_S5C7375 S5C7375 369 spearhead ARCH_SPEARHEAD SPEARHEAD 370 pantera ARCH_PANTERA PANTERA 371 prayoglite ARCH_PRAYOGLITE PRAYOGLITE 372 -gumstix ARCH_GUMSTIK GUMSTIK 373 +gumstix ARCH_GUMSTIX GUMSTIX 373 rcube ARCH_RCUBE RCUBE 374 rea_olv ARCH_REA_OLV REA_OLV 375 pxa_iphone ARCH_PXA_IPHONE PXA_IPHONE 376 @@ -1463,7 +1463,7 @@ artemis MACH_ARTEMIS ARTEMIS 1462 htctitan MACH_HTCTITAN HTCTITAN 1463 qranium MACH_QRANIUM QRANIUM 1464 adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 -adx_medinet MACH_ADX_MEDINET ADX_MEDINET 1466 +adx_medcom MACH_ADX_MEDINET ADX_MEDINET 1466 bboard MACH_BBOARD BBOARD 1467 cambria MACH_CAMBRIA CAMBRIA 1468 mt7xxx MACH_MT7XXX MT7XXX 1469 @@ -1611,3 +1611,112 @@ kb9263 MACH_KB9263 KB9263 1612 mt7108 MACH_MT7108 MT7108 1613 smtr2440 MACH_SMTR2440 SMTR2440 1614 manao MACH_MANAO MANAO 1615 +cm_x300 MACH_CM_X300 CM_X300 1616 +gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617 +lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618 +arma37 MACH_ARMA37 ARMA37 1619 +mendel MACH_MENDEL MENDEL 1620 +pelco_iliad MACH_PELCO_ILIAD PELCO_ILIAD 1621 +unit2p MACH_UNIT2P UNIT2P 1622 +inc20otter MACH_INC20OTTER INC20OTTER 1623 +at91sam9g20ek MACH_AT91SAM9G20EK AT91SAM9G20EK 1624 +sc_ge2 MACH_STORCENTER STORCENTER 1625 +smdk6410 MACH_SMDK6410 SMDK6410 1626 +u300 MACH_U300 U300 1627 +u500 MACH_U500 U500 1628 +ds9260 MACH_DS9260 DS9260 1629 +riverrock MACH_RIVERROCK RIVERROCK 1630 +scibath MACH_SCIBATH SCIBATH 1631 +at91sam7se MACH_AT91SAM7SE512EK AT91SAM7SE512EK 1632 +wrt350n_v2 MACH_WRT350N_V2 WRT350N_V2 1633 +multimedia MACH_MULTIMEDIA MULTIMEDIA 1634 +marvin MACH_MARVIN MARVIN 1635 +x500 MACH_X500 X500 1636 +awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637 +palermoc MACH_PALERMOC PALERMOC 1638 +omap_ldp MACH_OMAP_LDP OMAP_LDP 1639 +ip500 MACH_IP500 IP500 1640 +mx35ads MACH_MACH_MX35ADS MACH_MX35ADS 1641 +ase2 MACH_ASE2 ASE2 1642 +mx35evb MACH_MX35EVB MX35EVB 1643 +aml_m8050 MACH_AML_M8050 AML_M8050 1644 +mx35_3ds MACH_MX35_3DS MX35_3DS 1645 +mars MACH_MARS MARS 1646 +ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647 +badger MACH_BADGER BADGER 1648 +trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 +trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 +marlin MACH_MARLIN MARLIN 1651 +ts7800 MACH_TS7800 TS7800 1652 +hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653 +at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654 +ne1board MACH_NE1BOARD NE1BOARD 1655 +zante MACH_ZANTE ZANTE 1656 +sffsdr MACH_SFFSDR SFFSDR 1657 +tw2662 MACH_TW2662 TW2662 1658 +vf10xx MACH_VF10XX VF10XX 1659 +zoran43xx MACH_ZORAN43XX ZORAN43XX 1660 +sonix926 MACH_SONIX926 SONIX926 1661 +celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662 +cc9m2443 MACH_CC9M2443 CC9M2443 1663 +tw5334 MACH_TW5334 TW5334 1664 +omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665 +nal_hlite MACH_NAL_HLITE NAL_HLITE 1666 +htcvogue MACH_HTCVOGUE HTCVOGUE 1667 +smartweb MACH_SMARTWEB SMARTWEB 1668 +mv86xx MACH_MV86XX MV86XX 1669 +mv87xx MACH_MV87XX MV87XX 1670 +songyoungho MACH_SONGYOUNGHO SONGYOUNGHO 1671 +younghotema MACH_YOUNGHOTEMA YOUNGHOTEMA 1672 +pcm037 MACH_PCM037 PCM037 1673 +mmvp MACH_MMVP MMVP 1674 +mmap MACH_MMAP MMAP 1675 +ptid2410 MACH_PTID2410 PTID2410 1676 +james_926 MACH_JAMES_926 JAMES_926 1677 +fm6000 MACH_FM6000 FM6000 1678 +db88f6281_bp MACH_DB88F6281_BP DB88F6281_BP 1680 +rd88f6192_nas MACH_RD88F6192_NAS RD88F6192_NAS 1681 +rd88f6281 MACH_RD88F6281 RD88F6281 1682 +db78x00_bp MACH_DB78X00_BP DB78X00_BP 1683 +smdk2416 MACH_SMDK2416 SMDK2416 1685 +oce_spider_si MACH_OCE_SPIDER_SI OCE_SPIDER_SI 1686 +oce_spider_sk MACH_OCE_SPIDER_SK OCE_SPIDER_SK 1687 +rovern6 MACH_ROVERN6 ROVERN6 1688 +pelco_evolution MACH_PELCO_EVOLUTION PELCO_EVOLUTION 1689 +wbd111 MACH_WBD111 WBD111 1690 +elaracpe MACH_ELARACPE ELARACPE 1691 +mabv3 MACH_MABV3 MABV3 1692 +mv2120 MACH_MV2120 MV2120 1693 +csb737 MACH_CSB737 CSB737 1695 +mx51_3ds MACH_MX51_3DS MX51_3DS 1696 +g900 MACH_G900 G900 1697 +apf27 MACH_APF27 APF27 1698 +ggus2000 MACH_GGUS2000 GGUS2000 1699 +omap_2430_mimic MACH_OMAP_2430_MIMIC OMAP_2430_MIMIC 1700 +imx27lite MACH_IMX27LITE IMX27LITE 1701 +almex MACH_ALMEX ALMEX 1702 +control MACH_CONTROL CONTROL 1703 +mba2410 MACH_MBA2410 MBA2410 1704 +volcano MACH_VOLCANO VOLCANO 1705 +zenith MACH_ZENITH ZENITH 1706 +muchip MACH_MUCHIP MUCHIP 1707 +magellan MACH_MAGELLAN MAGELLAN 1708 +usb_a9260 MACH_USB_A9260 USB_A9260 1709 +usb_a9263 MACH_USB_A9263 USB_A9263 1710 +qil_a9260 MACH_QIL_A9260 QIL_A9260 1711 +cme9210 MACH_CME9210 CME9210 1712 +hczh4 MACH_HCZH4 HCZH4 1713 +spearbasic MACH_SPEARBASIC SPEARBASIC 1714 +dep2440 MACH_DEP2440 DEP2440 1715 +hdl_gxr MACH_HDL_GXR HDL_GXR 1716 +hdl_gt MACH_HDL_GT HDL_GT 1717 +hdl_4g MACH_HDL_4G HDL_4G 1718 +s3c6000 MACH_S3C6000 S3C6000 1719 +mmsp2_mdk MACH_MMSP2_MDK MMSP2_MDK 1720 +mpx220 MACH_MPX220 MPX220 1721 +kzm_arm11_01 MACH_KZM_ARM11_01 KZM_ARM11_01 1722 +htc_polaris MACH_HTC_POLARIS HTC_POLARIS 1723 +htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724 +lg_ks20 MACH_LG_KS20 LG_KS20 1725 +hhgps MACH_HHGPS HHGPS 1726 +nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727 diff --git a/trunk/drivers/ata/sata_mv.c b/trunk/drivers/ata/sata_mv.c index 83584b6e1ba5..6ebebde8454a 100644 --- a/trunk/drivers/ata/sata_mv.c +++ b/trunk/drivers/ata/sata_mv.c @@ -74,7 +74,6 @@ #include #include #include -#include #include #include #include @@ -353,9 +352,6 @@ enum { #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) -#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) -#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) - enum { /* DMA boundary 0xffff is required by the s/g splitting * we need on /length/ in mv_fill-sg(). @@ -2901,27 +2897,6 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) return 0; } -static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, - struct mbus_dram_target_info *dram) -{ - int i; - - for (i = 0; i < 4; i++) { - writel(0, hpriv->base + WINDOW_CTRL(i)); - writel(0, hpriv->base + WINDOW_BASE(i)); - } - - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - - writel(((cs->size - 1) & 0xffff0000) | - (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1, - hpriv->base + WINDOW_CTRL(i)); - writel(cs->base, hpriv->base + WINDOW_BASE(i)); - } -} - /** * mv_platform_probe - handle a positive probe of an soc Marvell * host @@ -2976,12 +2951,6 @@ static int mv_platform_probe(struct platform_device *pdev) res->end - res->start + 1); hpriv->base -= MV_SATAHC0_REG_BASE; - /* - * (Re-)program MBUS remapping windows if we are asked to. - */ - if (mv_platform_data->dram != NULL) - mv_conf_mbus_windows(hpriv, mv_platform_data->dram); - rc = mv_create_dma_pools(hpriv, &pdev->dev); if (rc) return rc; diff --git a/trunk/drivers/i2c/busses/Kconfig b/trunk/drivers/i2c/busses/Kconfig index b04c99580d0d..5fa9c3c67e0c 100644 --- a/trunk/drivers/i2c/busses/Kconfig +++ b/trunk/drivers/i2c/busses/Kconfig @@ -645,7 +645,7 @@ config I2C_PCA_ISA config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" - depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL + depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL help If you say yes to this option, support will be included for the built-in I2C interface on the Marvell 64xxx line of host bridges. diff --git a/trunk/drivers/mtd/nand/Kconfig b/trunk/drivers/mtd/nand/Kconfig index 959fb86cda01..4a3c6759492b 100644 --- a/trunk/drivers/mtd/nand/Kconfig +++ b/trunk/drivers/mtd/nand/Kconfig @@ -314,7 +314,7 @@ config MTD_ALAUDA config MTD_NAND_ORION tristate "NAND Flash support for Marvell Orion SoC" - depends on PLAT_ORION && MTD_NAND + depends on ARCH_ORION && MTD_NAND help This enables the NAND flash controller on Orion machines. diff --git a/trunk/drivers/mtd/nand/orion_nand.c b/trunk/drivers/mtd/nand/orion_nand.c index ec5ad28b237e..9162cca0182b 100644 --- a/trunk/drivers/mtd/nand/orion_nand.c +++ b/trunk/drivers/mtd/nand/orion_nand.c @@ -18,8 +18,8 @@ #include #include #include +#include #include -#include #ifdef CONFIG_MTD_CMDLINE_PARTS static const char *part_probes[] = { "cmdlinepart", NULL }; diff --git a/trunk/drivers/net/Kconfig b/trunk/drivers/net/Kconfig index 124d29f5fa0c..fe7b5ec09708 100644 --- a/trunk/drivers/net/Kconfig +++ b/trunk/drivers/net/Kconfig @@ -2415,7 +2415,7 @@ config UGETH_TX_ON_DEMAND config MV643XX_ETH tristate "Marvell Discovery (643XX) and Orion ethernet support" - depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || PLAT_ORION + depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION select MII help This driver supports the gigabit ethernet MACs in the diff --git a/trunk/drivers/usb/host/ehci-hcd.c b/trunk/drivers/usb/host/ehci-hcd.c index 85074cb36f38..46ee7f4c0912 100644 --- a/trunk/drivers/usb/host/ehci-hcd.c +++ b/trunk/drivers/usb/host/ehci-hcd.c @@ -1033,7 +1033,7 @@ MODULE_LICENSE ("GPL"); #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver #endif -#ifdef CONFIG_PLAT_ORION +#ifdef CONFIG_ARCH_ORION #include "ehci-orion.c" #define PLATFORM_DRIVER ehci_orion_driver #endif diff --git a/trunk/drivers/usb/host/ehci-orion.c b/trunk/drivers/usb/host/ehci-orion.c index d187d0313742..e129981f139f 100644 --- a/trunk/drivers/usb/host/ehci-orion.c +++ b/trunk/drivers/usb/host/ehci-orion.c @@ -11,18 +11,15 @@ #include #include #include -#include -#include +#include #define rdl(off) __raw_readl(hcd->regs + (off)) #define wrl(off, val) __raw_writel((val), hcd->regs + (off)) -#define USB_CMD 0x140 -#define USB_MODE 0x1a8 #define USB_CAUSE 0x310 #define USB_MASK 0x314 -#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) -#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) +#define USB_CMD 0x140 +#define USB_MODE 0x1a8 #define USB_IPG 0x360 #define USB_PHY_PWR_CTRL 0x400 #define USB_PHY_TX_CTRL 0x420 @@ -165,30 +162,8 @@ static const struct hc_driver ehci_orion_hc_driver = { .bus_resume = ehci_bus_resume, }; -static void __init -ehci_orion_conf_mbus_windows(struct usb_hcd *hcd, - struct mbus_dram_target_info *dram) -{ - int i; - - for (i = 0; i < 4; i++) { - wrl(USB_WINDOW_CTRL(i), 0); - wrl(USB_WINDOW_BASE(i), 0); - } - - for (i = 0; i < dram->num_cs; i++) { - struct mbus_dram_window *cs = dram->cs + i; - - wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | - (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1); - wrl(USB_WINDOW_BASE(i), cs->base); - } -} - static int __init ehci_orion_drv_probe(struct platform_device *pdev) { - struct orion_ehci_data *pd = pdev->dev.platform_data; struct resource *res; struct usb_hcd *hcd; struct ehci_hcd *ehci; @@ -251,12 +226,6 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev) ehci->is_tdi_rh_tt = 1; ehci->sbrn = 0x20; - /* - * (Re-)program MBUS remapping windows if we are asked to. - */ - if (pd != NULL && pd->dram != NULL) - ehci_orion_conf_mbus_windows(hcd, pd->dram); - /* * setup Orion USB controller */ diff --git a/trunk/include/asm-arm/arch-orion5x/debug-macro.S b/trunk/include/asm-arm/arch-orion/debug-macro.S similarity index 73% rename from trunk/include/asm-arm/arch-orion5x/debug-macro.S rename to trunk/include/asm-arm/arch-orion/debug-macro.S index 4f98f3ba2929..2746220f5d85 100644 --- a/trunk/include/asm-arm/arch-orion5x/debug-macro.S +++ b/trunk/include/asm-arm/arch-orion/debug-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion5x/debug-macro.S + * linux/include/asm-arm/arch-orion/debug-macro.S * * Debugging macro include header * @@ -8,13 +8,13 @@ * published by the Free Software Foundation. */ -#include +#include .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =ORION5X_REGS_PHYS_BASE - ldrne \rx, =ORION5X_REGS_VIRT_BASE + ldreq \rx, =ORION_REGS_PHYS_BASE + ldrne \rx, =ORION_REGS_VIRT_BASE orr \rx, \rx, #0x00012000 .endm diff --git a/trunk/include/asm-arm/arch-orion5x/dma.h b/trunk/include/asm-arm/arch-orion/dma.h similarity index 100% rename from trunk/include/asm-arm/arch-orion5x/dma.h rename to trunk/include/asm-arm/arch-orion/dma.h diff --git a/trunk/include/asm-arm/arch-orion5x/entry-macro.S b/trunk/include/asm-arm/arch-orion/entry-macro.S similarity index 90% rename from trunk/include/asm-arm/arch-orion5x/entry-macro.S rename to trunk/include/asm-arm/arch-orion/entry-macro.S index d8ef54c0ee9a..cda096b2acfd 100644 --- a/trunk/include/asm-arm/arch-orion5x/entry-macro.S +++ b/trunk/include/asm-arm/arch-orion/entry-macro.S @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion5x/entry-macro.S + * include/asm-arm/arch-orion/entry-macro.S * * Low-level IRQ helper macros for Orion platforms * @@ -8,7 +8,7 @@ * warranty of any kind, whether express or implied. */ -#include +#include .macro disable_fiq .endm diff --git a/trunk/include/asm-arm/arch-orion5x/gpio.h b/trunk/include/asm-arm/arch-orion/gpio.h similarity index 79% rename from trunk/include/asm-arm/arch-orion5x/gpio.h rename to trunk/include/asm-arm/arch-orion/gpio.h index c85e498388b6..d66284f9a14c 100644 --- a/trunk/include/asm-arm/arch-orion5x/gpio.h +++ b/trunk/include/asm-arm/arch-orion/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion5x/gpio.h + * include/asm-arm/arch-orion/gpio.h * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any @@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin); extern int gpio_direction_output(unsigned pin, int value); extern int gpio_get_value(unsigned pin); extern void gpio_set_value(unsigned pin, int value); -extern void orion5x_gpio_set_blink(unsigned pin, int blink); +extern void orion_gpio_set_blink(unsigned pin, int blink); extern void gpio_display(void); /* debug */ static inline int gpio_to_irq(int pin) { - return pin + IRQ_ORION5X_GPIO_START; + return pin + IRQ_ORION_GPIO_START; } static inline int irq_to_gpio(int irq) { - return irq - IRQ_ORION5X_GPIO_START; + return irq - IRQ_ORION_GPIO_START; } #include /* cansleep wrappers */ diff --git a/trunk/include/asm-arm/arch-orion5x/hardware.h b/trunk/include/asm-arm/arch-orion/hardware.h similarity index 64% rename from trunk/include/asm-arm/arch-orion5x/hardware.h rename to trunk/include/asm-arm/arch-orion/hardware.h index 5d2d8e0b5630..65da374de735 100644 --- a/trunk/include/asm-arm/arch-orion5x/hardware.h +++ b/trunk/include/asm-arm/arch-orion/hardware.h @@ -1,21 +1,21 @@ /* - * include/asm-arm/arch-orion5x/hardware.h + * include/asm-arm/arch-orion/hardware.h * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H +#ifndef __ASM_ARCH_HARDWARE_H__ +#define __ASM_ARCH_HARDWARE_H__ -#include "orion5x.h" +#include "orion.h" #define pcibios_assign_all_busses() 1 #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x01000000 -#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE +#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE #endif diff --git a/trunk/include/asm-arm/arch-orion/io.h b/trunk/include/asm-arm/arch-orion/io.h new file mode 100644 index 000000000000..e0b8c39b9167 --- /dev/null +++ b/trunk/include/asm-arm/arch-orion/io.h @@ -0,0 +1,27 @@ +/* + * include/asm-arm/arch-orion/io.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include "orion.h" + +#define IO_SPACE_LIMIT 0xffffffff +#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)addr; +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/trunk/include/asm-arm/arch-orion/irqs.h b/trunk/include/asm-arm/arch-orion/irqs.h new file mode 100644 index 000000000000..eea65ca6076a --- /dev/null +++ b/trunk/include/asm-arm/arch-orion/irqs.h @@ -0,0 +1,61 @@ +/* + * include/asm-arm/arch-orion/irqs.h + * + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#include "orion.h" /* need GPIO_MAX */ + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION_BRIDGE 0 +#define IRQ_ORION_DOORBELL_H2C 1 +#define IRQ_ORION_DOORBELL_C2H 2 +#define IRQ_ORION_UART0 3 +#define IRQ_ORION_UART1 4 +#define IRQ_ORION_I2C 5 +#define IRQ_ORION_GPIO_0_7 6 +#define IRQ_ORION_GPIO_8_15 7 +#define IRQ_ORION_GPIO_16_23 8 +#define IRQ_ORION_GPIO_24_31 9 +#define IRQ_ORION_PCIE0_ERR 10 +#define IRQ_ORION_PCIE0_INT 11 +#define IRQ_ORION_USB1_CTRL 12 +#define IRQ_ORION_DEV_BUS_ERR 14 +#define IRQ_ORION_PCI_ERR 15 +#define IRQ_ORION_USB_BR_ERR 16 +#define IRQ_ORION_USB0_CTRL 17 +#define IRQ_ORION_ETH_RX 18 +#define IRQ_ORION_ETH_TX 19 +#define IRQ_ORION_ETH_MISC 20 +#define IRQ_ORION_ETH_SUM 21 +#define IRQ_ORION_ETH_ERR 22 +#define IRQ_ORION_IDMA_ERR 23 +#define IRQ_ORION_IDMA_0 24 +#define IRQ_ORION_IDMA_1 25 +#define IRQ_ORION_IDMA_2 26 +#define IRQ_ORION_IDMA_3 27 +#define IRQ_ORION_CESA 28 +#define IRQ_ORION_SATA 29 +#define IRQ_ORION_XOR0 30 +#define IRQ_ORION_XOR1 31 + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS) + +#endif /* __ASM_ARCH_IRQS_H__ */ diff --git a/trunk/include/asm-arm/arch-orion5x/memory.h b/trunk/include/asm-arm/arch-orion/memory.h similarity index 64% rename from trunk/include/asm-arm/arch-orion5x/memory.h rename to trunk/include/asm-arm/arch-orion/memory.h index 80053a7afc7a..d954dba87ced 100644 --- a/trunk/include/asm-arm/arch-orion5x/memory.h +++ b/trunk/include/asm-arm/arch-orion/memory.h @@ -1,16 +1,15 @@ /* - * include/asm-arm/arch-orion5x/memory.h + * include/asm-arm/arch-orion/memory.h * * Marvell Orion memory definitions */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H #define PHYS_OFFSET UL(0x00000000) #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) - #endif diff --git a/trunk/include/asm-arm/arch-orion/orion.h b/trunk/include/asm-arm/arch-orion/orion.h new file mode 100644 index 000000000000..673a418a7419 --- /dev/null +++ b/trunk/include/asm-arm/arch-orion/orion.h @@ -0,0 +1,165 @@ +/* + * include/asm-arm/arch-orion/orion.h + * + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION_H__ +#define __ASM_ARCH_ORION_H__ + +/***************************************************************************** + * Orion Address Map + * + * virt phys size + * fdd00000 f1000000 1M on-chip peripheral registers + * fde00000 f2000000 1M PCIe I/O space + * fdf00000 f2100000 1M PCI I/O space + * fe000000 f0000000 16M PCIe WA space (Orion-NAS only) + ****************************************************************************/ +#define ORION_REGS_PHYS_BASE 0xf1000000 +#define ORION_REGS_VIRT_BASE 0xfdd00000 +#define ORION_REGS_SIZE SZ_1M + +#define ORION_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION_PCIE_IO_BUS_BASE 0x00000000 +#define ORION_PCIE_IO_SIZE SZ_1M + +#define ORION_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION_PCI_IO_BUS_BASE 0x00100000 +#define ORION_PCI_IO_SIZE SZ_1M + +/* Relevant only for Orion-NAS */ +#define ORION_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION_PCIE_WA_SIZE SZ_16M + +#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION_PCIE_MEM_SIZE SZ_128M + +#define ORION_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ +#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000) +#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x)) + +#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000) +#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000) +#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x)) +#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000) +#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100) + +#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000) +#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x)) + +#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000) +#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x)) + +#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000) +#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x)) + +#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000) +#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000) +#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x)) + +#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000) +#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000) +#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x)) + +#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000) +#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000) +#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x)) + +#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000) +#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000) +#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x)) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010) +#define GPIO_OUT ORION_DEV_BUS_REG(0x100) +#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104) +#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108) +#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c) +#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110) +#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114) +#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118) +#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c) +#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4) +#define GPIO_MAX 32 + +/*************************************************************************** + * Orion CPU Bridge Registers + **************************************************************************/ +#define CPU_CONF ORION_BRIDGE_REG(0x100) +#define CPU_CTRL ORION_BRIDGE_REG(0x104) +#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108) +#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c) +#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C) +#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110) +#define BRIDGE_MASK ORION_BRIDGE_REG(0x114) +#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200) +#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204) +#define TIMER_CTRL ORION_BRIDGE_REG(0x300) +#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8)) +#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8)) + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Helpers to access Orion registers + ******************************************************************************/ +#include +#include + +#define orion_read(r) __raw_readl(r) +#define orion_write(r, val) __raw_writel(val, r) + +/* + * These are not preempt safe. Locks, if needed, must be taken care by caller. + */ +#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask)) +#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask)) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_ORION_H__ */ diff --git a/trunk/include/asm-arm/plat-orion/orion_nand.h b/trunk/include/asm-arm/arch-orion/platform.h similarity index 64% rename from trunk/include/asm-arm/plat-orion/orion_nand.h rename to trunk/include/asm-arm/arch-orion/platform.h index ffd3852a0dd7..143c38e2fa0b 100644 --- a/trunk/include/asm-arm/plat-orion/orion_nand.h +++ b/trunk/include/asm-arm/arch-orion/platform.h @@ -1,13 +1,15 @@ /* - * include/asm-arm/plat-orion/orion_nand.h + * asm-arm/arch-orion/platform.h + * + * Tzachi Perelstein * * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#ifndef __ASM_PLAT_ORION_ORION_NAND_H -#define __ASM_PLAT_ORION_ORION_NAND_H +#ifndef __ASM_ARCH_PLATFORM_H__ +#define __ASM_ARCH_PLATFORM_H__ /* * Device bus NAND private data @@ -20,5 +22,4 @@ struct orion_nand_data { u8 width; /* buswidth */ }; - #endif diff --git a/trunk/include/asm-arm/arch-orion5x/system.h b/trunk/include/asm-arm/arch-orion/system.h similarity index 54% rename from trunk/include/asm-arm/arch-orion5x/system.h rename to trunk/include/asm-arm/arch-orion/system.h index 3f1d1e2d38f8..17704c68f90e 100644 --- a/trunk/include/asm-arm/arch-orion5x/system.h +++ b/trunk/include/asm-arm/arch-orion/system.h @@ -1,10 +1,10 @@ /* - * include/asm-arm/arch-orion5x/system.h + * include/asm-arm/arch-orion/system.h * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ @@ -12,7 +12,7 @@ #define __ASM_ARCH_SYSTEM_H #include -#include +#include static inline void arch_idle(void) { @@ -24,9 +24,8 @@ static inline void arch_reset(char mode) /* * Enable and issue soft reset */ - orion5x_setbits(CPU_RESET_MASK, (1 << 2)); - orion5x_setbits(CPU_SOFT_RESET, 1); + orion_setbits(CPU_RESET_MASK, (1 << 2)); + orion_setbits(CPU_SOFT_RESET, 1); } - #endif diff --git a/trunk/include/asm-arm/arch-orion/timex.h b/trunk/include/asm-arm/arch-orion/timex.h new file mode 100644 index 000000000000..26c2c91eecf0 --- /dev/null +++ b/trunk/include/asm-arm/arch-orion/timex.h @@ -0,0 +1,12 @@ +/* + * include/asm-arm/arch-orion/timex.h + * + * Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define ORION_TCLK 166666667 +#define CLOCK_TICK_RATE ORION_TCLK diff --git a/trunk/include/asm-arm/arch-orion5x/uncompress.h b/trunk/include/asm-arm/arch-orion/uncompress.h similarity index 71% rename from trunk/include/asm-arm/arch-orion5x/uncompress.h rename to trunk/include/asm-arm/arch-orion/uncompress.h index 5c13d4fafb4e..59f44039909a 100644 --- a/trunk/include/asm-arm/arch-orion5x/uncompress.h +++ b/trunk/include/asm-arm/arch-orion/uncompress.h @@ -1,14 +1,14 @@ /* - * include/asm-arm/arch-orion5x/uncompress.h + * include/asm-arm/arch-orion/uncompress.h * * Tzachi Perelstein * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include +#include #define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) #define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) diff --git a/trunk/include/asm-arm/arch-orion5x/vmalloc.h b/trunk/include/asm-arm/arch-orion/vmalloc.h similarity index 51% rename from trunk/include/asm-arm/arch-orion5x/vmalloc.h rename to trunk/include/asm-arm/arch-orion/vmalloc.h index 2b3061e90dc1..9d580278d2bc 100644 --- a/trunk/include/asm-arm/arch-orion5x/vmalloc.h +++ b/trunk/include/asm-arm/arch-orion/vmalloc.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-orion5x/vmalloc.h + * include/asm-arm/arch-orion/vmalloc.h */ #define VMALLOC_END 0xfd800000 diff --git a/trunk/include/asm-arm/arch-orion5x/io.h b/trunk/include/asm-arm/arch-orion5x/io.h deleted file mode 100644 index 5148ab7ad1f8..000000000000 --- a/trunk/include/asm-arm/arch-orion5x/io.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * include/asm-arm/arch-orion5x/io.h - * - * Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "orion5x.h" - -#define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE - -static inline void __iomem * -__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) -{ - void __iomem *retval; - - if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE && - paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) { - retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + - (paddr - ORION5X_REGS_PHYS_BASE); - } else { - retval = __arm_ioremap(paddr, size, mtype); - } - - return retval; -} - -static inline void -__arch_iounmap(void __iomem *addr) -{ - if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || - addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) - __iounmap(addr); -} - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)addr; -} - -#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) -#define __arch_iounmap(a) __arch_iounmap(a) -#define __io(a) __io(a) -#define __mem_pci(a) (a) - - -/***************************************************************************** - * Helpers to access Orion registers - ****************************************************************************/ -#define orion5x_read(r) __raw_readl(r) -#define orion5x_write(r, val) __raw_writel(val, r) - -/* - * These are not preempt-safe. Locks, if needed, must be taken - * care of by the caller. - */ -#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) -#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) - - -#endif diff --git a/trunk/include/asm-arm/arch-orion5x/irqs.h b/trunk/include/asm-arm/arch-orion5x/irqs.h deleted file mode 100644 index abdd61a4833a..000000000000 --- a/trunk/include/asm-arm/arch-orion5x/irqs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * include/asm-arm/arch-orion5x/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#include "orion5x.h" /* need GPIO_MAX */ - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION5X_BRIDGE 0 -#define IRQ_ORION5X_DOORBELL_H2C 1 -#define IRQ_ORION5X_DOORBELL_C2H 2 -#define IRQ_ORION5X_UART0 3 -#define IRQ_ORION5X_UART1 4 -#define IRQ_ORION5X_I2C 5 -#define IRQ_ORION5X_GPIO_0_7 6 -#define IRQ_ORION5X_GPIO_8_15 7 -#define IRQ_ORION5X_GPIO_16_23 8 -#define IRQ_ORION5X_GPIO_24_31 9 -#define IRQ_ORION5X_PCIE0_ERR 10 -#define IRQ_ORION5X_PCIE0_INT 11 -#define IRQ_ORION5X_USB1_CTRL 12 -#define IRQ_ORION5X_DEV_BUS_ERR 14 -#define IRQ_ORION5X_PCI_ERR 15 -#define IRQ_ORION5X_USB_BR_ERR 16 -#define IRQ_ORION5X_USB0_CTRL 17 -#define IRQ_ORION5X_ETH_RX 18 -#define IRQ_ORION5X_ETH_TX 19 -#define IRQ_ORION5X_ETH_MISC 20 -#define IRQ_ORION5X_ETH_SUM 21 -#define IRQ_ORION5X_ETH_ERR 22 -#define IRQ_ORION5X_IDMA_ERR 23 -#define IRQ_ORION5X_IDMA_0 24 -#define IRQ_ORION5X_IDMA_1 25 -#define IRQ_ORION5X_IDMA_2 26 -#define IRQ_ORION5X_IDMA_3 27 -#define IRQ_ORION5X_CESA 28 -#define IRQ_ORION5X_SATA 29 -#define IRQ_ORION5X_XOR0 30 -#define IRQ_ORION5X_XOR1 31 - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION5X_GPIO_START 32 -#define NR_GPIO_IRQS GPIO_MAX - -#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/trunk/include/asm-arm/arch-orion5x/orion5x.h b/trunk/include/asm-arm/arch-orion5x/orion5x.h deleted file mode 100644 index 206ddd71e193..000000000000 --- a/trunk/include/asm-arm/arch-orion5x/orion5x.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * include/asm-arm/arch-orion5x/orion5x.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION5X_H -#define __ASM_ARCH_ORION5X_H - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fdd00000 f1000000 1M on-chip peripheral registers - * fde00000 f2000000 1M PCIe I/O space - * fdf00000 f2100000 1M PCI I/O space - * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 -#define ORION5X_REGS_SIZE SZ_1M - -#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 -#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_1M - -#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 -#define ORION5X_PCI_IO_BUS_BASE 0x00100000 -#define ORION5X_PCI_IO_SIZE SZ_1M - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 -#define ORION5X_PCIE_WA_SIZE SZ_16M - -#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION5X_PCIE_MEM_SIZE SZ_128M - -#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION5X_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) -#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) - -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) - -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) -#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) - -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) -#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) - -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) -#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) - -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) -#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) - -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) -#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) - -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) -#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) - -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) -#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) -#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) -#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) -#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) -#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) -#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) -#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) -#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) -#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) -#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) -#define GPIO_MAX 32 - -/*************************************************************************** - * Orion CPU Bridge Registers - **************************************************************************/ -#define CPU_CONF ORION5X_BRIDGE_REG(0x100) -#define CPU_CTRL ORION5X_BRIDGE_REG(0x104) -#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) -#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) -#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) -#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) -#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) -#define BRIDGE_INT_TIMER0 0x0002 -#define BRIDGE_INT_TIMER1 0x0004 -#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) -#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) - - -#endif diff --git a/trunk/include/asm-arm/arch-orion5x/timex.h b/trunk/include/asm-arm/arch-orion5x/timex.h deleted file mode 100644 index 31c568e28cc3..000000000000 --- a/trunk/include/asm-arm/arch-orion5x/timex.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * include/asm-arm/arch-orion5x/timex.h - * - * Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) - -#define ORION5X_TCLK 166666667 diff --git a/trunk/include/asm-arm/arch-pxa/pxa3xx-regs.h b/trunk/include/asm-arm/arch-pxa/pxa3xx-regs.h index 8e1b3ead827f..fe9364c83a28 100644 --- a/trunk/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ b/trunk/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -12,6 +12,15 @@ #ifndef __ASM_ARCH_PXA3XX_REGS_H #define __ASM_ARCH_PXA3XX_REGS_H + +/* + * Oscillator Configuration Register (OSCC) + */ +#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ + +#define OSCC_PEN (1 << 11) /* 13MHz POUT */ + + /* * Service Power Management Unit (MPMU) */ diff --git a/trunk/include/asm-arm/plat-orion/ehci-orion.h b/trunk/include/asm-arm/plat-orion/ehci-orion.h deleted file mode 100644 index 785705651e24..000000000000 --- a/trunk/include/asm-arm/plat-orion/ehci-orion.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * include/asm-arm/plat-orion/ehci-orion.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_PLAT_ORION_EHCI_ORION_H -#define __ASM_PLAT_ORION_EHCI_ORION_H - -#include - -struct orion_ehci_data { - struct mbus_dram_target_info *dram; -}; - - -#endif diff --git a/trunk/include/asm-arm/plat-orion/irq.h b/trunk/include/asm-arm/plat-orion/irq.h deleted file mode 100644 index 94aeed919d5b..000000000000 --- a/trunk/include/asm-arm/plat-orion/irq.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * include/asm-arm/plat-orion/irq.h - * - * Marvell Orion SoC IRQ handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_PLAT_ORION_IRQ_H -#define __ASM_PLAT_ORION_IRQ_H - -void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr); - - -#endif diff --git a/trunk/include/asm-arm/plat-orion/pcie.h b/trunk/include/asm-arm/plat-orion/pcie.h deleted file mode 100644 index 6434ac685d21..000000000000 --- a/trunk/include/asm-arm/plat-orion/pcie.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * include/asm-arm/plat-orion/pcie.h - * - * Marvell Orion SoC PCIe handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_PLAT_ORION_PCIE_H -#define __ASM_PLAT_ORION_PCIE_H - -u32 orion_pcie_dev_id(void __iomem *base); -u32 orion_pcie_rev(void __iomem *base); -int orion_pcie_link_up(void __iomem *base); -int orion_pcie_get_local_bus_nr(void __iomem *base); -void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); -void orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram); -int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val); -int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val); -int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val); -int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val); - - -#endif diff --git a/trunk/include/asm-arm/plat-orion/time.h b/trunk/include/asm-arm/plat-orion/time.h deleted file mode 100644 index 0e85cc8f44d9..000000000000 --- a/trunk/include/asm-arm/plat-orion/time.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * include/asm-arm/plat-orion/time.h - * - * Marvell Orion SoC time handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_PLAT_ORION_TIME_H -#define __ASM_PLAT_ORION_TIME_H - -void orion_time_init(unsigned int irq, unsigned int tclk); - - -#endif diff --git a/trunk/include/linux/ata_platform.h b/trunk/include/linux/ata_platform.h index 9a26c83a2c9e..b856a2a590d9 100644 --- a/trunk/include/linux/ata_platform.h +++ b/trunk/include/linux/ata_platform.h @@ -27,10 +27,7 @@ extern int __devexit __pata_platform_remove(struct device *dev); /* * Marvell SATA private data */ -struct mbus_dram_target_info; - struct mv_sata_platform_data { - struct mbus_dram_target_info *dram; int n_ports; /* number of sata ports */ }; diff --git a/trunk/include/linux/mbus.h b/trunk/include/linux/mbus.h deleted file mode 100644 index c11ff2932549..000000000000 --- a/trunk/include/linux/mbus.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Marvell MBUS common definitions. - * - * Copyright (C) 2008 Marvell Semiconductor - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __LINUX_MBUS_H -#define __LINUX_MBUS_H - -struct mbus_dram_target_info -{ - /* - * The 4-bit MBUS target ID of the DRAM controller. - */ - u8 mbus_dram_target_id; - - /* - * The base address, size, and MBUS attribute ID for each - * of the possible DRAM chip selects. Peripherals are - * required to support at least 4 decode windows. - */ - int num_cs; - struct mbus_dram_window { - u8 cs_index; - u8 mbus_attr; - u32 base; - u32 size; - } cs[4]; -}; - - -#endif