From df26c54942de7f694375beaa1a8522d5762a7aa5 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 29 Jan 2009 17:08:41 -0700 Subject: [PATCH] --- yaml --- r: 130785 b: refs/heads/master c: e489a44e2473981474fe17f17418828ba341661a h: refs/heads/master i: 130783: 719f019bd5af7a857c21d1c331edd8df8e13b5c7 v: v3 --- [refs] | 2 +- .../arch/powerpc/platforms/52xx/mpc52xx_pci.c | 24 ++++++++----------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/[refs] b/[refs] index 9416a0866765..8e0043b29f37 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d35ec494a68218d646f31d8b4f03ddd39b262a3e +refs/heads/master: e489a44e2473981474fe17f17418828ba341661a diff --git a/trunk/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/trunk/arch/powerpc/platforms/52xx/mpc52xx_pci.c index c3f2c21024e3..87ff522f28b5 100644 --- a/trunk/arch/powerpc/platforms/52xx/mpc52xx_pci.c +++ b/trunk/arch/powerpc/platforms/52xx/mpc52xx_pci.c @@ -19,14 +19,6 @@ #include -/* ======================================================================== */ -/* PCI windows config */ -/* ======================================================================== */ - -#define MPC52xx_PCI_TARGET_IO 0xf0000000 -#define MPC52xx_PCI_TARGET_MEM 0x00000000 - - /* ======================================================================== */ /* Structures mapping & Defines for PCI Unit */ /* ======================================================================== */ @@ -244,7 +236,7 @@ static struct pci_ops mpc52xx_pci_ops = { static void __init mpc52xx_pci_setup(struct pci_controller *hose, - struct mpc52xx_pci __iomem *pci_regs) + struct mpc52xx_pci __iomem *pci_regs, phys_addr_t pci_phys) { struct resource *res; u32 tmp; @@ -314,10 +306,14 @@ mpc52xx_pci_setup(struct pci_controller *hose, /* Set all the IWCR fields at once; they're in the same reg */ out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2)); - out_be32(&pci_regs->tbatr0, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO ); - out_be32(&pci_regs->tbatr1, - MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM ); + /* Map IMMR onto PCI bus */ + pci_phys &= 0xfffc0000; /* bar0 has only 14 significant bits */ + out_be32(&pci_regs->tbatr0, MPC52xx_PCI_TBATR_ENABLE | pci_phys); + out_be32(&pci_regs->bar0, PCI_BASE_ADDRESS_MEM_PREFETCH | pci_phys); + + /* Map memory onto PCI bus */ + out_be32(&pci_regs->tbatr1, MPC52xx_PCI_TBATR_ENABLE); + out_be32(&pci_regs->bar1, PCI_BASE_ADDRESS_MEM_PREFETCH); out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); @@ -414,7 +410,7 @@ mpc52xx_add_bridge(struct device_node *node) /* Finish setting up PCI using values obtained by * pci_proces_bridge_OF_ranges */ - mpc52xx_pci_setup(hose, pci_regs); + mpc52xx_pci_setup(hose, pci_regs, rsrc.start); return 0; }