From e025ebdf32f42293a1d199da5c00c1920be47dba Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 15 Feb 2010 10:03:35 -0800 Subject: [PATCH] --- yaml --- r: 184722 b: refs/heads/master c: 07dcbd07866691c33a3ff6f2d845292f23760669 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/include/plat/control.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 5ce4a418d2bb..d270e8264157 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e3d4d0a2385593e7873e7d7688eeffea949facff +refs/heads/master: 07dcbd07866691c33a3ff6f2d845292f23760669 diff --git a/trunk/arch/arm/plat-omap/include/plat/control.h b/trunk/arch/arm/plat-omap/include/plat/control.h index fcdc71bf4c6e..207447399ad3 100644 --- a/trunk/arch/arm/plat-omap/include/plat/control.h +++ b/trunk/arch/arm/plat-omap/include/plat/control.h @@ -274,6 +274,23 @@ #define AM35XX_CPGMAC_FCLK_SHIFT 9 #define AM35XX_VPFE_FCLK_SHIFT 10 +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) +#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) +#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) +#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) +#define AM35XX_USBOTGSS_INT_CLR BIT(4) +#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) +#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) +#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) + +/*AM35XX CONTROL_IP_SW_RESET bits*/ +#define AM35XX_USBOTGSS_SW_RST BIT(0) +#define AM35XX_CPGMACSS_SW_RST BIT(1) +#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) +#define AM35XX_HECC_SW_RST BIT(3) +#define AM35XX_VPFE_PCLK_SW_RST BIT(4) + /* * CONTROL OMAP STATUS register to identify OMAP3 features */