From e0789410806e814bbc321010ead9a1823efd65e9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 9 Apr 2010 15:31:56 -0400 Subject: [PATCH] --- yaml --- r: 190009 b: refs/heads/master c: a1a4b23b66039c814c3d3a9a28d76d34800eadc5 h: refs/heads/master i: 190007: af2b8ffc29db563740b3b5614f08c89afae64a46 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/atombios_crtc.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 22bd12984787..f2d8d965ef46 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 08d075116db3592db218bfe0f554cd93c9e12505 +refs/heads/master: a1a4b23b66039c814c3d3a9a28d76d34800eadc5 diff --git a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c index fd4ef6d18849..a87990b3ae84 100644 --- a/trunk/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/trunk/drivers/gpu/drm/radeon/atombios_crtc.c @@ -521,6 +521,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) adjusted_clock = mode->clock * 2; + if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { + pll->algo = PLL_ALGO_LEGACY; + pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; + } } else { if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;