From e155c5da811b382c5e22992ea782280ec1bbdafd Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 8 Dec 2008 18:35:03 +0800 Subject: [PATCH] --- yaml --- r: 123943 b: refs/heads/master c: c1f99c215c58111629984a49ba87b2b145dd1f5b h: refs/heads/master i: 123941: 8a121ee214d66f2ce1d95ec217e047731eb17342 123939: 206a18e5585ad54372bc2b811fb81fb08b2f6614 123935: 46fd902eb0f4759d3b0518cbd6ba373273f05668 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-pxa/include/mach/pxafb.h | 4 ++++ trunk/drivers/video/pxafb.c | 4 +++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 3acce587e1a2..5ec0f7c9c767 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 07df1c4fea1474ae6db2c8554d2915cf5cf81369 +refs/heads/master: c1f99c215c58111629984a49ba87b2b145dd1f5b diff --git a/trunk/arch/arm/mach-pxa/include/mach/pxafb.h b/trunk/arch/arm/mach-pxa/include/mach/pxafb.h index cb44410cd456..4201a889ff4e 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/trunk/arch/arm/mach-pxa/include/mach/pxafb.h @@ -95,6 +95,10 @@ struct pxafb_mode_info { * in pxa27x and pxa3xx, initialize them to the same value or * the larger one will be used * 3. same to {rd,wr}_pulse_width + * + * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity + * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 + * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD */ unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ diff --git a/trunk/drivers/video/pxafb.c b/trunk/drivers/video/pxafb.c index 62d2dd0c1fa1..d6de84b42036 100644 --- a/trunk/drivers/video/pxafb.c +++ b/trunk/drivers/video/pxafb.c @@ -760,7 +760,9 @@ static void setup_smart_timing(struct pxafb_info *fbi, LCCR1_HorSnchWdth(__smart_timing(t3, lclk)); fbi->reg_lccr2 = LCCR2_DisHght(var->yres); - fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk)); + fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0; + fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; /* FIXME: make this configurable */ fbi->reg_cmdcr = 1;