From e1b490ce9c1f2a644050ac0d5cf519d9e0b068b2 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 25 Nov 2008 21:22:02 +0900 Subject: [PATCH] --- yaml --- r: 120063 b: refs/heads/master c: 0d5bbe0bc2583c4dc06ea00adccf07c3acd1481d h: refs/heads/master i: 120061: 2733b037ee0594742f74586661119e5d7dce74a3 120059: 809530a90053e495b199d3c8a2a663b470330961 120055: 94800b12da10f5560827af34a000a88528aa8d79 120047: 029bcbc42f5705bab49e8f334d62073d6cb5d479 120031: c76e93b0013e74e27905974c006e5876b20fce1e 119999: 161b27bd93f471f294c638cab2c8bb782ea91047 119935: 94459640674d4f8a430cf240512800792be3b7c9 119807: 0585e6c3f746da146717fef6805caa7566188d0c v: v3 --- [refs] | 2 +- trunk/arch/sh/include/asm/bitops-op32.h | 142 ++++++++++++++++++++++++ trunk/arch/sh/include/asm/bitops.h | 3 + 3 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 trunk/arch/sh/include/asm/bitops-op32.h diff --git a/[refs] b/[refs] index 5ac003c3bff5..4410bd6ab2ee 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8bcc5c1c332af97ba731f99fda780a47911e476f +refs/heads/master: 0d5bbe0bc2583c4dc06ea00adccf07c3acd1481d diff --git a/trunk/arch/sh/include/asm/bitops-op32.h b/trunk/arch/sh/include/asm/bitops-op32.h new file mode 100644 index 000000000000..f0ae7e9218e0 --- /dev/null +++ b/trunk/arch/sh/include/asm/bitops-op32.h @@ -0,0 +1,142 @@ +#ifndef __ASM_SH_BITOPS_OP32_H +#define __ASM_SH_BITOPS_OP32_H + +/* + * The bit modifying instructions on SH-2A are only capable of working + * with a 3-bit immediate, which signifies the shift position for the bit + * being worked on. + */ +#if defined(__BIG_ENDIAN) +#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) +#define BYTE_NUMBER(nr) ((nr ^ BITOP_LE_SWIZZLE) / BITS_PER_BYTE) +#define BYTE_OFFSET(nr) ((nr ^ BITOP_LE_SWIZZLE) % BITS_PER_BYTE) +#else +#define BYTE_NUMBER(nr) ((nr) / BITS_PER_BYTE) +#define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE) +#endif + +#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr)) + +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + __asm__ __volatile__ ( + "bset.b %1, @(%O2,%0) ! __set_bit\n\t" + : "+r" (addr) + : "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr)) + : "t", "memory" + ); + } else { + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; + } +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + __asm__ __volatile__ ( + "bclr.b %1, @(%O2,%0) ! __clear_bit\n\t" + : "+r" (addr) + : "i" (BYTE_OFFSET(nr)), + "i" (BYTE_NUMBER(nr)) + : "t", "memory" + ); + } else { + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; + } +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + if (IS_IMMEDIATE(nr)) { + __asm__ __volatile__ ( + "bxor.b %1, @(%O2,%0) ! __change_bit\n\t" + : "+r" (addr) + : "i" (BYTE_OFFSET(nr)), + "i" (BYTE_NUMBER(nr)) + : "t", "memory" + ); + } else { + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; + } +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* __ASM_SH_BITOPS_OP32_H */ diff --git a/trunk/arch/sh/include/asm/bitops.h b/trunk/arch/sh/include/asm/bitops.h index 9b141e04d10b..ebe595b7ab1f 100644 --- a/trunk/arch/sh/include/asm/bitops.h +++ b/trunk/arch/sh/include/asm/bitops.h @@ -13,6 +13,9 @@ #ifdef CONFIG_GUSA_RB #include +#elif defined(CONFIG_CPU_SH2A) +#include +#include #elif defined(CONFIG_CPU_SH4A) #include #else