From e21af9639ae7e8c49b2f75a4ba74df8f4d2a3c56 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 9 Nov 2012 16:58:11 -0700
Subject: [PATCH] --- yaml --- r: 342267 b: refs/heads/master c:
 20ffbd7d6b357ee2f8a607c63805fb2c1f78effb h: refs/heads/master i:   342265:
 1159e2e6be8719bc34da86505e359a6eea4fcaa9   342263:
 824f34a475053eb541ad3cef2dd45e2c78757eaf v: v3

---
 [refs]                                      |  2 +-
 trunk/arch/arm/boot/dts/tegra20-harmony.dts | 20 ++++++++++++++++----
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/[refs] b/[refs]
index cb19ef33a890..5fdf2411cdd9 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ed39097c2ad97688d2734600ca20b7d66c311b92
+refs/heads/master: 20ffbd7d6b357ee2f8a607c63805fb2c1f78effb
diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts
index a3f2f383c049..43eb72af8948 100644
--- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,6 +10,18 @@
 		reg = <0x00000000 0x40000000>;
 	};
 
+	host1x {
+		hdmi {
+			status = "okay";
+
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
 	pinmux {
 		pinctrl-names = "default";
 		pinctrl-0 = <&state_default>;
@@ -262,9 +274,9 @@
 		};
 	};
 
-	i2c@7000c400 {
+	hdmi_ddc: i2c@7000c400 {
 		status = "okay";
-		clock-frequency = <400000>;
+		clock-frequency = <100000>;
 	};
 
 	i2c@7000c500 {
@@ -369,13 +381,13 @@
 					regulator-max-microvolt = <1800000>;
 				};
 
-				ldo7 {
+				hdmi_vdd_reg: ldo7 {
 					regulator-name = "vdd_ldo7,avdd_hdmi";
 					regulator-min-microvolt = <3300000>;
 					regulator-max-microvolt = <3300000>;
 				};
 
-				ldo8 {
+				hdmi_pll_reg: ldo8 {
 					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;