From e228636fd9aca049b45944ebe2a76f802b1a5359 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Wed, 2 Feb 2011 17:40:58 +0100 Subject: [PATCH] --- yaml --- r: 234425 b: refs/heads/master c: 69d8e1e8ac0a7d829f1c0fd5bd07eb3022d9a1a0 h: refs/heads/master i: 234423: 82a7a1c2ea435ec3d81ac131c33bcd719fec16cb v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/cpu/perfctr-watchdog.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 1d0e037db5ad..6d5bd3e4fbd0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 41bf498949a263fa0b2d32524b89d696ac330e94 +refs/heads/master: 69d8e1e8ac0a7d829f1c0fd5bd07eb3022d9a1a0 diff --git a/trunk/arch/x86/kernel/cpu/perfctr-watchdog.c b/trunk/arch/x86/kernel/cpu/perfctr-watchdog.c index d5a236615501..966512b2cacf 100644 --- a/trunk/arch/x86/kernel/cpu/perfctr-watchdog.c +++ b/trunk/arch/x86/kernel/cpu/perfctr-watchdog.c @@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) /* returns the bit offset of the performance counter register */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: + if (msr >= MSR_F15H_PERF_CTR) + return (msr - MSR_F15H_PERF_CTR) >> 1; return msr - MSR_K7_PERFCTR0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) @@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) /* returns the bit offset of the event selection register */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: + if (msr >= MSR_F15H_PERF_CTL) + return (msr - MSR_F15H_PERF_CTL) >> 1; return msr - MSR_K7_EVNTSEL0; case X86_VENDOR_INTEL: if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))