diff --git a/[refs] b/[refs] index 365ac7a68d77..54640087027b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bf049ded36b2178e80bb9f227d4490714d838c11 +refs/heads/master: 3c76a8a95daeecd881718f88324041f6a5faab86 diff --git a/trunk/CREDITS b/trunk/CREDITS index afaa7cec6ea5..78163cb3eb6a 100644 --- a/trunk/CREDITS +++ b/trunk/CREDITS @@ -1510,14 +1510,6 @@ D: Natsemi ethernet D: Cobalt Networks (x86) support D: This-and-That -N: Mark M. Hoffman -E: mhoffman@lightlink.com -D: asb100, lm93 and smsc47b397 hardware monitoring drivers -D: hwmon subsystem core -D: hwmon subsystem maintainer -D: i2c-sis96x and i2c-stub SMBus drivers -S: USA - N: Dirk Hohndel E: hohndel@suse.de D: The XFree86[tm] Project diff --git a/trunk/Documentation/arm/sunxi/clocks.txt b/trunk/Documentation/arm/sunxi/clocks.txt deleted file mode 100644 index e09a88aa3136..000000000000 --- a/trunk/Documentation/arm/sunxi/clocks.txt +++ /dev/null @@ -1,56 +0,0 @@ -Frequently asked questions about the sunxi clock system -======================================================= - -This document contains useful bits of information that people tend to ask -about the sunxi clock system, as well as accompanying ASCII art when adequate. - -Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the - system? - -A: The 24MHz oscillator allows gating to save power. Indeed, if gated - carelessly the system would stop functioning, but with the right - steps, one can gate it and keep the system running. Consider this - simplified suspend example: - - While the system is operational, you would see something like - - 24MHz 32kHz - | - PLL1 - \ - \_ CPU Mux - | - [CPU] - - When you are about to suspend, you switch the CPU Mux to the 32kHz - oscillator: - - 24Mhz 32kHz - | | - PLL1 | - / - CPU Mux _/ - | - [CPU] - - Finally you can gate the main oscillator - - 32kHz - | - | - / - CPU Mux _/ - | - [CPU] - -Q: Were can I learn more about the sunxi clocks? - -A: The linux-sunxi wiki contains a page documenting the clock registers, - you can find it at - - http://linux-sunxi.org/A10/CCM - - The authoritative source for information at this time is the ccmu driver - released by Allwinner, you can find it at - - https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu diff --git a/trunk/Documentation/clk.txt b/trunk/Documentation/clk.txt index 4274a546eb57..1943fae014fd 100644 --- a/trunk/Documentation/clk.txt +++ b/trunk/Documentation/clk.txt @@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw) }; Below is a matrix detailing which clk_ops are mandatory based upon the -hardware capabilities of that clock. A cell marked as "y" means +hardware capbilities of that clock. A cell marked as "y" means mandatory, a cell marked as "n" implies that either including that -callback is invalid or otherwise unnecessary. Empty cells are either +callback is invalid or otherwise uneccesary. Empty cells are either optional or must be evaluated on a case-by-case basis. clock hardware characteristics diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/trunk/Documentation/devicetree/bindings/arm/omap/l3-noc.txt index c0105de55cbd..6888a5efc860 100644 --- a/trunk/Documentation/devicetree/bindings/arm/omap/l3-noc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/omap/l3-noc.txt @@ -6,7 +6,6 @@ provided by Arteris. Required properties: - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family Should be "ti,omap4-l3-noc" for OMAP4 family -- reg: Contains L3 register address range for each noc domain. - ti,hwmods: "l3_main_1", ... One hwmod for each noc domain. Examples: diff --git a/trunk/Documentation/devicetree/bindings/arm/omap/timer.txt b/trunk/Documentation/devicetree/bindings/arm/omap/timer.txt index d02e27c764ec..8732d4d41f8b 100644 --- a/trunk/Documentation/devicetree/bindings/arm/omap/timer.txt +++ b/trunk/Documentation/devicetree/bindings/arm/omap/timer.txt @@ -1,20 +1,7 @@ OMAP Timer bindings Required properties: -- compatible: Should be set to one of the below. Please note that - OMAP44xx devices have timer instances that are 100% - register compatible with OMAP3xxx devices as well as - newer timers that are not 100% register compatible. - So for OMAP44xx devices timer instances may use - different compatible strings. - - ti,omap2420-timer (applicable to OMAP24xx devices) - ti,omap3430-timer (applicable to OMAP3xxx/44xx devices) - ti,omap4430-timer (applicable to OMAP44xx devices) - ti,omap5430-timer (applicable to OMAP543x devices) - ti,am335x-timer (applicable to AM335x devices) - ti,am335x-timer-1ms (applicable to AM335x devices) - +- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. - reg: Contains timer register address range (base address and length). - interrupts: Contains the interrupt information for the timer. The @@ -35,7 +22,7 @@ Optional properties: Example: timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48304000 0x400>; interrupts = <95>; ti,hwmods = "timer12" diff --git a/trunk/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/trunk/Documentation/devicetree/bindings/arm/samsung/sysreg.txt deleted file mode 100644 index 5039c0a12f55..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/samsung/sysreg.txt +++ /dev/null @@ -1,7 +0,0 @@ -SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) - -Properties: - - name : should be 'sysreg'; - - compatible : should contain "samsung,-sysreg", "syscon"; - For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon"; - - reg : offset and length of the register set. diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index 1608a54e90e1..b5846e21cc2e 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -1,84 +1,19 @@ NVIDIA Tegra Power Management Controller (PMC) -The PMC block interacts with an external Power Management Unit. The PMC -mostly controls the entry and exit of the system from different sleep -modes. It provides power-gating controllers for SoC and CPU power-islands. - -Required properties: +Properties: - name : Should be pmc - compatible : Should contain "nvidia,tegra-pmc". - reg : Offset and length of the register set for the device -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pclk" (The Tegra clock of that name), - "clk32k_in" (The 32KHz clock input to Tegra). - -Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. The PMU is an external Power Management Unit, whose interrupt output signal is fed into the PMC. This signal is optionally inverted, and then fed into the ARM GIC. The PMC is not involved in the detection or handling of this interrupt signal, merely its inversion. -- nvidia,suspend-mode : The suspend mode that the platform should use. - Valid values are 0, 1 and 2: - 0 (LP0): CPU + Core voltage off and DRAM in self-refresh - 1 (LP1): CPU voltage off and DRAM in self-refresh - 2 (LP2): CPU voltage off -- nvidia,core-power-req-active-high : Boolean, core power request active-high -- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high -- nvidia,combined-power-req : Boolean, combined power request for CPU & Core -- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) - is enabled. - -Required properties when nvidia,suspend-mode is specified: -- nvidia,cpu-pwr-good-time : CPU power good time in uS. -- nvidia,cpu-pwr-off-time : CPU power off time in uS. -- nvidia,core-pwr-good-time : - Core power good time in uS. -- nvidia,core-pwr-off-time : Core power off time in uS. - -Required properties when nvidia,suspend-mode=<0>: -- nvidia,lp0-vec : Starting address and length of LP0 vector - The LP0 vector contains the warm boot code that is executed by AVP when - resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 - processor and always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed from the deep - sleep mode, the warm boot code will restore some PLLs, clocks and then - bring up CPU0 for resuming the system. Example: -/ SoC dts including file pmc@7000f400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,lp0-vec = <0xbdffd000 0x2000>; -}; - -/ Tegra board dts file -{ - ... - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - ... }; diff --git a/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt deleted file mode 100644 index 028b493e97ff..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt +++ /dev/null @@ -1,22 +0,0 @@ -Binding for the axi-clkgen clock generator - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "adi,axi-clkgen". -- #clock-cells : from common clock binding; Should always be set to 0. -- reg : Address and length of the axi-clkgen register set. -- clocks : Phandle and clock specifier for the parent clock. - -Optional properties: -- clock-output-names : From common clock binding. - -Example: - clock@0xff000000 { - compatible = "adi,axi-clkgen"; - #clock-cells = <0>; - reg = <0xff000000 0x1000>; - clocks = <&osc 1>; - }; diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt deleted file mode 100644 index ea5e26f16aec..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ /dev/null @@ -1,288 +0,0 @@ -* Samsung Exynos4 Clock Controller - -The Exynos4 clock controller generates and supplies clock to various controllers -within the Exynos4 SoC. The clock binding described here is applicable to all -SoC's in the Exynos4 family. - -Required Properties: - -- comptible: should be one of the following. - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. Some of the clocks are available only on a particular -Exynos4 SoC and this is specified where applicable. - - - [Core Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - xxti 1 - xusbxti 2 - fin_pll 3 - fout_apll 4 - fout_mpll 5 - fout_epll 6 - fout_vpll 7 - sclk_apll 8 - sclk_mpll 9 - sclk_epll 10 - sclk_vpll 11 - arm_clk 12 - aclk200 13 - aclk100 14 - aclk160 15 - aclk133 16 - mout_mpll_user_t 17 Exynos4x12 - mout_mpll_user_c 18 Exynos4x12 - mout_core 19 - mout_apll 20 - - - [Clock Gate for Special Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - sclk_fimc0 128 - sclk_fimc1 129 - sclk_fimc2 130 - sclk_fimc3 131 - sclk_cam0 132 - sclk_cam1 133 - sclk_csis0 134 - sclk_csis1 135 - sclk_hdmi 136 - sclk_mixer 137 - sclk_dac 138 - sclk_pixel 139 - sclk_fimd0 140 - sclk_mdnie0 141 Exynos4412 - sclk_mdnie_pwm0 12 142 Exynos4412 - sclk_mipi0 143 - sclk_audio0 144 - sclk_mmc0 145 - sclk_mmc1 146 - sclk_mmc2 147 - sclk_mmc3 148 - sclk_mmc4 149 - sclk_sata 150 Exynos4210 - sclk_uart0 151 - sclk_uart1 152 - sclk_uart2 153 - sclk_uart3 154 - sclk_uart4 155 - sclk_audio1 156 - sclk_audio2 157 - sclk_spdif 158 - sclk_spi0 159 - sclk_spi1 160 - sclk_spi2 161 - sclk_slimbus 162 - sclk_fimd1 163 Exynos4210 - sclk_mipi1 164 Exynos4210 - sclk_pcm1 165 - sclk_pcm2 166 - sclk_i2s1 167 - sclk_i2s2 168 - sclk_mipihsi 169 Exynos4412 - sclk_mfc 170 - sclk_pcm0 171 - sclk_g3d 172 - sclk_pwm_isp 173 Exynos4x12 - sclk_spi0_isp 174 Exynos4x12 - sclk_spi1_isp 175 Exynos4x12 - sclk_uart_isp 176 Exynos4x12 - - [Peripheral Clock Gates] - - Clock ID SoC (if specific) - ----------------------------------------------- - - fimc0 256 - fimc1 257 - fimc2 258 - fimc3 259 - csis0 260 - csis1 261 - jpeg 262 - smmu_fimc0 263 - smmu_fimc1 264 - smmu_fimc2 265 - smmu_fimc3 266 - smmu_jpeg 267 - vp 268 - mixer 269 - tvenc 270 Exynos4210 - hdmi 271 - smmu_tv 272 - mfc 273 - smmu_mfcl 274 - smmu_mfcr 275 - g3d 276 - g2d 277 Exynos4210 - rotator 278 Exynos4210 - mdma 279 Exynos4210 - smmu_g2d 280 Exynos4210 - smmu_rotator 281 Exynos4210 - smmu_mdma 282 Exynos4210 - fimd0 283 - mie0 284 - mdnie0 285 Exynos4412 - dsim0 286 - smmu_fimd0 287 - fimd1 288 Exynos4210 - mie1 289 Exynos4210 - dsim1 290 Exynos4210 - smmu_fimd1 291 Exynos4210 - pdma0 292 - pdma1 293 - pcie_phy 294 - sata_phy 295 Exynos4210 - tsi 296 - sdmmc0 297 - sdmmc1 298 - sdmmc2 299 - sdmmc3 300 - sdmmc4 301 - sata 302 Exynos4210 - sromc 303 - usb_host 304 - usb_device 305 - pcie 306 - onenand 307 - nfcon 308 - smmu_pcie 309 - gps 310 - smmu_gps 311 - uart0 312 - uart1 313 - uart2 314 - uart3 315 - uart4 316 - i2c0 317 - i2c1 318 - i2c2 319 - i2c3 320 - i2c4 321 - i2c5 322 - i2c6 323 - i2c7 324 - i2c_hdmi 325 - tsadc 326 - spi0 327 - spi1 328 - spi2 329 - i2s1 330 - i2s2 331 - pcm0 332 - i2s0 333 - pcm1 334 - pcm2 335 - pwm 336 - slimbus 337 - spdif 338 - ac97 339 - modemif 340 - chipid 341 - sysreg 342 - hdmi_cec 343 - mct 344 - wdt 345 - rtc 346 - keyif 347 - audss 348 - mipi_hsi 349 Exynos4210 - mdma2 350 Exynos4210 - pixelasyncm0 351 - pixelasyncm1 352 - fimc_lite0 353 Exynos4x12 - fimc_lite1 354 Exynos4x12 - ppmuispx 355 Exynos4x12 - ppmuispmx 356 Exynos4x12 - fimc_isp 357 Exynos4x12 - fimc_drc 358 Exynos4x12 - fimc_fd 359 Exynos4x12 - mcuisp 360 Exynos4x12 - gicisp 361 Exynos4x12 - smmu_isp 362 Exynos4x12 - smmu_drc 363 Exynos4x12 - smmu_fd 364 Exynos4x12 - smmu_lite0 365 Exynos4x12 - smmu_lite1 366 Exynos4x12 - mcuctl_isp 367 Exynos4x12 - mpwm_isp 368 Exynos4x12 - i2c0_isp 369 Exynos4x12 - i2c1_isp 370 Exynos4x12 - mtcadc_isp 371 Exynos4x12 - pwm_isp 372 Exynos4x12 - wdt_isp 373 Exynos4x12 - uart_isp 374 Exynos4x12 - asyncaxim 375 Exynos4x12 - smmu_ispcx 376 Exynos4x12 - spi0_isp 377 Exynos4x12 - spi1_isp 378 Exynos4x12 - pwm_isp_sclk 379 Exynos4x12 - spi0_isp_sclk 380 Exynos4x12 - spi1_isp_sclk 381 Exynos4x12 - uart_isp_sclk 382 Exynos4x12 - - [Mux Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - mout_fimc0 384 - mout_fimc1 385 - mout_fimc2 386 - mout_fimc3 387 - mout_cam0 388 - mout_cam1 389 - mout_csis0 390 - mout_csis1 391 - mout_g3d0 392 - mout_g3d1 393 - mout_g3d 394 - aclk400_mcuisp 395 Exynos4x12 - - [Div Clocks] - - Clock ID SoC (if specific) - ----------------------------------------------- - - div_isp0 450 Exynos4x12 - div_isp1 451 Exynos4x12 - div_mcuisp0 452 Exynos4x12 - div_mcuisp1 453 Exynos4x12 - div_aclk200 454 Exynos4x12 - div_aclk400_mcuisp 455 Exynos4x12 - - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@0x10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt deleted file mode 100644 index 781a6276adf7..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ /dev/null @@ -1,177 +0,0 @@ -* Samsung Exynos5250 Clock Controller - -The Exynos5250 clock controller generates and supplies clock to various -controllers within the Exynos5250 SoC. - -Required Properties: - -- comptible: should be one of the following. - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. - - - [Core Clocks] - - Clock ID - ---------------------------- - - fin_pll 1 - - [Clock Gate for Special Clocks] - - Clock ID - ---------------------------- - - sclk_cam_bayer 128 - sclk_cam0 129 - sclk_cam1 130 - sclk_gscl_wa 131 - sclk_gscl_wb 132 - sclk_fimd1 133 - sclk_mipi1 134 - sclk_dp 135 - sclk_hdmi 136 - sclk_pixel 137 - sclk_audio0 138 - sclk_mmc0 139 - sclk_mmc1 140 - sclk_mmc2 141 - sclk_mmc3 142 - sclk_sata 143 - sclk_usb3 144 - sclk_jpeg 145 - sclk_uart0 146 - sclk_uart1 147 - sclk_uart2 148 - sclk_uart3 149 - sclk_pwm 150 - sclk_audio1 151 - sclk_audio2 152 - sclk_spdif 153 - sclk_spi0 154 - sclk_spi1 155 - sclk_spi2 156 - - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - gscl0 256 - gscl1 257 - gscl2 258 - gscl3 259 - gscl_wa 260 - gscl_wb 261 - smmu_gscl0 262 - smmu_gscl1 263 - smmu_gscl2 264 - smmu_gscl3 265 - mfc 266 - smmu_mfcl 267 - smmu_mfcr 268 - rotator 269 - jpeg 270 - mdma1 271 - smmu_rotator 272 - smmu_jpeg 273 - smmu_mdma1 274 - pdma0 275 - pdma1 276 - sata 277 - usbotg 278 - mipi_hsi 279 - sdmmc0 280 - sdmmc1 281 - sdmmc2 282 - sdmmc3 283 - sromc 284 - usb2 285 - usb3 286 - sata_phyctrl 287 - sata_phyi2c 288 - uart0 289 - uart1 290 - uart2 291 - uart3 292 - uart4 293 - i2c0 294 - i2c1 295 - i2c2 296 - i2c3 297 - i2c4 298 - i2c5 299 - i2c6 300 - i2c7 301 - i2c_hdmi 302 - adc 303 - spi0 304 - spi1 305 - spi2 306 - i2s1 307 - i2s2 308 - pcm1 309 - pcm2 310 - pwm 311 - spdif 312 - ac97 313 - hsi2c0 314 - hsi2c1 315 - hs12c2 316 - hs12c3 317 - chipid 318 - sysreg 319 - pmu 320 - cmu_top 321 - cmu_core 322 - cmu_mem 323 - tzpc0 324 - tzpc1 325 - tzpc2 326 - tzpc3 327 - tzpc4 328 - tzpc5 329 - tzpc6 330 - tzpc7 331 - tzpc8 332 - tzpc9 333 - hdmi_cec 334 - mct 335 - wdt 336 - rtc 337 - tmu 338 - fimd1 339 - mie1 340 - dsim0 341 - dp 342 - mixer 343 - hdmi 345 - -Example 1: An example of a clock controller node is listed below. - - clock: clock-controller@0x10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; - }; - -Example 2: UART controller node that consumes the clock generated by the clock - controller. Refer to the standard clock bindings for information - about 'clocks' and 'clock-names' property. - - serial@13820000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13820000 0x100>; - interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; - clock-names = "uart", "clk_uart_baud0"; - }; diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt deleted file mode 100644 index 4499e9966bc9..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Samsung Exynos5440 Clock Controller - -The Exynos5440 clock controller generates and supplies clock to various -controllers within the Exynos5440 SoC. - -Required Properties: - -- comptible: should be "samsung,exynos5440-clock". - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. - - - [Core Clocks] - - Clock ID - ---------------------------- - - xtal 1 - arm_clk 2 - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - spi_baud 16 - pb0_250 17 - pr0_250 18 - pr1_250 19 - b_250 20 - b_125 21 - b_200 22 - sata 23 - usb 24 - gmac0 25 - cs250 26 - pb0_250_o 27 - pr0_250_o 28 - pr1_250_o 29 - b_250_o 30 - b_125_o 31 - b_200_o 32 - sata_o 33 - usb_o 34 - gmac0_o 35 - cs250_o 36 - -Example: An example of a clock controller node is listed below. - - clock: clock-controller@0x10010000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x10000>; - #clock-cells = <1>; - }; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt deleted file mode 100644 index d6cb083b90a2..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ /dev/null @@ -1,303 +0,0 @@ -NVIDIA Tegra114 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra114-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the CAR. - - The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - registers. These IDs often match those in the CAR's RST_DEVICES registers, - but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - this case, those clocks are assigned IDs above 160 in order to highlight - this issue. Implementations that interpret these clock IDs as bit values - within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - explicitly handle these special cases. - - The balance of the clocks controlled by the CAR are assigned IDs of 160 and - above. - - 0 unassigned - 1 unassigned - 2 unassigned - 3 unassigned - 4 rtc - 5 timer - 6 uarta - 7 unassigned (register bit affects uartb and vfir) - 8 unassigned - 9 sdmmc2 - 10 unassigned (register bit affects spdif_in and spdif_out) - 11 i2s1 - 12 i2c1 - 13 ndflash - 14 sdmmc1 - 15 sdmmc4 - 16 unassigned - 17 pwm - 18 i2s2 - 19 epp - 20 unassigned (register bit affects vi and vi_sensor) - 21 2d - 22 usbd - 23 isp - 24 3d - 25 unassigned - 26 disp2 - 27 disp1 - 28 host1x - 29 vcp - 30 i2s0 - 31 unassigned - - 32 unassigned - 33 unassigned - 34 apbdma - 35 unassigned - 36 kbc - 37 unassigned - 38 unassigned - 39 unassigned (register bit affects fuse and fuse_burn) - 40 kfuse - 41 sbc1 - 42 nor - 43 unassigned - 44 sbc2 - 45 unassigned - 46 sbc3 - 47 i2c5 - 48 dsia - 49 unassigned - 50 mipi - 51 hdmi - 52 csi - 53 unassigned - 54 i2c2 - 55 uartc - 56 mipi-cal - 57 emc - 58 usb2 - 59 usb3 - 60 msenc - 61 vde - 62 bsea - 63 bsev - - 64 unassigned - 65 uartd - 66 unassigned - 67 i2c3 - 68 sbc4 - 69 sdmmc3 - 70 unassigned - 71 owr - 72 afi - 73 csite - 74 unassigned - 75 unassigned - 76 la - 77 trace - 78 soc_therm - 79 dtv - 80 ndspeed - 81 i2cslow - 82 dsib - 83 tsec - 84 unassigned - 85 unassigned - 86 unassigned - 87 unassigned - 88 unassigned - 89 xusb_host - 90 unassigned - 91 msenc - 92 csus - 93 unassigned - 94 unassigned - 95 unassigned (bit affects xusb_dev and xusb_dev_src) - - 96 unassigned - 97 unassigned - 98 unassigned - 99 mselect - 100 tsensor - 101 i2s3 - 102 i2s4 - 103 i2c4 - 104 sbc5 - 105 sbc6 - 106 d_audio - 107 apbif - 108 dam0 - 109 dam1 - 110 dam2 - 111 hda2codec_2x - 112 unassigned - 113 audio0_2x - 114 audio1_2x - 115 audio2_2x - 116 audio3_2x - 117 audio4_2x - 118 spdif_2x - 119 actmon - 120 extern1 - 121 extern2 - 122 extern3 - 123 unassigned - 124 unassigned - 125 hda - 126 unassigned - 127 se - - 128 hda2hdmi - 129 unassigned - 130 unassigned - 131 unassigned - 132 unassigned - 133 unassigned - 134 unassigned - 135 unassigned - 136 unassigned - 137 unassigned - 138 unassigned - 139 unassigned - 140 unassigned - 141 unassigned - 142 unassigned - 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, - xusb_host_src and xusb_ss_src) - 144 cilab - 145 cilcd - 146 cile - 147 dsialp - 148 dsiblp - 149 unassigned - 150 dds - 151 unassigned - 152 dp2 - 153 amx - 154 adx - 155 unassigned (bit affects dfll_ref and dfll_soc) - 156 xusb_ss - - 192 uartb - 193 vfir - 194 spdif_in - 195 spdif_out - 196 vi - 197 vi_sensor - 198 fuse - 199 fuse_burn - 200 clk_32k - 201 clk_m - 202 clk_m_div2 - 203 clk_m_div4 - 204 pll_ref - 205 pll_c - 206 pll_c_out1 - 207 pll_c2 - 208 pll_c3 - 209 pll_m - 210 pll_m_out1 - 211 pll_p - 212 pll_p_out1 - 213 pll_p_out2 - 214 pll_p_out3 - 215 pll_p_out4 - 216 pll_a - 217 pll_a_out0 - 218 pll_d - 219 pll_d_out0 - 220 pll_d2 - 221 pll_d2_out0 - 222 pll_u - 223 pll_u_480M - 224 pll_u_60M - 225 pll_u_48M - 226 pll_u_12M - 227 pll_x - 228 pll_x_out0 - 229 pll_re_vco - 230 pll_re_out - 231 pll_e_out0 - 232 spdif_in_sync - 233 i2s0_sync - 234 i2s1_sync - 235 i2s2_sync - 236 i2s3_sync - 237 i2s4_sync - 238 vimclk_sync - 239 audio0 - 240 audio1 - 241 audio2 - 242 audio3 - 243 audio4 - 244 spdif - 245 clk_out_1 - 246 clk_out_2 - 247 clk_out_3 - 248 blink - 252 xusb_host_src - 253 xusb_falcon_src - 254 xusb_fs_src - 255 xusb_ss_src - 256 xusb_dev_src - 257 xusb_dev - 258 xusb_hs_src - 259 sclk - 260 hclk - 261 pclk - 262 cclk_g - 263 cclk_lp - 264 dfll_ref - 265 dfll_soc - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra114-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car 58>; /* usb2 */ - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index e885680f6b45..0921fac73528 100644 --- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt @@ -120,8 +120,8 @@ Required properties : 90 clk_d 91 unassigned 92 sus - 93 cdev2 - 94 cdev1 + 93 cdev1 + 94 cdev2 95 unassigned 96 uart2 diff --git a/trunk/Documentation/devicetree/bindings/clock/sunxi.txt b/trunk/Documentation/devicetree/bindings/clock/sunxi.txt deleted file mode 100644 index 20b8479c2760..000000000000 --- a/trunk/Documentation/devicetree/bindings/clock/sunxi.txt +++ /dev/null @@ -1,44 +0,0 @@ -Device Tree Clock bindings for arch-sunxi - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "allwinner,sun4i-osc-clk" - for a gatable oscillator - "allwinner,sun4i-pll1-clk" - for the main PLL clock - "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock - "allwinner,sun4i-axi-clk" - for the AXI clock - "allwinner,sun4i-ahb-clk" - for the AHB clock - "allwinner,sun4i-apb0-clk" - for the APB0 clock - "allwinner,sun4i-apb1-clk" - for the APB1 clock - "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing - -Required properties for all clocks: -- reg : shall be the control register address for the clock. -- clocks : shall be the input parent clock(s) phandle for the clock -- #clock-cells : from common clock binding; shall be set to 0. - -For example: - -osc24M: osc24M@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; - reg = <0x01c20050 0x4>; - clocks = <&osc24M_fixed>; -}; - -pll1: pll1@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; -}; - -cpu: cpu@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>; -}; diff --git a/trunk/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/trunk/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt index a4873e5e3e36..ded0398d3bdc 100644 --- a/trunk/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt +++ b/trunk/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt @@ -3,58 +3,17 @@ Required properties: - compatible : Should be "fsl,-dma-apbh" or "fsl,-dma-apbx" - reg : Should contain registers location and length -- interrupts : Should contain the interrupt numbers of DMA channels. - If a channel is empty/reserved, 0 should be filled in place. -- #dma-cells : Must be <1>. The number cell specifies the channel ID. -- dma-channels : Number of channels supported by the DMA controller - -Optional properties: -- interrupt-names : Name of DMA channel interrupts Supported chips: imx23, imx28. Examples: - -dma_apbh: dma-apbh@80004000 { +dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; + reg = <0x80004000 2000>; }; -dma_apbx: dma-apbx@80024000 { +dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; -}; - -DMA clients connected to the MXS DMA controller must use the format -described in the dma.txt file. - -Examples: - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; + reg = <0x80024000 2000>; }; diff --git a/trunk/Documentation/devicetree/bindings/fb/mxsfb.txt b/trunk/Documentation/devicetree/bindings/fb/mxsfb.txt index 96ec5179c8a0..b41e5e52a676 100644 --- a/trunk/Documentation/devicetree/bindings/fb/mxsfb.txt +++ b/trunk/Documentation/devicetree/bindings/fb/mxsfb.txt @@ -5,16 +5,9 @@ Required properties: imx23 and imx28. - reg: Address and length of the register set for lcdif - interrupts: Should contain lcdif interrupts -- display : phandle to display node (see below for details) -* display node - -Required properties: -- bits-per-pixel : <16> for RGB565, <32> for RGB888/666. -- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>. - -Required sub-node: -- display-timings : Refer to binding doc display-timing.txt for details. +Optional properties: +- panel-enable-gpios : Should specify the gpio for panel enable Examples: @@ -22,28 +15,5 @@ lcdif@80030000 { compatible = "fsl,imx28-lcdif"; reg = <0x80030000 2000>; interrupts = <38 86>; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <164>; - hback-porch = <89>; - hsync-len = <10>; - vback-porch = <23>; - vfront-porch = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; + panel-enable-gpios = <&gpio3 30 0>; }; diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio-omap.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio-omap.txt index a56e3a53a360..bff51a2fee1e 100644 --- a/trunk/Documentation/devicetree/bindings/gpio/gpio-omap.txt +++ b/trunk/Documentation/devicetree/bindings/gpio/gpio-omap.txt @@ -5,12 +5,12 @@ Required properties: - "ti,omap2-gpio" for OMAP2 controllers - "ti,omap3-gpio" for OMAP3 controllers - "ti,omap4-gpio" for OMAP4 controllers -- gpio-controller : Marks the device node as a GPIO controller. - #gpio-cells : Should be two. - first cell is the pin number - second cell is used to specify optional parameters (unused) -- interrupt-controller: Mark the device node as an interrupt controller. +- gpio-controller : Marks the device node as a GPIO controller. - #interrupt-cells : Should be 2. +- interrupt-controller: Mark the device node as an interrupt controller The first cell is the GPIO number. The second cell is used to specify flags: bits[3:0] trigger type and level flags: @@ -29,8 +29,8 @@ Example: gpio4: gpio4 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; - gpio-controller; #gpio-cells = <2>; - interrupt-controller; + gpio-controller; #interrupt-cells = <2>; + interrupt-controller; }; diff --git a/trunk/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/trunk/Documentation/devicetree/bindings/gpu/samsung-g2d.txt deleted file mode 100644 index 2b14a940eb75..000000000000 --- a/trunk/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Samsung 2D Graphics Accelerator - -Required properties: - - compatible : value should be one among the following: - (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC - (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs - (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : G2D interrupt number to the CPU. - -Example: - g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - status = "disabled"; - }; diff --git a/trunk/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/trunk/Documentation/devicetree/bindings/i2c/i2c-mxs.txt index 4e1c8ac01eba..7a3fe9e5f4cb 100644 --- a/trunk/Documentation/devicetree/bindings/i2c/i2c-mxs.txt +++ b/trunk/Documentation/devicetree/bindings/i2c/i2c-mxs.txt @@ -3,13 +3,10 @@ Required properties: - compatible: Should be "fsl,-i2c" - reg: Should contain registers location and length -- interrupts: Should contain ERROR interrupt number +- interrupts: Should contain ERROR and DMA interrupts - clock-frequency: Desired I2C bus clock frequency in Hz. Only 100000Hz and 400000Hz modes are supported. -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and I2C DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". +- fsl,i2c-dma-channel: APBX DMA channel for the I2C Examples: @@ -18,8 +15,7 @@ i2c0: i2c@80058000 { #size-cells = <0>; compatible = "fsl,imx28-i2c"; reg = <0x80058000 2000>; - interrupts = <111>; + interrupts = <111 68>; clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; + fsl,i2c-dma-channel = <6>; }; diff --git a/trunk/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/trunk/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt deleted file mode 100644 index ef77cc7a0e46..000000000000 --- a/trunk/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt +++ /dev/null @@ -1,60 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. - -Required properties: -- compatible : should be: - "nvidia,tegra114-i2c" - "nvidia,tegra30-i2c" - "nvidia,tegra20-i2c" - "nvidia,tegra20-i2c-dvc" - Details of compatible are as follows: - nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C - controller. This only support master mode of I2C communication. Register - interface/offset and interrupts handling are different than generic I2C - controller. Driver of DVC I2C controller is only compatible with - "nvidia,tegra20-i2c-dvc". - nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support - master and slave mode of I2C communication. The i2c-tegra driver only - support master mode of I2C communication. Driver of I2C controller is - only compatible with "nvidia,tegra20-i2c". - nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is - very much similar to Tegra20 I2C controller with additional feature: - Continue Transfer Support. This feature helps to implement M_NO_START - as per I2C core API transfer flags. Driver of I2C controller is - compatible with "nvidia,tegra30-i2c" to enable the continue transfer - support. This is also compatible with "nvidia,tegra20-i2c" without - continue transfer support. - nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is - very much similar to Tegra30 I2C controller with some hardware - modification: - - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and - fast-clk. Tegra114 has only one clock source called as div-clk and - hence clock mechanism is changed in I2C controller. - - Tegra30/Tegra20 I2C controller has enabled per packet transfer by - default and there is no way to disable it. Tegra114 has this - interrupt disable by default and SW need to enable explicitly. - Due to above changes, Tegra114 I2C driver makes incompatible with - previous hardware driver. Hence, tegra114 I2C controller is compatible - with "nvidia,tegra114-i2c". -- reg: Should contain I2C controller registers physical address and length. -- interrupts: Should contain I2C controller interrupts. -- address-cells: Address cells for I2C device address. -- size-cells: Size of the I2C device address. -- clocks: Clock ID as per - Documentation/devicetree/bindings/clock/tegra.txt - for I2C controller. -- clock-names: Name of the clock: - Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk". - Tegra114 I2C controller: "div-clk". - -Example: - - i2c@7000c000 { - compatible = "nvidia,tegra20-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>, <&tegra_car 124>; - clock-names = "div-clk", "fast-clk"; - status = "disabled"; - }; diff --git a/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt b/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt index bf0182d8da25..67ec3d4ccc7f 100644 --- a/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -21,24 +21,3 @@ Required properties: - samsung,mfc-l : Base address of the second memory bank used by MFC for DMA contiguous memory allocation and its size. - -Optional properties: - - samsung,power-domain : power-domain property defined with a phandle - to respective power domain. - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - samsung,power-domain = <&pd_mfc>; -}; - -Board specific DT entry: - -codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; -}; diff --git a/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt b/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt index c3a14e0ad0ad..13b707b7355c 100644 --- a/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt +++ b/trunk/Documentation/devicetree/bindings/mfd/ab8500.txt @@ -13,6 +13,9 @@ Required parent device properties: 4 = active high level-sensitive 8 = active low level-sensitive +Optional parent device properties: +- reg : contains the PRCMU mailbox address for the AB8500 i2c port + The AB8500 consists of a large and varied group of sub-devices: Device IRQ Names Supply Names Description @@ -83,8 +86,9 @@ Non-standard child device properties: - stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic - stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580) -ab8500 { +ab8500@5 { compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ interrupts = <0 40 0x4>; interrupt-controller; #interrupt-cells = <2>; diff --git a/trunk/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/trunk/Documentation/devicetree/bindings/mmc/mxs-mmc.txt index 515addc20070..54949f6faede 100644 --- a/trunk/Documentation/devicetree/bindings/mmc/mxs-mmc.txt +++ b/trunk/Documentation/devicetree/bindings/mmc/mxs-mmc.txt @@ -9,19 +9,15 @@ and the properties used by the mxsmmc driver. Required properties: - compatible: Should be "fsl,-mmc". The supported chips include imx23 and imx28. -- interrupts: Should contain ERROR interrupt number -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and SSP DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". +- interrupts: Should contain ERROR and DMA interrupts +- fsl,ssp-dma-channel: APBH DMA channel for the SSP Examples: ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; reg = <0x80010000 2000>; - interrupts = <96>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; + interrupts = <96 82>; + fsl,ssp-dma-channel = <0>; bus-width = <8>; }; diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index 551b2a179d01..3fb3f9015365 100644 --- a/trunk/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/trunk/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -7,12 +7,10 @@ Required properties: - compatible : should be "fsl,-gpmi-nand" - reg : should contain registers location and length for gpmi and bch. - reg-names: Should contain the reg names "gpmi-nand" and "bch" - - interrupts : BCH interrupt number. - - interrupt-names : Should be "bch". - - dmas: DMA specifier, consisting of a phandle to DMA controller node - and GPMI DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. - - dma-names: Must be "rx-tx". + - interrupts : The first is the DMA interrupt number for GPMI. + The second is the BCH interrupt number. + - interrupt-names : The interrupt names "gpmi-dma", "bch"; + - fsl,gpmi-dma-channel : Should contain the dma channel it uses. Optional properties: - nand-on-flash-bbt: boolean to enable on flash bbt option if not @@ -29,10 +27,9 @@ gpmi-nand@8000c000 { #size-cells = <1>; reg = <0x8000c000 2000>, <0x8000a000 2000>; reg-names = "gpmi-nand", "bch"; - interrupts = <41>; - interrupt-names = "bch"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; + interrupts = <88>, <41>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; partition@0 { ... diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt index 3077370c89af..f7e8e8f4d9a3 100644 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt @@ -70,10 +70,6 @@ Optional subnode-properties: 0: Disable the internal pull-up 1: Enable the internal pull-up -Note that when enabling the pull-up, the internal pad keeper gets disabled. -Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up -will only disable the internal pad keeper. - Examples: pinctrl@80018000 { diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt index 05ffecb57103..b77a97c9101e 100644 --- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt +++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt @@ -2,11 +2,6 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-alc5632" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -61,7 +56,4 @@ sound { nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&alc5632>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt index ef1fe7358279..04b14cfb1f16 100644 --- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt +++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt @@ -2,11 +2,6 @@ NVIDIA Tegra audio complex for TrimSlice Required properties: - compatible : "nvidia,tegra-audio-trimslice" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller - nvidia,audio-codec : The phandle of the WM8903 audio codec @@ -16,6 +11,4 @@ sound { compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt index d14510613a7f..c4dd39ce6165 100644 --- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt +++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt @@ -2,11 +2,6 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm8753" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -55,8 +50,5 @@ sound { nvidia,i2s-controller = <&i2s1>; nvidia,audio-codec = <&wm8753>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt index 3bf722deb722..d5b0da8bf1d8 100644 --- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt +++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt @@ -2,11 +2,6 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm8903" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -72,8 +67,5 @@ sound { nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt index ad589b163639..be35d34e8b26 100644 --- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt +++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt @@ -2,11 +2,6 @@ NVIDIA Tegra audio complex Required properties: - compatible : "nvidia,tegra-audio-wm9712" -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "pll_a" (The Tegra clock of that name), - "pll_a_out0" (The Tegra clock of that name), - "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) - nvidia,model : The user-visible name of this sound complex. - nvidia,audio-routing : A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, @@ -53,7 +48,4 @@ sound { "Mic", "MIC1"; nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; diff --git a/trunk/Documentation/devicetree/bindings/spi/mxs-spi.txt b/trunk/Documentation/devicetree/bindings/spi/mxs-spi.txt index 3499b73293c2..e2e13957c2a4 100644 --- a/trunk/Documentation/devicetree/bindings/spi/mxs-spi.txt +++ b/trunk/Documentation/devicetree/bindings/spi/mxs-spi.txt @@ -3,11 +3,8 @@ Required properties: - compatible: Should be "fsl,-spi", where soc is "imx23" or "imx28" - reg: Offset and length of the register set for the device -- interrupts: Should contain SSP ERROR interrupt -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and SSP DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: Must be "rx-tx". +- interrupts: Should contain SSP interrupts (error irq first, dma irq second) +- fsl,ssp-dma-channel: APBX DMA channel for the SSP Optional properties: - clock-frequency : Input clock frequency to the SPI block in Hz. @@ -20,7 +17,6 @@ ssp0: ssp@80010000 { #size-cells = <0>; compatible = "fsl,imx28-spi"; reg = <0x80010000 0x2000>; - interrupts = <96>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; + interrupts = <96 82>; + fsl,ssp-dma-channel = <0>; }; diff --git a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt deleted file mode 100644 index cb47bfbcaeea..000000000000 --- a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt +++ /dev/null @@ -1,68 +0,0 @@ -Samsung's Multi Core Timer (MCT) - -The Samsung's Multi Core Timer (MCT) module includes two main blocks, the -global timer and CPU local timers. The global timer is a 64-bit free running -up-counter and can generate 4 interrupts when the counter reaches one of the -four preset counter values. The CPU local timers are 32-bit free running -down-counters and generate an interrupt when the counter expires. There is -one CPU local timer instantiated in MCT for every CPU in the system. - -Required properties: - -- compatible: should be "samsung,exynos4210-mct". - (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. - (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. - -- reg: base address of the mct controller and length of the address space - it occupies. - -- interrupts: the list of interrupts generated by the controller. The following - should be the order of the interrupts specified. The local timer interrupts - should be specified after the four global timer interrupts have been - specified. - - 0: Global Timer Interrupt 0 - 1: Global Timer Interrupt 1 - 2: Global Timer Interrupt 2 - 3: Global Timer Interrupt 3 - 4: Local Timer Interrupt 0 - 5: Local Timer Interrupt 1 - 6: .. - 7: .. - i: Local Timer Interrupt n - -Example 1: In this example, the system uses only the first global timer - interrupt generated by MCT and the remaining three global timer - interrupts are unused. Two local timer interrupts have been - specified. - - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, - <0 42 0>, <0 48 0>; - }; - -Example 2: In this example, the MCT global and local timer interrupts are - connected to two seperate interrupt controllers. Hence, an - interrupt-map is created to map the interrupts to the respective - interrupt controllers. - - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/trunk/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt index 2c00ec64628e..273a8d5b3300 100644 --- a/trunk/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt +++ b/trunk/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt @@ -5,18 +5,20 @@ Required properties: imx23 and imx28. - reg : Address and length of the register set for the device - interrupts : Should contain the auart interrupt numbers -- dmas: DMA specifier, consisting of a phandle to DMA controller node - and AUART DMA channel ID. - Refer to dma.txt and fsl-mxs-dma.txt for details. -- dma-names: "rx" for RX channel, "tx" for TX channel. + +Optional properties: +- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other + is for TX. If you add this property, it also means that you + will enable the DMA support for the auart. + Note: due to the hardware bug in imx23(see errata : 2836), + only the imx28 can enable the DMA support for the auart. Example: auart0: serial@8006a000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; - interrupts = <112>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; + interrupts = <112 70 71>; + fsl,auart-dma-channel = <8 9>; }; Note: Each auart port should have an alias correctly numbered in "aliases" diff --git a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt index 8f01cb190f25..1e1145ca4f3c 100644 --- a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -11,9 +11,6 @@ Required properties: - "nvidia,tegra20-uart" - "nxp,lpc3220-uart" - "ibm,qpace-nwp-serial" - - "altr,16550-FIFO32" - - "altr,16550-FIFO64" - - "altr,16550-FIFO128" - "serial" if the port type is unknown. - reg : offset and length of the register set for the device. - interrupts : should contain uart interrupt. diff --git a/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt b/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt deleted file mode 100644 index b3abde736017..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ /dev/null @@ -1,50 +0,0 @@ -Samsung Exynos SoC USB controller - -The USB devices interface with USB controllers on Exynos SOCs. -The device node has following properties. - -EHCI -Required properties: - - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 - EHCI controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - -Optional properties: - - samsung,vbus-gpio: if present, specifies the GPIO that - needs to be pulled up for the bus to be powered. - -Example: - - usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - samsung,vbus-gpio = <&gpx2 6 1 3 3>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - }; - -OHCI -Required properties: - - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 - OHCI companion controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - -Example: - usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - }; diff --git a/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt b/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt index abce25684abc..1ef0ce71f8fa 100644 --- a/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt +++ b/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt @@ -18,7 +18,6 @@ OMAP MUSB GLUE represents PERIPHERAL. - power : Should be "50". This signifies the controller can supply upto 100mA when operating in host mode. - - usb-phy : the phandle for the PHY device Optional properties: - ctrl-module : phandle of the control module this glue uses to write to diff --git a/trunk/Documentation/devicetree/bindings/video/samsung-fimd.txt b/trunk/Documentation/devicetree/bindings/video/samsung-fimd.txt deleted file mode 100644 index 778838a0336a..000000000000 --- a/trunk/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ /dev/null @@ -1,65 +0,0 @@ -Device-Tree bindings for Samsung SoC display controller (FIMD) - -FIMD (Fully Interactive Mobile Display) is the Display Controller for the -Samsung series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ - "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ - "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */ - "samsung,s5pc100-fimd"; /* for S5PC100 SoC */ - "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ - "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ - "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ - -- reg: physical base address and length of the FIMD registers set. - -- interrupt-parent: should be the phandle of the fimd controller's - parent interrupt controller. - -- interrupts: should contain a list of all FIMD IP block interrupts in the - order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- interrupt-names: should contain the interrupt names: "fifo", "vsync", - "lcd_sys", in the same order as they were listed in the interrupts - property. - -- pinctrl-0: pin control group to be used for this controller. - -- pinctrl-names: must contain a "default" entry. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: list of clock names sorted in the same order as the clocks - property. Must contain "sclk_fimd" and "fimd". - -Optional Properties: -- samsung,power-domain: a phandle to FIMD power domain node. - -Example: - -SoC specific DT entry: - - fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock 140>, <&clock 283>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - status = "disabled"; - }; - -Board specific DT entry: - - fimd@11c00000 { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - }; diff --git a/trunk/Documentation/hwmon/lm75 b/trunk/Documentation/hwmon/lm75 index 69af1c7db6b7..c91a1d15fa28 100644 --- a/trunk/Documentation/hwmon/lm75 +++ b/trunk/Documentation/hwmon/lm75 @@ -23,7 +23,7 @@ Supported chips: Datasheet: Publicly available at the Maxim website http://www.maxim-ic.com/ * Microchip (TelCom) TCN75 - Prefix: 'tcn75' + Prefix: 'lm75' Addresses scanned: none Datasheet: Publicly available at the Microchip website http://www.microchip.com/ diff --git a/trunk/Documentation/i2c/busses/i2c-diolan-u2c b/trunk/Documentation/i2c/busses/i2c-diolan-u2c index 0d6018c316c7..30fe4bb9a069 100644 --- a/trunk/Documentation/i2c/busses/i2c-diolan-u2c +++ b/trunk/Documentation/i2c/busses/i2c-diolan-u2c @@ -5,7 +5,7 @@ Supported adapters: Documentation: http://www.diolan.com/i2c/u2c12.html -Author: Guenter Roeck +Author: Guenter Roeck Description ----------- diff --git a/trunk/Documentation/input/alps.txt b/trunk/Documentation/input/alps.txt index e544c7ff8cfa..3262b6e4d686 100644 --- a/trunk/Documentation/input/alps.txt +++ b/trunk/Documentation/input/alps.txt @@ -3,26 +3,10 @@ ALPS Touchpad Protocol Introduction ------------ -Currently the ALPS touchpad driver supports five protocol versions in use by -ALPS touchpads, called versions 1, 2, 3, 4 and 5. - -Since roughly mid-2010 several new ALPS touchpads have been released and -integrated into a variety of laptops and netbooks. These new touchpads -have enough behavior differences that the alps_model_data definition -table, describing the properties of the different versions, is no longer -adequate. The design choices were to re-define the alps_model_data -table, with the risk of regression testing existing devices, or isolate -the new devices outside of the alps_model_data table. The latter design -choice was made. The new touchpad signatures are named: "Rushmore", -"Pinnacle", and "Dolphin", which you will see in the alps.c code. -For the purposes of this document, this group of ALPS touchpads will -generically be called "new ALPS touchpads". - -We experimented with probing the ACPI interface _HID (Hardware ID)/_CID -(Compatibility ID) definition as a way to uniquely identify the -different ALPS variants but there did not appear to be a 1:1 mapping. -In fact, it appeared to be an m:n mapping between the _HID and actual -hardware type. + +Currently the ALPS touchpad driver supports four protocol versions in use by +ALPS touchpads, called versions 1, 2, 3, and 4. Information about the various +protocol versions is contained in the following sections. Detection --------- @@ -36,13 +20,9 @@ If the E6 report is successful, the touchpad model is identified using the "E7 report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is matched against known models in the alps_model_data_array. -For older touchpads supporting protocol versions 3 and 4, the E7 report -model signature is always 73-02-64. To differentiate between these -versions, the response from the "Enter Command Mode" sequence must be -inspected as described below. - -The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but -seem to be better differentiated by the EC Command Mode response. +With protocol versions 3 and 4, the E7 report model signature is always +73-02-64. To differentiate between these versions, the response from the +"Enter Command Mode" sequence must be inspected as described below. Command Mode ------------ @@ -67,14 +47,6 @@ address of the register being read, and the third contains the value of the register. Registers are written by writing the value one nibble at a time using the same encoding used for addresses. -For the new ALPS touchpads, the EC command is used to enter command -mode. The response in the new ALPS touchpads is significantly different, -and more important in determining the behavior. This code has been -separated from the original alps_model_data table and put in the -alps_identify function. For example, there seem to be two hardware init -sequences for the "Dolphin" touchpads as determined by the second byte -of the EC response. - Packet Format ------------- @@ -215,28 +187,3 @@ There are several things worth noting here. well. So far no v4 devices with tracksticks have been encountered. - -ALPS Absolute Mode - Protocol Version 5 ---------------------------------------- -This is basically Protocol Version 3 but with different logic for packet -decode. It uses the same alps_process_touchpad_packet_v3 call with a -specialized decode_fields function pointer to correctly interpret the -packets. This appears to only be used by the Dolphin devices. - -For single-touch, the 6-byte packet format is: - - byte 0: 1 1 0 0 1 0 0 0 - byte 1: 0 x6 x5 x4 x3 x2 x1 x0 - byte 2: 0 y6 y5 y4 y3 y2 y1 y0 - byte 3: 0 M R L 1 m r l - byte 4: y10 y9 y8 y7 x10 x9 x8 x7 - byte 5: 0 z6 z5 z4 z3 z2 z1 z0 - -For mt, the format is: - - byte 0: 1 1 1 n3 1 n2 n1 x24 - byte 1: 1 y7 y6 y5 y4 y3 y2 y1 - byte 2: ? x2 x1 y12 y11 y10 y9 y8 - byte 3: 0 x23 x22 x21 x20 x19 x18 x17 - byte 4: 0 x9 x8 x7 x6 x5 x4 x3 - byte 5: 0 x16 x15 x14 x13 x12 x11 x10 diff --git a/trunk/Documentation/networking/ipvs-sysctl.txt b/trunk/Documentation/networking/ipvs-sysctl.txt index 9573d0c48c6e..f2a2488f1bf3 100644 --- a/trunk/Documentation/networking/ipvs-sysctl.txt +++ b/trunk/Documentation/networking/ipvs-sysctl.txt @@ -15,13 +15,6 @@ amemthresh - INTEGER enabled and the variable is automatically set to 2, otherwise the strategy is disabled and the variable is set to 1. -backup_only - BOOLEAN - 0 - disabled (default) - not 0 - enabled - - If set, disable the director function while the server is - in backup mode to avoid packet loops for DR/TUN methods. - conntrack - BOOLEAN 0 - disabled (default) not 0 - enabled diff --git a/trunk/Documentation/networking/tuntap.txt b/trunk/Documentation/networking/tuntap.txt index 949d5dcdd9a3..c0aab985bad9 100644 --- a/trunk/Documentation/networking/tuntap.txt +++ b/trunk/Documentation/networking/tuntap.txt @@ -105,83 +105,6 @@ Copyright (C) 1999-2000 Maxim Krasnyansky Proto [2 bytes] Raw protocol(IP, IPv6, etc) frame. - 3.3 Multiqueue tuntap interface: - - From version 3.8, Linux supports multiqueue tuntap which can uses multiple - file descriptors (queues) to parallelize packets sending or receiving. The - device allocation is the same as before, and if user wants to create multiple - queues, TUNSETIFF with the same device name must be called many times with - IFF_MULTI_QUEUE flag. - - char *dev should be the name of the device, queues is the number of queues to - be created, fds is used to store and return the file descriptors (queues) - created to the caller. Each file descriptor were served as the interface of a - queue which could be accessed by userspace. - - #include - #include - - int tun_alloc_mq(char *dev, int queues, int *fds) - { - struct ifreq ifr; - int fd, err, i; - - if (!dev) - return -1; - - memset(&ifr, 0, sizeof(ifr)); - /* Flags: IFF_TUN - TUN device (no Ethernet headers) - * IFF_TAP - TAP device - * - * IFF_NO_PI - Do not provide packet information - * IFF_MULTI_QUEUE - Create a queue of multiqueue device - */ - ifr.ifr_flags = IFF_TAP | IFF_NO_PI | IFF_MULTI_QUEUE; - strcpy(ifr.ifr_name, dev); - - for (i = 0; i < queues; i++) { - if ((fd = open("/dev/net/tun", O_RDWR)) < 0) - goto err; - err = ioctl(fd, TUNSETIFF, (void *)&ifr); - if (err) { - close(fd); - goto err; - } - fds[i] = fd; - } - - return 0; - err: - for (--i; i >= 0; i--) - close(fds[i]); - return err; - } - - A new ioctl(TUNSETQUEUE) were introduced to enable or disable a queue. When - calling it with IFF_DETACH_QUEUE flag, the queue were disabled. And when - calling it with IFF_ATTACH_QUEUE flag, the queue were enabled. The queue were - enabled by default after it was created through TUNSETIFF. - - fd is the file descriptor (queue) that we want to enable or disable, when - enable is true we enable it, otherwise we disable it - - #include - #include - - int tun_set_queue(int fd, int enable) - { - struct ifreq ifr; - - memset(&ifr, 0, sizeof(ifr)); - - if (enable) - ifr.ifr_flags = IFF_ATTACH_QUEUE; - else - ifr.ifr_flags = IFF_DETACH_QUEUE; - - return ioctl(fd, TUNSETQUEUE, (void *)&ifr); - } - Universal TUN/TAP device driver Frequently Asked Question. 1. What platforms are supported by TUN/TAP driver ? diff --git a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt index 4499bd948860..ce6581c8ca26 100644 --- a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt +++ b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt @@ -912,7 +912,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. models depending on the codec chip. The list of available models is found in HD-Audio-Models.txt - The model name "generic" is treated as a special case. When this + The model name "genric" is treated as a special case. When this model is given, the driver uses the generic codec parser without "codec-patch". It's sometimes good for testing and debugging. diff --git a/trunk/Documentation/sound/alsa/seq_oss.html b/trunk/Documentation/sound/alsa/seq_oss.html index 9663b45f6fde..d9776cf60c07 100644 --- a/trunk/Documentation/sound/alsa/seq_oss.html +++ b/trunk/Documentation/sound/alsa/seq_oss.html @@ -285,7 +285,7 @@

7.2.4 Close Callback

The close callback is called when this device is closed by the -application. If any private data was allocated in open callback, it must +applicaion. If any private data was allocated in open callback, it must be released in the close callback. The deletion of ALSA port should be done here, too. This callback must not be NULL.

diff --git a/trunk/Documentation/trace/ftrace.txt b/trunk/Documentation/trace/ftrace.txt index a372304aef10..53d6a3c51d87 100644 --- a/trunk/Documentation/trace/ftrace.txt +++ b/trunk/Documentation/trace/ftrace.txt @@ -1873,7 +1873,7 @@ feature: status\input | 0 | 1 | else | --------------+------------+------------+------------+ - not allocated |(do nothing)| alloc+swap |(do nothing)| + not allocated |(do nothing)| alloc+swap | EINVAL | --------------+------------+------------+------------+ allocated | free | swap | clear | --------------+------------+------------+------------+ diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 74e58a4d035b..95616582c728 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -1338,6 +1338,12 @@ S: Maintained F: drivers/platform/x86/asus*.c F: drivers/platform/x86/eeepc*.c +ASUS ASB100 HARDWARE MONITOR DRIVER +M: "Mark M. Hoffman" +L: lm-sensors@lm-sensors.org +S: Maintained +F: drivers/hwmon/asb100.c + ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API M: Dan Williams W: http://sourceforge.net/projects/xscaleiop @@ -1461,12 +1467,6 @@ F: drivers/dma/at_hdmac.c F: drivers/dma/at_hdmac_regs.h F: include/linux/platform_data/dma-atmel.h -ATMEL I2C DRIVER -M: Ludovic Desroches -L: linux-i2c@vger.kernel.org -S: Supported -F: drivers/i2c/busses/i2c-at91.c - ATMEL ISI DRIVER M: Josh Wu L: linux-media@vger.kernel.org @@ -2629,7 +2629,7 @@ F: include/uapi/drm/ INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) M: Daniel Vetter -L: intel-gfx@lists.freedesktop.org +L: intel-gfx@lists.freedesktop.org (subscribers-only) L: dri-devel@lists.freedesktop.org T: git git://people.freedesktop.org/~danvet/drm-intel S: Supported @@ -3242,12 +3242,6 @@ F: Documentation/firmware_class/ F: drivers/base/firmware*.c F: include/linux/firmware.h -FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card) -M: Joshua Morris -M: Philip Kelleher -S: Maintained -F: drivers/block/rsxx/ - FLOPPY DRIVER M: Jiri Kosina T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git @@ -3857,7 +3851,7 @@ F: drivers/i2c/busses/i2c-ismt.c F: Documentation/i2c/busses/i2c-ismt I2C/SMBUS STUB DRIVER -M: Jean Delvare +M: "Mark M. Hoffman" L: linux-i2c@vger.kernel.org S: Maintained F: drivers/i2c/i2c-stub.c @@ -4011,22 +4005,6 @@ M: Stanislaw Gruszka S: Maintained F: drivers/usb/atm/ueagle-atm.c -INA209 HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/ina209 -F: Documentation/devicetree/bindings/i2c/ina209.txt -F: drivers/hwmon/ina209.c - -INA2XX HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/ina2xx -F: drivers/hwmon/ina2xx.c -F: include/linux/platform_data/ina2xx.h - INDUSTRY PACK SUBSYSTEM (IPACK) M: Samuel Iglesias Gonsalvez M: Jens Taprogge @@ -5120,15 +5098,6 @@ S: Maintained F: Documentation/hwmon/max6650 F: drivers/hwmon/max6650.c -MAX6697 HARDWARE MONITOR DRIVER -M: Guenter Roeck -L: lm-sensors@lm-sensors.org -S: Maintained -F: Documentation/hwmon/max6697 -F: Documentation/devicetree/bindings/i2c/max6697.txt -F: drivers/hwmon/max6697.c -F: include/linux/platform_data/max6697.h - MAXIRADIO FM RADIO RECEIVER DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org @@ -5653,14 +5622,6 @@ S: Maintained F: drivers/video/riva/ F: drivers/video/nvidia/ -NVM EXPRESS DRIVER -M: Matthew Wilcox -L: linux-nvme@lists.infradead.org -T: git git://git.infradead.org/users/willy/linux-nvme.git -S: Supported -F: drivers/block/nvme.c -F: include/linux/nvme.h - OMAP SUPPORT M: Tony Lindgren L: linux-omap@vger.kernel.org @@ -5689,7 +5650,7 @@ S: Maintained F: arch/arm/*omap*/*clock* OMAP POWER MANAGEMENT SUPPORT -M: Kevin Hilman +M: Kevin Hilman L: linux-omap@vger.kernel.org S: Maintained F: arch/arm/*omap*/*pm* @@ -5783,7 +5744,7 @@ F: arch/arm/*omap*/usb* OMAP GPIO DRIVER M: Santosh Shilimkar -M: Kevin Hilman +M: Kevin Hilman L: linux-omap@vger.kernel.org S: Maintained F: drivers/gpio/gpio-omap.c @@ -6215,7 +6176,7 @@ F: include/linux/power_supply.h F: drivers/power/ PNP SUPPORT -M: Rafael J. Wysocki +M: Adam Belay M: Bjorn Helgaas S: Maintained F: drivers/pnp/ @@ -6451,8 +6412,6 @@ F: Documentation/networking/LICENSE.qla3xxx F: drivers/net/ethernet/qlogic/qla3xxx.* QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER -M: Rajesh Borundia -M: Shahed Shaikh M: Jitendra Kalsaria M: Sony Chacko M: linux-driver@qlogic.com @@ -6557,6 +6516,12 @@ S: Maintained F: Documentation/blockdev/ramdisk.txt F: drivers/block/brd.c +RAMSAM DRIVER (IBM RamSan 70/80 PCI SSD Flash Card) +M: Joshua Morris +M: Philip Kelleher +S: Maintained +F: drivers/block/rsxx/ + RANDOM NUMBER DRIVER M: Theodore Ts'o" S: Maintained @@ -7173,7 +7138,7 @@ F: arch/arm/mach-s3c2410/bast-irq.c TI DAVINCI MACHINE SUPPORT M: Sekhar Nori -M: Kevin Hilman +M: Kevin Hilman L: davinci-linux-open-source@linux.davincidsp.com (moderated for non-subscribers) T: git git://gitorious.org/linux-davinci/linux-davinci.git Q: http://patchwork.kernel.org/project/linux-davinci/list/ @@ -7206,6 +7171,13 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/sis/sis900.* +SIS 96X I2C/SMBUS DRIVER +M: "Mark M. Hoffman" +L: linux-i2c@vger.kernel.org +S: Maintained +F: Documentation/i2c/busses/i2c-sis96x +F: drivers/i2c/busses/i2c-sis96x.c + SIS FRAMEBUFFER DRIVER M: Thomas Winischhofer W: http://www.winischhofer.net/linuxsisvga.shtml @@ -7283,7 +7255,7 @@ F: Documentation/hwmon/sch5627 F: drivers/hwmon/sch5627.c SMSC47B397 HARDWARE MONITOR DRIVER -M: Jean Delvare +M: "Mark M. Hoffman" L: lm-sensors@lm-sensors.org S: Maintained F: Documentation/hwmon/smsc47b397 @@ -7706,10 +7678,9 @@ F: include/linux/swiotlb.h SYNOPSYS ARC ARCHITECTURE M: Vineet Gupta +L: linux-snps-arc@vger.kernel.org S: Supported F: arch/arc/ -F: Documentation/devicetree/bindings/arc/ -F: drivers/tty/serial/arc-uart.c SYSV FILESYSTEM M: Christoph Hellwig diff --git a/trunk/Makefile b/trunk/Makefile index 58a165b02af1..a05ea42c5f18 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 9 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc2 NAME = Unicycling Gorilla # *DOCUMENTATION* diff --git a/trunk/arch/Kconfig b/trunk/arch/Kconfig index 1455579791ec..5a1779c93940 100644 --- a/trunk/arch/Kconfig +++ b/trunk/arch/Kconfig @@ -319,6 +319,13 @@ config ARCH_WANT_OLD_COMPAT_IPC select ARCH_WANT_COMPAT_IPC_PARSE_VERSION bool +config HAVE_VIRT_TO_BUS + bool + help + An architecture should select this if it implements the + deprecated interface virt_to_bus(). All new architectures + should probably not select this. + config HAVE_ARCH_SECCOMP_FILTER bool help diff --git a/trunk/arch/alpha/Kconfig b/trunk/arch/alpha/Kconfig index 8a33ba01301f..5833aa441481 100644 --- a/trunk/arch/alpha/Kconfig +++ b/trunk/arch/alpha/Kconfig @@ -9,7 +9,7 @@ config ALPHA select HAVE_PERF_EVENTS select HAVE_DMA_ATTRS select HAVE_GENERIC_HARDIRQS - select VIRT_TO_BUS + select HAVE_VIRT_TO_BUS select GENERIC_IRQ_PROBE select AUTO_IRQ_AFFINITY if SMP select GENERIC_IRQ_SHOW diff --git a/trunk/arch/arc/include/asm/dma-mapping.h b/trunk/arch/arc/include/asm/dma-mapping.h index 45b8e0cea176..31f77aec0823 100644 --- a/trunk/arch/arc/include/asm/dma-mapping.h +++ b/trunk/arch/arc/include/asm/dma-mapping.h @@ -126,7 +126,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int i; for_each_sg(sg, s, nents, i) - s->dma_address = dma_map_page(dev, sg_page(s), s->offset, + sg->dma_address = dma_map_page(dev, sg_page(s), s->offset, s->length, dir); return nents; diff --git a/trunk/arch/arc/include/asm/elf.h b/trunk/arch/arc/include/asm/elf.h index a26282857683..f4c8d36ebecb 100644 --- a/trunk/arch/arc/include/asm/elf.h +++ b/trunk/arch/arc/include/asm/elf.h @@ -72,4 +72,7 @@ extern int elf_check_arch(const struct elf32_hdr *); */ #define ELF_PLATFORM (NULL) +#define SET_PERSONALITY(ex) \ + set_personality(PER_LINUX | (current->personality & (~PER_MASK))) + #endif diff --git a/trunk/arch/arc/include/asm/entry.h b/trunk/arch/arc/include/asm/entry.h index eb2ae53187d9..23daa326fc9b 100644 --- a/trunk/arch/arc/include/asm/entry.h +++ b/trunk/arch/arc/include/asm/entry.h @@ -415,7 +415,7 @@ *-------------------------------------------------------------*/ .macro SAVE_ALL_EXCEPTION marker - st \marker, [sp, 8] /* orig_r8 */ + st \marker, [sp, 8] st r0, [sp, 4] /* orig_r0, needed only for sys calls */ /* Restore r9 used to code the early prologue */ diff --git a/trunk/arch/arc/include/asm/kgdb.h b/trunk/arch/arc/include/asm/kgdb.h index 4930957ca3d3..f3c4934f0ca9 100644 --- a/trunk/arch/arc/include/asm/kgdb.h +++ b/trunk/arch/arc/include/asm/kgdb.h @@ -13,7 +13,7 @@ #ifdef CONFIG_KGDB -#include +#include /* to ensure compatibility with Linux 2.6.35, we don't implement the get/set * register API yet */ @@ -53,7 +53,9 @@ enum arc700_linux_regnums { }; #else -#define kgdb_trap(regs, param) +static inline void kgdb_trap(struct pt_regs *regs, int param) +{ +} #endif #endif /* __ARC_KGDB_H__ */ diff --git a/trunk/arch/arc/include/asm/ptrace.h b/trunk/arch/arc/include/asm/ptrace.h index 6179de7e07c2..8ae783d20a81 100644 --- a/trunk/arch/arc/include/asm/ptrace.h +++ b/trunk/arch/arc/include/asm/ptrace.h @@ -123,7 +123,7 @@ static inline long regs_return_value(struct pt_regs *regs) #define orig_r8_IS_SCALL 0x0001 #define orig_r8_IS_SCALL_RESTARTED 0x0002 #define orig_r8_IS_BRKPT 0x0004 -#define orig_r8_IS_EXCPN 0x0008 +#define orig_r8_IS_EXCPN 0x0004 #define orig_r8_IS_IRQ1 0x0010 #define orig_r8_IS_IRQ2 0x0020 diff --git a/trunk/arch/arc/include/asm/syscalls.h b/trunk/arch/arc/include/asm/syscalls.h index dd785befe7fd..e53a5340ba4f 100644 --- a/trunk/arch/arc/include/asm/syscalls.h +++ b/trunk/arch/arc/include/asm/syscalls.h @@ -16,6 +16,8 @@ #include int sys_clone_wrapper(int, int, int, int, int); +int sys_fork_wrapper(void); +int sys_vfork_wrapper(void); int sys_cacheflush(uint32_t, uint32_t uint32_t); int sys_arc_settls(void *); int sys_arc_gettls(void); diff --git a/trunk/arch/arc/include/uapi/asm/ptrace.h b/trunk/arch/arc/include/uapi/asm/ptrace.h index 30333cec0fef..6afa4f702075 100644 --- a/trunk/arch/arc/include/uapi/asm/ptrace.h +++ b/trunk/arch/arc/include/uapi/asm/ptrace.h @@ -28,14 +28,14 @@ */ struct user_regs_struct { - struct { + struct scratch { long pad; long bta, lp_start, lp_end, lp_count; long status32, ret, blink, fp, gp; long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0; long sp; } scratch; - struct { + struct callee { long pad; long r25, r24, r23, r22, r21, r20; long r19, r18, r17, r16, r15, r14, r13; diff --git a/trunk/arch/arc/kernel/entry.S b/trunk/arch/arc/kernel/entry.S index 91eeab81f52d..ef6800ba2f03 100644 --- a/trunk/arch/arc/kernel/entry.S +++ b/trunk/arch/arc/kernel/entry.S @@ -452,7 +452,7 @@ tracesys: ; using ERET won't work since next-PC has already committed lr r12, [efa] GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11 - st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address + st r12, [r11, THREAD_FAULT_ADDR] ; PRE Sys Call Ptrace hook mov r0, sp ; pt_regs needed @@ -792,6 +792,31 @@ ARC_EXIT ret_from_fork ;################### Special Sys Call Wrappers ########################## +; TBD: call do_fork directly from here +ARC_ENTRY sys_fork_wrapper + SAVE_CALLEE_SAVED_USER + bl @sys_fork + DISCARD_CALLEE_SAVED_USER + + GET_CURR_THR_INFO_FLAGS r10 + btst r10, TIF_SYSCALL_TRACE + bnz tracesys_exit + + b ret_from_system_call +ARC_EXIT sys_fork_wrapper + +ARC_ENTRY sys_vfork_wrapper + SAVE_CALLEE_SAVED_USER + bl @sys_vfork + DISCARD_CALLEE_SAVED_USER + + GET_CURR_THR_INFO_FLAGS r10 + btst r10, TIF_SYSCALL_TRACE + bnz tracesys_exit + + b ret_from_system_call +ARC_EXIT sys_vfork_wrapper + ARC_ENTRY sys_clone_wrapper SAVE_CALLEE_SAVED_USER bl @sys_clone diff --git a/trunk/arch/arc/kernel/kgdb.c b/trunk/arch/arc/kernel/kgdb.c index 52bdc83c1495..2888ba5be47e 100644 --- a/trunk/arch/arc/kernel/kgdb.c +++ b/trunk/arch/arc/kernel/kgdb.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/trunk/arch/arc/kernel/setup.c b/trunk/arch/arc/kernel/setup.c index 2d95ac07df7b..dc0f968dae0a 100644 --- a/trunk/arch/arc/kernel/setup.c +++ b/trunk/arch/arc/kernel/setup.c @@ -232,8 +232,10 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) n += scnprintf(buf + n, len - n, "\n"); +#ifdef _ASM_GENERIC_UNISTD_H n += scnprintf(buf + n, len - n, - "OS ABI [v3]\t: no-legacy-syscalls\n"); + "OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n"); +#endif return buf; } diff --git a/trunk/arch/arc/kernel/sys.c b/trunk/arch/arc/kernel/sys.c index 9d6c1ca26af6..f6bdd07583f3 100644 --- a/trunk/arch/arc/kernel/sys.c +++ b/trunk/arch/arc/kernel/sys.c @@ -6,6 +6,8 @@ #include #define sys_clone sys_clone_wrapper +#define sys_fork sys_fork_wrapper +#define sys_vfork sys_vfork_wrapper #undef __SYSCALL #define __SYSCALL(nr, call) [nr] = (call), diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 135dff88e882..0c990b75082f 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -49,6 +49,7 @@ config ARM select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS select HAVE_UID16 + select HAVE_VIRT_TO_BUS select KTIME_SCALAR select PERF_USE_VMALLOC select RTC_LIB @@ -473,14 +474,12 @@ config ARCH_MXS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select CLKSRC_MMIO - select CLKSRC_OF select COMMON_CLK select GENERIC_CLOCKEVENTS select HAVE_CLK_PREPARE select MULTI_IRQ_HANDLER select PINCTRL select SPARSE_IRQ - select STMP_DEVICE select USE_OF help Support for Freescale MXS-based family of processors @@ -675,7 +674,6 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 - select SOC_BUS select SPARSE_IRQ select USE_OF help @@ -745,7 +743,6 @@ config ARCH_RPC select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NO_IOPORT - select VIRT_TO_BUS help On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive. @@ -772,10 +769,8 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" select ARCH_HAS_CPUFREQ + select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP - select CLKSRC_MMIO - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -792,11 +787,10 @@ config ARCH_S3C64XX bool "Samsung S3C64XX" select ARCH_HAS_CPUFREQ select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET select ARM_VIC select CLKDEV_LOOKUP - select CLKSRC_MMIO select CPU_V6 - select GENERIC_CLOCKEVENTS select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -830,11 +824,9 @@ config ARCH_S5P64X0 config ARCH_S5PC100 bool "Samsung S5PC100" + select ARCH_USES_GETTIMEOFFSET select CLKDEV_LOOKUP - select CLKSRC_MMIO select CPU_V7 - select GENERIC_CLOCKEVENTS - select GENERIC_GPIO select HAVE_CLK select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -867,7 +859,6 @@ config ARCH_EXYNOS select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SPARSEMEM_ENABLE select CLKDEV_LOOKUP - select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_CLK @@ -887,7 +878,6 @@ config ARCH_SHARK select ISA_DMA select NEED_MACH_MEMORY_H select PCI - select VIRT_TO_BUS select ZONE_DMA help Support for the StrongARM based Digital DNARD machine, also known @@ -1015,12 +1005,12 @@ config ARCH_MULTI_V4_V5 bool config ARCH_MULTI_V6 - bool "ARMv6 based platforms (ARM11)" + bool "ARMv6 based platforms (ARM11, Scorpion, ...)" select ARCH_MULTI_V6_V7 select CPU_V6 config ARCH_MULTI_V7 - bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" + bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)" default y select ARCH_MULTI_V6_V7 select ARCH_VEXPRESS @@ -1471,6 +1461,10 @@ config ISA_DMA bool select ISA_DMA_API +config ARCH_NO_VIRT_TO_BUS + def_bool y + depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK + # Select ISA DMA interface config ISA_DMA_API bool @@ -1602,7 +1596,6 @@ config HAVE_ARM_ARCH_TIMER config HAVE_ARM_TWD bool depends on SMP - select CLKSRC_OF if OF help This options enables support for the ARM timer and watchdog unit @@ -1656,23 +1649,20 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT) + select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system accounting to be spread across the timer interval, preventing a "thundering herd" at every timer tick. -# The GPIO number here must be sorted by descending number. In case of -# a multiplatform kernel, we just want the highest value required by the -# selected platforms. config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA - default 512 if SOC_OMAP5 default 355 if ARCH_U8500 - default 288 if ARCH_VT8500 || ARCH_SUNXI default 264 if MACH_H4700 + default 512 if SOC_OMAP5 + default 288 if ARCH_VT8500 || ARCH_SUNXI default 0 help Maximum number of GPIOs in the system. @@ -1896,9 +1886,8 @@ config XEN_DOM0 config XEN bool "Xen guest support on ARM (EXPERIMENTAL)" - depends on ARM && AEABI && OF + depends on ARM && OF depends on CPU_V7 && !CPU_V6 - depends on !GENERIC_ATOMIC64 help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index 9b31f4311ea2..acddddac7ee4 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -492,10 +492,9 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX31_UART || \ DEBUG_IMX35_UART || \ DEBUG_IMX51_UART || \ - DEBUG_IMX53_UART || \ + DEBUG_IMX50_IMX53_UART || \ DEBUG_IMX6Q_UART default 1 - depends on ARCH_MXC help Choose UART port on which kernel low-level debug messages should be output. diff --git a/trunk/arch/arm/boot/Makefile b/trunk/arch/arm/boot/Makefile index 84aa2caf07ed..71768b8a1ab9 100644 --- a/trunk/arch/arm/boot/Makefile +++ b/trunk/arch/arm/boot/Makefile @@ -115,4 +115,4 @@ i: $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ $(obj)/Image System.map "$(INSTALL_PATH)" -subdir- := bootp compressed dts +subdir- := bootp compressed diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile index 6cecf1437ea0..9c6255884cbb 100644 --- a/trunk/arch/arm/boot/dts/Makefile +++ b/trunk/arch/arm/boot/dts/Makefile @@ -42,11 +42,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ - exynos4412-odroidx.dtb \ exynos4412-smdk4412.dtb \ - exynos4412-origen.dtb \ - exynos5250-arndale.dtb \ - exynos5440-sd5v1.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ exynos5440-ssdk5440.dtb @@ -119,14 +115,10 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-tx28.dtb dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ - omap3430-sdp.dtb \ omap3-beagle.dtb \ - omap3-devkit8000.dtb \ omap3-beagle-xm.dtb \ omap3-evm.dtb \ omap3-tobi.dtb \ - omap3-igep0020.dtb \ - omap3-igep0030.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ diff --git a/trunk/arch/arm/boot/dts/am335x-bone.dts b/trunk/arch/arm/boot/dts/am335x-bone.dts index 5302f79c05b7..11b240c5d323 100644 --- a/trunk/arch/arm/boot/dts/am335x-bone.dts +++ b/trunk/arch/arm/boot/dts/am335x-bone.dts @@ -43,7 +43,7 @@ status = "okay"; }; - i2c0: i2c@44e0b000 { + i2c1: i2c@44e0b000 { status = "okay"; clock-frequency = <400000>; @@ -59,27 +59,27 @@ led@2 { label = "beaglebone:green:heartbeat"; - gpios = <&gpio1 21 0>; + gpios = <&gpio2 21 0>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led@3 { label = "beaglebone:green:mmc0"; - gpios = <&gpio1 22 0>; + gpios = <&gpio2 22 0>; linux,default-trigger = "mmc0"; default-state = "off"; }; led@4 { label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 0>; + gpios = <&gpio2 23 0>; default-state = "off"; }; led@5 { label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 0>; + gpios = <&gpio2 24 0>; default-state = "off"; }; }; diff --git a/trunk/arch/arm/boot/dts/am335x-evm.dts b/trunk/arch/arm/boot/dts/am335x-evm.dts index 0423298a26fe..d6496440fcea 100644 --- a/trunk/arch/arm/boot/dts/am335x-evm.dts +++ b/trunk/arch/arm/boot/dts/am335x-evm.dts @@ -51,7 +51,7 @@ status = "okay"; }; - i2c0: i2c@44e0b000 { + i2c1: i2c@44e0b000 { status = "okay"; clock-frequency = <400000>; @@ -60,7 +60,7 @@ }; }; - i2c1: i2c@4802a000 { + i2c2: i2c@4802a000 { status = "okay"; clock-frequency = <100000>; @@ -123,12 +123,12 @@ debounce-delay-ms = <5>; col-scan-delay-us = <2>; - row-gpios = <&gpio1 25 0 /* Bank1, pin25 */ - &gpio1 26 0 /* Bank1, pin26 */ - &gpio1 27 0>; /* Bank1, pin27 */ + row-gpios = <&gpio2 25 0 /* Bank1, pin25 */ + &gpio2 26 0 /* Bank1, pin26 */ + &gpio2 27 0>; /* Bank1, pin27 */ - col-gpios = <&gpio1 21 0 /* Bank1, pin21 */ - &gpio1 22 0>; /* Bank1, pin22 */ + col-gpios = <&gpio2 21 0 /* Bank1, pin21 */ + &gpio2 22 0>; /* Bank1, pin22 */ linux,keymap = <0x0000008b /* MENU */ 0x0100009e /* BACK */ @@ -147,14 +147,14 @@ switch@9 { label = "volume-up"; linux,code = <115>; - gpios = <&gpio0 2 1>; + gpios = <&gpio1 2 1>; gpio-key,wakeup; }; switch@10 { label = "volume-down"; linux,code = <114>; - gpios = <&gpio0 3 1>; + gpios = <&gpio1 3 1>; gpio-key,wakeup; }; }; diff --git a/trunk/arch/arm/boot/dts/am335x-evmsk.dts b/trunk/arch/arm/boot/dts/am335x-evmsk.dts index f67c360844f4..f5a6162a4ff2 100644 --- a/trunk/arch/arm/boot/dts/am335x-evmsk.dts +++ b/trunk/arch/arm/boot/dts/am335x-evmsk.dts @@ -58,7 +58,7 @@ status = "okay"; }; - i2c0: i2c@44e0b000 { + i2c1: i2c@44e0b000 { status = "okay"; clock-frequency = <400000>; @@ -115,26 +115,26 @@ led@1 { label = "evmsk:green:usr0"; - gpios = <&gpio1 4 0>; + gpios = <&gpio2 4 0>; default-state = "off"; }; led@2 { label = "evmsk:green:usr1"; - gpios = <&gpio1 5 0>; + gpios = <&gpio2 5 0>; default-state = "off"; }; led@3 { label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 0>; + gpios = <&gpio2 6 0>; linux,default-trigger = "mmc0"; default-state = "off"; }; led@4 { label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 0>; + gpios = <&gpio2 7 0>; linux,default-trigger = "heartbeat"; default-state = "off"; }; @@ -148,26 +148,26 @@ switch@1 { label = "button0"; linux,code = <0x100>; - gpios = <&gpio2 3 0>; + gpios = <&gpio3 3 0>; }; switch@2 { label = "button1"; linux,code = <0x101>; - gpios = <&gpio2 2 0>; + gpios = <&gpio3 2 0>; }; switch@3 { label = "button2"; linux,code = <0x102>; - gpios = <&gpio0 30 0>; + gpios = <&gpio1 30 0>; gpio-key,wakeup; }; switch@4 { label = "button3"; linux,code = <0x103>; - gpios = <&gpio2 5 0>; + gpios = <&gpio3 5 0>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/am33xx.dtsi b/trunk/arch/arm/boot/dts/am33xx.dtsi index df6283076e79..0957645b73af 100644 --- a/trunk/arch/arm/boot/dts/am33xx.dtsi +++ b/trunk/arch/arm/boot/dts/am33xx.dtsi @@ -21,8 +21,6 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - d_can0 = &dcan0; - d_can1 = &dcan1; }; cpus { @@ -89,7 +87,7 @@ reg = <0x48200000 0x1000>; }; - gpio0: gpio@44e07000 { + gpio1: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; gpio-controller; @@ -100,7 +98,7 @@ interrupts = <96>; }; - gpio1: gpio@4804c000 { + gpio2: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; @@ -111,7 +109,7 @@ interrupts = <98>; }; - gpio2: gpio@481ac000 { + gpio3: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; @@ -122,7 +120,7 @@ interrupts = <32>; }; - gpio3: gpio@481ae000 { + gpio4: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; @@ -187,7 +185,7 @@ status = "disabled"; }; - i2c0: i2c@44e0b000 { + i2c1: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -197,7 +195,7 @@ status = "disabled"; }; - i2c1: i2c@4802a000 { + i2c2: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -207,7 +205,7 @@ status = "disabled"; }; - i2c2: i2c@4819c000 { + i2c3: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; @@ -227,8 +225,7 @@ dcan0: d_can@481cc000 { compatible = "bosch,d_can"; ti,hwmods = "d_can0"; - reg = <0x481cc000 0x2000 - 0x44e10644 0x4>; + reg = <0x481cc000 0x2000>; interrupts = <52>; status = "disabled"; }; @@ -236,14 +233,13 @@ dcan1: d_can@481d0000 { compatible = "bosch,d_can"; ti,hwmods = "d_can1"; - reg = <0x481d0000 0x2000 - 0x44e10644 0x4>; + reg = <0x481d0000 0x2000>; interrupts = <55>; status = "disabled"; }; timer1: timer@44e31000 { - compatible = "ti,am335x-timer-1ms"; + compatible = "ti,omap2-timer"; reg = <0x44e31000 0x400>; interrupts = <67>; ti,hwmods = "timer1"; @@ -251,21 +247,21 @@ }; timer2: timer@48040000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x48040000 0x400>; interrupts = <68>; ti,hwmods = "timer2"; }; timer3: timer@48042000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x48042000 0x400>; interrupts = <69>; ti,hwmods = "timer3"; }; timer4: timer@48044000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x48044000 0x400>; interrupts = <92>; ti,hwmods = "timer4"; @@ -273,7 +269,7 @@ }; timer5: timer@48046000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x48046000 0x400>; interrupts = <93>; ti,hwmods = "timer5"; @@ -281,7 +277,7 @@ }; timer6: timer@48048000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x48048000 0x400>; interrupts = <94>; ti,hwmods = "timer6"; @@ -289,7 +285,7 @@ }; timer7: timer@4804a000 { - compatible = "ti,am335x-timer"; + compatible = "ti,omap2-timer"; reg = <0x4804a000 0x400>; interrupts = <95>; ti,hwmods = "timer7"; @@ -309,7 +305,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x48030000 0x400>; - interrupts = <65>; + interrupt = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; status = "disabled"; @@ -320,7 +316,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x481a0000 0x400>; - interrupts = <125>; + interrupt = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; status = "disabled"; diff --git a/trunk/arch/arm/boot/dts/am3517-evm.dts b/trunk/arch/arm/boot/dts/am3517-evm.dts index e9b5bdae4908..474f760ecadf 100644 --- a/trunk/arch/arm/boot/dts/am3517-evm.dts +++ b/trunk/arch/arm/boot/dts/am3517-evm.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +/include/ "omap3.dtsi" / { model = "TI AM3517 EVM (AM3517/05)"; diff --git a/trunk/arch/arm/boot/dts/am3517_mt_ventoux.dts b/trunk/arch/arm/boot/dts/am3517_mt_ventoux.dts index 556868388a23..5eb26d7d9b4e 100644 --- a/trunk/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ b/trunk/arch/arm/boot/dts/am3517_mt_ventoux.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +/include/ "omap3.dtsi" / { model = "TeeJet Mt.Ventoux"; diff --git a/trunk/arch/arm/boot/dts/armada-370-db.dts b/trunk/arch/arm/boot/dts/armada-370-db.dts index e34b280ce6ec..6403acdbb75f 100644 --- a/trunk/arch/arm/boot/dts/armada-370-db.dts +++ b/trunk/arch/arm/boot/dts/armada-370-db.dts @@ -94,5 +94,22 @@ spi-max-frequency = <50000000>; }; }; + + pcie-controller { + status = "okay"; + /* + * The two PCIe units are accessible through + * both standard PCIe slots and mini-PCIe + * slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..58ee79372206 100644 --- a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts @@ -33,6 +33,43 @@ clock-frequency = <600000000>; status = "okay"; }; + + pinctrl { + pwr_led_pin: pwr-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; + + stat_led_pins: stat-led-pins { + marvell,pins = "mpp64", "mpp65"; + marvell,function = "gpio"; + }; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_pin &stat_led_pins>; + + green_pwr_led { + label = "mirabox:green:pwr"; + gpios = <&gpio1 31 1>; + linux,default-trigger = "heartbeat"; + }; + + blue_stat_led { + label = "mirabox:blue:stat"; + gpios = <&gpio2 0 1>; + linux,default-trigger = "cpu0"; + }; + + green_stat_led { + label = "mirabox:green:stat"; + gpios = <&gpio2 1 1>; + default-state = "off"; + }; + }; + mdio { phy0: ethernet-phy@0 { reg = <0>; @@ -54,7 +91,7 @@ }; mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins2>; + pinctrl-0 = <&sdio_pins3>; pinctrl-names = "default"; status = "okay"; /* @@ -70,5 +107,32 @@ usb@d0051000 { status = "okay"; }; + + i2c@d0011000 { + status = "okay"; + clock-frequency = <100000>; + pca9505: pca9505@25 { + compatible = "nxp,pca9505"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x25>; + }; + }; + + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-370-rd.dts b/trunk/arch/arm/boot/dts/armada-370-rd.dts index 070bba4f2585..516dec31b469 100644 --- a/trunk/arch/arm/boot/dts/armada-370-rd.dts +++ b/trunk/arch/arm/boot/dts/armada-370-rd.dts @@ -73,4 +73,15 @@ status = "okay"; }; }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + button@1 { + label = "Software Button"; + linux,code = <116>; + gpios = <&gpio0 6 1>; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/armada-370-xp.dtsi b/trunk/arch/arm/boot/dts/armada-370-xp.dtsi index 5b708208b607..758c4ea90344 100644 --- a/trunk/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/trunk/arch/arm/boot/dts/armada-370-xp.dtsi @@ -181,6 +181,51 @@ clocks = <&coreclk 0>; status = "disabled"; }; + + devbus-bootcs@d0010400 { + compatible = "marvell,mvebu-devbus"; + reg = <0xd0010400 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs0@d0010408 { + compatible = "marvell,mvebu-devbus"; + reg = <0xd0010408 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs1@d0010410 { + compatible = "marvell,mvebu-devbus"; + reg = <0xd0010410 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs2@d0010418 { + compatible = "marvell,mvebu-devbus"; + reg = <0xd0010418 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + devbus-cs3@d0010420 { + compatible = "marvell,mvebu-devbus"; + reg = <0xd0010420 0x8>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-370.dtsi b/trunk/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..18f6eb47cc50 100644 --- a/trunk/arch/arm/boot/dts/armada-370.dtsi +++ b/trunk/arch/arm/boot/dts/armada-370.dtsi @@ -59,6 +59,12 @@ "mpp50", "mpp51", "mpp52"; marvell,function = "sd0"; }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; }; gpio0: gpio@d0018100 { @@ -153,5 +159,63 @@ clocks = <&coreclk 0>; }; + thermal@d0018300 { + compatible = "marvell,armada370-thermal"; + reg = <0xd0018300 0x4 + 0xd0018304 0x4>; + status = "okay"; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; + + reg-names = "pcie0.0", "pcie1.0"; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-db.dts b/trunk/arch/arm/boot/dts/armada-xp-db.dts index e83505e4c236..54cc5bb705fb 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-db.dts +++ b/trunk/arch/arm/boot/dts/armada-xp-db.dts @@ -121,5 +121,38 @@ spi-max-frequency = <20000000>; }; }; + + pcie-controller { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 0, Lane 2 */ + status = "okay"; + }; + pcie@4,0 { + /* Port 0, Lane 3 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-gp.dts b/trunk/arch/arm/boot/dts/armada-xp-gp.dts index 1c8afe2ffebc..04f28a712b98 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-gp.dts +++ b/trunk/arch/arm/boot/dts/armada-xp-gp.dts @@ -109,5 +109,55 @@ spi-max-frequency = <108000000>; }; }; + + devbus-bootcs@d0010400 { + status = "okay"; + ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 16 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@10,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/trunk/arch/arm/boot/dts/armada-xp-mv78230.dtsi index f56c40599f5b..c2c78459a4d4 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/trunk/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -76,5 +76,109 @@ #interrupts-cells = <2>; interrupts = <87>, <88>, <89>; }; + + /* + * MV78230 has 2 PCIe units Gen2.0: One unit can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/trunk/arch/arm/boot/dts/armada-xp-mv78260.dtsi index f8f2b787d2b0..885bf229eef7 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/trunk/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -96,5 +96,127 @@ clocks = <&gateclk 1>; status = "disabled"; }; + + /* + * MV78260 has 3 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. One unit is + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/trunk/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 936c25dc32b0..23a5ac4490a8 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/trunk/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -111,5 +111,193 @@ clocks = <&gateclk 1>; status = "disabled"; }; + + /* + * MV78460 has 4 PCIe units Gen2.0: Two units can be + * configured as x4 or quad x1 lanes. Two units are + * x4/x1. + */ + pcie-controller { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ + 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ + 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ + 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 59>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 6>; + status = "disabled"; + }; + + pcie@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; + reg = <0x1800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 60>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 7>; + status = "disabled"; + }; + + pcie@4,0 { + device_type = "pci"; + assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; + reg = <0x2000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 61>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + pcie@5,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + reg = <0x2800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + pcie@6,0 { + device_type = "pci"; + assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; + reg = <0x3000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 63>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <1>; + clocks = <&gateclk 10>; + status = "disabled"; + }; + + pcie@7,0 { + device_type = "pci"; + assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; + reg = <0x3800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 64>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <2>; + clocks = <&gateclk 11>; + status = "disabled"; + }; + + pcie@8,0 { + device_type = "pci"; + assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; + reg = <0x4000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 65>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <3>; + clocks = <&gateclk 12>; + status = "disabled"; + }; + pcie@9,0 { + device_type = "pci"; + assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; + reg = <0x4800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 99>; + marvell,pcie-port = <2>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + pcie@10,0 { + device_type = "pci"; + assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; + reg = <0x5000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 103>; + marvell,pcie-port = <3>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 27>; + status = "disabled"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/trunk/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 3818a82176a2..9d04f04d4e39 100644 --- a/trunk/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/trunk/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -139,5 +139,43 @@ usb@d0051000 { status = "okay"; }; + + devbus-bootcs@d0010400 { + status = "okay"; + ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; + }; + + pcie-controller { + status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/armada-xp.dtsi b/trunk/arch/arm/boot/dts/armada-xp.dtsi index ca00d8326c87..29dfeb6d4a26 100644 --- a/trunk/arch/arm/boot/dts/armada-xp.dtsi +++ b/trunk/arch/arm/boot/dts/armada-xp.dtsi @@ -151,5 +151,11 @@ status = "disabled"; }; + thermal@d00182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0xd00182b0 0x4 + 0xd00184d0 0x4>; + status = "okay"; + }; }; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi index a98c0d50fbbe..aa98e641931f 100644 --- a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi @@ -238,32 +238,8 @@ nand { pinctrl_nand: nand-0 { atmel,pins = - <3 0 0x1 0x0 /* PD0 periph A Read Enable */ - 3 1 0x1 0x0 /* PD1 periph A Write Enable */ - 3 2 0x1 0x0 /* PD2 periph A Address Latch Enable */ - 3 3 0x1 0x0 /* PD3 periph A Command Latch Enable */ - 3 4 0x0 0x1 /* PD4 gpio Chip Enable pin pull_up */ - 3 5 0x0 0x1 /* PD5 gpio RDY/BUSY pin pull_up */ - 3 6 0x1 0x0 /* PD6 periph A Data bit 0 */ - 3 7 0x1 0x0 /* PD7 periph A Data bit 1 */ - 3 8 0x1 0x0 /* PD8 periph A Data bit 2 */ - 3 9 0x1 0x0 /* PD9 periph A Data bit 3 */ - 3 10 0x1 0x0 /* PD10 periph A Data bit 4 */ - 3 11 0x1 0x0 /* PD11 periph A Data bit 5 */ - 3 12 0x1 0x0 /* PD12 periph A Data bit 6 */ - 3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */ - }; - - pinctrl_nand_16bits: nand_16bits-0 { - atmel,pins = - <3 14 0x1 0x0 /* PD14 periph A Data bit 8 */ - 3 15 0x1 0x0 /* PD15 periph A Data bit 9 */ - 3 16 0x1 0x0 /* PD16 periph A Data bit 10 */ - 3 17 0x1 0x0 /* PD17 periph A Data bit 11 */ - 3 18 0x1 0x0 /* PD18 periph A Data bit 12 */ - 3 19 0x1 0x0 /* PD19 periph A Data bit 13 */ - 3 20 0x1 0x0 /* PD20 periph A Data bit 14 */ - 3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */ + <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */ + 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */ }; }; diff --git a/trunk/arch/arm/boot/dts/bcm2835.dtsi b/trunk/arch/arm/boot/dts/bcm2835.dtsi index 7e0481e2441a..4bf2a8774aa7 100644 --- a/trunk/arch/arm/boot/dts/bcm2835.dtsi +++ b/trunk/arch/arm/boot/dts/bcm2835.dtsi @@ -105,7 +105,7 @@ compatible = "fixed-clock"; reg = <1>; #clock-cells = <0>; - clock-frequency = <250000000>; + clock-frequency = <150000000>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/cros5250-common.dtsi b/trunk/arch/arm/boot/dts/cros5250-common.dtsi index 8a5b3a6cdc58..46c098017036 100644 --- a/trunk/arch/arm/boot/dts/cros5250-common.dtsi +++ b/trunk/arch/arm/boot/dts/cros5250-common.dtsi @@ -19,168 +19,31 @@ chosen { }; - pinctrl@11400000 { - /* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ - i2c2_bus: i2c2-bus { - samsung,pin-pud = <0>; - }; - }; - i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - - max77686@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; + gpios = <&gpb3 0 2 3 0>, + <&gpb3 1 2 3 0>; }; i2c@12C70000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; + gpios = <&gpb3 2 2 3 0>, + <&gpb3 3 2 3 0>; }; i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + /* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ + gpios = <&gpa0 6 3 0 0>, + <&gpa0 7 3 0 0>; + hdmiddc@50 { compatible = "samsung,exynos5-hdmiddc"; reg = <0x50>; @@ -190,6 +53,8 @@ i2c@12C90000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa1 2 3 3 0>, + <&gpa1 3 3 3 0>; }; i2c@12CA0000 { @@ -199,6 +64,8 @@ i2c@12CB0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa2 2 3 3 0>, + <&gpa2 3 3 3 0>; }; i2c@12CC0000 { @@ -208,6 +75,8 @@ i2c@12CD0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpb2 2 3 3 0>, + <&gpb2 3 3 3 0>; }; i2c@12CE0000 { @@ -229,12 +98,15 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; slot@0 { reg = <0>; bus-width = <8>; + gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, + <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, + <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, + <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, + <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; }; }; @@ -250,13 +122,15 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; slot@0 { reg = <0>; bus-width = <4>; - wp-gpios = <&gpc2 1 0>; + samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; + wp-gpios = <&gpc2 1 0 0 3>; + gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>, + <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>, + <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>; }; }; @@ -269,11 +143,11 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - /* See board-specific dts files for pin setup */ slot@0 { reg = <0>; bus-width = <4>; + /* See board-specific dts files for GPIOs */ }; }; @@ -282,6 +156,9 @@ }; spi_1: spi@12d30000 { + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; samsung,spi-src-clk = <0>; num-cs = <1>; }; @@ -291,7 +168,7 @@ }; hdmi { - hpd-gpio = <&gpx3 7 0>; + hpd-gpio = <&gpx3 7 0xf 1 3>; }; gpio-keys { @@ -299,7 +176,7 @@ power { label = "Power"; - gpios = <&gpx1 3 1>; + gpios = <&gpx1 3 0 0x10000 0>; linux,code = <116>; /* KEY_POWER */ gpio-key,wakeup; }; diff --git a/trunk/arch/arm/boot/dts/dbx5x0.dtsi b/trunk/arch/arm/boot/dts/dbx5x0.dtsi index 9de93096601a..69140ba99f46 100644 --- a/trunk/arch/arm/boot/dts/dbx5x0.dtsi +++ b/trunk/arch/arm/boot/dts/dbx5x0.dtsi @@ -319,8 +319,9 @@ }; }; - ab8500 { + ab8500@5 { compatible = "stericsson,ab8500"; + reg = <5>; /* mailbox 5 is i2c */ interrupt-parent = <&intc>; interrupts = <0 40 0x4>; interrupt-controller; diff --git a/trunk/arch/arm/boot/dts/dove.dtsi b/trunk/arch/arm/boot/dts/dove.dtsi index f7509cafc377..6cab46849cdb 100644 --- a/trunk/arch/arm/boot/dts/dove.dtsi +++ b/trunk/arch/arm/boot/dts/dove.dtsi @@ -50,6 +50,11 @@ #clock-cells = <1>; }; + thermal: thermal@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; diff --git a/trunk/arch/arm/boot/dts/exynos4.dtsi b/trunk/arch/arm/boot/dts/exynos4.dtsi index b8771c5cb2a3..e1347fceb5bc 100644 --- a/trunk/arch/arm/boot/dts/exynos4.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4.dtsi @@ -82,17 +82,10 @@ reg = <0x10440000 0x1000>; }; - sys_reg: sysreg { - compatible = "samsung,exynos4-sysreg", "syscon"; - reg = <0x10010000 0x400>; - }; - watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; interrupts = <0 43 0>; - clocks = <&clock 345>; - clock-names = "watchdog"; status = "disabled"; }; @@ -100,8 +93,6 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 44 0>, <0 45 0>; - clocks = <&clock 346>; - clock-names = "rtc"; status = "disabled"; }; @@ -109,8 +100,6 @@ compatible = "samsung,s5pv210-keypad"; reg = <0x100A0000 0x100>; interrupts = <0 109 0>; - clocks = <&clock 347>; - clock-names = "keypad"; status = "disabled"; }; @@ -118,8 +107,6 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12510000 0x100>; interrupts = <0 73 0>; - clocks = <&clock 297>, <&clock 145>; - clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -127,8 +114,6 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12520000 0x100>; interrupts = <0 74 0>; - clocks = <&clock 298>, <&clock 146>; - clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -136,8 +121,6 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12530000 0x100>; interrupts = <0 75 0>; - clocks = <&clock 299>, <&clock 147>; - clock-names = "hsmmc", "mmc_busclk.2"; status = "disabled"; }; @@ -145,16 +128,6 @@ compatible = "samsung,exynos4210-sdhci"; reg = <0x12540000 0x100>; interrupts = <0 76 0>; - clocks = <&clock 300>, <&clock 148>; - clock-names = "hsmmc", "mmc_busclk.2"; - status = "disabled"; - }; - - mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - samsung,power-domain = <&pd_mfc>; status = "disabled"; }; @@ -162,8 +135,6 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; interrupts = <0 52 0>; - clocks = <&clock 312>, <&clock 151>; - clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -171,8 +142,6 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13810000 0x100>; interrupts = <0 53 0>; - clocks = <&clock 313>, <&clock 152>; - clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -180,8 +149,6 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 314>, <&clock 153>; - clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -189,8 +156,6 @@ compatible = "samsung,exynos4210-uart"; reg = <0x13830000 0x100>; interrupts = <0 55 0>; - clocks = <&clock 315>, <&clock 154>; - clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; @@ -200,10 +165,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13860000 0x100>; interrupts = <0 58 0>; - clocks = <&clock 317>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; status = "disabled"; }; @@ -213,10 +174,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13870000 0x100>; interrupts = <0 59 0>; - clocks = <&clock 318>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; status = "disabled"; }; @@ -226,8 +183,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13880000 0x100>; interrupts = <0 60 0>; - clocks = <&clock 319>; - clock-names = "i2c"; status = "disabled"; }; @@ -237,8 +192,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x13890000 0x100>; interrupts = <0 61 0>; - clocks = <&clock 320>; - clock-names = "i2c"; status = "disabled"; }; @@ -248,8 +201,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138A0000 0x100>; interrupts = <0 62 0>; - clocks = <&clock 321>; - clock-names = "i2c"; status = "disabled"; }; @@ -259,8 +210,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138B0000 0x100>; interrupts = <0 63 0>; - clocks = <&clock 322>; - clock-names = "i2c"; status = "disabled"; }; @@ -270,8 +219,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138C0000 0x100>; interrupts = <0 64 0>; - clocks = <&clock 323>; - clock-names = "i2c"; status = "disabled"; }; @@ -281,8 +228,6 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x138D0000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 324>; - clock-names = "i2c"; status = "disabled"; }; @@ -294,10 +239,6 @@ rx-dma-channel = <&pdma0 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 327>, <&clock 159>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; status = "disabled"; }; @@ -309,10 +250,6 @@ rx-dma-channel = <&pdma1 6>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 328>, <&clock 160>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; status = "disabled"; }; @@ -324,10 +261,6 @@ rx-dma-channel = <&pdma0 8>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 329>, <&clock 161>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; status = "disabled"; }; @@ -342,45 +275,18 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 292>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <0 36 0>; - clocks = <&clock 293>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 279>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <1>; }; }; - - fimd: fimd@11c00000 { - compatible = "samsung,exynos4210-fimd"; - interrupt-parent = <&combiner>; - reg = <0x11c00000 0x20000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <11 0>, <11 1>, <11 2>; - clocks = <&clock 140>, <&clock 283>; - clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; - status = "disabled"; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4210-origen.dts b/trunk/arch/arm/boot/dts/exynos4210-origen.dts index 524b90846df5..f2710018e84e 100644 --- a/trunk/arch/arm/boot/dts/exynos4210-origen.dts +++ b/trunk/arch/arm/boot/dts/exynos4210-origen.dts @@ -57,16 +57,6 @@ status = "okay"; }; - g2d@12800000 { - status = "okay"; - }; - - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; - }; - serial@13800000 { status = "okay"; }; @@ -131,16 +121,4 @@ linux,default-trigger = "heartbeat"; }; }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts b/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts index 91332b72acf5..f63490707f3a 100644 --- a/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -30,19 +30,16 @@ }; sdhci@12530000 { - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - status = "okay"; - }; - - g2d@12800000 { - status = "okay"; - }; - - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; + samsung,sdhci-bus-width = <4>; + linux,mmc_cap_4_bit_data; + samsung,sdhci-cd-internal; + gpio-cd = <&gpk2 2 2 3 3>; + gpios = <&gpk2 0 2 0 3>, + <&gpk2 1 2 0 3>, + <&gpk2 3 2 3 3>, + <&gpk2 4 2 3 3>, + <&gpk2 5 2 3 3>, + <&gpk2 6 2 3 3>; status = "okay"; }; @@ -62,32 +59,25 @@ status = "okay"; }; - pinctrl@11000000 { - keypad_rows: keypad-rows { - samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - keypad_cols: keypad-cols { - samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", - "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; - keypad@100A0000 { samsung,keypad-num-rows = <2>; samsung,keypad-num-columns = <8>; linux,keypad-no-autorepeat; linux,keypad-wakeup; - pinctrl-names = "default"; - pinctrl-0 = <&keypad_rows &keypad_cols>; status = "okay"; + row-gpios = <&gpx2 0 3 3 0>, + <&gpx2 1 3 3 0>; + + col-gpios = <&gpx1 0 3 0 0>, + <&gpx1 1 3 0 0>, + <&gpx1 2 3 0 0>, + <&gpx1 3 3 0 0>, + <&gpx1 4 3 0 0>, + <&gpx1 5 3 0 0>, + <&gpx1 6 3 0 0>, + <&gpx1 7 3 0 0>; + key_1 { keypad,row = <0>; keypad,column = <3>; @@ -153,7 +143,9 @@ #address-cells = <1>; #size-cells = <0>; samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <100000>; + samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpd1 0 2 3 0>, + <&gpd1 1 2 3 0>; status = "okay"; eeprom@50 { @@ -168,6 +160,9 @@ }; spi_2: spi@13940000 { + gpios = <&gpc1 1 5 3 0>, + <&gpc1 3 5 3 0>, + <&gpc1 4 5 3 0>; status = "okay"; w25x80@0 { @@ -178,7 +173,7 @@ spi-max-frequency = <1000000>; controller-data { - cs-gpio = <&gpc1 2 0>; + cs-gpio = <&gpc1 2 1 0 3>; samsung,spi-feedback-delay = <0>; }; @@ -194,16 +189,4 @@ }; }; }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <12000000>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4210-trats.dts b/trunk/arch/arm/boot/dts/exynos4210-trats.dts index 9a14484c7bb1..c346b64dff55 100644 --- a/trunk/arch/arm/boot/dts/exynos4210-trats.dts +++ b/trunk/arch/arm/boot/dts/exynos4210-trats.dts @@ -289,16 +289,4 @@ }; }; }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4210.dtsi b/trunk/arch/arm/boot/dts/exynos4210.dtsi index 9e6f381fa835..2feffc70814c 100644 --- a/trunk/arch/arm/boot/dts/exynos4210.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4210.dtsi @@ -47,36 +47,6 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; - mct@10050000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - clocks = <&clock 3>, <&clock 344>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &gic 0 69 0>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 0 42 0>, - <0x5 0 &gic 0 48 0>; - }; - }; - - clock: clock-controller@0x10030000 { - compatible = "samsung,exynos4210-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; @@ -106,11 +76,4 @@ reg = <0x100C0000 0x100>; interrupts = <2 4>; }; - - g2d@12800000 { - compatible = "samsung,s5pv210-g2d"; - reg = <0x12800000 0x1000>; - interrupts = <0 89 0>; - status = "disabled"; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4212.dtsi b/trunk/arch/arm/boot/dts/exynos4212.dtsi index 36d4299789ef..c6ae2005961f 100644 --- a/trunk/arch/arm/boot/dts/exynos4212.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4212.dtsi @@ -25,26 +25,4 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x8000>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts b/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts deleted file mode 100644 index 15dc0a38b96d..000000000000 --- a/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Hardkernel's Exynos4412 based ODROID-X board device tree source - * - * Copyright (c) 2012 Dongjin Kim - * - * Device tree source file for Hardkernel's ODROID-X board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -/include/ "exynos4412.dtsi" - -/ { - model = "Hardkernel ODROID-X board based on Exynos4412"; - compatible = "hardkernel,odroid-x", "samsung,exynos4412"; - - memory { - reg = <0x40000000 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - label = "led1:heart"; - gpios = <&gpc1 0 1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - led2 { - label = "led2:mmc0"; - gpios = <&gpc1 2 1>; - default-state = "on"; - linux,default-trigger = "mmc0"; - }; - }; - - mshc@12550000 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - num-slots = <1>; - supports-highspeed; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - regulator_p3v3 { - compatible = "regulator-fixed"; - regulator-name = "p3v3_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpa1 1 1>; - enable-active-high; - regulator-boot-on; - }; - - rtc@10070000 { - status = "okay"; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - pinctrl-names = "default"; - status = "okay"; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/exynos4412-origen.dts b/trunk/arch/arm/boot/dts/exynos4412-origen.dts deleted file mode 100644 index b39bffccde86..000000000000 --- a/trunk/arch/arm/boot/dts/exynos4412-origen.dts +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Insignal's Exynos4412 based Origen board device tree source - * - * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Device tree source file for Insignal's Origen board which is based on - * Samsung's Exynos4412 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -/include/ "exynos4412.dtsi" - -/ { - model = "Insignal Origen evaluation board based on Exynos4412"; - compatible = "insignal,origen4412", "samsung,exynos4412"; - - memory { - reg = <0x40000000 0x40000000>; - }; - - chosen { - bootargs ="console=ttySAC2,115200"; - }; - - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 0>; - enable-active-high; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - vmmc-supply = <&mmc_reg>; - status = "okay"; - }; - - mshc@12550000 { - pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; - pinctrl-names = "default"; - status = "okay"; - - num-slots = <1>; - supports-highspeed; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; - }; - - fimd@11c00000 { - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; - pinctrl-names = "default"; - status = "okay"; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing { - clock-frequency = <50000>; - hactive = <1024>; - vactive = <600>; - hfront-porch = <64>; - hback-porch = <16>; - hsync-len = <48>; - vback-porch = <64>; - vfront-porch = <16>; - vsync-len = <3>; - }; - }; - - serial@13800000 { - status = "okay"; - }; - - serial@13810000 { - status = "okay"; - }; - - serial@13820000 { - status = "okay"; - }; - - serial@13830000 { - status = "okay"; - }; - - i2c@13860000 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - pinctrl-0 = <&i2c0_bus>; - pinctrl-names = "default"; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck-default-dvs-idx = <3>; - - s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>, - <&gpx2 4 0>, - <&gpx2 5 0>; - - s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>, - <&gpm3 6 0>, - <&gpm3 7 0>; - - s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>, - <1100000>, <1100000>; - - s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_M12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo3_reg: LDO3 { - regulator-name = "VDDIOAP_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo4_reg: LDO4 { - regulator-name = "VDDQ_PRE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD18_2M"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD10_XPLL"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD10_MIPI"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD33_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD18_MIPI"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD18_ABB1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD33_UOTG"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDIOPERI_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB02"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_USH"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDIOAP_MMC012_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo18_reg: LDO18 { - regulator-name = "VDDIOPERI_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo19_reg: LDO19 { - regulator-name = "DVDD25"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo20_reg: LDO20 { - regulator-name = "VDD28_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo21_reg: LDO21 { - regulator-name = "VDD28_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo22_reg: LDO22 { - regulator-name = "VDDA28_2M"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo23_reg: LDO23 { - regulator-name = "VDD28_TF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo24_reg: LDO24 { - regulator-name = "VDD33_A31"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo25_reg: LDO25 { - regulator-name = "VDD18_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo26_reg: LDO26 { - regulator-name = "VDD18_A31"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo27_reg: LDO27 { - regulator-name = "GPS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - ldo28_reg: LDO28 { - regulator-name = "DVDD12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - - buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; /* Normal Mode */ - }; - }; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts b/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts index dd564310d4a5..f05bf575cc45 100644 --- a/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -27,27 +27,6 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; }; - g2d@10800000 { - status = "okay"; - }; - - g2d@10800000 { - status = "okay"; - }; - - sdhci@12530000 { - bus-width = <4>; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; - pinctrl-names = "default"; - status = "okay"; - }; - - codec@13400000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - status = "okay"; - }; - serial@13800000 { status = "okay"; }; @@ -63,16 +42,4 @@ serial@13830000 { status = "okay"; }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <0>; - }; - - xusbxti { - compatible = "samsung,clock-xusbxti"; - clock-frequency = <24000000>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4412.dtsi b/trunk/arch/arm/boot/dts/exynos4412.dtsi index d75c047e80a9..d7dfe312772a 100644 --- a/trunk/arch/arm/boot/dts/exynos4412.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4412.dtsi @@ -25,30 +25,4 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x4000>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>; - clocks = <&clock 3>, <&clock 344>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>, - <0x6 0 &gic 1 12 0>, - <0x7 0 &gic 1 12 0>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4x12.dtsi b/trunk/arch/arm/boot/dts/exynos4x12.dtsi index e3380a7a285c..9a8780694909 100644 --- a/trunk/arch/arm/boot/dts/exynos4x12.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4x12.dtsi @@ -36,12 +36,6 @@ <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; }; - clock: clock-controller@0x10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x20000>; - #clock-cells = <1>; - }; - pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; @@ -72,11 +66,4 @@ reg = <0x106E0000 0x1000>; interrupts = <0 72 0>; }; - - g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = <0 89 0>; - status = "disabled"; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5250-arndale.dts b/trunk/arch/arm/boot/dts/exynos5250-arndale.dts deleted file mode 100644 index 02cfc76d002f..000000000000 --- a/trunk/arch/arm/boot/dts/exynos5250-arndale.dts +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Samsung's Exynos5250 based Arndale board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -/include/ "exynos5250.dtsi" - -/ { - model = "Insignal Arndale evaluation board based on EXYNOS5250"; - compatible = "insignal,arndale", "samsung,exynos5250"; - - memory { - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=ttySAC2,115200"; - }; - - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - }; - - i2c@12C60000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - - s5m8767,pmic-buck2-dvs-voltage = <1300000>; - s5m8767,pmic-buck3-dvs-voltage = <1100000>; - s5m8767,pmic-buck4-dvs-voltage = <1200000>; - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>, - <&gpd1 1 0>, - <&gpd1 2 0>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, - <&gpx2 4 0>, - <&gpx2 5 0>; - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; - }; - - i2c@12C70000 { - status = "disabled"; - }; - - i2c@12C80000 { - status = "disabled"; - }; - - i2c@12C90000 { - status = "disabled"; - }; - - i2c@12CA0000 { - status = "disabled"; - }; - - i2c@12CB0000 { - status = "disabled"; - }; - - i2c@12CC0000 { - status = "disabled"; - }; - - i2c@12CD0000 { - status = "disabled"; - }; - - i2c@121D0000 { - status = "disabled"; - }; - - dwmmc_0: dwmmc0@12200000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - fifo-depth = <0x80>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - dwmmc_1: dwmmc1@12210000 { - status = "disabled"; - }; - - dwmmc_2: dwmmc2@12220000 { - num-slots = <1>; - supports-highspeed; - fifo-depth = <0x80>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - dwmmc_3: dwmmc3@12230000 { - status = "disabled"; - }; - - spi_0: spi@12d20000 { - status = "disabled"; - }; - - spi_1: spi@12d30000 { - status = "disabled"; - }; - - spi_2: spi@12d40000 { - status = "disabled"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - menu { - label = "SW-TACT2"; - gpios = <&gpx1 4 1>; - linux,code = <139>; - gpio-key,wakeup; - }; - - home { - label = "SW-TACT3"; - gpios = <&gpx1 5 1>; - linux,code = <102>; - gpio-key,wakeup; - }; - - up { - label = "SW-TACT4"; - gpios = <&gpx1 6 1>; - linux,code = <103>; - gpio-key,wakeup; - }; - - down { - label = "SW-TACT5"; - gpios = <&gpx1 7 1>; - linux,code = <108>; - gpio-key,wakeup; - }; - - back { - label = "SW-TACT6"; - gpios = <&gpx2 0 1>; - linux,code = <158>; - gpio-key,wakeup; - }; - - wakeup { - label = "SW-TACT7"; - gpios = <&gpx2 1 1>; - linux,code = <143>; - gpio-key,wakeup; - }; - }; - - hdmi { - hpd-gpio = <&gpx3 7 2>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - }; - - mmc_reg: voltage-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 1>; - enable-active-high; - }; - - reg_hdmi_en: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-en"; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/trunk/arch/arm/boot/dts/exynos5250-pinctrl.dtsi deleted file mode 100644 index d1650fb34c0a..000000000000 --- a/trunk/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ /dev/null @@ -1,783 +0,0 @@ -/* - * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/ { - pinctrl@11400000 { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb1: gpb1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb2: gpb2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb3: gpb3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy1: gpy1 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy2: gpy2 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy3: gpy3 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy4: gpy4 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy5: gpy5 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpy6: gpy6 { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc4: gpc4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <23 0>, <24 0>, <25 0>, <25 1>, - <26 0>, <26 1>, <27 0>, <27 1>; - }; - - gpx1: gpx1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&combiner>; - #interrupt-cells = <2>; - interrupts = <28 0>, <28 1>, <29 0>, <29 1>, - <30 0>, <30 1>, <31 0>, <31 1>; - }; - - gpx2: gpx2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpx3: gpx3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - i2c2_hs_bus: i2c2-hs-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - uart2_data: uart2-data { - samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart2_fctl: uart2-fctl { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - i2c3_bus: i2c3-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - i2c3_hs_bus: i2c3-hs-bus { - samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c4_bus: i2c4-bus { - samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - i2c5_bus: i2c5-bus { - samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - ac97_bus: ac97-bus { - samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", - "gpb0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - i2s2_bus: i2s2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pcm2_bus: pcm2-bus { - samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", - "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c6_bus: i2c6-bus { - samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c7_bus: i2c7-bus { - samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c1_bus: i2c1-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - i2c0_hs_bus: i2c0-hs-bus { - samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - i2c1_hs_bus: i2c1-hs-bus { - samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpc3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd2_bus8: sd2-bus-width8 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_clk: sd3-clk { - samsung,pins = "gpc4-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd3_cmd: sd3-cmd { - samsung,pins = "gpc4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; - }; - - sd3_cd: sd3-cd { - samsung,pins = "gpc4-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_bus1: sd3-bus-width1 { - samsung,pins = "gpc4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - }; - - pinctrl@13400000 { - gpe0: gpe0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe1: gpe1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph0: gph0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - cam_gpio_a: cam-gpio-a { - samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", - "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", - "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - cam_gpio_b: cam-gpio-b { - samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - cam_i2c2_bus: cam-i2c2-bus { - samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - cam_spi1_bus: cam-spi1-bus { - samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - cam_i2c1_bus: cam-i2c1-bus { - samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - cam_i2c0_bus: cam-i2c0-bus { - samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samaung,pin-drv = <0>; - }; - - cam_spi0_bus: cam-spi0-bus { - samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - cam_bayrgb_bus: cam-bayrgb-bus { - samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", - "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", - "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", - "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", - "gpg2-0", "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - cam_port_a: cam-port-a { - samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", - "gph1-0", "gph1-1", "gph1-2", "gph1-3", - "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - }; - - pinctrl@10d10000 { - gpv0: gpv0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv1: gpv1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv2: gpv2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv3: gpv3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv4: gpv4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - c2c_rxd: c2c-rxd { - samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", - "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", - "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", - "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - - c2c_txd: c2c-txd { - samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", - "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", - "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", - "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samaung,pin-drv = <0>; - }; - }; - - pinctrl@03680000 { - gpz: gpz { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", - "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts b/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts index 26d856ba50a1..1b8d4106d338 100644 --- a/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -30,6 +30,8 @@ i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpb3 0 2 3 0>, + <&gpb3 1 2 3 0>; eeprom@50 { compatible = "samsung,s524ad0xd1"; @@ -40,6 +42,8 @@ i2c@12C70000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + gpios = <&gpb3 2 2 3 0>, + <&gpb3 3 2 3 0>; eeprom@51 { compatible = "samsung,s524ad0xd1"; @@ -70,6 +74,8 @@ i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + gpios = <&gpa0 6 3 3 0>, + <&gpa0 7 3 3 0>; hdmiddc@50 { compatible = "samsung,exynos5-hdmiddc"; @@ -116,12 +122,15 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; slot@0 { reg = <0>; bus-width = <8>; + gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, + <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, + <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, + <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, + <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; }; }; @@ -137,13 +146,17 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; slot@0 { reg = <0>; bus-width = <4>; + samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>; disable-wp; + gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>, + <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>, + <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>, + <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>, + <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>; }; }; @@ -156,6 +169,10 @@ }; spi_1: spi@12d30000 { + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + w25q80bw@0 { #address-cells = <1>; #size-cells = <1>; @@ -164,7 +181,7 @@ spi-max-frequency = <1000000>; controller-data { - cs-gpio = <&gpa2 5 0>; + cs-gpio = <&gpa2 5 1 0 3>; samsung,spi-feedback-delay = <0>; }; @@ -186,7 +203,7 @@ }; hdmi { - hpd-gpio = <&gpx3 7 0>; + hpd-gpio = <&gpx3 7 0xf 1 3>; }; codec@11000000 { @@ -195,7 +212,9 @@ }; i2s0: i2s@03830000 { - status = "okay"; + gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>, + <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>, + <&gpz 6 2 0 0>; }; i2s1: i2s@12D60000 { @@ -212,40 +231,4 @@ samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&wm8994>; }; - - usb@12110000 { - samsung,vbus-gpio = <&gpx2 6 1 3 3>; - }; - - dp-controller { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5250-snow.dts b/trunk/arch/arm/boot/dts/exynos5250-snow.dts index 581ffae27e13..17dd951c1cd2 100644 --- a/trunk/arch/arm/boot/dts/exynos5250-snow.dts +++ b/trunk/arch/arm/boot/dts/exynos5250-snow.dts @@ -16,27 +16,12 @@ model = "Google Snow"; compatible = "google,snow", "samsung,exynos5250"; - pinctrl@11400000 { - sd3_clk: sd3-clk { - samsung,pin-drv = <0>; - }; - - sd3_cmd: sd3-cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pin-drv = <0>; - }; - }; - gpio-keys { compatible = "gpio-keys"; lid-switch { label = "Lid"; - gpios = <&gpx3 5 1>; + gpios = <&gpx3 5 0 0x10000 0>; linux,input-type = <5>; /* EV_SW */ linux,code = <0>; /* SW_LID */ debounce-interval = <1>; @@ -50,19 +35,9 @@ */ dwmmc3@12230000 { slot@0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - }; - }; - - usb@12110000 { - samsung,vbus-gpio = <&gpx1 1 1 3 3>; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; + gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>, + <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>, + <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>; }; }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5250.dtsi b/trunk/arch/arm/boot/dts/exynos5250.dtsi index af66e6b7bc77..b1ac73e21c80 100644 --- a/trunk/arch/arm/boot/dts/exynos5250.dtsi +++ b/trunk/arch/arm/boot/dts/exynos5250.dtsi @@ -18,7 +18,6 @@ */ /include/ "skeleton.dtsi" -/include/ "exynos5250-pinctrl.dtsi" / { compatible = "samsung,exynos5250"; @@ -45,45 +44,13 @@ i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - }; - - pd_gsc: gsc-power-domain@0x10044000 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044000 0x20>; - }; - - pd_mfc: mfc-power-domain@0x10044040 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10044040 0x20>; - }; - - clock: clock-controller@0x10010000 { - compatible = "samsung,exynos5250-clock"; - reg = <0x10010000 0x30000>; - #clock-cells = <1>; }; gic:interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + reg = <0x10481000 0x1000>, <0x10482000 0x2000>; }; combiner:interrupt-controller@10440000 { @@ -102,129 +69,58 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; - mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; - interrupt-controller; - #interrups-cells = <2>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - clocks = <&clock 1>, <&clock 335>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &combiner 23 3>, - <0x1 0 &combiner 23 4>, - <0x2 0 &combiner 25 2>, - <0x3 0 &combiner 25 3>, - <0x4 0 &gic 0 120 0>, - <0x5 0 &gic 0 121 0>; - }; - }; - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 46 0>; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - - pinctrl_1: pinctrl@13400000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x13400000 0x1000>; - interrupts = <0 45 0>; - }; - - pinctrl_2: pinctrl@10d10000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x10d10000 0x1000>; - interrupts = <0 50 0>; - }; - - pinctrl_3: pinctrl@03680000 { - compatible = "samsung,exynos5250-pinctrl"; - reg = <0x0368000 0x1000>; - interrupts = <0 47 0>; - }; - watchdog { compatible = "samsung,s3c2410-wdt"; reg = <0x101D0000 0x100>; interrupts = <0 42 0>; - clocks = <&clock 336>; - clock-names = "watchdog"; }; codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; - samsung,power-domain = <&pd_mfc>; }; rtc { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; interrupts = <0 43 0>, <0 44 0>; - clocks = <&clock 337>; - clock-names = "rtc"; }; tmu@10060000 { compatible = "samsung,exynos5250-tmu"; reg = <0x10060000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 338>; - clock-names = "tmu_apbif"; }; serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <0 51 0>; - clocks = <&clock 289>, <&clock 146>; - clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; interrupts = <0 52 0>; - clocks = <&clock 290>, <&clock 147>; - clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; interrupts = <0 53 0>; - clocks = <&clock 291>, <&clock 148>; - clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C30000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 292>, <&clock 149>; - clock-names = "uart", "clk_uart_baud0"; }; sata@122F0000 { compatible = "samsung,exynos5-sata-ahci"; reg = <0x122F0000 0x1ff>; interrupts = <0 115 0>; - clocks = <&clock 277>, <&clock 143>; - clock-names = "sata", "sclk_sata"; }; sata-phy@12170000 { @@ -238,10 +134,6 @@ interrupts = <0 56 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 294>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; }; i2c_1: i2c@12C70000 { @@ -250,10 +142,6 @@ interrupts = <0 57 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 295>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_bus>; }; i2c_2: i2c@12C80000 { @@ -262,10 +150,6 @@ interrupts = <0 58 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 296>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_bus>; }; i2c_3: i2c@12C90000 { @@ -274,10 +158,6 @@ interrupts = <0 59 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 297>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_bus>; }; i2c_4: i2c@12CA0000 { @@ -286,10 +166,6 @@ interrupts = <0 60 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 298>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_bus>; }; i2c_5: i2c@12CB0000 { @@ -298,10 +174,6 @@ interrupts = <0 61 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 299>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_bus>; }; i2c_6: i2c@12CC0000 { @@ -310,10 +182,6 @@ interrupts = <0 62 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 300>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_bus>; }; i2c_7: i2c@12CD0000 { @@ -322,10 +190,6 @@ interrupts = <0 63 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 301>; - clock-names = "i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_bus>; }; i2c_8: i2c@12CE0000 { @@ -334,8 +198,6 @@ interrupts = <0 64 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 302>; - clock-names = "i2c"; }; i2c@121D0000 { @@ -343,8 +205,6 @@ reg = <0x121D0000 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 288>; - clock-names = "i2c"; }; spi_0: spi@12d20000 { @@ -356,10 +216,6 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 304>, <&clock 154>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; }; spi_1: spi@12d30000 { @@ -371,10 +227,6 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 305>, <&clock 155>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; }; spi_2: spi@12d40000 { @@ -386,10 +238,6 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 306>, <&clock 156>; - clock-names = "spi", "spi_busclk0"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; }; dwmmc_0: dwmmc0@12200000 { @@ -398,8 +246,6 @@ interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 280>, <&clock 139>; - clock-names = "biu", "ciu"; }; dwmmc_1: dwmmc1@12210000 { @@ -408,8 +254,6 @@ interrupts = <0 76 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 281>, <&clock 140>; - clock-names = "biu", "ciu"; }; dwmmc_2: dwmmc2@12220000 { @@ -418,8 +262,6 @@ interrupts = <0 77 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 282>, <&clock 141>; - clock-names = "biu", "ciu"; }; dwmmc_3: dwmmc3@12230000 { @@ -428,8 +270,6 @@ interrupts = <0 78 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 283>, <&clock 142>; - clock-names = "biu", "ciu"; }; i2s0: i2s@03830000 { @@ -443,8 +283,6 @@ samsung,supports-rstclr; samsung,supports-secdai; samsung,idma-addr = <0x03000000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; }; i2s1: i2s@12D60000 { @@ -453,8 +291,6 @@ dmas = <&pdma1 12 &pdma1 11>; dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; }; i2s2: i2s@12D70000 { @@ -463,26 +299,6 @@ dmas = <&pdma0 12 &pdma0 11>; dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - }; - - usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - }; - - usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock 285>; - clock-names = "usbhost"; }; amba { @@ -496,8 +312,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 275>; - clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; @@ -507,8 +321,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 276>; - clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; @@ -518,8 +330,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <0 33 0>; - clocks = <&clock 271>; - clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; @@ -529,58 +339,287 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <0 124 0>; - clocks = <&clock 271>; - clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; }; }; + gpio-controllers { + #address-cells = <1>; + #size-cells = <1>; + gpio-controller; + ranges; + + gpa0: gpio-controller@11400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400000 0x20>; + #gpio-cells = <4>; + }; + + gpa1: gpio-controller@11400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400020 0x20>; + #gpio-cells = <4>; + }; + + gpa2: gpio-controller@11400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400040 0x20>; + #gpio-cells = <4>; + }; + + gpb0: gpio-controller@11400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400060 0x20>; + #gpio-cells = <4>; + }; + + gpb1: gpio-controller@11400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400080 0x20>; + #gpio-cells = <4>; + }; + + gpb2: gpio-controller@114000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000A0 0x20>; + #gpio-cells = <4>; + }; + + gpb3: gpio-controller@114000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000C0 0x20>; + #gpio-cells = <4>; + }; + + gpc0: gpio-controller@114000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114000E0 0x20>; + #gpio-cells = <4>; + }; + + gpc1: gpio-controller@11400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400100 0x20>; + #gpio-cells = <4>; + }; + + gpc2: gpio-controller@11400120 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400120 0x20>; + #gpio-cells = <4>; + }; + + gpc3: gpio-controller@11400140 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400140 0x20>; + #gpio-cells = <4>; + }; + + gpc4: gpio-controller@114002E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114002E0 0x20>; + #gpio-cells = <4>; + }; + + gpd0: gpio-controller@11400160 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400160 0x20>; + #gpio-cells = <4>; + }; + + gpd1: gpio-controller@11400180 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400180 0x20>; + #gpio-cells = <4>; + }; + + gpy0: gpio-controller@114001A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001A0 0x20>; + #gpio-cells = <4>; + }; + + gpy1: gpio-controller@114001C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001C0 0x20>; + #gpio-cells = <4>; + }; + + gpy2: gpio-controller@114001E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x114001E0 0x20>; + #gpio-cells = <4>; + }; + + gpy3: gpio-controller@11400200 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400200 0x20>; + #gpio-cells = <4>; + }; + + gpy4: gpio-controller@11400220 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400220 0x20>; + #gpio-cells = <4>; + }; + + gpy5: gpio-controller@11400240 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400240 0x20>; + #gpio-cells = <4>; + }; + + gpy6: gpio-controller@11400260 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400260 0x20>; + #gpio-cells = <4>; + }; + + gpx0: gpio-controller@11400C00 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C00 0x20>; + #gpio-cells = <4>; + }; + + gpx1: gpio-controller@11400C20 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C20 0x20>; + #gpio-cells = <4>; + }; + + gpx2: gpio-controller@11400C40 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C40 0x20>; + #gpio-cells = <4>; + }; + + gpx3: gpio-controller@11400C60 { + compatible = "samsung,exynos4-gpio"; + reg = <0x11400C60 0x20>; + #gpio-cells = <4>; + }; + + gpe0: gpio-controller@13400000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400000 0x20>; + #gpio-cells = <4>; + }; + + gpe1: gpio-controller@13400020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400020 0x20>; + #gpio-cells = <4>; + }; + + gpf0: gpio-controller@13400040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400040 0x20>; + #gpio-cells = <4>; + }; + + gpf1: gpio-controller@13400060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400060 0x20>; + #gpio-cells = <4>; + }; + + gpg0: gpio-controller@13400080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400080 0x20>; + #gpio-cells = <4>; + }; + + gpg1: gpio-controller@134000A0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000A0 0x20>; + #gpio-cells = <4>; + }; + + gpg2: gpio-controller@134000C0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000C0 0x20>; + #gpio-cells = <4>; + }; + + gph0: gpio-controller@134000E0 { + compatible = "samsung,exynos4-gpio"; + reg = <0x134000E0 0x20>; + #gpio-cells = <4>; + }; + + gph1: gpio-controller@13400100 { + compatible = "samsung,exynos4-gpio"; + reg = <0x13400100 0x20>; + #gpio-cells = <4>; + }; + + gpv0: gpio-controller@10D10000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10000 0x20>; + #gpio-cells = <4>; + }; + + gpv1: gpio-controller@10D10020 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10020 0x20>; + #gpio-cells = <4>; + }; + + gpv2: gpio-controller@10D10040 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10060 0x20>; + #gpio-cells = <4>; + }; + + gpv3: gpio-controller@10D10060 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D10080 0x20>; + #gpio-cells = <4>; + }; + + gpv4: gpio-controller@10D10080 { + compatible = "samsung,exynos4-gpio"; + reg = <0x10D100C0 0x20>; + #gpio-cells = <4>; + }; + + gpz: gpio-controller@03860000 { + compatible = "samsung,exynos4-gpio"; + reg = <0x03860000 0x20>; + #gpio-cells = <4>; + }; + }; + gsc_0: gsc@0x13e00000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; - samsung,power-domain = <&pd_gsc>; - clocks = <&clock 256>; - clock-names = "gscl"; }; gsc_1: gsc@0x13e10000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; - samsung,power-domain = <&pd_gsc>; - clocks = <&clock 257>; - clock-names = "gscl"; }; gsc_2: gsc@0x13e20000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; - samsung,power-domain = <&pd_gsc>; - clocks = <&clock 258>; - clock-names = "gscl"; }; gsc_3: gsc@0x13e30000 { compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; - samsung,power-domain = <&pd_gsc>; - clocks = <&clock 259>; - clock-names = "gscl"; }; hdmi { compatible = "samsung,exynos5-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 333>, <&clock 136>, <&clock 137>, - <&clock 333>, <&clock 333>; - clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", - "sclk_hdmiphy", "hdmiphy"; }; mixer { @@ -588,28 +627,4 @@ reg = <0x14450000 0x10000>; interrupts = <0 94 0>; }; - - dp-controller { - compatible = "samsung,exynos5-dp"; - reg = <0x145b0000 0x1000>; - interrupts = <10 3>; - interrupt-parent = <&combiner>; - #address-cells = <1>; - #size-cells = <0>; - - dptx-phy { - reg = <0x10040720>; - samsung,enable-mask = <1>; - }; - }; - - fimd { - compatible = "samsung,exynos5250-fimd"; - interrupt-parent = <&combiner>; - reg = <0x14400000 0x40000>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = <18 4>, <18 5>, <18 6>; - clocks = <&clock 133>, <&clock 339>; - clock-names = "sclk_fimd", "fimd"; - }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5440-sd5v1.dts b/trunk/arch/arm/boot/dts/exynos5440-sd5v1.dts deleted file mode 100644 index ef747b52b674..000000000000 --- a/trunk/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SAMSUNG SD5v1 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; -/include/ "exynos5440.dtsi" - -/ { - model = "SAMSUNG SD5v1 board based on EXYNOS5440"; - compatible = "samsung,sd5v1", "samsung,exynos5440"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; - - gmac: ethernet@00230000 { - fixed_phy; - phy_addr = <1>; - }; - - spi { - status = "disabled"; - }; - -}; diff --git a/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d55042beb5c5..81e2c964a900 100644 --- a/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -16,18 +16,31 @@ model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; compatible = "samsung,ssdk5440", "samsung,exynos5440"; + memory { + reg = <0x80000000 0x80000000>; + }; + chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc"; }; spi { status = "disabled"; }; - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; + i2c@F0000 { + status = "disabled"; + }; + + i2c@100000 { + status = "disabled"; + }; + + watchdog { + status = "disabled"; + }; + + rtc { + status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5440.dtsi b/trunk/arch/arm/boot/dts/exynos5440.dtsi index 93e9028edaaf..5f3562ad6746 100644 --- a/trunk/arch/arm/boot/dts/exynos5440.dtsi +++ b/trunk/arch/arm/boot/dts/exynos5440.dtsi @@ -16,89 +16,63 @@ interrupt-parent = <&gic>; - clock: clock-controller@0x160000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x1000>; - #clock-cells = <1>; - }; - gic:interrupt-controller@2E0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x2E1000 0x1000>, - <0x2E2000 0x1000>, - <0x2E4000 0x2000>, - <0x2E6000 0x2000>; - interrupts = <1 9 0xf04>; + reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>; }; cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { compatible = "arm,cortex-a15"; - reg = <0>; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>; + clock-frequency = <1000000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; - reg = <1>; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 14 0xf08>; + clock-frequency = <1000000>; + }; }; cpu@2 { compatible = "arm,cortex-a15"; - reg = <2>; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 14 0xf08>; + clock-frequency = <1000000>; + }; }; cpu@3 { compatible = "arm,cortex-a15"; - reg = <3>; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 14 0xf08>; + clock-frequency = <1000000>; + }; }; }; - arm-pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 52 4>, - <0 53 4>, - <0 54 4>, - <0 55 4>; - }; - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <50000000>; - }; + common { + compatible = "samsung,exynos5440"; - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = <0 57 0>; - operating-points = < - /* KHz uV */ - 1200000 1025000 - 1000000 975000 - 800000 925000 - >; }; serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>; interrupts = <0 2 0>; - clocks = <&clock 21>, <&clock 21>; - clock-names = "uart", "clk_uart_baud0"; }; serial@C0000 { compatible = "samsung,exynos4210-uart"; reg = <0xC0000 0x1000>; interrupts = <0 3 0>; - clocks = <&clock 21>, <&clock 21>; - clock-names = "uart", "clk_uart_baud0"; }; spi { @@ -109,15 +83,11 @@ rx-dma-channel = <&pdma0 4>; /* preliminary */ #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>, <&clock 16>; - clock-names = "spi", "spi_busclk0"; }; pinctrl { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; - interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, - <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; interrupt-controller; #interrupt-cells = <2>; #gpio-cells = <2>; @@ -140,42 +110,25 @@ }; i2c@F0000 { - compatible = "samsung,exynos5440-i2c"; + compatible = "samsung,s3c2440-i2c"; reg = <0xF0000 0x1000>; interrupts = <0 5 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; - clock-names = "i2c"; }; i2c@100000 { - compatible = "samsung,exynos5440-i2c"; + compatible = "samsung,s3c2440-i2c"; reg = <0x100000 0x1000>; interrupts = <0 6 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 21>; - clock-names = "i2c"; }; watchdog { compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; interrupts = <0 1 0>; - clocks = <&clock 21>; - clock-names = "watchdog"; - }; - - gmac: ethernet@00230000 { - compatible = "snps,dwmac-3.70a"; - reg = <0x00230000 0x8000>; - interrupt-parent = <&gic>; - interrupts = <0 31 4>; - interrupt-names = "macirq"; - phy-mode = "sgmii"; - clocks = <&clock 25>; - clock-names = "stmmaceth"; }; amba { @@ -185,26 +138,16 @@ interrupt-parent = <&gic>; ranges; - pdma0: pdma@00121000 { + pdma0: pdma@121A0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121000 0x1000>; - interrupts = <0 46 0>; - clocks = <&clock 8>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; + reg = <0x120000 0x1000>; + interrupts = <0 34 0>; }; - pdma1: pdma@00120000 { + pdma1: pdma@121B0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <0 47 0>; - clocks = <&clock 8>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; + reg = <0x121000 0x1000>; + interrupts = <0 35 0>; }; }; @@ -212,7 +155,5 @@ compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; interrupts = <0 17 0>, <0 16 0>; - clocks = <&clock 21>; - clock-names = "rtc"; }; }; diff --git a/trunk/arch/arm/boot/dts/href.dtsi b/trunk/arch/arm/boot/dts/href.dtsi index 379128eb9d98..592fb9dc35bd 100644 --- a/trunk/arch/arm/boot/dts/href.dtsi +++ b/trunk/arch/arm/boot/dts/href.dtsi @@ -221,7 +221,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/hrefv60plus.dts b/trunk/arch/arm/boot/dts/hrefv60plus.dts index 2b587a74b813..55f4191a626e 100644 --- a/trunk/arch/arm/boot/dts/hrefv60plus.dts +++ b/trunk/arch/arm/boot/dts/hrefv60plus.dts @@ -158,7 +158,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/imx23-evk.dts b/trunk/arch/arm/boot/dts/imx23-evk.dts index da0588a04131..035c13f9d3c0 100644 --- a/trunk/arch/arm/boot/dts/imx23-evk.dts +++ b/trunk/arch/arm/boot/dts/imx23-evk.dts @@ -59,33 +59,8 @@ lcdif@80030000 { pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a>; - lcd-supply = <®_lcd_3v3>; - display = <&display>; + panel-enable-gpios = <&gpio1 18 0>; status = "okay"; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hback-porch = <15>; - hfront-porch = <8>; - vback-porch = <12>; - vfront-porch = <4>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; }; @@ -120,15 +95,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio1 29 0>; }; - - reg_lcd_3v3: lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 18 0>; - enable-active-high; - }; }; backlight { diff --git a/trunk/arch/arm/boot/dts/imx23-olinuxino.dts b/trunk/arch/arm/boot/dts/imx23-olinuxino.dts index d107c4af321f..e7484e4ea659 100644 --- a/trunk/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/trunk/arch/arm/boot/dts/imx23-olinuxino.dts @@ -29,7 +29,6 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; bus-width = <4>; - broken-cd; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/imx23.dtsi b/trunk/arch/arm/boot/dts/imx23.dtsi index 73fd7d0887b5..56afcf41aae0 100644 --- a/trunk/arch/arm/boot/dts/imx23.dtsi +++ b/trunk/arch/arm/boot/dts/imx23.dtsi @@ -49,15 +49,9 @@ reg = <0x80000000 0x2000>; }; - dma_apbh: dma-apbh@80004000 { + dma-apbh@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; - interrupts = <0 14 20 0 - 13 13 13 13>; - interrupt-names = "empty", "ssp0", "ssp1", "empty", - "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <8>; clocks = <&clks 15>; }; @@ -76,8 +70,6 @@ interrupt-names = "gpmi-dma", "bch"; clocks = <&clks 34>; clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -86,8 +78,6 @@ reg = <0x80010000 0x2000>; interrupts = <15 14>; clocks = <&clks 33>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -305,7 +295,6 @@ }; digctl@8001c000 { - compatible = "fsl,imx23-digctl"; reg = <0x8001c000 2000>; status = "disabled"; }; @@ -315,19 +304,9 @@ status = "disabled"; }; - dma_apbx: dma-apbx@80024000 { + dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; - interrupts = <7 5 9 26 - 19 0 25 23 - 60 58 9 0 - 0 0 0 0>; - interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", - "saif0", "empty", "auart0-rx", "auart0-tx", - "auart1-rx", "auart1-tx", "saif1", "empty", - "empty", "empty", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; clocks = <&clks 16>; }; @@ -342,7 +321,6 @@ }; ocotp@8002c000 { - compatible = "fsl,ocotp"; reg = <0x8002c000 0x2000>; status = "disabled"; }; @@ -364,8 +342,6 @@ reg = <0x80034000 0x2000>; interrupts = <2 20>; clocks = <&clks 33>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -384,15 +360,13 @@ ranges; clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl", "fsl,clkctrl"; + compatible = "fsl,imx23-clkctrl"; reg = <0x80040000 0x2000>; #clock-cells = <1>; }; saif0: saif@80042000 { reg = <0x80042000 0x2000>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; status = "disabled"; }; @@ -403,22 +377,16 @@ saif1: saif@80046000 { reg = <0x80046000 0x2000>; - dmas = <&dma_apbx 10>; - dma-names = "rx-tx"; status = "disabled"; }; audio-out@80048000 { reg = <0x80048000 0x2000>; - dmas = <&dma_apbx 1>; - dma-names = "tx"; status = "disabled"; }; audio-in@8004c000 { reg = <0x8004c000 0x2000>; - dmas = <&dma_apbx 0>; - dma-names = "rx"; status = "disabled"; }; @@ -431,15 +399,11 @@ spdif@80054000 { reg = <0x80054000 2000>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; status = "disabled"; }; i2c@80058000 { reg = <0x80058000 0x2000>; - dmas = <&dma_apbx 3>; - dma-names = "rx-tx"; status = "disabled"; }; @@ -462,7 +426,6 @@ compatible = "fsl,imx23-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; interrupts = <28 29 30 31>; - clocks = <&clks 28>; }; auart0: serial@8006c000 { @@ -470,8 +433,6 @@ reg = <0x8006c000 0x2000>; interrupts = <24 25 23>; clocks = <&clks 32>; - dmas = <&dma_apbx 6>, <&dma_apbx 7>; - dma-names = "rx", "tx"; status = "disabled"; }; @@ -480,8 +441,6 @@ reg = <0x8006e000 0x2000>; interrupts = <59 60 58>; clocks = <&clks 32>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/imx28-apf28dev.dts b/trunk/arch/arm/boot/dts/imx28-apf28dev.dts index 3d905d16cbec..6d8865bfb4b7 100644 --- a/trunk/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/trunk/arch/arm/boot/dts/imx28-apf28dev.dts @@ -72,32 +72,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_16bit_pins_a &lcdif_pins_apf28dev>; - display = <&display>; status = "okay"; - - display: display { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts b/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts index 43bf3c796cba..5171667a7763 100644 --- a/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/trunk/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -94,32 +94,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_apx4>; - display = <&display>; status = "okay"; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hfront-porch = <40>; - vback-porch = <32>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/imx28-cfa10049.dts b/trunk/arch/arm/boot/dts/imx28-cfa10049.dts index 063e62059890..a0d3e9f1738e 100644 --- a/trunk/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/trunk/arch/arm/boot/dts/imx28-cfa10049.dts @@ -30,6 +30,7 @@ reg = <0>; fsl,pinmux-ids = < 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ + 0x1153 /* MX28_PAD_LCD_D22__GPIO_1_21 */ 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ @@ -119,48 +120,13 @@ fsl,voltage = <1>; fsl,pull-up = <0>; }; - - w1_gpio_pins: w1-gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */ - >; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <0>; /* 0 will enable the keeper */ - }; }; lcdif@80030000 { pinctrl-names = "default"; pinctrl-0 = <&lcdif_18bit_pins_cfa10049 &lcdif_pins_cfa10049>; - display = <&display>; status = "okay"; - - display: display { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; }; }; @@ -217,11 +183,6 @@ usbphy1: usbphy@8007e000 { status = "okay"; }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; }; }; @@ -343,14 +304,5 @@ pwms = <&pwm 3 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; - - }; - - onewire@0 { - compatible = "w1-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&w1_gpio_pins>; - status = "okay"; - gpios = <&gpio1 21 0>; }; }; diff --git a/trunk/arch/arm/boot/dts/imx28-evk.dts b/trunk/arch/arm/boot/dts/imx28-evk.dts index 3637bf3b1d59..2da316e04409 100644 --- a/trunk/arch/arm/boot/dts/imx28-evk.dts +++ b/trunk/arch/arm/boot/dts/imx28-evk.dts @@ -123,33 +123,8 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_evk>; - lcd-supply = <®_lcd_3v3>; - display = <&display>; + panel-enable-gpios = <&gpio3 30 0>; status = "okay"; - - display: display { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; }; can0: can@80032000 { @@ -310,15 +285,6 @@ gpio = <&gpio3 8 0>; enable-active-high; }; - - reg_lcd_3v3: lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; - enable-active-high; - }; }; sound { diff --git a/trunk/arch/arm/boot/dts/imx28-m28evk.dts b/trunk/arch/arm/boot/dts/imx28-m28evk.dts index 5f0ba99aa809..6ce3d17c3a29 100644 --- a/trunk/arch/arm/boot/dts/imx28-m28evk.dts +++ b/trunk/arch/arm/boot/dts/imx28-m28evk.dts @@ -119,32 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; - display = <&display>; status = "okay"; - - display: display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <0>; - hfront-porch = <256>; - vback-porch = <0>; - vfront-porch = <45>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; }; can0: can@80032000 { @@ -246,8 +221,6 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/imx28.dtsi b/trunk/arch/arm/boot/dts/imx28.dtsi index 600f7cb51f3e..7ba49662b9bc 100644 --- a/trunk/arch/arm/boot/dts/imx28.dtsi +++ b/trunk/arch/arm/boot/dts/imx28.dtsi @@ -61,24 +61,12 @@ hsadc@80002000 { reg = <0x80002000 0x2000>; interrupts = <13 87>; - dmas = <&dma_apbh 12>; - dma-names = "rx"; status = "disabled"; }; - dma_apbh: dma-apbh@80004000 { + dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; - #dma-cells = <1>; - dma-channels = <16>; clocks = <&clks 25>; }; @@ -98,8 +86,6 @@ interrupt-names = "gpmi-dma", "bch"; clocks = <&clks 50>; clock-names = "gpmi_io"; - dmas = <&dma_apbh 4>; - dma-names = "rx-tx"; fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -110,8 +96,6 @@ reg = <0x80010000 0x2000>; interrupts = <96 82>; clocks = <&clks 46>; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <0>; status = "disabled"; }; @@ -122,8 +106,6 @@ reg = <0x80012000 0x2000>; interrupts = <97 83>; clocks = <&clks 47>; - dmas = <&dma_apbh 1>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <1>; status = "disabled"; }; @@ -134,8 +116,6 @@ reg = <0x80014000 0x2000>; interrupts = <98 84>; clocks = <&clks 48>; - dmas = <&dma_apbh 2>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <2>; status = "disabled"; }; @@ -146,8 +126,6 @@ reg = <0x80016000 0x2000>; interrupts = <99 85>; clocks = <&clks 49>; - dmas = <&dma_apbh 3>; - dma-names = "rx-tx"; fsl,ssp-dma-channel = <3>; status = "disabled"; }; @@ -669,7 +647,6 @@ }; digctl@8001c000 { - compatible = "fsl,imx28-digctl"; reg = <0x8001c000 0x2000>; interrupts = <89>; status = "disabled"; @@ -680,19 +657,9 @@ status = "disabled"; }; - dma_apbx: dma-apbx@80024000 { + dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; - #dma-cells = <1>; - dma-channels = <16>; clocks = <&clks 26>; }; @@ -709,7 +676,6 @@ }; ocotp@8002c000 { - compatible = "fsl,ocotp"; reg = <0x8002c000 0x2000>; status = "disabled"; }; @@ -724,8 +690,6 @@ reg = <0x80030000 0x2000>; interrupts = <38 86>; clocks = <&clks 55>; - dmas = <&dma_apbh 13>; - dma-names = "rx"; status = "disabled"; }; @@ -791,7 +755,7 @@ ranges; clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; + compatible = "fsl,imx28-clkctrl"; reg = <0x80040000 0x2000>; #clock-cells = <1>; }; @@ -801,8 +765,6 @@ reg = <0x80042000 0x2000>; interrupts = <59 80>; clocks = <&clks 53>; - dmas = <&dma_apbx 4>; - dma-names = "rx-tx"; fsl,saif-dma-channel = <4>; status = "disabled"; }; @@ -817,8 +779,6 @@ reg = <0x80046000 0x2000>; interrupts = <58 81>; clocks = <&clks 54>; - dmas = <&dma_apbx 5>; - dma-names = "rx-tx"; fsl,saif-dma-channel = <5>; status = "disabled"; }; @@ -834,8 +794,6 @@ spdif@80054000 { reg = <0x80054000 0x2000>; interrupts = <45 66>; - dmas = <&dma_apbx 2>; - dma-names = "tx"; status = "disabled"; }; @@ -852,8 +810,6 @@ reg = <0x80058000 0x2000>; interrupts = <111 68>; clock-frequency = <100000>; - dmas = <&dma_apbx 6>; - dma-names = "rx-tx"; fsl,i2c-dma-channel = <6>; status = "disabled"; }; @@ -865,8 +821,6 @@ reg = <0x8005a000 0x2000>; interrupts = <110 69>; clock-frequency = <100000>; - dmas = <&dma_apbx 7>; - dma-names = "rx-tx"; fsl,i2c-dma-channel = <7>; status = "disabled"; }; @@ -884,15 +838,12 @@ compatible = "fsl,imx28-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; interrupts = <48 49 50 51>; - clocks = <&clks 26>; }; auart0: serial@8006a000 { compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; - dmas = <&dma_apbx 8>, <&dma_apbx 9>; - dma-names = "rx", "tx"; fsl,auart-dma-channel = <8 9>; clocks = <&clks 45>; status = "disabled"; @@ -902,8 +853,6 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; - dmas = <&dma_apbx 10>, <&dma_apbx 11>; - dma-names = "rx", "tx"; clocks = <&clks 45>; status = "disabled"; }; @@ -912,8 +861,6 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; - dmas = <&dma_apbx 12>, <&dma_apbx 13>; - dma-names = "rx", "tx"; clocks = <&clks 45>; status = "disabled"; }; @@ -922,8 +869,6 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; - dmas = <&dma_apbx 14>, <&dma_apbx 15>; - dma-names = "rx", "tx"; clocks = <&clks 45>; status = "disabled"; }; @@ -932,8 +877,6 @@ compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; - dmas = <&dma_apbx 0>, <&dma_apbx 1>; - dma-names = "rx", "tx"; clocks = <&clks 45>; status = "disabled"; }; @@ -997,8 +940,8 @@ compatible = "fsl,imx28-fec"; reg = <0x800f0000 0x4000>; interrupts = <101>; - clocks = <&clks 57>, <&clks 57>, <&clks 64>; - clock-names = "ipg", "ahb", "enet_out"; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/imx53-mba53.dts b/trunk/arch/arm/boot/dts/imx53-mba53.dts index 468c0a1d48d9..e54fffd48369 100644 --- a/trunk/arch/arm/boot/dts/imx53-mba53.dts +++ b/trunk/arch/arm/boot/dts/imx53-mba53.dts @@ -42,9 +42,10 @@ fsl,pins = <689 0x10000 /* DISP1_DRDY */ 482 0x10000 /* DISP1_HSYNC */ 489 0x10000 /* DISP1_VSYNC */ + 684 0x10000 /* DISP1_DAT_0 */ 515 0x10000 /* DISP1_DAT_22 */ 523 0x10000 /* DISP1_DAT_23 */ - 545 0x10000 /* DISP1_DAT_21 */ + 543 0x10000 /* DISP1_DAT_21 */ 553 0x10000 /* DISP1_DAT_20 */ 558 0x10000 /* DISP1_DAT_19 */ 564 0x10000 /* DISP1_DAT_18 */ diff --git a/trunk/arch/arm/boot/dts/imx6qdl.dtsi b/trunk/arch/arm/boot/dts/imx6qdl.dtsi index 59e970f74e8f..06ec460b4581 100644 --- a/trunk/arch/arm/boot/dts/imx6qdl.dtsi +++ b/trunk/arch/arm/boot/dts/imx6qdl.dtsi @@ -65,13 +65,9 @@ interrupt-parent = <&intc>; ranges; - dma_apbh: dma-apbh@00110000 { + dma-apbh@00110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; - interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; clocks = <&clks 106>; }; @@ -87,8 +83,6 @@ <&clks 150>, <&clks 149>; clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; fsl,gpmi-dma-channel = <0>; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/kirkwood-6282.dtsi b/trunk/arch/arm/boot/dts/kirkwood-6282.dtsi index 192cf76fbf93..23991e45bc55 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/trunk/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -49,6 +49,12 @@ }; }; + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; diff --git a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -77,6 +77,7 @@ }; nand@3000000 { + chip-delay = <40>; status = "okay"; partition@0 { diff --git a/trunk/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/trunk/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 9555a86297c2..44fd97dfc1f3 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -69,6 +69,10 @@ status = "okay"; nr-ports = <1>; }; + + mvsdio@90000 { + status = "okay"; + }; }; gpio-leds { diff --git a/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 93c3afbef9ee..3694e94f6e99 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -96,11 +96,11 @@ marvell,function = "gpio"; }; pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { - marvell,pins = "mpp44"; + marvell,pins = "mpp46"; marvell,function = "gpio"; }; pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { - marvell,pins = "mpp45"; + marvell,pins = "mpp47"; marvell,function = "gpio"; }; @@ -157,14 +157,14 @@ gpios = <&gpio0 16 0>; linux,default-trigger = "default-on"; }; - health_led1 { + rebuild_led { + label = "status:white:rebuild_led"; + gpios = <&gpio1 4 0>; + }; + health_led { label = "status:red:health_led"; gpios = <&gpio1 5 0>; }; - health_led2 { - label = "status:white:health_led"; - gpios = <&gpio1 4 0>; - }; backup_led { label = "status:blue:backup_led"; gpios = <&gpio0 15 0>; diff --git a/trunk/arch/arm/boot/dts/omap2.dtsi b/trunk/arch/arm/boot/dts/omap2.dtsi index 37aa7487d4d8..761c4b69b25b 100644 --- a/trunk/arch/arm/boot/dts/omap2.dtsi +++ b/trunk/arch/arm/boot/dts/omap2.dtsi @@ -26,11 +26,6 @@ }; }; - pmu { - compatible = "arm,arm1136-pmu"; - interrupts = <3>; - }; - soc { compatible = "ti,omap-infra"; mpu { @@ -54,18 +49,6 @@ reg = <0x480FE000 0x1000>; }; - sdma: dma-controller@48056000 { - compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <64>; - }; - uart1: serial@4806a000 { compatible = "ti,omap2-uart"; ti,hwmods = "uart1"; @@ -85,28 +68,28 @@ }; timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x4802a000 0x400>; interrupts = <38>; ti,hwmods = "timer2"; }; timer3: timer@48078000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48078000 0x400>; interrupts = <39>; ti,hwmods = "timer3"; }; timer4: timer@4807a000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x4807a000 0x400>; interrupts = <40>; ti,hwmods = "timer4"; }; timer5: timer@4807c000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x4807c000 0x400>; interrupts = <41>; ti,hwmods = "timer5"; @@ -114,7 +97,7 @@ }; timer6: timer@4807e000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x4807e000 0x400>; interrupts = <42>; ti,hwmods = "timer6"; @@ -122,7 +105,7 @@ }; timer7: timer@48080000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48080000 0x400>; interrupts = <43>; ti,hwmods = "timer7"; @@ -130,7 +113,7 @@ }; timer8: timer@48082000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48082000 0x400>; interrupts = <44>; ti,hwmods = "timer8"; @@ -138,7 +121,7 @@ }; timer9: timer@48084000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48084000 0x400>; interrupts = <45>; ti,hwmods = "timer9"; @@ -146,7 +129,7 @@ }; timer10: timer@48086000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48086000 0x400>; interrupts = <46>; ti,hwmods = "timer10"; @@ -154,7 +137,7 @@ }; timer11: timer@48088000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48088000 0x400>; interrupts = <47>; ti,hwmods = "timer11"; @@ -162,7 +145,7 @@ }; timer12: timer@4808a000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x4808a000 0x400>; interrupts = <48>; ti,hwmods = "timer12"; diff --git a/trunk/arch/arm/boot/dts/omap2420-h4.dts b/trunk/arch/arm/boot/dts/omap2420-h4.dts index 68282ee13e26..9b0d07746cba 100644 --- a/trunk/arch/arm/boot/dts/omap2420-h4.dts +++ b/trunk/arch/arm/boot/dts/omap2420-h4.dts @@ -18,49 +18,3 @@ reg = <0x80000000 0x4000000>; /* 64 MB */ }; }; - -&gpmc { - ranges = <0 0 0x08000000 0x04000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,ge28f256l18b85"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x04000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <10>; - gpmc,cs-rd-off-ns = <160>; - gpmc,cs-wr-off-ns = <160>; - gpmc,adv-on-ns = <20>; - gpmc,adv-rd-off-ns = <50>; - gpmc,adv-wr-off-ns = <50>; - gpmc,oe-on-ns = <60>; - gpmc,oe-off-ns = <120>; - gpmc,we-on-ns = <60>; - gpmc,we-off-ns = <120>; - gpmc,rd-cycle-ns = <170>; - gpmc,wr-cycle-ns = <170>; - gpmc,access-ns = <150>; - gpmc,page-burst-access-ns = <10>; - - partition@0 { - label = "bootloader"; - reg = <0 0x20000>; - }; - partition@0x20000 { - label = "params"; - reg = <0x20000 0x20000>; - }; - partition@0x40000 { - label = "kernel"; - reg = <0x40000 0x200000>; - }; - partition@0x240000 { - label = "file-system"; - reg = <0x240000 0x3dc0000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap2420.dtsi b/trunk/arch/arm/boot/dts/omap2420.dtsi index da5b285b73be..af6560908905 100644 --- a/trunk/arch/arm/boot/dts/omap2420.dtsi +++ b/trunk/arch/arm/boot/dts/omap2420.dtsi @@ -29,65 +29,6 @@ pinctrl-single,function-mask = <0x3f>; }; - gpio1: gpio@48018000 { - compatible = "ti,omap2-gpio"; - reg = <0x48018000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4801a000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801a000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@4801c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801c000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@4801e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4801e000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6800a000 { - compatible = "ti,omap2420-gpmc"; - reg = <0x6800a000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - }; - mcbsp1: mcbsp@48074000 { compatible = "ti,omap2420-mcbsp"; reg = <0x48074000 0xff>; @@ -96,9 +37,6 @@ <60>; /* RX interrupt */ interrupt-names = "tx", "rx"; ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; }; mcbsp2: mcbsp@48076000 { @@ -109,13 +47,10 @@ <63>; /* RX interrupt */ interrupt-names = "tx", "rx"; ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; }; timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x48028000 0x400>; interrupts = <37>; ti,hwmods = "timer1"; diff --git a/trunk/arch/arm/boot/dts/omap2430.dtsi b/trunk/arch/arm/boot/dts/omap2430.dtsi index 054bc4439568..c3924457c9b6 100644 --- a/trunk/arch/arm/boot/dts/omap2430.dtsi +++ b/trunk/arch/arm/boot/dts/omap2430.dtsi @@ -29,76 +29,6 @@ pinctrl-single,function-mask = <0x3f>; }; - gpio1: gpio@4900c000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900c000 0x200>; - interrupts = <29>; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio2: gpio@4900e000 { - compatible = "ti,omap2-gpio"; - reg = <0x4900e000 0x200>; - interrupts = <30>; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio3: gpio@49010000 { - compatible = "ti,omap2-gpio"; - reg = <0x49010000 0x200>; - interrupts = <31>; - ti,hwmods = "gpio3"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio4: gpio@49012000 { - compatible = "ti,omap2-gpio"; - reg = <0x49012000 0x200>; - interrupts = <32>; - ti,hwmods = "gpio4"; - ti,gpio-always-on; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpio5: gpio@480b6000 { - compatible = "ti,omap2-gpio"; - reg = <0x480b6000 0x200>; - interrupts = <33>; - ti,hwmods = "gpio5"; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap2430-gpmc"; - reg = <0x6e000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; - }; - mcbsp1: mcbsp@48074000 { compatible = "ti,omap2430-mcbsp"; reg = <0x48074000 0xff>; @@ -110,9 +40,6 @@ interrupt-names = "common", "tx", "rx", "rx_overflow"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; }; mcbsp2: mcbsp@48076000 { @@ -125,9 +52,6 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; }; mcbsp3: mcbsp@4808c000 { @@ -140,9 +64,6 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; }; mcbsp4: mcbsp@4808e000 { @@ -155,9 +76,6 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; }; mcbsp5: mcbsp@48096000 { @@ -170,13 +88,10 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; }; timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; + compatible = "ti,omap2-timer"; reg = <0x49018000 0x400>; interrupts = <37>; ti,hwmods = "timer1"; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts b/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts index 5a31964ae339..3705a81c1fc2 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -13,12 +13,6 @@ model = "TI OMAP3 BeagleBoard xM"; compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ @@ -26,6 +20,10 @@ leds { compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 0>; /* LEDB */ + }; heartbeat { label = "beagleboard::usr0"; @@ -40,16 +38,6 @@ }; }; - pwmleds { - compatible = "pwm-leds"; - - pmu_stat { - label = "beagleboard::pmu_stat"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; - }; - }; - sound { compatible = "ti,omap-twl4030"; ti,model = "omap3beagle"; @@ -119,9 +107,3 @@ */ ti,pulldowns = <0x03a1c4>; }; - -&usb_otg_hs { - interface-type = <0>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts index 6eec69997607..f624dc85d441 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts @@ -7,18 +7,12 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +/include/ "omap3.dtsi" / { model = "TI OMAP3 BeagleBoard"; compatible = "ti,omap3-beagle", "ti,omap3"; - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ @@ -44,57 +38,6 @@ }; }; - /* HS USB Port 2 RESET */ - hsusb2_reset: hsusb2_reset_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_reset"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 19 0>; /* gpio_147 */ - startup-delay-us = <70000>; - enable-active-high; - }; - - /* HS USB Port 2 Power */ - hsusb2_power: hsusb2_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb2_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { - compatible = "usb-nop-xceiv"; - reset-supply = <&hsusb2_reset>; - vcc-supply = <&hsusb2_power>; - }; -}; - -&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb2_pins - >; - - hsusbb2_pins: pinmux_hsusbb2_pins { - pinctrl-single,pins = < - 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */ - 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */ - 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */ - 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */ - 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */ - 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */ - 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */ - 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */ - 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */ - 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */ - 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */ - 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */ - >; - }; }; &i2c1 { @@ -122,23 +65,3 @@ &mmc3 { status = "disabled"; }; - -&usbhshost { - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - -&twl_gpio { - ti,use-leds; - /* pullups: BIT(1) */ - ti,pullups = <0x000002>; - /* - * pulldowns: - * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) - * BIT(15), BIT(16), BIT(17) - */ - ti,pulldowns = <0x03a1c4>; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-devkit8000.dts b/trunk/arch/arm/boot/dts/omap3-devkit8000.dts deleted file mode 100644 index 8a5cdcc6debd..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-devkit8000.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Author: Anil Kumar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap34xx.dtsi" -/ { - model = "TimLL OMAP3 Devkit8000"; - compatible = "timll,omap3-devkit8000", "ti,omap3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "devkit8000::led1"; - gpios = <&gpio6 26 0>; /* 186 -> LED1 */ - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "devkit8000::led2"; - gpios = <&gpio6 3 0>; /* 163 -> LED2 */ - default-state = "on"; - linux,default-trigger = "none"; - }; - - usr { - label = "devkit8000::led3"; - gpios = <&gpio6 4 0>; /* 164 -> LED3 */ - default-state = "on"; - linux,default-trigger = "usr"; - }; - - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "devkit8000"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - ti,audio-routing = - "Ext Spk", "PREDRIVEL", - "Ext Spk", "PREDRIVER", - "MAINMIC", "Main Mic", - "Main Mic", "Mic Bias 1"; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -/include/ "twl4030.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&wdt2 { - status = "disabled"; -}; - -&mcbsp1 { - status = "disabled"; -}; - -&mcbsp3 { - status = "disabled"; -}; - -&mcbsp4 { - status = "disabled"; -}; - -&mcbsp5 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ - - nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ - nand-bus-width = <16>; - - gpmc,sync-clk = <0>; - gpmc,cs-on = <0>; - gpmc,cs-rd-off = <44>; - gpmc,cs-wr-off = <44>; - gpmc,adv-on = <6>; - gpmc,adv-rd-off = <34>; - gpmc,adv-wr-off = <44>; - gpmc,we-off = <40>; - gpmc,oe-off = <54>; - gpmc,access = <64>; - gpmc,rd-cycle = <82>; - gpmc,wr-cycle = <82>; - gpmc,wr-access = <40>; - gpmc,wr-data-mux-bus = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - x-loader@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - - bootloaders@80000 { - label = "U-Boot"; - reg = <0x80000 0x1e0000>; - }; - - bootloaders_env@260000 { - label = "U-Boot Env"; - reg = <0x260000 0x20000>; - }; - - kernel@280000 { - label = "Kernel"; - reg = <0x280000 0x400000>; - }; - - filesystem@680000 { - label = "File System"; - reg = <0x680000 0xf980000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-evm.dts b/trunk/arch/arm/boot/dts/omap3-evm.dts index 05f51e10ddd6..e8ba1c247a39 100644 --- a/trunk/arch/arm/boot/dts/omap3-evm.dts +++ b/trunk/arch/arm/boot/dts/omap3-evm.dts @@ -7,18 +7,12 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +/include/ "omap3.dtsi" / { model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; compatible = "ti,omap3-evm", "ti,omap3"; - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ @@ -65,9 +59,3 @@ &twl_gpio { ti,use-leds; }; - -&usb_otg_hs { - interface-type = <0>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-igep.dtsi b/trunk/arch/arm/boot/dts/omap3-igep.dtsi deleted file mode 100644 index f8fe3b748c3e..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-igep.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Device Tree Source for IGEP Technology devices - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap34xx.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "igep2"; - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; -}; - -&omap3_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */ - 0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a 0x100 /* uart2_rx.uart2_rx INPUT | MODE0 */ - 0x148 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e 0x100 /* uart3_rx.uart3_rx INPUT | MODE0 */ - 0x170 0 /* uart3_tx.uart3_tx OUTPUT | MODE0 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 0x0118 /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */ - 0x116 0x0118 /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */ - 0x118 0x0118 /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */ - 0x11a 0x0118 /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */ - 0x11c 0x0118 /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */ - 0x11e 0x0118 /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */ - 0x120 0x0100 /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */ - 0x122 0x0100 /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */ - 0x124 0x0100 /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */ - 0x126 0x0100 /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -/include/ "twl4030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-igep0020.dts b/trunk/arch/arm/boot/dts/omap3-igep0020.dts deleted file mode 100644 index e2b98490cc9a..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-igep0020.dts +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Device Tree Source for IGEPv2 board - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/include/ "omap3-igep.dtsi" - -/ { - model = "IGEPv2"; - compatible = "isee,omap3-igep0020", "ti,omap3"; - - leds { - compatible = "gpio-leds"; - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 0>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 0>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 0>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 1>; - }; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-igep0030.dts b/trunk/arch/arm/boot/dts/omap3-igep0030.dts deleted file mode 100644 index 9dc48d262ffb..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-igep0030.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Device Tree Source for IGEP COM Module - * - * Copyright (C) 2012 Javier Martinez Canillas - * Copyright (C) 2012 Enric Balletbo i Serra - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/include/ "omap3-igep.dtsi" - -/ { - model = "IGEP COM Module"; - compatible = "isee,omap3-igep0030", "ti,omap3"; - - leds { - compatible = "gpio-leds"; - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 1>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 1>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 1>; /* LEDB */ - default-state = "off"; - }; - - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 1>; - default-state = "off"; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap3-overo.dtsi b/trunk/arch/arm/boot/dts/omap3-overo.dtsi index d4a7280d18b7..89808ce01673 100644 --- a/trunk/arch/arm/boot/dts/omap3-overo.dtsi +++ b/trunk/arch/arm/boot/dts/omap3-overo.dtsi @@ -11,26 +11,17 @@ */ /dts-v1/; -/include/ "omap34xx.dtsi" +/include/ "omap3.dtsi" / { - pwmleds { - compatible = "pwm-leds"; - + leds { + compatible = "gpio-leds"; overo { label = "overo:blue:COM"; - pwms = <&twl_pwmled 1 7812500>; - max-brightness = <127>; + gpios = <&twl_gpio 19 0>; + linux,default-trigger = "mmc0"; }; }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "overo"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; }; &i2c1 { @@ -40,12 +31,6 @@ reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; }; }; @@ -70,9 +55,3 @@ &twl_gpio { ti,use-leds; }; - -&usb_otg_hs { - interface-type = <0>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index 4ad03d9dbf0c..1acc26148ffc 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -26,14 +26,8 @@ }; }; - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - ti,hwmods = "debugss"; - }; - /* - * The soc node represents the soc top level view. It is used for IPs + * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { @@ -81,101 +75,76 @@ reg = <0x48200000 0x1000>; }; - sdma: dma-controller@48056000 { - compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; - reg = <0x48056000 0x1000>; - interrupts = <12>, - <13>, - <14>, - <15>; - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <96>; - }; - omap3_pmx_core: pinmux@48002030 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x48002030 0x05cc>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7f1f>; + pinctrl-single,function-mask = <0x7fff>; }; - omap3_pmx_wkup: pinmux@0x48002a00 { + omap3_pmx_wkup: pinmux@0x48002a58 { compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002a00 0x5c>; + reg = <0x48002a58 0x5c>; #address-cells = <1>; #size-cells = <0>; pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7f1f>; + pinctrl-single,function-mask = <0x7fff>; }; gpio1: gpio@48310000 { compatible = "ti,omap3-gpio"; - reg = <0x48310000 0x200>; - interrupts = <29>; ti,hwmods = "gpio1"; - ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio2: gpio@49050000 { compatible = "ti,omap3-gpio"; - reg = <0x49050000 0x200>; - interrupts = <30>; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio3: gpio@49052000 { compatible = "ti,omap3-gpio"; - reg = <0x49052000 0x200>; - interrupts = <31>; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio4: gpio@49054000 { compatible = "ti,omap3-gpio"; - reg = <0x49054000 0x200>; - interrupts = <32>; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio5: gpio@49056000 { compatible = "ti,omap3-gpio"; - reg = <0x49056000 0x200>; - interrupts = <33>; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio6: gpio@49058000 { compatible = "ti,omap3-gpio"; - reg = <0x49058000 0x200>; - interrupts = <34>; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; uart1: serial@4806a000 { @@ -223,16 +192,6 @@ #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { @@ -241,11 +200,6 @@ #size-cells = <0>; ti,hwmods = "mcspi2"; ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi3: spi@480b8000 { @@ -254,11 +208,6 @@ #size-cells = <0>; ti,hwmods = "mcspi3"; ti,spi-num-cs = <2>; - dmas = <&sdma 15>, - <&sdma 16>, - <&sdma 23>, - <&sdma 24>; - dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi4: spi@480ba000 { @@ -267,30 +216,22 @@ #size-cells = <0>; ti,hwmods = "mcspi4"; ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; }; mmc1: mmc@4809c000 { compatible = "ti,omap3-hsmmc"; ti,hwmods = "mmc1"; ti,dual-volt; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; }; mmc2: mmc@480b4000 { compatible = "ti,omap3-hsmmc"; ti,hwmods = "mmc2"; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; }; mmc3: mmc@480ad000 { compatible = "ti,omap3-hsmmc"; ti,hwmods = "mmc3"; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; }; wdt2: wdt@48314000 { @@ -308,9 +249,6 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; }; mcbsp2: mcbsp@49022000 { @@ -325,9 +263,6 @@ interrupt-names = "common", "tx", "rx", "sidetone"; ti,buffer-size = <1280>; ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; }; mcbsp3: mcbsp@49024000 { @@ -342,9 +277,6 @@ interrupt-names = "common", "tx", "rx", "sidetone"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; }; mcbsp4: mcbsp@49026000 { @@ -357,9 +289,6 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; }; mcbsp5: mcbsp@48096000 { @@ -372,13 +301,10 @@ interrupt-names = "common", "tx", "rx"; ti,buffer-size = <128>; ti,hwmods = "mcbsp5"; - dmas = <&sdma 21>, - <&sdma 22>; - dma-names = "tx", "rx"; }; timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48318000 0x400>; interrupts = <37>; ti,hwmods = "timer1"; @@ -386,28 +312,28 @@ }; timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x49032000 0x400>; interrupts = <38>; ti,hwmods = "timer2"; }; timer3: timer@49034000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x49034000 0x400>; interrupts = <39>; ti,hwmods = "timer3"; }; timer4: timer@49036000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x49036000 0x400>; interrupts = <40>; ti,hwmods = "timer4"; }; timer5: timer@49038000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x49038000 0x400>; interrupts = <41>; ti,hwmods = "timer5"; @@ -415,7 +341,7 @@ }; timer6: timer@4903a000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4903a000 0x400>; interrupts = <42>; ti,hwmods = "timer6"; @@ -423,7 +349,7 @@ }; timer7: timer@4903c000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4903c000 0x400>; interrupts = <43>; ti,hwmods = "timer7"; @@ -431,7 +357,7 @@ }; timer8: timer@4903e000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4903e000 0x400>; interrupts = <44>; ti,hwmods = "timer8"; @@ -440,7 +366,7 @@ }; timer9: timer@49040000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x49040000 0x400>; interrupts = <45>; ti,hwmods = "timer9"; @@ -448,7 +374,7 @@ }; timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48086000 0x400>; interrupts = <46>; ti,hwmods = "timer10"; @@ -456,7 +382,7 @@ }; timer11: timer@48088000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48088000 0x400>; interrupts = <47>; ti,hwmods = "timer11"; @@ -464,65 +390,12 @@ }; timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48304000 0x400>; interrupts = <95>; ti,hwmods = "timer12"; ti,timer-alwon; ti,timer-secure; }; - - usbhstll: usbhstll@48062000 { - compatible = "ti,usbhs-tll"; - reg = <0x48062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@48064000 { - compatible = "ti,usbhs-host"; - reg = <0x48064000 0x400>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@48064400 { - compatible = "ti,ohci-omap3", "usb-ohci"; - reg = <0x48064400 0x400>; - interrupt-parent = <&intc>; - interrupts = <76>; - }; - - usbhsehci: ehci@48064800 { - compatible = "ti,ehci-omap", "usb-ehci"; - reg = <0x48064800 0x400>; - interrupt-parent = <&intc>; - interrupts = <77>; - }; - }; - - gpmc: gpmc@6e000000 { - compatible = "ti,omap3430-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x6e000000 0x02d0>; - interrupts = <20>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - #address-cells = <2>; - #size-cells = <1>; - }; - - usb_otg_hs: usb_otg_hs@480ab000 { - compatible = "ti,omap3-musb"; - reg = <0x480ab000 0x1000>; - interrupts = <0 92 0x4>, <0 93 0x4>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - usb-phy = <&usb2_phy>; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap3430-sdp.dts b/trunk/arch/arm/boot/dts/omap3430-sdp.dts deleted file mode 100644 index 144ae43453c4..000000000000 --- a/trunk/arch/arm/boot/dts/omap3430-sdp.dts +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap34xx.dtsi" - -/ { - model = "TI OMAP3430 SDP"; - compatible = "ti,omap3430-sdp", "ti,omap3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - }; -}; - -/include/ "twl4030.dtsi" - -&mmc1 { - vmmc-supply = <&vmmc1>; - vmmc_aux-supply = <&vsim>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x08000000>, - <2 0 0x20000000 0x10000000>; - - nor@0,0 { - compatible = "cfi-flash"; - linux,mtd-name= "intel,pf48f6000m0y1be"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x08000000>; - bank-width = <2>; - - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <186>; - gpmc,cs-wr-off-ns = <186>; - gpmc,adv-on-ns = <12>; - gpmc,adv-rd-off-ns = <48>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <114>; - gpmc,page-burst-access-ns = <6>; - gpmc,bus-turnaround-ns = <12>; - gpmc,cycle2cycle-delay-ns = <18>; - gpmc,wr-data-mux-bus-ns = <90>; - gpmc,wr-access-ns = <186>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; - - partition@0 { - label = "bootloader-nor"; - reg = <0 0x40000>; - }; - partition@0x40000 { - label = "params-nor"; - reg = <0x40000 0x40000>; - }; - partition@0x80000 { - label = "kernel-nor"; - reg = <0x80000 0x200000>; - }; - partition@0x280000 { - label = "filesystem-nor"; - reg = <0x240000 0x7d80000>; - }; - }; - - nand@1,0 { - linux,mtd-name= "micron,mt29f1g08abb"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1 0 0x08000000>; - nand-bus-width = <8>; - - ti,nand-ecc-opt = "sw"; - gpmc,device-nand; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <36>; - gpmc,cs-wr-off-ns = <36>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <24>; - gpmc,adv-wr-off-ns = <36>; - gpmc,oe-on-ns = <6>; - gpmc,oe-off-ns = <48>; - gpmc,we-on-ns = <6>; - gpmc,we-off-ns = <30>; - gpmc,rd-cycle-ns = <72>; - gpmc,wr-cycle-ns = <72>; - gpmc,access-ns = <54>; - gpmc,wr-access-ns = <30>; - - partition@0 { - label = "xloader-nand"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "bootloader-nand"; - reg = <0x80000 0x140000>; - }; - partition@0x1c0000 { - label = "params-nand"; - reg = <0x1c0000 0xc0000>; - }; - partition@0x280000 { - label = "kernel-nand"; - reg = <0x280000 0x500000>; - }; - partition@0x780000 { - label = "filesystem-nand"; - reg = <0x780000 0x7880000>; - }; - }; - - onenand@2,0 { - linux,mtd-name= "samsung,kfm2g16q2m-deb8"; - #address-cells = <1>; - #size-cells = <1>; - reg = <2 0 0x10000000>; - - gpmc,device-width = <2>; - gpmc,mux-add-data = <2>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <84>; - gpmc,cs-wr-off-ns = <72>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <18>; - gpmc,oe-on-ns = <30>; - gpmc,oe-off-ns = <84>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <42>; - gpmc,rd-cycle-ns = <108>; - gpmc,wr-cycle-ns = <96>; - gpmc,access-ns = <78>; - gpmc,wr-data-mux-bus-ns = <30>; - - partition@0 { - label = "xloader-onenand"; - reg = <0 0x80000>; - }; - partition@0x80000 { - label = "bootloader-onenand"; - reg = <0x80000 0x40000>; - }; - partition@0xc0000 { - label = "params-onenand"; - reg = <0xc0000 0x20000>; - }; - partition@0xe0000 { - label = "kernel-onenand"; - reg = <0xe0000 0x200000>; - }; - partition@0x2e0000 { - label = "filesystem-onenand"; - reg = <0x2e0000 0xfd20000>; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap34xx.dtsi b/trunk/arch/arm/boot/dts/omap34xx.dtsi deleted file mode 100644 index 75ed4ae2e631..000000000000 --- a/trunk/arch/arm/boot/dts/omap34xx.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Device Tree Source for OMAP34xx/OMAP35xx SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "omap3.dtsi" - -/ { - cpus { - cpu@0 { - /* OMAP343x/OMAP35xx variants OPP1-5 */ - operating-points = < - /* kHz uV */ - 125000 975000 - 250000 1075000 - 500000 1200000 - 550000 1270000 - 600000 1350000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap36xx.dtsi b/trunk/arch/arm/boot/dts/omap36xx.dtsi index b89233e43b0f..96bf0287cb9f 100644 --- a/trunk/arch/arm/boot/dts/omap36xx.dtsi +++ b/trunk/arch/arm/boot/dts/omap36xx.dtsi @@ -15,19 +15,6 @@ serial3 = &uart4; }; - cpus { - /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ - cpu@0 { - operating-points = < - /* kHz uV */ - 300000 975000 - 600000 1075000 - 800000 1200000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - ocp { uart4: serial@49042000 { compatible = "ti,omap3-uart"; diff --git a/trunk/arch/arm/boot/dts/omap4-panda-a4.dts b/trunk/arch/arm/boot/dts/omap4-panda-a4.dts index e30cdf0f5ac1..75466d2abfb5 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda-a4.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda-a4.dts @@ -5,10 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -/include/ "omap443x.dtsi" -/include/ "omap4-panda-common.dtsi" +/include/ "omap4-panda.dts" /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ &dss_hdmi_pins { diff --git a/trunk/arch/arm/boot/dts/omap4-panda-common.dtsi b/trunk/arch/arm/boot/dts/omap4-panda-common.dtsi deleted file mode 100644 index 03bd60deb52b..000000000000 --- a/trunk/arch/arm/boot/dts/omap4-panda-common.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/include/ "elpida_ecb240abacn.dtsi" - -/ { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - leds { - compatible = "gpio-leds"; - heartbeat { - label = "pandaboard::status1"; - gpios = <&gpio1 7 0>; - linux,default-trigger = "heartbeat"; - }; - - mmc { - label = "pandaboard::status2"; - gpios = <&gpio1 8 0>; - linux,default-trigger = "mmc0"; - }; - }; - - sound: sound { - compatible = "ti,abe-twl6040"; - ti,model = "PandaBoard"; - - ti,mclk-freq = <38400000>; - - ti,mcpdm = <&mcpdm>; - - ti,twl6040 = <&twl6040>; - - /* Audio routing */ - ti,audio-routing = - "Headset Stereophone", "HSOL", - "Headset Stereophone", "HSOR", - "Ext Spk", "HFL", - "Ext Spk", "HFR", - "Line Out", "AUXL", - "Line Out", "AUXR", - "HSMIC", "Headset Mic", - "Headset Mic", "Headset Mic Bias", - "AFML", "Line In", - "AFMR", "Line In"; - }; -}; - -&omap4_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &twl6040_pins - &mcpdm_pins - &mcbsp1_pins - &dss_hdmi_pins - &tpd12s015_pins - >; - - twl6040_pins: pinmux_twl6040_pins { - pinctrl-single,pins = < - 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ - 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ - >; - }; - - mcpdm_pins: pinmux_mcpdm_pins { - pinctrl-single,pins = < - 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ - 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ - 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ - 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ - 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ - >; - }; - - mcbsp1_pins: pinmux_mcbsp1_pins { - pinctrl-single,pins = < - 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ - 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ - 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ - 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ - >; - }; - - dss_hdmi_pins: pinmux_dss_hdmi_pins { - pinctrl-single,pins = < - 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ - 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ - 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ - 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ - 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ - 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ - 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; - }; - - twl6040: twl@4b { - compatible = "ti,twl6040"; - reg = <0x4b>; - /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ - interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; - ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ - - vio-supply = <&v1v8>; - v2v1-supply = <&v2v1>; - enable-active-high; - }; -}; - -/include/ "twl6030.dtsi" - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in their EEPROM as EDID data. - * The EEPROM is connected as I2C slave device. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - - clock-frequency = <400000>; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - bus-width = <8>; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - ti,non-removable; - bus-width = <4>; -}; - -&emif1 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&emif2 { - cs1-used; - device-handle = <&elpida_ECB240ABACN>; -}; - -&mcbsp2 { - status = "disabled"; -}; - -&mcbsp3 { - status = "disabled"; -}; - -&dmic { - status = "disabled"; -}; - -&twl_usb_comparator { - usb-supply = <&vusb>; -}; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/arch/arm/boot/dts/omap4-panda-es.dts b/trunk/arch/arm/boot/dts/omap4-panda-es.dts index f1d8c217ce12..73bc1a67e444 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda-es.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda-es.dts @@ -5,10 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -/include/ "omap4460.dtsi" -/include/ "omap4-panda-common.dtsi" +/include/ "omap4-panda.dts" /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ &sound { diff --git a/trunk/arch/arm/boot/dts/omap4-panda.dts b/trunk/arch/arm/boot/dts/omap4-panda.dts index f8b221f0168e..4122efe31cfd 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda.dts @@ -7,5 +7,202 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" -/include/ "omap4-panda-common.dtsi" +/include/ "omap4.dtsi" +/include/ "elpida_ecb240abacn.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "pandaboard::status1"; + gpios = <&gpio1 7 0>; + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "pandaboard::status2"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "mmc0"; + }; + }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "PandaBoard"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &twl6040_pins + &mcpdm_pins + &mcbsp1_pins + &dss_hdmi_pins + &tpd12s015_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ + 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ + 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ + 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ + 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ + 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ + >; + }; + + mcbsp1_pins: pinmux_mcbsp1_pins { + pinctrl-single,pins = < + 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ + 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ + 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ + 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ + >; + }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ + 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ + 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ + 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ + 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +/include/ "twl6030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in their EEPROM as EDID data. + * The EEPROM is connected as I2C slave device. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + ti,non-removable; + bus-width = <4>; +}; + +&emif1 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&emif2 { + cs1-used; + device-handle = <&elpida_ECB240ABACN>; +}; + +&mcbsp2 { + status = "disabled"; +}; + +&mcbsp3 { + status = "disabled"; +}; + +&dmic { + status = "disabled"; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; diff --git a/trunk/arch/arm/boot/dts/omap4-sdp.dts b/trunk/arch/arm/boot/dts/omap4-sdp.dts index c387bdc1b1d1..43e5258a9372 100644 --- a/trunk/arch/arm/boot/dts/omap4-sdp.dts +++ b/trunk/arch/arm/boot/dts/omap4-sdp.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" +/include/ "omap4.dtsi" /include/ "elpida_ecb240abacn.dtsi" / { @@ -80,32 +80,6 @@ }; }; - pwmleds { - compatible = "pwm-leds"; - kpad { - label = "omap4::keypad"; - pwms = <&twl_pwm 0 7812500>; - max-brightness = <127>; - }; - - charging { - label = "omap4:green:chrg"; - pwms = <&twl_pwmled 0 7812500>; - max-brightness = <255>; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&twl_pwm 1 7812500>; - brightness-levels = < - 0 10 20 30 40 - 50 60 70 80 90 - 100 110 120 127 - >; - default-brightness-level = <13>; - }; - sound { compatible = "ti,abe-twl6040"; ti,model = "SDP4430"; @@ -238,40 +212,9 @@ 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ >; }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ - 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ - 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ - 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; twl: twl@48 { @@ -310,16 +253,10 @@ /include/ "twl6030.dtsi" &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; }; &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; /* @@ -342,9 +279,6 @@ }; &i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; /* @@ -494,9 +428,3 @@ &twl_usb_comparator { usb-supply = <&vusb>; }; - -&usb_otg_hs { - interface-type = <1>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/arch/arm/boot/dts/omap4-var-som.dts b/trunk/arch/arm/boot/dts/omap4-var-som.dts index 222a413c2c51..6601e6af6092 100644 --- a/trunk/arch/arm/boot/dts/omap4-var-som.dts +++ b/trunk/arch/arm/boot/dts/omap4-var-som.dts @@ -7,7 +7,7 @@ */ /dts-v1/; -/include/ "omap443x.dtsi" +/include/ "omap4.dtsi" / { model = "Variscite OMAP4 SOM"; diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index 2a5642882c8a..739bb79e410e 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -94,11 +94,6 @@ #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x1000>, - <0x44800000 0x2000>, - <0x45000000 0x1000>; - interrupts = <0 9 0x4>, - <0 10 0x4>; counter32k: counter@4a304000 { compatible = "ti,omap-counter32k"; @@ -123,28 +118,15 @@ pinctrl-single,function-mask = <0x7fff>; }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = <0 12 0x4>, - <0 13 0x4>, - <0 14 0x4>, - <0 15 0x4>; - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <127>; - }; - gpio1: gpio@4a310000 { compatible = "ti,omap4-gpio"; reg = <0x4a310000 0x200>; interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; - ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio2: gpio@48055000 { @@ -155,7 +137,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio3: gpio@48057000 { @@ -166,7 +148,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio4: gpio@48059000 { @@ -177,7 +159,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio5: gpio@4805b000 { @@ -188,7 +170,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio6: gpio@4805d000 { @@ -199,18 +181,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <0 20 0x4>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; + #interrupt-cells = <1>; }; uart1: serial@4806a000 { @@ -289,16 +260,6 @@ #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { @@ -309,11 +270,6 @@ #size-cells = <0>; ti,hwmods = "mcspi2"; ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi3: spi@480b8000 { @@ -324,8 +280,6 @@ #size-cells = <0>; ti,hwmods = "mcspi3"; ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; }; mcspi4: spi@480ba000 { @@ -336,8 +290,6 @@ #size-cells = <0>; ti,hwmods = "mcspi4"; ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; }; mmc1: mmc@4809c000 { @@ -347,8 +299,6 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; }; mmc2: mmc@480b4000 { @@ -357,8 +307,6 @@ interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; }; mmc3: mmc@480ad000 { @@ -367,8 +315,6 @@ interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; }; mmc4: mmc@480d1000 { @@ -377,8 +323,6 @@ interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; }; mmc5: mmc@480d5000 { @@ -387,8 +331,6 @@ interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; }; wdt2: wdt@4a314000 { @@ -405,9 +347,6 @@ reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; }; dmic: dmic@4012e000 { @@ -417,8 +356,6 @@ reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; }; mcbsp1: mcbsp@40122000 { @@ -430,9 +367,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; }; mcbsp2: mcbsp@40124000 { @@ -444,9 +378,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; }; mcbsp3: mcbsp@40126000 { @@ -458,9 +389,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; }; mcbsp4: mcbsp@48096000 { @@ -471,9 +399,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp4"; - dmas = <&sdma 31>, - <&sdma 32>; - dma-names = "tx", "rx"; }; keypad: keypad@4a31c000 { @@ -513,15 +438,10 @@ #size-cells = <1>; ranges; ti,hwmods = "ocp2scp_usb_phy"; - usb2_phy: usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb>; - }; }; timer1: timer@4a318000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4a318000 0x80>; interrupts = <0 37 0x4>; ti,hwmods = "timer1"; @@ -529,28 +449,28 @@ }; timer2: timer@48032000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48032000 0x80>; interrupts = <0 38 0x4>; ti,hwmods = "timer2"; }; timer3: timer@48034000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48034000 0x80>; interrupts = <0 39 0x4>; ti,hwmods = "timer3"; }; timer4: timer@48036000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48036000 0x80>; interrupts = <0 40 0x4>; ti,hwmods = "timer4"; }; timer5: timer@40138000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x40138000 0x80>, <0x49038000 0x80>; interrupts = <0 41 0x4>; @@ -559,7 +479,7 @@ }; timer6: timer@4013a000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013a000 0x80>, <0x4903a000 0x80>; interrupts = <0 42 0x4>; @@ -568,7 +488,7 @@ }; timer7: timer@4013c000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013c000 0x80>, <0x4903c000 0x80>; interrupts = <0 43 0x4>; @@ -577,7 +497,7 @@ }; timer8: timer@4013e000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013e000 0x80>, <0x4903e000 0x80>; interrupts = <0 44 0x4>; @@ -587,7 +507,7 @@ }; timer9: timer@4803e000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4803e000 0x80>; interrupts = <0 45 0x4>; ti,hwmods = "timer9"; @@ -595,7 +515,7 @@ }; timer10: timer@48086000 { - compatible = "ti,omap3430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48086000 0x80>; interrupts = <0 46 0x4>; ti,hwmods = "timer10"; @@ -603,62 +523,11 @@ }; timer11: timer@48088000 { - compatible = "ti,omap4430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48088000 0x80>; interrupts = <0 47 0x4>; ti,hwmods = "timer11"; ti,timer-pwm; }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = <0 78 0x4>; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3", "usb-ohci"; - reg = <0x4a064800 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap", "usb-ehci"; - reg = <0x4a064c00 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; - }; - }; - - omap_control_usb: omap-control-usb@4a002300 { - compatible = "ti,omap-control-usb"; - reg = <0x4a002300 0x4>, - <0x4a00233c 0x4>; - reg-names = "control_dev_conf", "otghs_control"; - ti,type = <1>; - }; - - usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - reg = <0x4a0ab000 0x7ff>; - interrupts = <0 92 0x4>, <0 93 0x4>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - usb-phy = <&usb2_phy>; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; - ti,has-mailbox; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap443x.dtsi b/trunk/arch/arm/boot/dts/omap443x.dtsi deleted file mode 100644 index cccf39af4925..000000000000 --- a/trunk/arch/arm/boot/dts/omap443x.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Device Tree Source for OMAP443x SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/include/ "omap4.dtsi" - -/ { - cpus { - cpu@0 { - /* OMAP443x variants OPP50-OPPNT */ - operating-points = < - /* kHz uV */ - 300000 1025000 - 600000 1200000 - 800000 1313000 - 1008000 1375000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap4460.dtsi b/trunk/arch/arm/boot/dts/omap4460.dtsi deleted file mode 100644 index 7c2c23cc17ef..000000000000 --- a/trunk/arch/arm/boot/dts/omap4460.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Device Tree Source for OMAP4460 SoC - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ -/include/ "omap4.dtsi" - -/ { - cpus { - /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */ - cpu@0 { - operating-points = < - /* kHz uV */ - 350000 975000 - 700000 1075000 - 920000 1200000 - >; - clock-latency = <300000>; /* From legacy driver */ - }; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 54 0x4>, - <0 55 0x4>; - ti,hwmods = "debugss"; - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap5-evm.dts b/trunk/arch/arm/boot/dts/omap5-evm.dts index 982acd19477d..8722c15bbba2 100644 --- a/trunk/arch/arm/boot/dts/omap5-evm.dts +++ b/trunk/arch/arm/boot/dts/omap5-evm.dts @@ -16,7 +16,7 @@ memory { device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2032 MB */ + reg = <0x80000000 0x80000000>; /* 2 GB */ }; vmmcsd_fixed: fixedregulator-mmcsd { @@ -80,68 +80,6 @@ 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */ >; }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x1b2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ - 0x1b4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x178 0x100 /* i2c2_scl INPUTENABLE | MODE0 */ - 0x17a 0x100 /* i2c2_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - 0x13a 0x100 /* i2c3_scl INPUTENABLE | MODE0 */ - 0x13c 0x100 /* i2c3_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c4_pins: pinmux_i2c4_pins { - pinctrl-single,pins = < - 0xb8 0x100 /* i2c4_scl INPUTENABLE | MODE0 */ - 0xba 0x100 /* i2c4_sda INPUTENABLE | MODE0 */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x184 0x100 /* i2c5_scl INPUTENABLE | MODE0 */ - 0x186 0x100 /* i2c5_sda INPUTENABLE | MODE0 */ - >; - }; - - mcspi2_pins: pinmux_mcspi2_pins { - pinctrl-single,pins = < - 0xbc 0x100 /* MCSPI2_CLK INPUTENABLE | MODE0 */ - 0xbe 0x100 /* MCSPI2_SIMO INPUTENABLE | MODE0 */ - 0xc0 0x118 /* MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/ - 0xc2 0x0 /* MCSPI2_CS MODE0*/ - >; - }; - - mcspi3_pins: pinmux_mcspi3_pins { - pinctrl-single,pins = < - 0x78 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ - 0x7a 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ - 0x7c 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ - 0x7e 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ - >; - }; - - mcspi4_pins: pinmux_mcspi4_pins { - pinctrl-single,pins = < - 0x164 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ - 0x168 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ - 0x16a 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ - 0x16c 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ - >; - }; }; &mmc1 { @@ -168,17 +106,7 @@ status = "disabled"; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - clock-frequency = <400000>; -}; - &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; /* Pressure Sensor */ @@ -188,17 +116,7 @@ }; }; -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - - clock-frequency = <400000>; -}; - &i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; /* Temperature Sensor */ @@ -208,13 +126,6 @@ }; }; -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - - clock-frequency = <400000>; -}; - &keypad { keypad,num-rows = <8>; keypad,num-columns = <8>; @@ -240,22 +151,3 @@ cs1-used; device-handle = <&samsung_K3PE0E000B>; }; - -&mcspi1 { - -}; - -&mcspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; -}; - -&mcspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi3_pins>; -}; - -&mcspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi4_pins>; -}; diff --git a/trunk/arch/arm/boot/dts/omap5.dtsi b/trunk/arch/arm/boot/dts/omap5.dtsi index 3dd7ff825828..790bb2a4b343 100644 --- a/trunk/arch/arm/boot/dts/omap5.dtsi +++ b/trunk/arch/arm/boot/dts/omap5.dtsi @@ -18,9 +18,6 @@ /include/ "skeleton.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,omap5"; interrupt-parent = <&gic>; @@ -36,32 +33,24 @@ cpus { cpu@0 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; cpu@1 { compatible = "arm,cortex-a15"; + timer { + compatible = "arm,armv7-timer"; + /* 14th PPI IRQ, active low level-sensitive */ + interrupts = <1 14 0x308>; + clock-frequency = <6144000>; + }; }; }; - timer { - compatible = "arm,armv7-timer"; - /* PPI secure/nonsecure IRQ, active low level-sensitive */ - interrupts = <1 13 0x308>, - <1 14 0x308>, - <1 11 0x308>, - <1 10 0x308>; - clock-frequency = <6144000>; - }; - - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>, - <0x48214000 0x2000>, - <0x48216000 0x2000>; - }; - /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -87,11 +76,6 @@ #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>, - <0x45000000 0x4000>; - interrupts = <0 9 0x4>, - <0 10 0x4>; counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; @@ -116,16 +100,12 @@ pinctrl-single,function-mask = <0x7fff>; }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = <0 12 0x4>, - <0 13 0x4>, - <0 14 0x4>, - <0 15 0x4>; - #dma-cells = <1>; - #dma-channels = <32>; - #dma-requests = <127>; + gic: interrupt-controller@48211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48211000 0x1000>, + <0x48212000 0x1000>; }; gpio1: gpio@4ae10000 { @@ -133,11 +113,10 @@ reg = <0x4ae10000 0x200>; interrupts = <0 29 0x4>; ti,hwmods = "gpio1"; - ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio2: gpio@48055000 { @@ -148,7 +127,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio3: gpio@48057000 { @@ -159,7 +138,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio4: gpio@48059000 { @@ -170,7 +149,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio5: gpio@4805b000 { @@ -181,7 +160,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio6: gpio@4805d000 { @@ -192,7 +171,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio7: gpio@48051000 { @@ -203,7 +182,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; }; gpio8: gpio@48053000 { @@ -214,18 +193,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <0 20 0x4>; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; + #interrupt-cells = <1>; }; i2c1: i2c@48070000 { @@ -273,65 +241,6 @@ ti,hwmods = "i2c5"; }; - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = <0 65 0x4>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = <0 66 0x4>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = <0 91 0x4>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = <0 48 0x4>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; @@ -387,8 +296,6 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; }; mmc2: mmc@480b4000 { @@ -397,8 +304,6 @@ interrupts = <0 86 0x4>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; }; mmc3: mmc@480ad000 { @@ -407,8 +312,6 @@ interrupts = <0 94 0x4>; ti,hwmods = "mmc3"; ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; }; mmc4: mmc@480d1000 { @@ -417,8 +320,6 @@ interrupts = <0 96 0x4>; ti,hwmods = "mmc4"; ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; }; mmc5: mmc@480d5000 { @@ -427,13 +328,10 @@ interrupts = <0 59 0x4>; ti,hwmods = "mmc5"; ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; }; keypad: keypad@4ae1c000 { compatible = "ti,omap4-keypad"; - reg = <0x4ae1c000 0x400>; ti,hwmods = "kbd"; }; @@ -444,9 +342,6 @@ reg-names = "mpu", "dma"; interrupts = <0 112 0x4>; ti,hwmods = "mcpdm"; - dmas = <&sdma 65>, - <&sdma 66>; - dma-names = "up_link", "dn_link"; }; dmic: dmic@4012e000 { @@ -456,8 +351,6 @@ reg-names = "mpu", "dma"; interrupts = <0 114 0x4>; ti,hwmods = "dmic"; - dmas = <&sdma 67>; - dma-names = "up_link"; }; mcbsp1: mcbsp@40122000 { @@ -469,9 +362,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; - dmas = <&sdma 33>, - <&sdma 34>; - dma-names = "tx", "rx"; }; mcbsp2: mcbsp@40124000 { @@ -483,9 +373,6 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; - dmas = <&sdma 17>, - <&sdma 18>; - dma-names = "tx", "rx"; }; mcbsp3: mcbsp@40126000 { @@ -497,13 +384,10 @@ interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; - dmas = <&sdma 19>, - <&sdma 20>; - dma-names = "tx", "rx"; }; timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4ae18000 0x80>; interrupts = <0 37 0x4>; ti,hwmods = "timer1"; @@ -511,28 +395,28 @@ }; timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48032000 0x80>; interrupts = <0 38 0x4>; ti,hwmods = "timer2"; }; timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48034000 0x80>; interrupts = <0 39 0x4>; ti,hwmods = "timer3"; }; timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48036000 0x80>; interrupts = <0 40 0x4>; ti,hwmods = "timer4"; }; timer5: timer@40138000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x40138000 0x80>, <0x49038000 0x80>; interrupts = <0 41 0x4>; @@ -541,7 +425,7 @@ }; timer6: timer@4013a000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013a000 0x80>, <0x4903a000 0x80>; interrupts = <0 42 0x4>; @@ -551,7 +435,7 @@ }; timer7: timer@4013c000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013c000 0x80>, <0x4903c000 0x80>; interrupts = <0 43 0x4>; @@ -560,7 +444,7 @@ }; timer8: timer@4013e000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4013e000 0x80>, <0x4903e000 0x80>; interrupts = <0 44 0x4>; @@ -570,34 +454,27 @@ }; timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x4803e000 0x80>; interrupts = <0 45 0x4>; ti,hwmods = "timer9"; }; timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48086000 0x80>; interrupts = <0 46 0x4>; ti,hwmods = "timer10"; }; timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; + compatible = "ti,omap2-timer"; reg = <0x48088000 0x80>; interrupts = <0 47 0x4>; ti,hwmods = "timer11"; ti,timer-pwm; }; - wdt2: wdt@4ae14000 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = <0 80 0x4>; - ti,hwmods = "wd_timer2"; - }; - emif1: emif@0x4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; @@ -619,53 +496,5 @@ hw-caps-ll-interface; hw-caps-temp-alert; }; - - omap_control_usb: omap-control-usb@4a002300 { - compatible = "ti,omap-control-usb"; - reg = <0x4a002300 0x4>, - <0x4a002370 0x4>; - reg-names = "control_dev_conf", "phy_power_usb"; - ti,type = <2>; - }; - - omap_dwc3@4a020000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss"; - reg = <0x4a020000 0x1000>; - interrupts = <0 93 4>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - dwc3@4a030000 { - compatible = "synopsys,dwc3"; - reg = <0x4a030000 0x1000>; - interrupts = <0 92 4>; - usb-phy = <&usb2_phy>, <&usb3_phy>; - tx-fifo-resize; - }; - }; - - ocp2scp { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp1"; - usb2_phy: usb2phy@4a084000 { - compatible = "ti,omap-usb2"; - reg = <0x4a084000 0x7c>; - ctrl-module = <&omap_control_usb>; - }; - - usb3_phy: usb3phy@4a084400 { - compatible = "ti,omap-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb>; - }; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/orion5x.dtsi b/trunk/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..892c64e3f1e1 100644 --- a/trunk/arch/arm/boot/dts/orion5x.dtsi +++ b/trunk/arch/arm/boot/dts/orion5x.dtsi @@ -13,6 +13,9 @@ compatible = "marvell,orion5x"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + }; intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller; @@ -32,7 +35,9 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; interrupts = <6>, <7>, <8>, <9>; }; @@ -69,6 +74,20 @@ status = "okay"; }; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; @@ -86,12 +105,31 @@ status = "disabled"; }; + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor00 { + interrupts = <30>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <31>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + crypto@90000 { compatible = "marvell,orion-crypto"; reg = <0x90000 0x10000>, <0xf2200000 0x800>; reg-names = "regs", "sram"; - interrupts = <22>; + interrupts = <28>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/skeleton64.dtsi b/trunk/arch/arm/boot/dts/skeleton64.dtsi new file mode 100644 index 000000000000..15994158a998 --- /dev/null +++ b/trunk/arch/arm/boot/dts/skeleton64.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/trunk/arch/arm/boot/dts/snowball.dts b/trunk/arch/arm/boot/dts/snowball.dts index d3ec32f6b790..27f31a5fa494 100644 --- a/trunk/arch/arm/boot/dts/snowball.dts +++ b/trunk/arch/arm/boot/dts/snowball.dts @@ -298,7 +298,7 @@ }; }; - ab8500 { + ab8500@5 { ab8500-regulators { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; diff --git a/trunk/arch/arm/boot/dts/socfpga.dtsi b/trunk/arch/arm/boot/dts/socfpga.dtsi index 7e8769bd5977..936d2306e7e1 100644 --- a/trunk/arch/arm/boot/dts/socfpga.dtsi +++ b/trunk/arch/arm/boot/dts/socfpga.dtsi @@ -75,9 +75,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; interrupts = <0 180 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts index 72c1f27af7f3..a30aca62658a 100644 --- a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts @@ -10,915 +10,12 @@ reg = <0x80000000 0x40000000>; }; - pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk1_out_pw4 { - nvidia,pins = "clk1_out_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2", - "dap1_fs_pn0", - "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", - "dap4_fs_pp4", - "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_data0_po1", - "ulpi_data1_po2", - "ulpi_data2_po3", - "ulpi_data3_po4", - "ulpi_data4_po5", - "ulpi_data5_po6", - "ulpi_data6_po7", - "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1", - "ulpi_nxt_py2"; - nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0", - "pbb0"; - nvidia,function = "vi_alt3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - nvidia,lock = <0>; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; - }; - gmi_a16_pj7 { - nvidia,pins = "gmi_a16_pj7"; - nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_a17_pb0 { - nvidia,pins = "gmi_a17_pb0", - "gmi_a18_pb1"; - nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - gmi_a19_pk7 { - nvidia,pins = "gmi_a19_pk7"; - nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_ad5_pg5 { - nvidia,pins = "gmi_ad5_pg5", - "gmi_cs6_n_pi3", - "gmi_wr_n_pi0"; - nvidia,function = "spi4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gmi_ad6_pg6 { - nvidia,pins = "gmi_ad6_pg6", - "gmi_ad7_pg7"; - nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gmi_ad12_ph4 { - nvidia,pins = "gmi_ad12_ph4"; - nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_ad9_ph1 { - nvidia,pins = "gmi_ad9_ph1"; - nvidia,function = "pwm1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_cs1_n_pj2 { - nvidia,pins = "gmi_cs1_n_pj2", - "gmi_oe_n_pi1"; - nvidia,function = "soc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "blink"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0", - "kb_col1_pq1", - "kb_col2_pq2", - "kb_row0_pr0", - "kb_row1_pr1", - "kb_row2_pr2"; - nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1", - "dap3_sclk_pp3"; - nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; - }; - sys_clk_req_pz5 { - nvidia,pins = "sys_clk_req_pz5"; - nvidia,function = "sysclk"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1", - "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0", - "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "owr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,rcv-sel = <1>; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <1>; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4", - "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - pbb3 { - nvidia,pins = "pbb3", - "pbb5", - "pbb6", - "pbb7"; - nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pcc1 { - nvidia,pins = "pcc1", - "pcc2"; - nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gmi_ad0_pg0 { - nvidia,pins = "gmi_ad0_pg0", - "gmi_ad1_pg1"; - nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_ad10_ph2 { - nvidia,pins = "gmi_ad10_ph2", - "gmi_ad11_ph3", - "gmi_ad13_ph5", - "gmi_ad8_ph0", - "gmi_clk_pk1"; - nvidia,function = "gmi"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - gmi_ad2_pg2 { - nvidia,pins = "gmi_ad2_pg2", - "gmi_ad3_pg3"; - nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gmi_adv_n_pk0 { - nvidia,pins = "gmi_adv_n_pk0", - "gmi_cs0_n_pj0", - "gmi_cs2_n_pk3", - "gmi_cs4_n_pk2", - "gmi_cs7_n_pi6", - "gmi_dqs_p_pj3", - "gmi_iordy_pi5", - "gmi_wp_n_pc7"; - nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - gmi_cs3_n_pk4 { - nvidia,pins = "gmi_cs3_n_pk4"; - nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3", - "kb_col6_pq6", - "kb_col7_pq7"; - nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3", - "kb_row4_pr4", - "kb_row6_pr6", - "kb_row8_ps0"; - nvidia,function = "kbc"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - }; - pu5 { - nvidia,pins = "pu5", - "pu6"; - nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - }; - clk1_req_pee2 { - nvidia,pins = "clk1_req_pee2", - "usb_vbus_en1_pn5"; - nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <2>; - nvidia,slew-rate-falling = <2>; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; - nvidia,drive-type = <1>; - }; - }; - }; - serial@70006300 { status = "okay"; - }; - - i2c@7000c000 { - status = "okay"; - clock-frequency = <100000>; - - battery: smart-battery { - compatible = "ti,bq20z45", "sbs,sbs-battery"; - reg = <0xb>; - battery-name = "battery"; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <100>; - }; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - tps51632 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1520000>; - regulator-boot-on; - regulator-always-on; - }; - - tps65090 { - compatible = "ti,tps65090"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = <72 0x04>; /* gpio PJ0 */ - - vsys1-supply = <&vdd_ac_bat_reg>; - vsys2-supply = <&vdd_ac_bat_reg>; - vsys3-supply = <&vdd_ac_bat_reg>; - infet1-supply = <&vdd_ac_bat_reg>; - infet2-supply = <&vdd_ac_bat_reg>; - infet3-supply = <&tps65090_dcdc2_reg>; - infet4-supply = <&tps65090_dcdc2_reg>; - infet5-supply = <&tps65090_dcdc2_reg>; - infet6-supply = <&tps65090_dcdc2_reg>; - infet7-supply = <&tps65090_dcdc2_reg>; - vsys-l1-supply = <&vdd_ac_bat_reg>; - vsys-l2-supply = <&vdd_ac_bat_reg>; - - regulators { - tps65090_dcdc1_reg: dcdc1 { - regulator-name = "vdd-sys-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - tps65090_dcdc2_reg: dcdc2 { - regulator-name = "vdd-sys-3v3"; - regulator-always-on; - regulator-boot-on; - }; - - dcdc3 { - regulator-name = "vdd-ao"; - regulator-always-on; - regulator-boot-on; - }; - - fet1 { - regulator-name = "vdd-lcd-bl"; - }; - - fet3 { - regulator-name = "vdd-modem-3v3"; - }; - - fet4 { - regulator-name = "avdd-lcd"; - }; - - fet5 { - regulator-name = "vdd-lvds"; - }; - - fet6 { - regulator-name = "vdd-sd-slot"; - regulator-always-on; - regulator-boot-on; - }; - - fet7 { - regulator-name = "vdd-com-3v3"; - }; - - ldo1 { - regulator-name = "vdd-sby-5v0"; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "vdd-sby-3v3"; - regulator-always-on; - regulator-boot-on; - }; - }; - }; + clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; - - sdhci@78000400 { - cd-gpios = <&gpio 170 1>; /* gpio PV2 */ - bus-width = <4>; - status = "okay"; - }; - - sdhci@78000600 { - bus-width = <8>; - status = "okay"; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - dvdd_ts_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio 61 0>; /* GPIO PH5 */ - }; - - lcd_bl_en_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio 58 0>; /* GPIO PH2 */ - }; - - usb1_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio 108 0>; /* GPIO PN4 */ - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - usb3_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio 86 0>; /* GPIO PK6 */ - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; - - vdd_hdmi_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio 81 0>; /* GPIO PK1 */ - vin-supply = <&tps65090_dcdc1_reg>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114-pluto.dts b/trunk/arch/arm/boot/dts/tegra114-pluto.dts index 6bbc8efae9c0..9bea8f57aa47 100644 --- a/trunk/arch/arm/boot/dts/tegra114-pluto.dts +++ b/trunk/arch/arm/boot/dts/tegra114-pluto.dts @@ -12,22 +12,10 @@ serial@70006300 { status = "okay"; + clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114.dtsi b/trunk/arch/arm/boot/dts/tegra114.dtsi index 629415ffd8dc..1dfaf2874c57 100644 --- a/trunk/arch/arm/boot/dts/tegra114.dtsi +++ b/trunk/arch/arm/boot/dts/tegra114.dtsi @@ -4,13 +4,6 @@ compatible = "nvidia,tegra114"; interrupt-parent = <&gic>; - aliases { - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -31,53 +24,14 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { - compatible = "nvidia,tegra114-car"; + compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; - apbdma: dma { - compatible = "nvidia,tegra114-apbdma"; - reg = <0x6000a000 0x1400>; - interrupts = <0 104 0x04 - 0 105 0x04 - 0 106 0x04 - 0 107 0x04 - 0 108 0x04 - 0 109 0x04 - 0 110 0x04 - 0 111 0x04 - 0 112 0x04 - 0 113 0x04 - 0 114 0x04 - 0 115 0x04 - 0 116 0x04 - 0 117 0x04 - 0 118 0x04 - 0 119 0x04 - 0 128 0x04 - 0 129 0x04 - 0 130 0x04 - 0 131 0x04 - 0 132 0x04 - 0 133 0x04 - 0 134 0x04 - 0 135 0x04 - 0 136 0x04 - 0 137 0x04 - 0 138 0x04 - 0 139 0x04 - 0 140 0x04 - 0 141 0x04 - 0 142 0x04 - 0 143 0x04>; - clocks = <&tegra_car 34>; - }; - ahb: ahb { compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; @@ -106,186 +60,35 @@ 0x70003000 0x40c>; /* Mux registers */ }; - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performace. To enable the 8250 based driver, the compatible - * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is - * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { + serial@70006000 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; - nvidia,dma-request-selector = <&apbdma 8>; status = "disabled"; - clocks = <&tegra_car 6>; }; - uartb: serial@70006040 { + serial@70006040 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; - nvidia,dma-request-selector = <&apbdma 9>; status = "disabled"; - clocks = <&tegra_car 192>; }; - uartc: serial@70006200 { + serial@70006200 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; - nvidia,dma-request-selector = <&apbdma 10>; status = "disabled"; - clocks = <&tegra_car 55>; }; - uartd: serial@70006300 { + serial@70006300 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; - nvidia,dma-request-selector = <&apbdma 19>; - status = "disabled"; - clocks = <&tegra_car 65>; - }; - - pwm: pwm { - compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car 17>; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; - interrupts = <0 38 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 12>; - clock-names = "div-clk"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; - interrupts = <0 84 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 54>; - clock-names = "div-clk"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; - interrupts = <0 92 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 67>; - clock-names = "div-clk"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; - interrupts = <0 120 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 103>; - clock-names = "div-clk"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; - interrupts = <0 53 0x04>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 47>; - clock-names = "div-clk"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; - interrupts = <0 59 0x04>; - nvidia,dma-request-selector = <&apbdma 15>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 41>; - clock-names = "spi"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; - interrupts = <0 82 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 44>; - clock-names = "spi"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; - interrupts = <0 83 0x04>; - nvidia,dma-request-selector = <&apbdma 17>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 46>; - clock-names = "spi"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; - interrupts = <0 93 0x04>; - nvidia,dma-request-selector = <&apbdma 18>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 68>; - clock-names = "spi"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; - interrupts = <0 94 0x04>; - nvidia,dma-request-selector = <&apbdma 27>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 104>; - clock-names = "spi"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; - interrupts = <0 79 0x04>; - nvidia,dma-request-selector = <&apbdma 28>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car 105>; - clock-names = "spi"; status = "disabled"; }; @@ -293,22 +96,11 @@ compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; - }; - - kbc { - compatible = "nvidia,tegra114-kbc"; - reg = <0x7000e200 0x100>; - interrupts = <0 85 0x04>; - clocks = <&tegra_car 36>; - status = "disabled"; }; pmc { - compatible = "nvidia,tegra114-pmc"; + compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 261>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; iommu { @@ -322,38 +114,6 @@ nvidia,ahb = <&ahb>; }; - sdhci@78000000 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000000 0x200>; - interrupts = <0 14 0x04>; - clocks = <&tegra_car 14>; - status = "disable"; - }; - - sdhci@78000200 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000200 0x200>; - interrupts = <0 15 0x04>; - clocks = <&tegra_car 9>; - status = "disable"; - }; - - sdhci@78000400 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000400 0x200>; - interrupts = <0 19 0x04>; - clocks = <&tegra_car 69>; - status = "disable"; - }; - - sdhci@78000600 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; - reg = <0x78000600 0x200>; - interrupts = <0 31 0x04>; - clocks = <&tegra_car 15>; - status = "disable"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi index a573b94b7c93..444162090042 100644 --- a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -361,15 +361,6 @@ }; }; - pmc { - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - memory-controller@7000f400 { emc-table@83250 { reg = <83250>; @@ -453,20 +444,7 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 23 1>; /* gpio PC7 */ - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + cd-gpios = <&gpio 23 0>; /* gpio PC7 */ }; sound { @@ -482,9 +460,6 @@ "Mic", "MIC1"; nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; regulators { diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index e7d5de4e00b9..61d027f03617 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -416,12 +416,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; }; usb@c5000000 { @@ -443,7 +437,7 @@ sdhci@c8000200 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <4>; @@ -451,36 +445,12 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; - kbc { status = "okay"; nvidia,debounce-delay-ms = <2>; @@ -686,8 +656,5 @@ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts b/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts index ace23437da89..a2d6d6541f83 100644 --- a/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/trunk/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -6,10 +6,6 @@ model = "Avionic Design Medcom-Wide board"; compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - pwm { - status = "okay"; - }; - i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; @@ -58,8 +54,5 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra20-paz00.dts index e3e0c9977df4..54d6fce00a59 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra20-paz00.dts @@ -415,12 +415,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,sys-clock-req-active-high; }; usb@c5000000 { @@ -442,7 +436,7 @@ sdhci@c8000000 { status = "okay"; - cd-gpios = <&gpio 173 1>; /* gpio PV5 */ + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 169 0>; /* gpio PV1 */ bus-width = <4>; @@ -451,20 +445,6 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; gpio-keys { @@ -521,8 +501,5 @@ nvidia,audio-codec = <&alc5632>; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-plutux.dts b/trunk/arch/arm/boot/dts/tegra20-plutux.dts index 1a17cc30bb9d..289480026fbf 100644 --- a/trunk/arch/arm/boot/dts/tegra20-plutux.dts +++ b/trunk/arch/arm/boot/dts/tegra20-plutux.dts @@ -52,8 +52,5 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts index cee4c34010fe..37b3a57ec0f1 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts @@ -517,12 +517,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; }; memory-controller@7000f400 { @@ -586,12 +580,11 @@ status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ bus-width = <4>; - keep-power-in-suspend; }; sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -600,20 +593,6 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; gpio-keys { @@ -829,8 +808,5 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi index 50b3ec16b93a..4766abae7a72 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -458,12 +458,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; }; usb@c5008000 { @@ -471,25 +465,12 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 1>; /* gpio PH2 */ + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ bus-width = <4>; status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - regulators { compatible = "simple-bus"; diff --git a/trunk/arch/arm/boot/dts/tegra20-tec.dts b/trunk/arch/arm/boot/dts/tegra20-tec.dts index 742f0b38d21d..402b21004bef 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tec.dts +++ b/trunk/arch/arm/boot/dts/tegra20-tec.dts @@ -52,8 +52,5 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts index 9cc78a15d739..5d79e4fc49a6 100644 --- a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts @@ -300,15 +300,6 @@ }; }; - pmc { - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - usb@c5000000 { status = "okay"; nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ @@ -334,35 +325,11 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 121 1>; /* gpio PP1 */ + cd-gpios = <&gpio 121 0>; /* gpio PP1 */ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ bus-width = <4>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio 190 1>; /* gpio PX6, active low */ - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; - poweroff { compatible = "gpio-poweroff"; gpios = <&gpio 191 1>; /* gpio PX7, active low */ @@ -396,8 +363,5 @@ compatible = "nvidia,tegra-audio-trimslice"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index dd38f1f03834..425c89000c20 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -493,12 +493,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; }; usb@c5000000 { @@ -522,12 +516,11 @@ status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ bus-width = <4>; - keep-power-in-suspend; }; sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -536,31 +529,6 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio 170 1>; /* gpio PV2, active low */ - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; }; regulators { @@ -639,8 +607,5 @@ nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts index d2567f83aaff..ea57c0f6dcce 100644 --- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts +++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts @@ -496,14 +496,6 @@ pmc { nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <1000>; - nvidia,core-pwr-good-time = <0 3845>; - nvidia,core-pwr-off-time = <93727>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,combined-power-req; }; usb@c5000000 { @@ -518,7 +510,6 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 173 0>; /* gpio PV5 */ bus-width = <8>; }; @@ -526,20 +517,6 @@ sdhci@c8000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; kbc { @@ -548,7 +525,6 @@ nvidia,repeat-delay-ms = <160>; nvidia,kbc-row-pins = <0 1 2>; nvidia,kbc-col-pins = <16 17>; - nvidia,wakeup-source; linux,keymap = <0x00000074 /* KEY_POWER */ 0x01000066 /* KEY_HOME */ 0x0101009E /* KEY_BACK */ @@ -583,8 +559,5 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&codec>; - - clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index 56a91106041b..9a428931d042 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -118,7 +118,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; interrupts = <1 13 0x304>; - clocks = <&tegra_car 132>; }; intc: interrupt-controller { @@ -145,7 +144,6 @@ 0 1 0x04 0 41 0x04 0 42 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -209,7 +207,7 @@ compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; - + tegra_ac97: ac97 { compatible = "nvidia,tegra20-ac97"; reg = <0x70002000 0x200>; @@ -299,14 +297,12 @@ reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car 17>; - status = "disabled"; }; rtc { compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -388,7 +384,7 @@ spi@7000d800 { compatible = "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; + reg = <0x7000d480 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; @@ -419,8 +415,6 @@ pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 110>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; memory-controller@7000f000 { @@ -443,6 +437,31 @@ #size-cells = <0>; }; + phy1: usb-phy@c5000400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5000400 0x3c00>; + phy_type = "utmi"; + nvidia,has-legacy-mode; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + + phy2: usb-phy@c5004400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004400 0x3c00>; + phy_type = "ulpi"; + clocks = <&tegra_car 94>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + + phy3: usb-phy@c5008400 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5008400 0x3C00>; + phy_type = "utmi"; + clocks = <&tegra_car 22>, <&tegra_car 127>; + clock-names = "phy", "pll_u"; + }; + usb@c5000000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5000000 0x4000>; @@ -455,15 +474,6 @@ status = "disabled"; }; - phy1: usb-phy@c5000400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000400 0x3c00>; - phy_type = "utmi"; - nvidia,has-legacy-mode; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - usb@c5004000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5004000 0x4000>; @@ -474,14 +484,6 @@ status = "disabled"; }; - phy2: usb-phy@c5004400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004400 0x3c00>; - phy_type = "ulpi"; - clocks = <&tegra_car 93>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - usb@c5008000 { compatible = "nvidia,tegra20-ehci", "usb-ehci"; reg = <0xc5008000 0x4000>; @@ -492,14 +494,6 @@ status = "disabled"; }; - phy3: usb-phy@c5008400 { - compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008400 0x3c00>; - phy_type = "utmi"; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; - }; - sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; diff --git a/trunk/arch/arm/boot/dts/tegra30-beaver.dts b/trunk/arch/arm/boot/dts/tegra30-beaver.dts index b732f7c13a66..8ff2ff20e4a3 100644 --- a/trunk/arch/arm/boot/dts/tegra30-beaver.dts +++ b/trunk/arch/arm/boot/dts/tegra30-beaver.dts @@ -253,18 +253,11 @@ pmc { status = "okay"; nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; }; sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -273,20 +266,6 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; regulators { diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts index e392bd2dab9b..adc88aa50eb6 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -88,7 +88,6 @@ status = "okay"; power-gpios = <&gpio 28 0>; /* gpio PD4 */ bus-width = <4>; - keep-power-in-suspend; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts index d0db6c7e774f..08163e145d57 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -100,6 +100,5 @@ status = "okay"; power-gpios = <&gpio 27 0>; /* gpio PD3 */ bus-width = <4>; - keep-power-in-suspend; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi index 01b4c26fad96..17499272a4ef 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -307,18 +307,11 @@ pmc { status = "okay"; nvidia,invert-interrupt; - nvidia,suspend-mode = <2>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <200>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <0>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; }; sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -327,20 +320,6 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; regulators { @@ -517,8 +496,5 @@ nvidia,spkr-en-gpios = <&wm8903 2 0>; nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ - - clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 15ded605142a..767803e1fd55 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -119,7 +119,6 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; interrupts = <1 13 0xf04>; - clocks = <&tegra_car 214>; }; intc: interrupt-controller { @@ -148,7 +147,6 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; - clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -286,14 +284,12 @@ reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car 17>; - status = "disabled"; }; rtc { compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -375,7 +371,7 @@ spi@7000d800 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; - reg = <0x7000d800 0x200>; + reg = <0x7000d480 0x200>; interrupts = <0 83 0x04>; nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; @@ -426,10 +422,8 @@ }; pmc { - compatible = "nvidia,tegra30-pmc"; + compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; - clocks = <&tegra_car 218>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; }; memory-controller { diff --git a/trunk/arch/arm/boot/dts/twl4030.dtsi b/trunk/arch/arm/boot/dts/twl4030.dtsi index b3034da00a37..ed0bc9546837 100644 --- a/trunk/arch/arm/boot/dts/twl4030.dtsi +++ b/trunk/arch/arm/boot/dts/twl4030.dtsi @@ -23,12 +23,6 @@ compatible = "ti,twl4030-wdt"; }; - vcc: regulator-vdd1 { - compatible = "ti,twl4030-vdd1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1450000>; - }; - vdac: regulator-vdac { compatible = "ti,twl4030-vdac"; regulator-min-microvolt = <1800000>; @@ -73,7 +67,7 @@ #interrupt-cells = <1>; }; - usb2_phy: twl4030-usb { + twl4030-usb { compatible = "ti,twl4030-usb"; interrupts = <10>, <4>; usb1v5-supply = <&vusb1v5>; @@ -81,14 +75,4 @@ usb3v1-supply = <&vusb3v1>; usb_mode = <1>; }; - - twl_pwm: pwm { - compatible = "ti,twl4030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - compatible = "ti,twl4030-pwmled"; - #pwm-cells = <2>; - }; }; diff --git a/trunk/arch/arm/boot/dts/twl6030.dtsi b/trunk/arch/arm/boot/dts/twl6030.dtsi index 2e3bd3172b23..9996cfc5ee80 100644 --- a/trunk/arch/arm/boot/dts/twl6030.dtsi +++ b/trunk/arch/arm/boot/dts/twl6030.dtsi @@ -91,16 +91,4 @@ compatible = "ti,twl6030-usb"; interrupts = <4>, <10>; }; - - twl_pwm: pwm { - /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; - }; - - twl_pwmled: pwmled { - /* provides one PWM (id 0 for Charging indicator LED) */ - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; - }; }; diff --git a/trunk/arch/arm/configs/dove_defconfig b/trunk/arch/arm/configs/dove_defconfig index 3fe8dae8d32d..4364eff5b01e 100644 --- a/trunk/arch/arm/configs/dove_defconfig +++ b/trunk/arch/arm/configs/dove_defconfig @@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y CONFIG_SPI=y CONFIG_SPI_ORION=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_DOVE_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y diff --git a/trunk/arch/arm/configs/kirkwood_defconfig b/trunk/arch/arm/configs/kirkwood_defconfig index 13482ea58b09..8f0065bb6f39 100644 --- a/trunk/arch/arm/configs/kirkwood_defconfig +++ b/trunk/arch/arm/configs/kirkwood_defconfig @@ -119,6 +119,8 @@ CONFIG_SPI=y CONFIG_SPI_ORION=y CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_KIRKWOOD_THERMAL=y CONFIG_WATCHDOG=y CONFIG_ORION_WATCHDOG=y CONFIG_HID_DRAGONRISE=y diff --git a/trunk/arch/arm/configs/mvebu_defconfig b/trunk/arch/arm/configs/mvebu_defconfig index 2ec8119cff73..f3e8ae001ff1 100644 --- a/trunk/arch/arm/configs/mvebu_defconfig +++ b/trunk/arch/arm/configs/mvebu_defconfig @@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y CONFIG_MTD=y CONFIG_MTD_CHAR=y CONFIG_MTD_M25P80=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_SERIAL_8250_DW=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y +CONFIG_THERMAL=y +CONFIG_ARMADA_THERMAL=y CONFIG_USB_SUPPORT=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_MV=y CONFIG_DMADEVICES=y CONFIG_MV_XOR=y +CONFIG_MEMORY=y +CONFIG_MVEBU_DEVBUS=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y diff --git a/trunk/arch/arm/configs/mxs_defconfig b/trunk/arch/arm/configs/mxs_defconfig index 6a99e30f81d2..fbbc5bb022d5 100644 --- a/trunk/arch/arm/configs/mxs_defconfig +++ b/trunk/arch/arm/configs/mxs_defconfig @@ -116,7 +116,6 @@ CONFIG_SND_SOC=y CONFIG_SND_MXS_SOC=y CONFIG_SND_SOC_MXS_SGTL5000=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_CHIPIDEA=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_STORAGE=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap2plus_defconfig index bd07864f14a0..b16bae2c9a60 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap2plus_defconfig @@ -126,8 +126,6 @@ CONFIG_INPUT_MISC=y CONFIG_INPUT_TWL4030_PWRBUTTON=y CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=32 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y diff --git a/trunk/arch/arm/include/asm/smp_twd.h b/trunk/arch/arm/include/asm/smp_twd.h index 7b2899c2f7fc..0f01f4677bd2 100644 --- a/trunk/arch/arm/include/asm/smp_twd.h +++ b/trunk/arch/arm/include/asm/smp_twd.h @@ -34,4 +34,12 @@ struct twd_local_timer name __initdata = { \ int twd_local_timer_register(struct twd_local_timer *); +#ifdef CONFIG_HAVE_ARM_TWD +void twd_local_timer_of_register(void); +#else +static inline void twd_local_timer_of_register(void) +{ +} +#endif + #endif diff --git a/trunk/arch/arm/include/asm/xen/events.h b/trunk/arch/arm/include/asm/xen/events.h index 8b1f37bfeeec..5c27696de14f 100644 --- a/trunk/arch/arm/include/asm/xen/events.h +++ b/trunk/arch/arm/include/asm/xen/events.h @@ -2,7 +2,6 @@ #define _ASM_ARM_XEN_EVENTS_H #include -#include enum ipi_vector { XEN_PLACEHOLDER_VECTOR, @@ -16,8 +15,26 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) return raw_irqs_disabled_flags(regs->ARM_cpsr); } -#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \ - atomic64_t, \ - counter), (val)) +/* + * We cannot use xchg because it does not support 8-byte + * values. However it is safe to use {ldr,dtd}exd directly because all + * platforms which Xen can run on support those instructions. + */ +static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val) +{ + xen_ulong_t oldval; + unsigned int tmp; + + wmb(); + asm volatile("@ xchg_xen_ulong\n" + "1: ldrexd %0, %H0, [%3]\n" + " strexd %1, %2, %H2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (oldval), "=&r" (tmp) + : "r" (val), "r" (ptr) + : "memory", "cc"); + return oldval; +} #endif /* _ASM_ARM_XEN_EVENTS_H */ diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 79078edbb9bc..31644f1978d5 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -480,7 +480,7 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) evt->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY; - evt->rating = 100; + evt->rating = 400; evt->mult = 1; evt->set_mode = broadcast_timer_set_mode; diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index 90525d9d290b..3f2565037480 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -362,13 +362,25 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) } #ifdef CONFIG_OF -static void __init twd_local_timer_of_register(struct device_node *np) +const static struct of_device_id twd_of_match[] __initconst = { + { .compatible = "arm,cortex-a9-twd-timer", }, + { .compatible = "arm,cortex-a5-twd-timer", }, + { .compatible = "arm,arm11mp-twd-timer", }, + { }, +}; + +void __init twd_local_timer_of_register(void) { + struct device_node *np; int err; if (!is_smp() || !setup_max_cpus) return; + np = of_find_matching_node(NULL, twd_of_match); + if (!np) + return; + twd_ppi = irq_of_parse_and_map(np, 0); if (!twd_ppi) { err = -EINVAL; @@ -386,7 +398,4 @@ static void __init twd_local_timer_of_register(struct device_node *np) out: WARN(err, "twd_local_timer_of_register failed (%d)\n", err); } -CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); -CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); #endif diff --git a/trunk/arch/arm/lib/memset.S b/trunk/arch/arm/lib/memset.S index 94b0650ea98f..d912e7397ecc 100644 --- a/trunk/arch/arm/lib/memset.S +++ b/trunk/arch/arm/lib/memset.S @@ -14,15 +14,31 @@ .text .align 5 + .word 0 + +1: subs r2, r2, #4 @ 1 do we have enough + blt 5f @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [ip], #1 @ 1 + strleb r1, [ip], #1 @ 1 + strb r1, [ip], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) +/* + * The pointer is now aligned and the length is adjusted. Try doing the + * memset again. + */ ENTRY(memset) - ands r3, r0, #3 @ 1 unaligned? - mov ip, r0 @ preserve r0 as return value - bne 6f @ 1 +/* + * Preserve the contents of r0 for the return value. + */ + mov ip, r0 + ands r3, ip, #3 @ 1 unaligned? + bne 1b @ 1 /* * we know that the pointer in ip is aligned to a word boundary. */ -1: orr r1, r1, r1, lsl #8 + orr r1, r1, r1, lsl #8 orr r1, r1, r1, lsl #16 mov r3, r1 cmp r2, #16 @@ -111,13 +127,4 @@ ENTRY(memset) tst r2, #1 strneb r1, [ip], #1 mov pc, lr - -6: subs r2, r2, #4 @ 1 do we have enough - blt 5b @ 1 bytes to align with? - cmp r3, #2 @ 1 - strltb r1, [ip], #1 @ 1 - strleb r1, [ip], #1 @ 1 - strb r1, [ip], #1 @ 1 - add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) - b 1b ENDPROC(memset) diff --git a/trunk/arch/arm/mach-at91/board-foxg20.c b/trunk/arch/arm/mach-at91/board-foxg20.c index c20a870ea9c9..2ea7059b840b 100644 --- a/trunk/arch/arm/mach-at91/board-foxg20.c +++ b/trunk/arch/arm/mach-at91/board-foxg20.c @@ -176,7 +176,6 @@ static struct w1_gpio_platform_data w1_gpio_pdata = { /* If you choose to use a pin other than PB16 it needs to be 3.3V */ .pin = AT91_PIN_PB16, .is_open_drain = 1, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device w1_device = { diff --git a/trunk/arch/arm/mach-at91/board-stamp9g20.c b/trunk/arch/arm/mach-at91/board-stamp9g20.c index 869cbecf00b7..a033b8df9fb2 100644 --- a/trunk/arch/arm/mach-at91/board-stamp9g20.c +++ b/trunk/arch/arm/mach-at91/board-stamp9g20.c @@ -188,7 +188,6 @@ static struct spi_board_info portuxg20_spi_devices[] = { static struct w1_gpio_platform_data w1_gpio_pdata = { .pin = AT91_PIN_PA29, .is_open_drain = 1, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device w1_device = { diff --git a/trunk/arch/arm/mach-at91/include/mach/gpio.h b/trunk/arch/arm/mach-at91/include/mach/gpio.h index 5fc23771c154..eed465ab0dd7 100644 --- a/trunk/arch/arm/mach-at91/include/mach/gpio.h +++ b/trunk/arch/arm/mach-at91/include/mach/gpio.h @@ -209,14 +209,6 @@ extern int at91_get_gpio_value(unsigned pin); extern void at91_gpio_suspend(void); extern void at91_gpio_resume(void); -#ifdef CONFIG_PINCTRL_AT91 -extern void at91_pinctrl_gpio_suspend(void); -extern void at91_pinctrl_gpio_resume(void); -#else -static inline void at91_pinctrl_gpio_suspend(void) {} -static inline void at91_pinctrl_gpio_resume(void) {} -#endif - #endif /* __ASSEMBLY__ */ #endif diff --git a/trunk/arch/arm/mach-at91/irq.c b/trunk/arch/arm/mach-at91/irq.c index e0ca59171022..8e210262aeee 100644 --- a/trunk/arch/arm/mach-at91/irq.c +++ b/trunk/arch/arm/mach-at91/irq.c @@ -92,21 +92,23 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value) void at91_irq_suspend(void) { - int bit = -1; + int i = 0, bit; if (has_aic5()) { /* disable enabled irqs */ - while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { + while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IDCR, 1); + i = bit; } /* enable wakeup irqs */ - bit = -1; - while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { + i = 0; + while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IECR, 1); + i = bit; } } else { at91_aic_write(AT91_AIC_IDCR, *backups); @@ -116,21 +118,23 @@ void at91_irq_suspend(void) void at91_irq_resume(void) { - int bit = -1; + int i = 0, bit; if (has_aic5()) { /* disable wakeup irqs */ - while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) { + while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IDCR, 1); + i = bit; } /* enable irqs disabled for suspend */ - bit = -1; - while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) { + i = 0; + while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { at91_aic_write(AT91_AIC5_SSR, bit & AT91_AIC5_INTSEL_MSK); at91_aic_write(AT91_AIC5_IECR, 1); + i = bit; } } else { at91_aic_write(AT91_AIC_IDCR, *wakeups); diff --git a/trunk/arch/arm/mach-at91/pm.c b/trunk/arch/arm/mach-at91/pm.c index 73f1f250403a..adb6db888a1f 100644 --- a/trunk/arch/arm/mach-at91/pm.c +++ b/trunk/arch/arm/mach-at91/pm.c @@ -201,10 +201,7 @@ extern u32 at91_slow_clock_sz; static int at91_pm_enter(suspend_state_t state) { - if (of_have_populated_dt()) - at91_pinctrl_gpio_suspend(); - else - at91_gpio_suspend(); + at91_gpio_suspend(); at91_irq_suspend(); pr_debug("AT91: PM - wake mask %08x, pm state %d\n", @@ -289,10 +286,7 @@ static int at91_pm_enter(suspend_state_t state) error: target_state = PM_SUSPEND_ON; at91_irq_resume(); - if (of_have_populated_dt()) - at91_pinctrl_gpio_resume(); - else - at91_gpio_resume(); + at91_gpio_resume(); return 0; } diff --git a/trunk/arch/arm/mach-davinci/dma.c b/trunk/arch/arm/mach-davinci/dma.c index 45b7c71d9cc1..a685e9706b7b 100644 --- a/trunk/arch/arm/mach-davinci/dma.c +++ b/trunk/arch/arm/mach-davinci/dma.c @@ -743,9 +743,6 @@ EXPORT_SYMBOL(edma_free_channel); */ int edma_alloc_slot(unsigned ctlr, int slot) { - if (!edma_cc[ctlr]) - return -EINVAL; - if (slot >= 0) slot = EDMA_CHAN_SLOT(slot); diff --git a/trunk/arch/arm/mach-exynos/Kconfig b/trunk/arch/arm/mach-exynos/Kconfig index ef3b69a6277c..70f94c87479d 100644 --- a/trunk/arch/arm/mach-exynos/Kconfig +++ b/trunk/arch/arm/mach-exynos/Kconfig @@ -61,7 +61,6 @@ config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y depends on ARCH_EXYNOS5 - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select S5P_DEV_MFC @@ -80,6 +79,12 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support +config EXYNOS4_MCT + bool + default y + help + Use MCT (Multi Core Timer) as kernel timers + config EXYNOS_DEV_DMA bool help @@ -271,8 +276,8 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_ONENAND select S5P_DEV_TV select S5P_GPIO_INT + select S5P_HRT select S5P_SETUP_MIPIPHY - select SAMSUNG_HRT help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -401,12 +406,10 @@ config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" depends on ARCH_EXYNOS4 select ARM_AMBA - select CLKSRC_OF select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL select PINCTRL_EXYNOS - select S5P_DEV_MFC select USE_OF help Machine support for Samsung Exynos4 machine with device tree enabled. @@ -419,7 +422,6 @@ config MACH_EXYNOS5_DT default y depends on ARCH_EXYNOS5 select ARM_AMBA - select CLKSRC_OF select USE_OF help Machine support for Samsung EXYNOS5 machine with device tree enabled. diff --git a/trunk/arch/arm/mach-exynos/Makefile b/trunk/arch/arm/mach-exynos/Makefile index d2f6b362b6dd..435757e57bb4 100644 --- a/trunk/arch/arm/mach-exynos/Makefile +++ b/trunk/arch/arm/mach-exynos/Makefile @@ -13,6 +13,10 @@ obj- := # Core obj-$(CONFIG_ARCH_EXYNOS) += common.o +obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o +obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o +obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o +obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o @@ -22,6 +26,8 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_EXYNOS4_MCT) += mct.o + obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4.c b/trunk/arch/arm/mach-exynos/clock-exynos4.c new file mode 100644 index 000000000000..8a8468d83c8c --- /dev/null +++ b/trunk/arch/arm/mach-exynos/clock-exynos4.c @@ -0,0 +1,1601 @@ +/* + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "clock-exynos4.h" + +#ifdef CONFIG_PM_SLEEP +static struct sleep_save exynos4_clock_save[] = { + SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), + SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS), + SAVE_ITEM(EXYNOS4_CLKSRC_TOP0), + SAVE_ITEM(EXYNOS4_CLKSRC_TOP1), + SAVE_ITEM(EXYNOS4_CLKSRC_CAM), + SAVE_ITEM(EXYNOS4_CLKSRC_TV), + SAVE_ITEM(EXYNOS4_CLKSRC_MFC), + SAVE_ITEM(EXYNOS4_CLKSRC_G3D), + SAVE_ITEM(EXYNOS4_CLKSRC_LCD0), + SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKSRC_FSYS), + SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0), + SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV_CAM), + SAVE_ITEM(EXYNOS4_CLKDIV_TV), + SAVE_ITEM(EXYNOS4_CLKDIV_MFC), + SAVE_ITEM(EXYNOS4_CLKDIV_G3D), + SAVE_ITEM(EXYNOS4_CLKDIV_LCD0), + SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2), + SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4), + SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5), + SAVE_ITEM(EXYNOS4_CLKDIV_TOP), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1), + SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO), + SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL), + SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK), + SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC), + SAVE_ITEM(EXYNOS4_CLKSRC_DMC), + SAVE_ITEM(EXYNOS4_CLKDIV_DMC0), + SAVE_ITEM(EXYNOS4_CLKDIV_DMC1), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC), + SAVE_ITEM(EXYNOS4_CLKSRC_CPU), + SAVE_ITEM(EXYNOS4_CLKDIV_CPU), + SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4), + SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU), + SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU), +}; +#endif + +static struct clk exynos4_clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", + .rate = 27000000, +}; + +static struct clk exynos4_clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", +}; + +static struct clk exynos4_clk_sclk_usbphy0 = { + .name = "sclk_usbphy0", + .rate = 27000000, +}; + +static struct clk exynos4_clk_sclk_usbphy1 = { + .name = "sclk_usbphy1", +}; + +static struct clk dummy_apb_pclk = { + .name = "apb_pclk", + .id = -1, +}; + +static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); +} + +static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable); +} + +static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable); +} + +int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable); +} + +static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable); +} + +static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable); +} + +static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable); +} + +static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable); +} + +static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable); +} + +static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); +} + +int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); +} + +static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable); +} + +int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable); +} + +int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable); +} + +static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable); +} + +static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); +} + +int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable); +} + +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + +/* Core list of CMU_CPU side */ + +static struct clksrc_clk exynos4_clk_mout_apll = { + .clk = { + .name = "mout_apll", + }, + .sources = &clk_src_apll, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_apll = { + .clk = { + .name = "sclk_apll", + .parent = &exynos4_clk_mout_apll.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_mout_epll = { + .clk = { + .name = "mout_epll", + }, + .sources = &clk_src_epll, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 }, +}; + +struct clksrc_clk exynos4_clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + }, + .sources = &clk_src_mpll, + + /* reg_src will be added in each SoCs' clock */ +}; + +static struct clk *exynos4_clkset_moutcore_list[] = { + [0] = &exynos4_clk_mout_apll.clk, + [1] = &exynos4_clk_mout_mpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_moutcore = { + .sources = exynos4_clkset_moutcore_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list), +}; + +static struct clksrc_clk exynos4_clk_moutcore = { + .clk = { + .name = "moutcore", + }, + .sources = &exynos4_clkset_moutcore, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_coreclk = { + .clk = { + .name = "core_clk", + .parent = &exynos4_clk_moutcore.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_armclk = { + .clk = { + .name = "armclk", + .parent = &exynos4_clk_coreclk.clk, + }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corem0 = { + .clk = { + .name = "aclk_corem0", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_cores = { + .clk = { + .name = "aclk_cores", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corem1 = { + .clk = { + .name = "aclk_corem1", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_periphclk = { + .clk = { + .name = "periphclk", + .parent = &exynos4_clk_coreclk.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, +}; + +/* Core list of CMU_CORE side */ + +static struct clk *exynos4_clkset_corebus_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +struct clksrc_sources exynos4_clkset_mout_corebus = { + .sources = exynos4_clkset_corebus_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list), +}; + +static struct clksrc_clk exynos4_clk_mout_corebus = { + .clk = { + .name = "mout_corebus", + }, + .sources = &exynos4_clkset_mout_corebus, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_dmc = { + .clk = { + .name = "sclk_dmc", + .parent = &exynos4_clk_mout_corebus.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_cored = { + .clk = { + .name = "aclk_cored", + .parent = &exynos4_clk_sclk_dmc.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_corep = { + .clk = { + .name = "aclk_corep", + .parent = &exynos4_clk_aclk_cored.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_acp = { + .clk = { + .name = "aclk_acp", + .parent = &exynos4_clk_mout_corebus.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_pclk_acp = { + .clk = { + .name = "pclk_acp", + .parent = &exynos4_clk_aclk_acp.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 }, +}; + +/* Core list of CMU_TOP side */ + +struct clk *exynos4_clkset_aclk_top_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +static struct clksrc_sources exynos4_clkset_aclk = { + .sources = exynos4_clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list), +}; + +static struct clksrc_clk exynos4_clk_aclk_200 = { + .clk = { + .name = "aclk_200", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_100 = { + .clk = { + .name = "aclk_100", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_aclk_160 = { + .clk = { + .name = "aclk_160", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 }, +}; + +struct clksrc_clk exynos4_clk_aclk_133 = { + .clk = { + .name = "aclk_133", + }, + .sources = &exynos4_clkset_aclk, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 }, +}; + +static struct clk *exynos4_clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &exynos4_clk_sclk_hdmi27m, +}; + +static struct clksrc_sources exynos4_clkset_vpllsrc = { + .sources = exynos4_clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list), +}; + +static struct clksrc_clk exynos4_clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .enable = exynos4_clksrc_mask_top_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_vpllsrc, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_sclk_vpll_list[] = { + [0] = &exynos4_clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources exynos4_clkset_sclk_vpll = { + .sources = exynos4_clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + }, + .sources = &exynos4_clkset_sclk_vpll, + .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 }, +}; + +static struct clk exynos4_init_clocks_off[] = { + { + .name = "timers", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1<<24), + }, { + .name = "csis", + .devname = "s5p-mipi-csis.0", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "csis", + .devname = "s5p-mipi-csis.1", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "jpeg", + .id = 0, + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "fimc", + .devname = "exynos4-fimc.0", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "fimc", + .devname = "exynos4-fimc.1", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "fimc", + .devname = "exynos4-fimc.2", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "fimc", + .devname = "exynos4-fimc.3", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "tsi", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "hsmmc", + .devname = "exynos4-sdhci.0", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "hsmmc", + .devname = "exynos4-sdhci.1", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "hsmmc", + .devname = "exynos4-sdhci.2", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "hsmmc", + .devname = "exynos4-sdhci.3", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "biu", + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "onenand", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "nfcon", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "dac", + .devname = "s5p-sdo", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "vp", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hdmi", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "hdmiphy", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "adc", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "tmu_apbif", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "keypad", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "rtc", + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "watchdog", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_perir_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "usbhost", + .enable = exynos4_clk_ip_fsys_ctrl , + .ctrlbit = (1 << 12), + }, { + .name = "otg", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 18), + }, { + .name = "iis", + .devname = "samsung-i2s.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "iis", + .devname = "samsung-i2s.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "pcm", + .devname = "samsung-pcm.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 22), + }, { + .name = "pcm", + .devname = "samsung-pcm.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 23), + }, { + .name = "slimbus", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "spdif", + .devname = "samsung-spdif", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 26), + }, { + .name = "ac97", + .devname = "samsung-ac97", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 27), + }, { + .name = "mfc", + .devname = "s5p-mfc", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.0", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.1", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.2", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.3", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.4", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.5", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.6", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.7", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &exynos4_clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.0", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.1", + .enable = exynos4_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.2", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.3", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.4", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.5", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.6", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.7", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.8", + .enable = exynos4_clk_ip_cam_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.10", + .enable = exynos4_clk_ip_lcd0_ctrl, + .ctrlbit = (1 << 4), + } +}; + +static struct clk exynos4_init_clocks_on[] = { + { + .name = "uart", + .devname = "s5pv210-uart.0", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .devname = "s5pv210-uart.1", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .devname = "s5pv210-uart.2", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .devname = "s5pv210-uart.3", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "uart", + .devname = "s5pv210-uart.4", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "uart", + .devname = "s5pv210-uart.5", + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 5), + } +}; + +static struct clk exynos4_clk_pdma0 = { + .name = "dma", + .devname = "dma-pl330.0", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), +}; + +static struct clk exynos4_clk_pdma1 = { + .name = "dma", + .devname = "dma-pl330.1", + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), +}; + +static struct clk exynos4_clk_mdma1 = { + .name = "dma", + .devname = "dma-pl330.2", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), +}; + +static struct clk exynos4_clk_fimd0 = { + .name = "fimd", + .devname = "exynos4-fb.0", + .enable = exynos4_clk_ip_lcd0_ctrl, + .ctrlbit = (1 << 0), +}; + +struct clk *exynos4_clkset_group_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &clk_xusbxti, + [2] = &exynos4_clk_sclk_hdmi27m, + [3] = &exynos4_clk_sclk_usbphy0, + [4] = &exynos4_clk_sclk_usbphy1, + [5] = &exynos4_clk_sclk_hdmiphy, + [6] = &exynos4_clk_mout_mpll.clk, + [7] = &exynos4_clk_mout_epll.clk, + [8] = &exynos4_clk_sclk_vpll.clk, +}; + +struct clksrc_sources exynos4_clkset_group = { + .sources = exynos4_clkset_group_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list), +}; + +static struct clk *exynos4_clkset_mout_g2d0_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +struct clksrc_sources exynos4_clkset_mout_g2d0 = { + .sources = exynos4_clkset_mout_g2d0_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), +}; + +static struct clk *exynos4_clkset_mout_g2d1_list[] = { + [0] = &exynos4_clk_mout_epll.clk, + [1] = &exynos4_clk_sclk_vpll.clk, +}; + +struct clksrc_sources exynos4_clkset_mout_g2d1 = { + .sources = exynos4_clkset_mout_g2d1_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), +}; + +static struct clk *exynos4_clkset_mout_mfc0_list[] = { + [0] = &exynos4_clk_mout_mpll.clk, + [1] = &exynos4_clk_sclk_apll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc0 = { + .sources = exynos4_clkset_mout_mfc0_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list), +}; + +static struct clksrc_clk exynos4_clk_mout_mfc0 = { + .clk = { + .name = "mout_mfc0", + }, + .sources = &exynos4_clkset_mout_mfc0, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_mfc1_list[] = { + [0] = &exynos4_clk_mout_epll.clk, + [1] = &exynos4_clk_sclk_vpll.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc1 = { + .sources = exynos4_clkset_mout_mfc1_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list), +}; + +static struct clksrc_clk exynos4_clk_mout_mfc1 = { + .clk = { + .name = "mout_mfc1", + }, + .sources = &exynos4_clkset_mout_mfc1, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 }, +}; + +static struct clk *exynos4_clkset_mout_mfc_list[] = { + [0] = &exynos4_clk_mout_mfc0.clk, + [1] = &exynos4_clk_mout_mfc1.clk, +}; + +static struct clksrc_sources exynos4_clkset_mout_mfc = { + .sources = exynos4_clkset_mout_mfc_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list), +}; + +static struct clk *exynos4_clkset_sclk_dac_list[] = { + [0] = &exynos4_clk_sclk_vpll.clk, + [1] = &exynos4_clk_sclk_hdmiphy, +}; + +static struct clksrc_sources exynos4_clkset_sclk_dac = { + .sources = exynos4_clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_dac = { + .clk = { + .name = "sclk_dac", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_sclk_dac, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", + .parent = &exynos4_clk_sclk_vpll.clk, + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 }, +}; + +static struct clk *exynos4_clkset_sclk_hdmi_list[] = { + [0] = &exynos4_clk_sclk_pixel.clk, + [1] = &exynos4_clk_sclk_hdmiphy, +}; + +static struct clksrc_sources exynos4_clkset_sclk_hdmi = { + .sources = exynos4_clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_sclk_hdmi, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos4_clkset_sclk_mixer_list[] = { + [0] = &exynos4_clk_sclk_dac.clk, + [1] = &exynos4_clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources exynos4_clkset_sclk_mixer = { + .sources = exynos4_clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list), +}; + +static struct clksrc_clk exynos4_clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_sclk_mixer, + .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *exynos4_sclk_tv[] = { + &exynos4_clk_sclk_dac, + &exynos4_clk_sclk_pixel, + &exynos4_clk_sclk_hdmi, + &exynos4_clk_sclk_mixer, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc0 = { + .clk = { + .name = "dout_mmc0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc1 = { + .clk = { + .name = "dout_mmc1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc2 = { + .clk = { + .name = "dout_mmc2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc3 = { + .clk = { + .name = "dout_mmc3", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_dout_mmc4 = { + .clk = { + .name = "dout_mmc4", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clksrcs[] = { + { + .clk = { + .name = "sclk_pwm", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .devname = "s5p-mipi-csis.0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_csis", + .devname = "s5p-mipi-csis.1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.0", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.1", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.2", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimc", + .devname = "exynos4-fimc.3", + .enable = exynos4_clksrc_mask_cam_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .devname = "exynos4-fb.0", + .enable = exynos4_clksrc_mask_lcd0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_mfc", + .devname = "s5p-mfc", + }, + .sources = &exynos4_clkset_mout_mfc, + .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "ciu", + .parent = &exynos4_clk_dout_mmc4.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, + } +}; + +static struct clksrc_clk exynos4_clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.0", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.1", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.2", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.3", + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc0 = { + .clk = { + .name = "sclk_mmc", + .devname = "exynos4-sdhci.0", + .parent = &exynos4_clk_dout_mmc0.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc1 = { + .clk = { + .name = "sclk_mmc", + .devname = "exynos4-sdhci.1", + .parent = &exynos4_clk_dout_mmc1.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc2 = { + .clk = { + .name = "sclk_mmc", + .devname = "exynos4-sdhci.2", + .parent = &exynos4_clk_dout_mmc2.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_mmc3 = { + .clk = { + .name = "sclk_mmc", + .devname = "exynos4-sdhci.3", + .parent = &exynos4_clk_dout_mmc3.clk, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos4_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, + .enable = exynos4_clksrc_mask_peril1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, +}; + +/* Clock initialization code */ +static struct clksrc_clk *exynos4_sysclks[] = { + &exynos4_clk_mout_apll, + &exynos4_clk_sclk_apll, + &exynos4_clk_mout_epll, + &exynos4_clk_mout_mpll, + &exynos4_clk_moutcore, + &exynos4_clk_coreclk, + &exynos4_clk_armclk, + &exynos4_clk_aclk_corem0, + &exynos4_clk_aclk_cores, + &exynos4_clk_aclk_corem1, + &exynos4_clk_periphclk, + &exynos4_clk_mout_corebus, + &exynos4_clk_sclk_dmc, + &exynos4_clk_aclk_cored, + &exynos4_clk_aclk_corep, + &exynos4_clk_aclk_acp, + &exynos4_clk_pclk_acp, + &exynos4_clk_vpllsrc, + &exynos4_clk_sclk_vpll, + &exynos4_clk_aclk_200, + &exynos4_clk_aclk_100, + &exynos4_clk_aclk_160, + &exynos4_clk_aclk_133, + &exynos4_clk_dout_mmc0, + &exynos4_clk_dout_mmc1, + &exynos4_clk_dout_mmc2, + &exynos4_clk_dout_mmc3, + &exynos4_clk_dout_mmc4, + &exynos4_clk_mout_mfc0, + &exynos4_clk_mout_mfc1, +}; + +static struct clk *exynos4_clk_cdev[] = { + &exynos4_clk_pdma0, + &exynos4_clk_pdma1, + &exynos4_clk_mdma1, + &exynos4_clk_fimd0, +}; + +static struct clksrc_clk *exynos4_clksrc_cdev[] = { + &exynos4_clk_sclk_uart0, + &exynos4_clk_sclk_uart1, + &exynos4_clk_sclk_uart2, + &exynos4_clk_sclk_uart3, + &exynos4_clk_sclk_mmc0, + &exynos4_clk_sclk_mmc1, + &exynos4_clk_sclk_mmc2, + &exynos4_clk_sclk_mmc3, + &exynos4_clk_sclk_spi0, + &exynos4_clk_sclk_spi1, + &exynos4_clk_sclk_spi2, + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, +}; + +static struct clk_lookup exynos4_clk_lookup[] = { + CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), + CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), + CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), + CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), + CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), +}; + +static int xtal_rate; + +static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) +{ + if (soc_is_exynos4210()) + return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), + pll_4508); + else if (soc_is_exynos4212() || soc_is_exynos4412()) + return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0)); + else + return 0; +} + +static struct clk_ops exynos4_fout_apll_ops = { + .get_rate = exynos4_fout_apll_get_rate, +}; + +static u32 exynos4_vpll_div[][8] = { + { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, + { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, +}; + +static unsigned long exynos4_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con0, vpll_con1 = 0; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); + vpll_con0 &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1); + vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ + PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ + PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { + if (exynos4_vpll_div[i][0] == rate) { + vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; + vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; + vpll_con0 |= exynos4_vpll_div[i][7] << 27; + break; + } + } + + if (i == ARRAY_SIZE(exynos4_vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); + __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1); + + /* Wait for VPLL lock */ + while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} + +static struct clk_ops exynos4_vpll_ops = { + .get_rate = exynos4_vpll_get_rate, + .set_rate = exynos4_vpll_set_rate, +}; + +void __init_or_cpufreq exynos4_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long apll = 0; + unsigned long mpll = 0; + unsigned long epll = 0; + unsigned long vpll = 0; + unsigned long vpllsrc; + unsigned long xtal; + unsigned long armclk; + unsigned long sclk_dmc; + unsigned long aclk_200; + unsigned long aclk_100; + unsigned long aclk_160; + unsigned long aclk_133; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + if (soc_is_exynos4210()) { + apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), + pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), + pll_4508); + epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), + __raw_readl(EXYNOS4_EPLL_CON1), pll_4600); + + vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); + vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), + __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c); + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0)); + mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0)); + epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), + __raw_readl(EXYNOS4_EPLL_CON1)); + + vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); + vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), + __raw_readl(EXYNOS4_VPLL_CON1)); + } else { + /* nothing */ + } + + clk_fout_apll.ops = &exynos4_fout_apll_ops; + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &exynos4_vpll_ops; + clk_fout_vpll.rate = vpll; + + printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", + apll, mpll, epll, vpll); + + armclk = clk_get_rate(&exynos4_clk_armclk.clk); + sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk); + + aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk); + aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk); + aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk); + aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk); + + printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" + "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", + armclk, sclk_dmc, aclk_200, + aclk_100, aclk_160, aclk_133); + + clk_f.rate = armclk; + clk_h.rate = sclk_dmc; + clk_p.rate = aclk_100; + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++) + s3c_set_clksrc(&exynos4_clksrcs[ptr], true); +} + +static struct clk *exynos4_clks[] __initdata = { + &exynos4_clk_sclk_hdmi27m, + &exynos4_clk_sclk_hdmiphy, + &exynos4_clk_sclk_usbphy0, + &exynos4_clk_sclk_usbphy1, +}; + +#ifdef CONFIG_PM_SLEEP +static int exynos4_clock_suspend(void) +{ + s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); + return 0; +} + +static void exynos4_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); +} + +#else +#define exynos4_clock_suspend NULL +#define exynos4_clock_resume NULL +#endif + +static struct syscore_ops exynos4_clock_syscore_ops = { + .suspend = exynos4_clock_suspend, + .resume = exynos4_clock_resume, +}; + +void __init exynos4_register_clocks(void) +{ + int ptr; + + s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks)); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++) + s3c_register_clksrc(exynos4_sysclks[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++) + s3c_register_clksrc(exynos4_sclk_tv[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++) + s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1); + + s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs)); + s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on)); + + s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++) + s3c_disable_clocks(exynos4_clk_cdev[ptr], 1); + + s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); + s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); + clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); + + register_syscore_ops(&exynos4_clock_syscore_ops); + s3c24xx_register_clock(&dummy_apb_pclk); + + s3c_pwmclk_init(); +} diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4.h b/trunk/arch/arm/mach-exynos/clock-exynos4.h new file mode 100644 index 000000000000..bd12d5f8b63d --- /dev/null +++ b/trunk/arch/arm/mach-exynos/clock-exynos4.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Header file for exynos4 clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H __FILE__ + +#include + +extern struct clksrc_clk exynos4_clk_aclk_133; +extern struct clksrc_clk exynos4_clk_mout_mpll; + +extern struct clksrc_sources exynos4_clkset_mout_corebus; +extern struct clksrc_sources exynos4_clkset_group; + +extern struct clk *exynos4_clkset_aclk_top_list[]; +extern struct clk *exynos4_clkset_group_list[]; + +extern struct clksrc_sources exynos4_clkset_mout_g2d0; +extern struct clksrc_sources exynos4_clkset_mout_g2d1; + +extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable); +extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4210.c b/trunk/arch/arm/mach-exynos/clock-exynos4210.c new file mode 100644 index 000000000000..19af9f783c56 --- /dev/null +++ b/trunk/arch/arm/mach-exynos/clock-exynos4210.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4210 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "clock-exynos4.h" + +#ifdef CONFIG_PM_SLEEP +static struct sleep_save exynos4210_clock_save[] = { + SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE), + SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE), + SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1), + SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1), + SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1), + SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR), +}; +#endif + +static struct clksrc_clk *sysclks[] = { + /* nothing here yet */ +}; + +static struct clksrc_clk exynos4210_clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + }, + .sources = &exynos4_clkset_mout_g2d0, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk exynos4210_clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + }, + .sources = &exynos4_clkset_mout_g2d1, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 }, +}; + +static struct clk *exynos4210_clkset_mout_g2d_list[] = { + [0] = &exynos4210_clk_mout_g2d0.clk, + [1] = &exynos4210_clk_mout_g2d1.clk, +}; + +static struct clksrc_sources exynos4210_clkset_mout_g2d = { + .sources = exynos4210_clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list), +}; + +static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable); +} + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "sclk_sata", + .id = -1, + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos4_clkset_mout_corebus, + .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clksrc_mask_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimg2d", + }, + .sources = &exynos4210_clkset_mout_g2d, + .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 }, + }, +}; + +static struct clk init_clocks_off[] = { + { + .name = "sataphy", + .id = -1, + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "sata", + .id = -1, + .parent = &exynos4_clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.9", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.11", + .enable = exynos4_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "fimg2d", + .enable = exynos4_clk_ip_image_ctrl, + .ctrlbit = (1 << 0), + }, +}; + +#ifdef CONFIG_PM_SLEEP +static int exynos4210_clock_suspend(void) +{ + s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); + + return 0; +} + +static void exynos4210_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); +} + +#else +#define exynos4210_clock_suspend NULL +#define exynos4210_clock_resume NULL +#endif + +static struct syscore_ops exynos4210_clock_syscore_ops = { + .suspend = exynos4210_clock_suspend, + .resume = exynos4210_clock_resume, +}; + +void __init exynos4210_register_clocks(void) +{ + int ptr; + + exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU; + exynos4_clk_mout_mpll.reg_src.shift = 8; + exynos4_clk_mout_mpll.reg_src.size = 1; + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + register_syscore_ops(&exynos4210_clock_syscore_ops); +} diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4212.c b/trunk/arch/arm/mach-exynos/clock-exynos4212.c new file mode 100644 index 000000000000..529476f8ec71 --- /dev/null +++ b/trunk/arch/arm/mach-exynos/clock-exynos4212.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4212 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "clock-exynos4.h" + +#ifdef CONFIG_PM_SLEEP +static struct sleep_save exynos4212_clock_save[] = { + SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE), + SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE), + SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE), + SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR), +}; +#endif + +static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable); +} + +static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable); +} + +static struct clk *clk_src_mpll_user_list[] = { + [0] = &clk_fin_mpll, + [1] = &exynos4_clk_mout_mpll.clk, +}; + +static struct clksrc_sources clk_src_mpll_user = { + .sources = clk_src_mpll_user_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list), +}; + +static struct clksrc_clk clk_mout_mpll_user = { + .clk = { + .name = "mout_mpll_user", + }, + .sources = &clk_src_mpll_user, + .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk exynos4x12_clk_mout_g2d0 = { + .clk = { + .name = "mout_g2d0", + }, + .sources = &exynos4_clkset_mout_g2d0, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 }, +}; + +static struct clksrc_clk exynos4x12_clk_mout_g2d1 = { + .clk = { + .name = "mout_g2d1", + }, + .sources = &exynos4_clkset_mout_g2d1, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 }, +}; + +static struct clk *exynos4x12_clkset_mout_g2d_list[] = { + [0] = &exynos4x12_clk_mout_g2d0.clk, + [1] = &exynos4x12_clk_mout_g2d1.clk, +}; + +static struct clksrc_sources exynos4x12_clkset_mout_g2d = { + .sources = exynos4x12_clkset_mout_g2d_list, + .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list), +}; + +static struct clksrc_clk *sysclks[] = { + &clk_mout_mpll_user, +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "sclk_fimg2d", + }, + .sources = &exynos4x12_clkset_mout_g2d, + .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 }, + }, +}; + +static struct clk init_clocks_off[] = { + { + .name = "sysmmu", + .devname = "exynos-sysmmu.9", + .enable = exynos4_clk_ip_dmc_ctrl, + .ctrlbit = (1 << 24), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.12", + .enable = exynos4212_clk_ip_isp0_ctrl, + .ctrlbit = (7 << 8), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.13", + .enable = exynos4212_clk_ip_isp1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.14", + .enable = exynos4212_clk_ip_isp0_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.15", + .enable = exynos4212_clk_ip_isp0_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "flite", + .devname = "exynos-fimc-lite.0", + .enable = exynos4212_clk_ip_isp0_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "flite", + .devname = "exynos-fimc-lite.1", + .enable = exynos4212_clk_ip_isp0_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "fimg2d", + .enable = exynos4_clk_ip_dmc_ctrl, + .ctrlbit = (1 << 23), + }, +}; + +#ifdef CONFIG_PM_SLEEP +static int exynos4212_clock_suspend(void) +{ + s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); + + return 0; +} + +static void exynos4212_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); +} + +#else +#define exynos4212_clock_suspend NULL +#define exynos4212_clock_resume NULL +#endif + +static struct syscore_ops exynos4212_clock_syscore_ops = { + .suspend = exynos4212_clock_suspend, + .resume = exynos4212_clock_resume, +}; + +void __init exynos4212_register_clocks(void) +{ + int ptr; + + /* usbphy1 is removed */ + exynos4_clkset_group_list[4] = NULL; + + /* mout_mpll_user is used */ + exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk; + exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; + + exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC; + exynos4_clk_mout_mpll.reg_src.shift = 12; + exynos4_clk_mout_mpll.reg_src.size = 1; + + for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) + s3c_register_clksrc(sysclks[ptr], 1); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + + s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); + + register_syscore_ops(&exynos4212_clock_syscore_ops); +} diff --git a/trunk/arch/arm/mach-exynos/clock-exynos5.c b/trunk/arch/arm/mach-exynos/clock-exynos5.c new file mode 100644 index 000000000000..b0ea31fc9fb8 --- /dev/null +++ b/trunk/arch/arm/mach-exynos/clock-exynos5.c @@ -0,0 +1,1645 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Clock support for EXYNOS5 SoCs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" + +#ifdef CONFIG_PM_SLEEP +static struct sleep_save exynos5_clock_save[] = { + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0), + SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC), + SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS), + SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK), + SAVE_ITEM(EXYNOS5_CLKDIV_TOP0), + SAVE_ITEM(EXYNOS5_CLKDIV_TOP1), + SAVE_ITEM(EXYNOS5_CLKDIV_GSCL), + SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0), + SAVE_ITEM(EXYNOS5_CLKDIV_GEN), + SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO), + SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0), + SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1), + SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2), + SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4), + SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5), + SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP), + SAVE_ITEM(EXYNOS5_CLKSRC_TOP0), + SAVE_ITEM(EXYNOS5_CLKSRC_TOP1), + SAVE_ITEM(EXYNOS5_CLKSRC_TOP2), + SAVE_ITEM(EXYNOS5_CLKSRC_TOP3), + SAVE_ITEM(EXYNOS5_CLKSRC_GSCL), + SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0), + SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO), + SAVE_ITEM(EXYNOS5_CLKSRC_FSYS), + SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0), + SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1), + SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP), + SAVE_ITEM(EXYNOS5_EPLL_CON0), + SAVE_ITEM(EXYNOS5_EPLL_CON1), + SAVE_ITEM(EXYNOS5_EPLL_CON2), + SAVE_ITEM(EXYNOS5_VPLL_CON0), + SAVE_ITEM(EXYNOS5_VPLL_CON1), + SAVE_ITEM(EXYNOS5_VPLL_CON2), + SAVE_ITEM(EXYNOS5_PWR_CTRL1), + SAVE_ITEM(EXYNOS5_PWR_CTRL2), +}; +#endif + +static struct clk exynos5_clk_sclk_dptxphy = { + .name = "sclk_dptx", +}; + +static struct clk exynos5_clk_sclk_hdmi24m = { + .name = "sclk_hdmi24m", + .rate = 24000000, +}; + +static struct clk exynos5_clk_sclk_hdmi27m = { + .name = "sclk_hdmi27m", + .rate = 27000000, +}; + +static struct clk exynos5_clk_sclk_hdmiphy = { + .name = "sclk_hdmiphy", +}; + +static struct clk exynos5_clk_sclk_usbphy = { + .name = "sclk_usbphy", + .rate = 48000000, +}; + +static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable); +} + +static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable); +} + +static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable); +} + +static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable); +} + +static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); +} + +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); +} + +static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); +} + +static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable); +} + +static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable); +} + +static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable); +} + +static int exynos5_clk_block_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable); +} + +static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); +} + +static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); +} + +static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable); +} + +static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable); +} + +static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable); +} + +static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable); +} + +static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable); +} + +static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +/* Core list of CMU_CPU side */ + +static struct clksrc_clk exynos5_clk_mout_apll = { + .clk = { + .name = "mout_apll", + }, + .sources = &clk_src_apll, + .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_apll = { + .clk = { + .name = "sclk_apll", + .parent = &exynos5_clk_mout_apll.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_mout_bpll_fout = { + .clk = { + .name = "mout_bpll_fout", + }, + .sources = &clk_src_bpll_fout, + .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos5_clk_src_bpll_list[] = { + [0] = &clk_fin_bpll, + [1] = &exynos5_clk_mout_bpll_fout.clk, +}; + +static struct clksrc_sources exynos5_clk_src_bpll = { + .sources = exynos5_clk_src_bpll_list, + .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list), +}; + +static struct clksrc_clk exynos5_clk_mout_bpll = { + .clk = { + .name = "mout_bpll", + }, + .sources = &exynos5_clk_src_bpll, + .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos5_clk_src_bpll_user_list[] = { + [0] = &clk_fin_mpll, + [1] = &exynos5_clk_mout_bpll.clk, +}; + +static struct clksrc_sources exynos5_clk_src_bpll_user = { + .sources = exynos5_clk_src_bpll_user_list, + .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list), +}; + +static struct clksrc_clk exynos5_clk_mout_bpll_user = { + .clk = { + .name = "mout_bpll_user", + }, + .sources = &exynos5_clk_src_bpll_user, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_mout_cpll = { + .clk = { + .name = "mout_cpll", + }, + .sources = &clk_src_cpll, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_mout_epll = { + .clk = { + .name = "mout_epll", + }, + .sources = &clk_src_epll, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_mout_mpll_fout = { + .clk = { + .name = "mout_mpll_fout", + }, + .sources = &clk_src_mpll_fout, + .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 }, +}; + +static struct clk *exynos5_clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &exynos5_clk_mout_mpll_fout.clk, +}; + +static struct clksrc_sources exynos5_clk_src_mpll = { + .sources = exynos5_clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list), +}; + +static struct clksrc_clk exynos5_clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + }, + .sources = &exynos5_clk_src_mpll, + .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, +}; + +static struct clk *exynos_clkset_vpllsrc_list[] = { + [0] = &clk_fin_vpll, + [1] = &exynos5_clk_sclk_hdmi27m, +}; + +static struct clksrc_sources exynos5_clkset_vpllsrc = { + .sources = exynos_clkset_vpllsrc_list, + .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list), +}; + +static struct clksrc_clk exynos5_clk_vpllsrc = { + .clk = { + .name = "vpll_src", + .enable = exynos5_clksrc_mask_top_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_vpllsrc, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 }, +}; + +static struct clk *exynos5_clkset_sclk_vpll_list[] = { + [0] = &exynos5_clk_vpllsrc.clk, + [1] = &clk_fout_vpll, +}; + +static struct clksrc_sources exynos5_clkset_sclk_vpll = { + .sources = exynos5_clkset_sclk_vpll_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list), +}; + +static struct clksrc_clk exynos5_clk_sclk_vpll = { + .clk = { + .name = "sclk_vpll", + }, + .sources = &exynos5_clkset_sclk_vpll, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", + .parent = &exynos5_clk_sclk_vpll.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 }, +}; + +static struct clk *exynos5_clkset_sclk_hdmi_list[] = { + [0] = &exynos5_clk_sclk_pixel.clk, + [1] = &exynos5_clk_sclk_hdmiphy, +}; + +static struct clksrc_sources exynos5_clkset_sclk_hdmi = { + .sources = exynos5_clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk exynos5_clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", + .enable = exynos5_clksrc_mask_disp1_0_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &exynos5_clkset_sclk_hdmi, + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 }, +}; + +static struct clksrc_clk *exynos5_sclk_tv[] = { + &exynos5_clk_sclk_pixel, + &exynos5_clk_sclk_hdmi, +}; + +static struct clk *exynos5_clk_src_mpll_user_list[] = { + [0] = &clk_fin_mpll, + [1] = &exynos5_clk_mout_mpll.clk, +}; + +static struct clksrc_sources exynos5_clk_src_mpll_user = { + .sources = exynos5_clk_src_mpll_user_list, + .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list), +}; + +static struct clksrc_clk exynos5_clk_mout_mpll_user = { + .clk = { + .name = "mout_mpll_user", + }, + .sources = &exynos5_clk_src_mpll_user, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 }, +}; + +static struct clk *exynos5_clkset_mout_cpu_list[] = { + [0] = &exynos5_clk_mout_apll.clk, + [1] = &exynos5_clk_mout_mpll.clk, +}; + +static struct clksrc_sources exynos5_clkset_mout_cpu = { + .sources = exynos5_clkset_mout_cpu_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list), +}; + +static struct clksrc_clk exynos5_clk_mout_cpu = { + .clk = { + .name = "mout_cpu", + }, + .sources = &exynos5_clkset_mout_cpu, + .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 }, +}; + +static struct clksrc_clk exynos5_clk_dout_armclk = { + .clk = { + .name = "dout_armclk", + .parent = &exynos5_clk_mout_cpu.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_dout_arm2clk = { + .clk = { + .name = "dout_arm2clk", + .parent = &exynos5_clk_dout_armclk.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 }, +}; + +static struct clk exynos5_clk_armclk = { + .name = "armclk", + .parent = &exynos5_clk_dout_arm2clk.clk, +}; + +/* Core list of CMU_CDREX side */ + +static struct clk *exynos5_clkset_cdrex_list[] = { + [0] = &exynos5_clk_mout_mpll.clk, + [1] = &exynos5_clk_mout_bpll.clk, +}; + +static struct clksrc_sources exynos5_clkset_cdrex = { + .sources = exynos5_clkset_cdrex_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list), +}; + +static struct clksrc_clk exynos5_clk_cdrex = { + .clk = { + .name = "clk_cdrex", + }, + .sources = &exynos5_clkset_cdrex, + .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_acp = { + .clk = { + .name = "aclk_acp", + .parent = &exynos5_clk_mout_mpll.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_pclk_acp = { + .clk = { + .name = "pclk_acp", + .parent = &exynos5_clk_aclk_acp.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 }, +}; + +/* Core list of CMU_TOP side */ + +static struct clk *exynos5_clkset_aclk_top_list[] = { + [0] = &exynos5_clk_mout_mpll_user.clk, + [1] = &exynos5_clk_mout_bpll_user.clk, +}; + +static struct clksrc_sources exynos5_clkset_aclk = { + .sources = exynos5_clkset_aclk_top_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list), +}; + +static struct clksrc_clk exynos5_clk_aclk_400 = { + .clk = { + .name = "aclk_400", + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, +}; + +static struct clk *exynos5_clkset_aclk_333_166_list[] = { + [0] = &exynos5_clk_mout_cpll.clk, + [1] = &exynos5_clk_mout_mpll_user.clk, +}; + +static struct clksrc_sources exynos5_clkset_aclk_333_166 = { + .sources = exynos5_clkset_aclk_333_166_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list), +}; + +static struct clksrc_clk exynos5_clk_aclk_333 = { + .clk = { + .name = "aclk_333", + }, + .sources = &exynos5_clkset_aclk_333_166, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_166 = { + .clk = { + .name = "aclk_166", + }, + .sources = &exynos5_clkset_aclk_333_166, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_266 = { + .clk = { + .name = "aclk_266", + .parent = &exynos5_clk_mout_mpll_user.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_200 = { + .clk = { + .name = "aclk_200", + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_66_pre = { + .clk = { + .name = "aclk_66_pre", + .parent = &exynos5_clk_mout_mpll_user.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_aclk_66 = { + .clk = { + .name = "aclk_66", + .parent = &exynos5_clk_aclk_66_pre.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 }, +}; + +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { + .clk = { + .name = "mout_aclk_300_gscl_mid", + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, +}; + +static struct clk *exynos5_clkset_aclk_300_mid1_list[] = { + [0] = &exynos5_clk_sclk_vpll.clk, + [1] = &exynos5_clk_mout_cpll.clk, +}; + +static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = { + .sources = exynos5_clkset_aclk_300_mid1_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list), +}; + +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = { + .clk = { + .name = "mout_aclk_300_gscl_mid1", + }, + .sources = &exynos5_clkset_aclk_300_gscl_mid1, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 }, +}; + +static struct clk *exynos5_clkset_aclk_300_gscl_list[] = { + [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, + [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk, +}; + +static struct clksrc_sources exynos5_clkset_aclk_300_gscl = { + .sources = exynos5_clkset_aclk_300_gscl_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list), +}; + +static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = { + .clk = { + .name = "mout_aclk_300_gscl", + }, + .sources = &exynos5_clkset_aclk_300_gscl, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 }, +}; + +static struct clk *exynos5_clk_src_gscl_300_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &exynos5_clk_mout_aclk_300_gscl.clk, +}; + +static struct clksrc_sources exynos5_clk_src_gscl_300 = { + .sources = exynos5_clk_src_gscl_300_list, + .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list), +}; + +static struct clksrc_clk exynos5_clk_aclk_300_gscl = { + .clk = { + .name = "aclk_300_gscl", + }, + .sources = &exynos5_clk_src_gscl_300, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, +}; + +static struct clk exynos5_init_clocks_off[] = { + { + .name = "timers", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 24), + }, { + .name = "tmu_apbif", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peris_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "rtc", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peris_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "watchdog", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peris_ctrl, + .ctrlbit = (1 << 19), + }, { + .name = "biu", /* bus interface unit clock */ + .devname = "dw_mmc.0", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "biu", + .devname = "dw_mmc.1", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "biu", + .devname = "dw_mmc.2", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "biu", + .devname = "dw_mmc.3", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 15), + }, { + .name = "sata", + .devname = "exynos5-sata", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "sata-phy", + .devname = "exynos5-sata-phy", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 24), + }, { + .name = "i2c", + .devname = "exynos5-sata-phy-i2c", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 25), + }, { + .name = "mfc", + .devname = "s5p-mfc-v6", + .enable = exynos5_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hdmi", + .devname = "exynos5-hdmi", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "hdmiphy", + .devname = "exynos5-hdmi", + .enable = exynos5_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "mixer", + .devname = "exynos5-mixer", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 5), + }, { + .name = "dp", + .devname = "exynos-dp", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "jpeg", + .enable = exynos5_clk_ip_gen_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "dsim0", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "iis", + .devname = "samsung-i2s.1", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 20), + }, { + .name = "iis", + .devname = "samsung-i2s.2", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 21), + }, { + .name = "pcm", + .devname = "samsung-pcm.1", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 22), + }, { + .name = "pcm", + .devname = "samsung-pcm.2", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 23), + }, { + .name = "spdif", + .devname = "samsung-spdif", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 26), + }, { + .name = "ac97", + .devname = "samsung-ac97", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 27), + }, { + .name = "usbhost", + .enable = exynos5_clk_ip_fsys_ctrl , + .ctrlbit = (1 << 18), + }, { + .name = "usbotg", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "nfcon", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 22), + }, { + .name = "iop", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)), + }, { + .name = "core_iop", + .enable = exynos5_clk_ip_core_ctrl, + .ctrlbit = ((1 << 21) | (1 << 3)), + }, { + .name = "mcu_iop", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 6), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.3", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.4", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.5", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.6", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "i2c", + .devname = "s3c2440-i2c.7", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 13), + }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 14), + }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 18), + }, { + .name = "gscl", + .devname = "exynos-gsc.0", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "gscl", + .devname = "exynos-gsc.1", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "gscl", + .devname = "exynos-gsc.2", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "gscl", + .devname = "exynos-gsc.3", + .enable = exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.1", + .enable = &exynos5_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.0", + .enable = &exynos5_clk_ip_mfc_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.2", + .enable = &exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 9) + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.3", + .enable = &exynos5_clk_ip_gen_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.4", + .enable = &exynos5_clk_ip_gen_ctrl, + .ctrlbit = (1 << 6) + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.5", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 7), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.6", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.7", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.8", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.9", + .enable = &exynos5_clk_ip_isp0_ctrl, + .ctrlbit = (0x3F << 8), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.10", + .enable = &exynos5_clk_ip_isp1_ctrl, + .ctrlbit = (0xF << 4), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.11", + .enable = &exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 8) + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.12", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.13", + .enable = &exynos5_clk_ip_gscl_ctrl, + .ctrlbit = (1 << 12), + }, { + .name = "sysmmu", + .devname = "exynos-sysmmu.14", + .enable = &exynos5_clk_ip_acp_ctrl, + .ctrlbit = (1 << 7) + } +}; + +static struct clk exynos5_init_clocks_on[] = { + { + .name = "uart", + .devname = "s5pv210-uart.0", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "uart", + .devname = "s5pv210-uart.1", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "uart", + .devname = "s5pv210-uart.2", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "uart", + .devname = "s5pv210-uart.3", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "uart", + .devname = "s5pv210-uart.4", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 4), + }, { + .name = "uart", + .devname = "s5pv210-uart.5", + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 5), + } +}; + +static struct clk exynos5_clk_pdma0 = { + .name = "dma", + .devname = "dma-pl330.0", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 1), +}; + +static struct clk exynos5_clk_pdma1 = { + .name = "dma", + .devname = "dma-pl330.1", + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 2), +}; + +static struct clk exynos5_clk_mdma1 = { + .name = "dma", + .devname = "dma-pl330.2", + .enable = exynos5_clk_ip_gen_ctrl, + .ctrlbit = (1 << 4), +}; + +static struct clk exynos5_clk_fimd1 = { + .name = "fimd", + .devname = "exynos5-fb.1", + .enable = exynos5_clk_ip_disp1_ctrl, + .ctrlbit = (1 << 0), +}; + +static struct clk *exynos5_clkset_group_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = NULL, + [2] = &exynos5_clk_sclk_hdmi24m, + [3] = &exynos5_clk_sclk_dptxphy, + [4] = &exynos5_clk_sclk_usbphy, + [5] = &exynos5_clk_sclk_hdmiphy, + [6] = &exynos5_clk_mout_mpll_user.clk, + [7] = &exynos5_clk_mout_epll.clk, + [8] = &exynos5_clk_sclk_vpll.clk, + [9] = &exynos5_clk_mout_cpll.clk, +}; + +static struct clksrc_sources exynos5_clkset_group = { + .sources = exynos5_clkset_group_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list), +}; + +/* Possible clock sources for aclk_266_gscl_sub Mux */ +static struct clk *clk_src_gscl_266_list[] = { + [0] = &clk_ext_xtal_mux, + [1] = &exynos5_clk_aclk_266.clk, +}; + +static struct clksrc_sources clk_src_gscl_266 = { + .sources = clk_src_gscl_266_list, + .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list), +}; + +static struct clksrc_clk exynos5_clk_dout_mmc0 = { + .clk = { + .name = "dout_mmc0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_dout_mmc1 = { + .clk = { + .name = "dout_mmc1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_dout_mmc2 = { + .clk = { + .name = "dout_mmc2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_dout_mmc3 = { + .clk = { + .name = "dout_mmc3", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_dout_mmc4 = { + .clk = { + .name = "dout_mmc4", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_uart0 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.0", + .enable = exynos5_clksrc_mask_peric0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_uart1 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.1", + .enable = exynos5_clksrc_mask_peric0_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_uart2 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.2", + .enable = exynos5_clksrc_mask_peric0_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_uart3 = { + .clk = { + .name = "uclk1", + .devname = "exynos4210-uart.3", + .enable = exynos5_clksrc_mask_peric0_ctrl, + .ctrlbit = (1 << 12), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_mmc0 = { + .clk = { + .name = "ciu", /* card interface unit clock */ + .devname = "dw_mmc.0", + .parent = &exynos5_clk_dout_mmc0.clk, + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 0), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_mmc1 = { + .clk = { + .name = "ciu", + .devname = "dw_mmc.1", + .parent = &exynos5_clk_dout_mmc1.clk, + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 4), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_mmc2 = { + .clk = { + .name = "ciu", + .devname = "dw_mmc.2", + .parent = &exynos5_clk_dout_mmc2.clk, + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 8), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_mmc3 = { + .clk = { + .name = "ciu", + .devname = "dw_mmc.3", + .parent = &exynos5_clk_dout_mmc3.clk, + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 12), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_mdout_spi0.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_mdout_spi1.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_mdout_spi2.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_fimd1 = { + .clk = { + .name = "sclk_fimd", + .devname = "exynos5-fb.1", + .enable = exynos5_clksrc_mask_disp1_0_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clksrcs[] = { + { + .clk = { + .name = "aclk_266_gscl", + }, + .sources = &clk_src_gscl_266, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 }, + }, { + .clk = { + .name = "sclk_g3d", + .devname = "mali-t604.0", + .enable = exynos5_clk_block_ctrl, + .ctrlbit = (1 << 1), + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, + }, { + .clk = { + .name = "sclk_sata", + .devname = "exynos5-sata", + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos5_clkset_aclk, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_gscl_wrap", + .devname = "s5p-mipi-csis.0", + .enable = exynos5_clksrc_mask_gscl_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 }, + }, { + .clk = { + .name = "sclk_gscl_wrap", + .devname = "s5p-mipi-csis.1", + .enable = exynos5_clksrc_mask_gscl_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam0", + .enable = exynos5_clksrc_mask_gscl_ctrl, + .ctrlbit = (1 << 16), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "sclk_cam1", + .enable = exynos5_clksrc_mask_gscl_ctrl, + .ctrlbit = (1 << 20), + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 }, + }, { + .clk = { + .name = "sclk_jpeg", + .parent = &exynos5_clk_mout_cpll.clk, + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 }, + }, +}; + +/* Clock initialization code */ +static struct clksrc_clk *exynos5_sysclks[] = { + &exynos5_clk_mout_apll, + &exynos5_clk_sclk_apll, + &exynos5_clk_mout_bpll, + &exynos5_clk_mout_bpll_fout, + &exynos5_clk_mout_bpll_user, + &exynos5_clk_mout_cpll, + &exynos5_clk_mout_epll, + &exynos5_clk_mout_mpll, + &exynos5_clk_mout_mpll_fout, + &exynos5_clk_mout_mpll_user, + &exynos5_clk_vpllsrc, + &exynos5_clk_sclk_vpll, + &exynos5_clk_mout_cpu, + &exynos5_clk_dout_armclk, + &exynos5_clk_dout_arm2clk, + &exynos5_clk_cdrex, + &exynos5_clk_aclk_400, + &exynos5_clk_aclk_333, + &exynos5_clk_aclk_266, + &exynos5_clk_aclk_200, + &exynos5_clk_aclk_166, + &exynos5_clk_aclk_300_gscl, + &exynos5_clk_mout_aclk_300_gscl, + &exynos5_clk_mout_aclk_300_gscl_mid, + &exynos5_clk_mout_aclk_300_gscl_mid1, + &exynos5_clk_aclk_66_pre, + &exynos5_clk_aclk_66, + &exynos5_clk_dout_mmc0, + &exynos5_clk_dout_mmc1, + &exynos5_clk_dout_mmc2, + &exynos5_clk_dout_mmc3, + &exynos5_clk_dout_mmc4, + &exynos5_clk_aclk_acp, + &exynos5_clk_pclk_acp, + &exynos5_clk_sclk_spi0, + &exynos5_clk_sclk_spi1, + &exynos5_clk_sclk_spi2, + &exynos5_clk_mdout_spi0, + &exynos5_clk_mdout_spi1, + &exynos5_clk_mdout_spi2, + &exynos5_clk_sclk_fimd1, +}; + +static struct clk *exynos5_clk_cdev[] = { + &exynos5_clk_pdma0, + &exynos5_clk_pdma1, + &exynos5_clk_mdma1, + &exynos5_clk_fimd1, +}; + +static struct clksrc_clk *exynos5_clksrc_cdev[] = { + &exynos5_clk_sclk_uart0, + &exynos5_clk_sclk_uart1, + &exynos5_clk_sclk_uart2, + &exynos5_clk_sclk_uart3, + &exynos5_clk_sclk_mmc0, + &exynos5_clk_sclk_mmc1, + &exynos5_clk_sclk_mmc2, + &exynos5_clk_sclk_mmc3, +}; + +static struct clk_lookup exynos5_clk_lookup[] = { + CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk), + CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), + CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), + CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), + CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), + CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), + CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), + CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), + CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), + CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), + CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), + CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1), +}; + +static unsigned long exynos5_epll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static struct clk *exynos5_clks[] __initdata = { + &exynos5_clk_sclk_hdmi27m, + &exynos5_clk_sclk_hdmiphy, + &clk_fout_bpll, + &clk_fout_bpll_div2, + &clk_fout_cpll, + &clk_fout_mpll_div2, + &exynos5_clk_armclk, +}; + +static u32 epll_div[][6] = { + { 192000000, 0, 48, 3, 1, 0 }, + { 180000000, 0, 45, 3, 1, 0 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 67737600, 1, 90, 4, 3, 20762 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 45158400, 0, 45, 3, 3, 10381 }, + { 180633600, 0, 45, 3, 1, 10381 }, +}; + +static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + unsigned int tmp; + unsigned int epll_rate; + unsigned int locktime; + unsigned int lockcnt; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + if (clk->parent) + epll_rate = clk_get_rate(clk->parent); + else + epll_rate = clk_ext_xtal_mux.rate; + + if (epll_rate != 24000000) { + pr_err("Invalid Clock : recommended clock is 24MHz.\n"); + return -EINVAL; + } + + epll_con = __raw_readl(EXYNOS5_EPLL_CON0); + epll_con &= ~(0x1 << 27 | \ + PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k = epll_div[i][5] << 0; + epll_con |= epll_div[i][1] << 27; + epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT; + epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT; + epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT; + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", + __func__); + return -EINVAL; + } + + epll_rate /= 1000000; + + /* 3000 max_cycls : specification data */ + locktime = 3000 / epll_rate * epll_div[i][3]; + lockcnt = locktime * 10000 / (10000 / epll_rate); + + __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK); + + __raw_writel(epll_con, EXYNOS5_EPLL_CON0); + __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1); + + do { + tmp = __raw_readl(EXYNOS5_EPLL_CON0); + } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT)); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops exynos5_epll_ops = { + .get_rate = exynos5_epll_get_rate, + .set_rate = exynos5_epll_set_rate, +}; + +static int xtal_rate; + +static unsigned long exynos5_fout_apll_get_rate(struct clk *clk) +{ + return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0)); +} + +static struct clk_ops exynos5_fout_apll_ops = { + .get_rate = exynos5_fout_apll_get_rate, +}; + +#ifdef CONFIG_PM +static int exynos5_clock_suspend(void) +{ + s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save)); + + return 0; +} + +static void exynos5_clock_resume(void) +{ + s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save)); +} +#else +#define exynos5_clock_suspend NULL +#define exynos5_clock_resume NULL +#endif + +static struct syscore_ops exynos5_clock_syscore_ops = { + .suspend = exynos5_clock_suspend, + .resume = exynos5_clock_resume, +}; + +void __init_or_cpufreq exynos5_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long apll; + unsigned long bpll; + unsigned long cpll; + unsigned long mpll; + unsigned long epll; + unsigned long vpll; + unsigned long vpllsrc; + unsigned long xtal; + unsigned long armclk; + unsigned long mout_cdrex; + unsigned long aclk_400; + unsigned long aclk_333; + unsigned long aclk_266; + unsigned long aclk_200; + unsigned long aclk_166; + unsigned long aclk_66; + unsigned int ptr; + + printk(KERN_DEBUG "%s: registering clocks\n", __func__); + + xtal_clk = clk_get(NULL, "xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + + xtal_rate = xtal; + + clk_put(xtal_clk); + + printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); + + apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0)); + bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0)); + cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0)); + mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0)); + epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0), + __raw_readl(EXYNOS5_EPLL_CON1)); + + vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk); + vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0), + __raw_readl(EXYNOS5_VPLL_CON1)); + + clk_fout_apll.ops = &exynos5_fout_apll_ops; + clk_fout_bpll.rate = bpll; + clk_fout_bpll_div2.rate = bpll >> 1; + clk_fout_cpll.rate = cpll; + clk_fout_mpll.rate = mpll; + clk_fout_mpll_div2.rate = mpll >> 1; + clk_fout_epll.rate = epll; + clk_fout_vpll.rate = vpll; + + printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n" + "M=%ld, E=%ld V=%ld", + apll, bpll, cpll, mpll, epll, vpll); + + armclk = clk_get_rate(&exynos5_clk_armclk); + mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk); + + aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk); + aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk); + aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk); + aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk); + aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk); + aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk); + + printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n" + "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n" + "ACLK166=%ld, ACLK66=%ld\n", + armclk, mout_cdrex, aclk_400, + aclk_333, aclk_266, aclk_200, + aclk_166, aclk_66); + + + clk_fout_epll.ops = &exynos5_epll_ops; + + if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) + printk(KERN_ERR "Unable to set parent %s of clock %s.\n", + clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); + + clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000); + clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000); + + clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000); + clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++) + s3c_set_clksrc(&exynos5_clksrcs[ptr], true); +} + +void __init exynos5_register_clocks(void) +{ + int ptr; + + s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks)); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++) + s3c_register_clksrc(exynos5_sysclks[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++) + s3c_register_clksrc(exynos5_sclk_tv[ptr], 1); + + for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++) + s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1); + + s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs)); + s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on)); + + s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev)); + for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++) + s3c_disable_clocks(exynos5_clk_cdev[ptr], 1); + + s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off)); + s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off)); + clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup)); + + register_syscore_ops(&exynos5_clock_syscore_ops); + s3c_pwmclk_init(); +} diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c index 02e35abd136b..d63d399c7bae 100644 --- a/trunk/arch/arm/mach-exynos/common.c +++ b/trunk/arch/arm/mach-exynos/common.c @@ -25,8 +25,6 @@ #include #include #include -#include -#include #include #include @@ -41,6 +39,7 @@ #include #include +#include #include #include #include @@ -66,16 +65,17 @@ static const char name_exynos5440[] = "EXYNOS5440"; static void exynos4_map_io(void); static void exynos5_map_io(void); static void exynos5440_map_io(void); +static void exynos4_init_clocks(int xtal); +static void exynos5_init_clocks(int xtal); static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); static int exynos_init(void); -unsigned long xxti_f = 0, xusbxti_f = 0; - static struct cpu_table cpu_ids[] __initdata = { { .idcode = EXYNOS4210_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, + .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4210, @@ -83,6 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS4212_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, + .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4212, @@ -90,6 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS4412_CPU_ID, .idmask = EXYNOS4_CPU_MASK, .map_io = exynos4_map_io, + .init_clocks = exynos4_init_clocks, .init_uarts = exynos4_init_uarts, .init = exynos_init, .name = name_exynos4412, @@ -97,6 +99,7 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = EXYNOS5250_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io, + .init_clocks = exynos5_init_clocks, .init = exynos_init, .name = name_exynos5250, }, { @@ -253,6 +256,11 @@ static struct map_desc exynos5_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_SYSRAM, .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), @@ -394,26 +402,43 @@ static void __init exynos5_map_io(void) iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); } +static void __init exynos4_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + + if (soc_is_exynos4210()) + exynos4210_register_clocks(); + else if (soc_is_exynos4212() || soc_is_exynos4412()) + exynos4212_register_clocks(); + + exynos4_register_clocks(); + exynos4_setup_clocks(); +} + static void __init exynos5440_map_io(void) { iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); } -void __init exynos_init_time(void) +static void __init exynos5_init_clocks(int xtal) { - if (of_have_populated_dt()) { -#ifdef CONFIG_OF - of_clk_init(NULL); - clocksource_of_init(); -#endif - } else { - /* todo: remove after migrating legacy E4 platforms to dt */ -#ifdef CONFIG_ARCH_EXYNOS4 - exynos4_clk_init(NULL); - exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + /* EXYNOS5440 can support only common clock framework */ + + if (soc_is_exynos5440()) + return; + +#ifdef CONFIG_SOC_EXYNOS5250 + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + + exynos5_register_clocks(); + exynos5_setup_clocks(); #endif - mct_init(); - } } void __init exynos4_init_irq(void) diff --git a/trunk/arch/arm/mach-exynos/common.h b/trunk/arch/arm/mach-exynos/common.h index cb89ab886950..9339bb8954be 100644 --- a/trunk/arch/arm/mach-exynos/common.h +++ b/trunk/arch/arm/mach-exynos/common.h @@ -12,11 +12,7 @@ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H -#include - -extern void mct_init(void); -void exynos_init_time(void); -extern unsigned long xxti_f, xusbxti_f; +extern void exynos4_timer_init(void); struct map_desc; void exynos_init_io(struct map_desc *mach_desc, int size); @@ -26,10 +22,6 @@ void exynos4_restart(char mode, const char *cmd); void exynos5_restart(char mode, const char *cmd); void exynos_init_late(void); -/* ToDo: remove these after migrating legacy exynos4 platforms to dt */ -void exynos4_clk_init(struct device_node *np); -void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); - #ifdef CONFIG_PM_GENERIC_DOMAINS int exynos_pm_late_initcall(void); #else diff --git a/trunk/arch/arm/mach-exynos/include/mach/irqs.h b/trunk/arch/arm/mach-exynos/include/mach/irqs.h index c0e75d8dd737..1f4dc35cd4b9 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/irqs.h +++ b/trunk/arch/arm/mach-exynos/include/mach/irqs.h @@ -30,6 +30,8 @@ /* For EXYNOS4 and EXYNOS5 */ +#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) + #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) /* For EXYNOS4 SoCs */ @@ -321,6 +323,8 @@ #define EXYNOS5_IRQ_CEC IRQ_SPI(114) #define EXYNOS5_IRQ_SATA IRQ_SPI(115) +#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) +#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) @@ -415,6 +419,8 @@ #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) +#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) +#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h index 7f99b7b187d6..1df6abbf53b8 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -65,6 +65,7 @@ #define EXYNOS5_PA_CMU 0x10010000 #define EXYNOS4_PA_SYSTIMER 0x10050000 +#define EXYNOS5_PA_SYSTIMER 0x101C0000 #define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS5_PA_WATCHDOG 0x101D0000 diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h b/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h index 20fbbdddd105..d36ad76ad6a4 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/trunk/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -256,6 +256,113 @@ #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) +/* For EXYNOS5250 */ + +#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) +#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) +#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) +#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) +#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) +#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) +#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) +#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) + +#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) +#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) + +#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) +#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) + +#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) + +#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) + +#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) +#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) +#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138) +#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) +#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) +#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148) +#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) + +#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) +#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214) +#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) +#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) +#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) +#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) +#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240) +#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) +#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) +#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254) +#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270) + +#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) +#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) +#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) +#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334) +#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) +#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) +#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354) + +#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) +#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) +#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) +#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) +#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) +#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544) +#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) +#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) +#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) +#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) +#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) +#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C) +#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560) +#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564) +#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568) +#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) +#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) + +#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) +#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) +#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) +#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) +#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) +#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) +#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930) +#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) +#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) +#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) +#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) +#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) +#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) + +#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) +#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) +#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) + +#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) + +#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) + +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) + +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + /* Compatibility defines and inclusion */ #include diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h new file mode 100644 index 000000000000..80dd02ad6d61 --- /dev/null +++ b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h @@ -0,0 +1,53 @@ +/* arch/arm/mach-exynos4/include/mach/regs-mct.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * EXYNOS4 MCT configutation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_MCT_H +#define __ASM_ARCH_REGS_MCT_H __FILE__ + +#include + +#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x)) + +#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) +#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) +#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) + +#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) +#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) +#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) + +#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) + +#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) +#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) +#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) + +#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_MASK (0xffffff00) + +#define MCT_L_TCNTB_OFFSET (0x00) +#define MCT_L_ICNTB_OFFSET (0x08) +#define MCT_L_TCON_OFFSET (0x20) +#define MCT_L_INT_CSTAT_OFFSET (0x30) +#define MCT_L_INT_ENB_OFFSET (0x34) +#define MCT_L_WSTAT_OFFSET (0x40) + +#define MCT_G_TCON_START (1 << 8) +#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) +#define MCT_G_TCON_COMP0_ENABLE (1 << 0) + +#define MCT_L_TCON_INTERVAL_MODE (1 << 2) +#define MCT_L_TCON_INT_START (1 << 1) +#define MCT_L_TCON_TIMER_START (1 << 0) + +#endif /* __ASM_ARCH_REGS_MCT_H */ diff --git a/trunk/arch/arm/mach-exynos/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c index 2c23b659ae3e..685f29173afa 100644 --- a/trunk/arch/arm/mach-exynos/mach-armlex4210.c +++ b/trunk/arch/arm/mach-exynos/mach-armlex4210.c @@ -177,6 +177,7 @@ static void __init armlex4210_smsc911x_init(void) static void __init armlex4210_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(armlex4210_uartcfgs, ARRAY_SIZE(armlex4210_uartcfgs)); } @@ -201,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .map_io = armlex4210_map_io, .init_machine = armlex4210_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c index ac27f3cd121f..3358088c822a 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -11,26 +11,121 @@ * published by the Free Software Foundation. */ -#include #include -#include #include -#include -#include #include -#include +#include + +#include +#include #include "common.h" +/* + * The following lookup table is used to override device names when devices + * are registered from device tree. This is temporarily added to enable + * device tree support addition for the Exynos4 architecture. + * + * For drivers that require platform data to be provided from the machine + * file, a platform data pointer can also be supplied along with the + * devices names. Usually, the platform data elements that cannot be parsed + * from the device tree by the drivers (example: function pointers) are + * supplied. But it should be noted that this is a temporary mechanism and + * at some point, the drivers should be capable of parsing all the platform + * data from the device tree. + */ +static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0, + "exynos4210-uart.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1, + "exynos4210-uart.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2, + "exynos4210-uart.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3, + "exynos4210-uart.3", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), + "exynos4-sdhci.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1), + "exynos4-sdhci.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2), + "exynos4-sdhci.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3), + "exynos4-sdhci.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), + "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1), + "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2), + "s3c2440-i2c.2", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3), + "s3c2440-i2c.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4), + "s3c2440-i2c.4", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5), + "s3c2440-i2c.5", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6), + "s3c2440-i2c.6", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7), + "s3c2440-i2c.7", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, + "exynos4210-spi.2", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU, + "exynos-tmu", NULL), + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000, + "exynos-sysmmu.0", NULL), /* MFC_L */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000, + "exynos-sysmmu.1", NULL), /* MFC_R */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000, + "exynos-sysmmu.2", NULL), /* TV */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000, + "exynos-sysmmu.3", NULL), /* JPEG */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000, + "exynos-sysmmu.4", NULL), /* ROTATOR */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000, + "exynos-sysmmu.5", NULL), /* FIMC0 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000, + "exynos-sysmmu.6", NULL), /* FIMC1 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000, + "exynos-sysmmu.7", NULL), /* FIMC2 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000, + "exynos-sysmmu.8", NULL), /* FIMC3 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000, + "exynos-sysmmu.9", NULL), /* G2D(4210) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000, + "exynos-sysmmu.9", NULL), /* G2D(4x12) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000, + "exynos-sysmmu.10", NULL), /* FIMD0 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000, + "exynos-sysmmu.11", NULL), /* FIMD1(4210) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000, + "exynos-sysmmu.12", NULL), /* IS0(4x12) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000, + "exynos-sysmmu.13", NULL), /* IS1(4x12) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000, + "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000, + "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */ + {}, +}; + static void __init exynos4_dt_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(24000000); } static void __init exynos4_dt_machine_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + exynos4_auxdata_lookup, NULL); } static char const *exynos4_dt_compat[] __initdata = { @@ -40,18 +135,6 @@ static char const *exynos4_dt_compat[] __initdata = { NULL }; -static void __init exynos4_reserve(void) -{ -#ifdef CONFIG_S5P_DEV_MFC - struct s5p_mfc_dt_meminfo mfc_mem; - - /* Reserve memory for MFC only if it's available */ - mfc_mem.compatible = "samsung,mfc-v5"; - if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem)) - s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff, - mfc_mem.lsize); -#endif -} DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") /* Maintainer: Thomas Abraham */ .smp = smp_ops(exynos_smp_ops), @@ -59,8 +142,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .map_io = exynos4_dt_map_io, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, - .reserve = exynos4_reserve, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c index 753b94f3fca7..acaeb14db54b 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -11,21 +11,151 @@ #include #include +#include #include #include -#include #include +#include #include #include +#include #include #include "common.h" +/* + * The following lookup table is used to override device names when devices + * are registered from device tree. This is temporarily added to enable + * device tree support addition for the EXYNOS5 architecture. + * + * For drivers that require platform data to be provided from the machine + * file, a platform data pointer can also be supplied along with the + * devices names. Usually, the platform data elements that cannot be parsed + * from the device tree by the drivers (example: function pointers) are + * supplied. But it should be noted that this is a temporary mechanism and + * at some point, the drivers should be capable of parsing all the platform + * data from the device tree. + */ +static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0, + "exynos4210-uart.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1, + "exynos4210-uart.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2, + "exynos4210-uart.2", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3, + "exynos4210-uart.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0), + "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), + "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2), + "s3c2440-i2c.2", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3), + "s3c2440-i2c.3", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4), + "s3c2440-i2c.4", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5), + "s3c2440-i2c.5", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6), + "s3c2440-i2c.6", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7), + "s3c2440-i2c.7", NULL), + OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8), + "s3c2440-hdmiphy-i2c", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0, + "dw_mmc.0", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1, + "dw_mmc.1", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2, + "dw_mmc.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3, + "dw_mmc.3", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, + "exynos4210-spi.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000, + "exynos5-sata", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000, + "exynos5-sata-phy", NULL), + OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000, + "exynos5-sata-phy-i2c", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), + OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0, + "exynos-gsc.0", NULL), + OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1, + "exynos-gsc.1", NULL), + OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2, + "exynos-gsc.2", NULL), + OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3, + "exynos-gsc.3", NULL), + OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000, + "exynos5-hdmi", NULL), + OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000, + "exynos5-mixer", NULL), + OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL), + OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000, + "exynos-tmu", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000, + "samsung-i2s.0", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000, + "samsung-i2s.1", NULL), + OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000, + "samsung-i2s.2", NULL), + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000, + "exynos-sysmmu.0", "mfc"), /* MFC_L */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000, + "exynos-sysmmu.1", "mfc"), /* MFC_R */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000, + "exynos-sysmmu.2", NULL), /* TV */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000, + "exynos-sysmmu.3", "jpeg"), /* JPEG */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000, + "exynos-sysmmu.4", NULL), /* ROTATOR */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000, + "exynos-sysmmu.5", "gscl"), /* GSCL0 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000, + "exynos-sysmmu.6", "gscl"), /* GSCL1 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000, + "exynos-sysmmu.7", "gscl"), /* GSCL2 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000, + "exynos-sysmmu.8", "gscl"), /* GSCL3 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000, + "exynos-sysmmu.9", NULL), /* FIMC-IS0 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000, + "exynos-sysmmu.10", NULL), /* FIMC-IS1 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000, + "exynos-sysmmu.11", NULL), /* FIMD1 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000, + "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000, + "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */ + OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000, + "exynos-sysmmu.14", NULL), /* G2D */ + {}, +}; + +static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0, + "exynos4210-uart.0", NULL), + {}, +}; + static void __init exynos5_dt_map_io(void) { + unsigned long root = of_get_flat_dt_root(); + exynos_init_io(NULL, 0); + + if (of_flat_dt_is_compatible(root, "samsung,exynos5250")) + s3c24xx_init_clocks(24000000); } static void __init exynos5_dt_machine_init(void) @@ -52,7 +182,12 @@ static void __init exynos5_dt_machine_init(void) } } - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + if (of_machine_is_compatible("samsung,exynos5250")) + of_platform_populate(NULL, of_default_bus_match_table, + exynos5250_auxdata_lookup, NULL); + else if (of_machine_is_compatible("samsung,exynos5440")) + of_platform_populate(NULL, of_default_bus_match_table, + exynos5440_auxdata_lookup, NULL); } static char const *exynos5_dt_compat[] __initdata = { @@ -81,7 +216,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .map_io = exynos5_dt_map_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index 0c10852423c3..1ea79730187f 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -1330,9 +1330,8 @@ static struct platform_device *nuri_devices[] __initdata = { static void __init nuri_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; } static void __init nuri_reserve(void) @@ -1381,7 +1380,7 @@ MACHINE_START(NURI, "NURI") .map_io = nuri_map_io, .init_machine = nuri_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .reserve = &nuri_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index a9aa5c034b23..579d2d171daa 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -754,9 +754,8 @@ static void s5p_tv_setup(void) static void __init origen_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); - xxti_f = 0; - xusbxti_f = 24000000; } static void __init origen_power_init(void) @@ -816,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN") .map_io = origen_map_io, .init_machine = origen_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .reserve = &origen_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c index 184faa3bd93a..fe6149624b84 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c @@ -322,6 +322,7 @@ static struct platform_device *smdk4x12_devices[] __initdata = { static void __init smdk4x12_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs)); } @@ -375,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212") .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END @@ -389,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412") .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index 75eca7d4e128..d71672922b19 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -371,9 +371,8 @@ static void s5p_tv_setup(void) static void __init smdkv310_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); - xxti_f = 12000000; - xusbxti_f = 24000000; } static void __init smdkv310_reserve(void) @@ -424,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END @@ -437,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210") .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, - .init_time = exynos_init_time, + .init_time = exynos4_timer_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c index 72f08fd7cfa9..497fcb793dc1 100644 --- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c +++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include @@ -1092,10 +1092,9 @@ static struct platform_device *universal_devices[] __initdata = { static void __init universal_map_io(void) { exynos_init_io(NULL, 0); + s3c24xx_init_clocks(clk_xusbxti.rate); s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4); - xxti_f = 0; - xusbxti_f = 24000000; + s5p_set_timer_source(S5P_PWM2, S5P_PWM4); } static void s5p_tv_setup(void) @@ -1153,7 +1152,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") .map_io = universal_map_io, .init_machine = universal_machine_init, .init_late = exynos_init_late, - .init_time = samsung_timer_init, + .init_time = s5p_timer_init, .reserve = &universal_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/drivers/clocksource/exynos_mct.c b/trunk/arch/arm/mach-exynos/mct.c similarity index 65% rename from trunk/drivers/clocksource/exynos_mct.c rename to trunk/arch/arm/mach-exynos/mct.c index 203ac05e2b3d..c9d6650f9b5d 100644 --- a/trunk/drivers/clocksource/exynos_mct.c +++ b/trunk/arch/arm/mach-exynos/mct.c @@ -20,9 +20,6 @@ #include #include #include -#include -#include -#include #include #include @@ -31,36 +28,9 @@ #include #include +#include #include -#define EXYNOS4_MCTREG(x) (x) -#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) -#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) -#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) -#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) -#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) -#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) -#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) -#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) -#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) -#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) -#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) -#define EXYNOS4_MCT_L_MASK (0xffffff00) - -#define MCT_L_TCNTB_OFFSET (0x00) -#define MCT_L_ICNTB_OFFSET (0x08) -#define MCT_L_TCON_OFFSET (0x20) -#define MCT_L_INT_CSTAT_OFFSET (0x30) -#define MCT_L_INT_ENB_OFFSET (0x34) -#define MCT_L_WSTAT_OFFSET (0x40) -#define MCT_G_TCON_START (1 << 8) -#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) -#define MCT_G_TCON_COMP0_ENABLE (1 << 0) -#define MCT_L_TCON_INTERVAL_MODE (1 << 2) -#define MCT_L_TCON_INT_START (1 << 1) -#define MCT_L_TCON_TIMER_START (1 << 0) - #define TICK_BASE_CNT 1 enum { @@ -68,75 +38,64 @@ enum { MCT_INT_PPI }; -enum { - MCT_G0_IRQ, - MCT_G1_IRQ, - MCT_G2_IRQ, - MCT_G3_IRQ, - MCT_L0_IRQ, - MCT_L1_IRQ, - MCT_L2_IRQ, - MCT_L3_IRQ, - MCT_NR_IRQS, -}; - -static void __iomem *reg_base; static unsigned long clk_rate; static unsigned int mct_int_type; -static int mct_irqs[MCT_NR_IRQS]; struct mct_clock_event_device { struct clock_event_device *evt; - unsigned long base; + void __iomem *base; char name[10]; }; -static void exynos4_mct_write(unsigned int value, unsigned long offset) +static void exynos4_mct_write(unsigned int value, void *addr) { - unsigned long stat_addr; + void __iomem *stat_addr; u32 mask; u32 i; - __raw_writel(value, reg_base + offset); + __raw_writel(value, addr); - if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { - stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; - switch (offset & EXYNOS4_MCT_L_MASK) { - case MCT_L_TCON_OFFSET: + if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) { + u32 base = (u32) addr & EXYNOS4_MCT_L_MASK; + switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) { + case (u32) MCT_L_TCON_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 3; /* L_TCON write status */ break; - case MCT_L_ICNTB_OFFSET: + case (u32) MCT_L_ICNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 1; /* L_ICNTB write status */ break; - case MCT_L_TCNTB_OFFSET: + case (u32) MCT_L_TCNTB_OFFSET: + stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET; mask = 1 << 0; /* L_TCNTB write status */ break; default: return; } } else { - switch (offset) { - case EXYNOS4_MCT_G_TCON: + switch ((u32) addr) { + case (u32) EXYNOS4_MCT_G_TCON: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 16; /* G_TCON write status */ break; - case EXYNOS4_MCT_G_COMP0_L: + case (u32) EXYNOS4_MCT_G_COMP0_L: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 0; /* G_COMP0_L write status */ break; - case EXYNOS4_MCT_G_COMP0_U: + case (u32) EXYNOS4_MCT_G_COMP0_U: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 1; /* G_COMP0_U write status */ break; - case EXYNOS4_MCT_G_COMP0_ADD_INCR: + case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: stat_addr = EXYNOS4_MCT_G_WSTAT; mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ break; - case EXYNOS4_MCT_G_CNT_L: + case (u32) EXYNOS4_MCT_G_CNT_L: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 0; /* G_CNT_L write status */ break; - case EXYNOS4_MCT_G_CNT_U: + case (u32) EXYNOS4_MCT_G_CNT_U: stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; mask = 1 << 1; /* G_CNT_U write status */ break; @@ -147,12 +106,12 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset) /* Wait maximum 1 ms until written values are applied */ for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) - if (__raw_readl(reg_base + stat_addr) & mask) { - __raw_writel(mask, reg_base + stat_addr); + if (__raw_readl(stat_addr) & mask) { + __raw_writel(mask, stat_addr); return; } - panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); + panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr); } /* Clocksource handling */ @@ -163,7 +122,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); - reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + reg = __raw_readl(EXYNOS4_MCT_G_TCON); reg |= MCT_G_TCON_START; exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); } @@ -171,12 +130,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo) static cycle_t exynos4_frc_read(struct clocksource *cs) { unsigned int lo, hi; - u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); + u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); do { hi = hi2; - lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); - hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); + lo = __raw_readl(EXYNOS4_MCT_G_CNT_L); + hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U); } while (hi != hi2); return ((cycle_t)hi << 32) | lo; @@ -208,7 +167,7 @@ static void exynos4_mct_comp0_stop(void) { unsigned int tcon; - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + tcon = __raw_readl(EXYNOS4_MCT_G_TCON); tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); @@ -221,7 +180,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode, unsigned int tcon; cycle_t comp_cycle; - tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); + tcon = __raw_readl(EXYNOS4_MCT_G_TCON); if (mode == CLOCK_EVT_MODE_PERIODIC) { tcon |= MCT_G_TCON_COMP0_AUTO_INC; @@ -298,7 +257,11 @@ static void exynos4_clockevent_init(void) mct_comp_device.cpumask = cpumask_of(0); clockevents_config_and_register(&mct_comp_device, clk_rate, 0xf, 0xffffffff); - setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); + + if (soc_is_exynos5250()) + setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); + else + setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq); } #ifdef CONFIG_LOCAL_TIMERS @@ -310,12 +273,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) { unsigned long tmp; unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; - unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; + void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET; - tmp = __raw_readl(reg_base + offset); + tmp = __raw_readl(addr); if (tmp & mask) { tmp &= ~mask; - exynos4_mct_write(tmp, offset); + exynos4_mct_write(tmp, addr); } } @@ -334,7 +297,7 @@ static void exynos4_mct_tick_start(unsigned long cycles, /* enable MCT tick interrupt */ exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); - tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); + tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET); tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | MCT_L_TCON_INTERVAL_MODE; exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); @@ -386,7 +349,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) exynos4_mct_tick_stop(mevt); /* Clear the MCT tick interrupt */ - if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { + if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); return 1; } else { @@ -422,6 +385,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) { struct mct_clock_event_device *mevt; unsigned int cpu = smp_processor_id(); + int mct_lx_irq; mevt = this_cpu_ptr(&percpu_mct_tick); mevt->evt = evt; @@ -442,17 +406,21 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) if (mct_int_type == MCT_INT_SPI) { if (cpu == 0) { + mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 : + EXYNOS5_IRQ_MCT_L0; mct_tick0_event_irq.dev_id = mevt; - evt->irq = mct_irqs[MCT_L0_IRQ]; - setup_irq(evt->irq, &mct_tick0_event_irq); + evt->irq = mct_lx_irq; + setup_irq(mct_lx_irq, &mct_tick0_event_irq); } else { + mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 : + EXYNOS5_IRQ_MCT_L1; mct_tick1_event_irq.dev_id = mevt; - evt->irq = mct_irqs[MCT_L1_IRQ]; - setup_irq(evt->irq, &mct_tick1_event_irq); - irq_set_affinity(evt->irq, cpumask_of(1)); + evt->irq = mct_lx_irq; + setup_irq(mct_lx_irq, &mct_tick1_event_irq); + irq_set_affinity(mct_lx_irq, cpumask_of(1)); } } else { - enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); + enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); } return 0; @@ -468,7 +436,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt) else remove_irq(evt->irq, &mct_tick1_event_irq); else - disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); + disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER); } static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { @@ -477,82 +445,41 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { }; #endif /* CONFIG_LOCAL_TIMERS */ -static void __init exynos4_timer_resources(struct device_node *np) +static void __init exynos4_timer_resources(void) { - struct clk *mct_clk, *tick_clk; - - tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : - clk_get(NULL, "fin_pll"); - if (IS_ERR(tick_clk)) - panic("%s: unable to determine tick clock rate\n", __func__); - clk_rate = clk_get_rate(tick_clk); - - mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); - if (IS_ERR(mct_clk)) - panic("%s: unable to retrieve mct clock instance\n", __func__); - clk_prepare_enable(mct_clk); + struct clk *mct_clk; + mct_clk = clk_get(NULL, "xtal"); - reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER; - if (!reg_base) - panic("%s: unable to ioremap mct address space\n", __func__); + clk_rate = clk_get_rate(mct_clk); #ifdef CONFIG_LOCAL_TIMERS if (mct_int_type == MCT_INT_PPI) { int err; - err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], + err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, exynos4_mct_tick_isr, "MCT", &percpu_mct_tick); WARN(err, "MCT: can't request IRQ %d (%d)\n", - mct_irqs[MCT_L0_IRQ], err); + EXYNOS_IRQ_MCT_LOCALTIMER, err); } local_timer_register(&exynos4_mct_tick_ops); #endif /* CONFIG_LOCAL_TIMERS */ } -static const struct of_device_id exynos_mct_ids[] = { - { .compatible = "samsung,exynos4210-mct", .data = (void *)MCT_INT_SPI }, - { .compatible = "samsung,exynos4412-mct", .data = (void *)MCT_INT_PPI }, -}; - -void __init mct_init(void) +void __init exynos4_timer_init(void) { - struct device_node *np = NULL; - const struct of_device_id *match; - u32 nr_irqs, i; - -#ifdef CONFIG_OF - np = of_find_matching_node_and_match(NULL, exynos_mct_ids, &match); -#endif - if (np) { - mct_int_type = (u32)(match->data); - - /* This driver uses only one global timer interrupt */ - mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); - - /* - * Find out the number of local irqs specified. The local - * timer irqs are specified after the four global timer - * irqs are specified. - */ -#ifdef CONFIG_OF - nr_irqs = of_irq_count(np); -#endif - for (i = MCT_L0_IRQ; i < nr_irqs; i++) - mct_irqs[i] = irq_of_parse_and_map(np, i); - } else if (soc_is_exynos4210()) { - mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; - mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; - mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; - mct_int_type = MCT_INT_SPI; - } else { - panic("unable to determine mct controller type\n"); + if (soc_is_exynos5440()) { + arch_timer_of_register(); + return; } - exynos4_timer_resources(np); + if ((soc_is_exynos4210()) || (soc_is_exynos5250())) + mct_int_type = MCT_INT_SPI; + else + mct_int_type = MCT_INT_PPI; + + exynos4_timer_resources(); exynos4_clocksource_init(); exynos4_clockevent_init(); } -CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init) -CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init) diff --git a/trunk/arch/arm/mach-footbridge/Kconfig b/trunk/arch/arm/mach-footbridge/Kconfig index 0f2111a11315..abda5a18a664 100644 --- a/trunk/arch/arm/mach-footbridge/Kconfig +++ b/trunk/arch/arm/mach-footbridge/Kconfig @@ -67,7 +67,6 @@ config ARCH_NETWINDER select ISA select ISA_DMA select PCI - select VIRT_TO_BUS help Say Y here if you intend to run this kernel on the Rebel.COM NetWinder. Information about this machine can be found at: diff --git a/trunk/arch/arm/mach-highbank/highbank.c b/trunk/arch/arm/mach-highbank/highbank.c index 76c1170b3528..a4f9f50247d4 100644 --- a/trunk/arch/arm/mach-highbank/highbank.c +++ b/trunk/arch/arm/mach-highbank/highbank.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -118,10 +119,10 @@ static void __init highbank_timer_init(void) sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); sp804_clockevents_init(timer_base, irq, "timer0"); + twd_local_timer_of_register(); + arch_timer_of_register(); arch_timer_sched_clock_init(); - - clocksource_of_init(); } static void highbank_power_off(void) diff --git a/trunk/arch/arm/mach-imx/clk-busy.c b/trunk/arch/arm/mach-imx/clk-busy.c index 85b728cc27ab..1ab91b5209e6 100644 --- a/trunk/arch/arm/mach-imx/clk-busy.c +++ b/trunk/arch/arm/mach-imx/clk-busy.c @@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, busy->mux.reg = reg; busy->mux.shift = shift; - busy->mux.mask = BIT(width) - 1; + busy->mux.width = width; busy->mux.lock = &imx_ccm_lock; busy->mux_ops = &clk_mux_ops; diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index e13a8fa5e62c..74e3a34d78b8 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -264,7 +264,6 @@ int __init mx35_clocks_init(void) clk_prepare_enable(clk[gpio3_gate]); clk_prepare_enable(clk[iim_gate]); clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); /* * SCC is needed to boot via mmc after a watchdog reset. The clock code diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 2f9ff93a4e61..7b025ee528a5 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -172,7 +172,7 @@ static struct clk *clk[clk_max]; static struct clk_onecell_data clk_data; static enum mx6q_clks const clks_init_on[] __initconst = { - mmdc_ch0_axi, rom, pll1_sys, + mmdc_ch0_axi, rom, }; static struct clk_div_table clk_enet_ref_table[] = { diff --git a/trunk/arch/arm/mach-imx/headsmp.S b/trunk/arch/arm/mach-imx/headsmp.S index a58c8b0527cc..921fc1555854 100644 --- a/trunk/arch/arm/mach-imx/headsmp.S +++ b/trunk/arch/arm/mach-imx/headsmp.S @@ -26,16 +26,16 @@ ENDPROC(v7_secondary_startup) #ifdef CONFIG_PM /* - * The following code must assume it is running from physical address - * where absolute virtual addresses to the data section have to be - * turned into relative ones. + * The following code is located into the .data section. This is to + * allow phys_l2x0_saved_regs to be accessed with a relative load + * as we are running on physical address here. */ + .data + .align #ifdef CONFIG_CACHE_L2X0 .macro pl310_resume - adr r0, l2x0_saved_regs_offset - ldr r2, [r0] - add r2, r2, r0 + ldr r2, phys_l2x0_saved_regs ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl @@ -43,9 +43,9 @@ ENDPROC(v7_secondary_startup) str r1, [r0, #L2X0_CTRL] @ re-enable L2 .endm -l2x0_saved_regs_offset: - .word l2x0_saved_regs - . - + .globl phys_l2x0_saved_regs +phys_l2x0_saved_regs: + .long 0 #else .macro pl310_resume .endm diff --git a/trunk/arch/arm/mach-imx/imx25-dt.c b/trunk/arch/arm/mach-imx/imx25-dt.c index 82348391582a..03b65e5ea541 100644 --- a/trunk/arch/arm/mach-imx/imx25-dt.c +++ b/trunk/arch/arm/mach-imx/imx25-dt.c @@ -27,11 +27,6 @@ static const char * const imx25_dt_board_compat[] __initconst = { NULL }; -static void __init imx25_timer_init(void) -{ - mx25_clocks_init_dt(); -} - DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") .map_io = mx25_map_io, .init_early = imx25_init_early, diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index b59ddcb57c78..9ffd103b27e4 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -12,7 +12,6 @@ #include #include -#include #include #include #include @@ -29,9 +28,11 @@ #include #include #include +#include #include #include #include +#include #include #include "common.h" @@ -291,7 +292,7 @@ static void __init imx6q_init_irq(void) static void __init imx6q_timer_init(void) { mx6q_clocks_init(); - clocksource_of_init(); + twd_local_timer_of_register(); imx_print_silicon_rev("i.MX6Q", imx6q_revision()); } diff --git a/trunk/arch/arm/mach-imx/pm-imx6q.c b/trunk/arch/arm/mach-imx/pm-imx6q.c index 5faba7a3c95f..ee42d20cba19 100644 --- a/trunk/arch/arm/mach-imx/pm-imx6q.c +++ b/trunk/arch/arm/mach-imx/pm-imx6q.c @@ -22,6 +22,8 @@ #include "common.h" #include "hardware.h" +extern unsigned long phys_l2x0_saved_regs; + static int imx6q_suspend_finish(unsigned long val) { cpu_do_idle(); @@ -55,5 +57,18 @@ static const struct platform_suspend_ops imx6q_pm_ops = { void __init imx6q_pm_init(void) { + /* + * The l2x0 core code provides an infrastucture to save and restore + * l2x0 registers across suspend/resume cycle. But because imx6q + * retains L2 content during suspend and needs to resume L2 before + * MMU is enabled, it can only utilize register saving support and + * have to take care of restoring on its own. So we save physical + * address of the data structure used by l2x0 core to save registers, + * and later restore the necessary ones in imx6q resume entry. + */ +#ifdef CONFIG_CACHE_L2X0 + phys_l2x0_saved_regs = __pa(&l2x0_saved_regs); +#endif + suspend_set_ops(&imx6q_pm_ops); } diff --git a/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c b/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c index d599e354ca57..d42730a1d4ab 100644 --- a/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c +++ b/trunk/arch/arm/mach-ixp4xx/vulcan-setup.c @@ -163,7 +163,6 @@ static struct platform_device vulcan_max6369 = { static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = { .pin = 14, - .ext_pullup_enable_pin = -EINVAL, }; static struct platform_device vulcan_w1_gpio = { diff --git a/trunk/arch/arm/mach-kirkwood/board-guruplug.c b/trunk/arch/arm/mach-kirkwood/board-guruplug.c index 0a0df4554d8b..a857163954a5 100644 --- a/trunk/arch/arm/mach-kirkwood/board-guruplug.c +++ b/trunk/arch/arm/mach-kirkwood/board-guruplug.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "common.h" static struct mv643xx_eth_platform_data guruplug_ge00_data = { @@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(1), }; -static struct mvsdio_platform_data guruplug_mvsdio_data = { - /* unfortunately the CD signal has not been connected */ -}; - void __init guruplug_dt_init(void) { /* @@ -35,5 +30,4 @@ void __init guruplug_dt_init(void) */ kirkwood_ge00_init(&guruplug_ge00_data); kirkwood_ge01_init(&guruplug_ge01_data); - kirkwood_sdio_init(&guruplug_mvsdio_data); } diff --git a/trunk/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/trunk/arch/arm/mach-kirkwood/board-iomega_ix2_200.c index f655b2637b0e..e5f70415905a 100644 --- a/trunk/arch/arm/mach-kirkwood/board-iomega_ix2_200.c +++ b/trunk/arch/arm/mach-kirkwood/board-iomega_ix2_200.c @@ -20,10 +20,15 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = { .duplex = DUPLEX_FULL, }; +static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(11), +}; + void __init iomega_ix2_200_init(void) { /* * Basic setup. Needs to be called early. */ - kirkwood_ge01_init(&iomega_ix2_200_ge00_data); + kirkwood_ge00_init(&iomega_ix2_200_ge00_data); + kirkwood_ge01_init(&iomega_ix2_200_ge01_data); } diff --git a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { static struct mvsdio_platform_data guruplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ + .gpio_card_detect = -1, + .gpio_write_protect = -1, }; static struct gpio_led guruplug_led_pins[] = { diff --git a/trunk/arch/arm/mach-kirkwood/openrd-setup.c b/trunk/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/trunk/arch/arm/mach-kirkwood/openrd-setup.c +++ b/trunk/arch/arm/mach-kirkwood/openrd-setup.c @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { static struct mvsdio_platform_data openrd_mvsdio_data = { .gpio_card_detect = 29, /* MPP29 used as SD card detect */ + .gpio_write_protect = -1, }; static unsigned int openrd_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { static struct mvsdio_platform_data rd88f6281_mvsdio_data = { .gpio_card_detect = 28, + .gpio_write_protect = -1, }; static unsigned int rd88f6281_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-mmp/gplugd.c b/trunk/arch/arm/mach-mmp/gplugd.c index f62b68d926f4..d1e2d595e79c 100644 --- a/trunk/arch/arm/mach-mmp/gplugd.c +++ b/trunk/arch/arm/mach-mmp/gplugd.c @@ -9,7 +9,6 @@ */ #include -#include #include #include diff --git a/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c b/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c index 274ff58271de..d5970f5a1e8d 100644 --- a/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/trunk/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -44,6 +44,8 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5) + #define ACTIVE_DOORBELLS (8) static DEFINE_RAW_SPINLOCK(irq_controller_lock); @@ -59,36 +61,26 @@ static struct irq_domain *armada_370_xp_mpic_domain; */ static void armada_370_xp_irq_mask(struct irq_data *d) { -#ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); else writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); -#endif } static void armada_370_xp_irq_unmask(struct irq_data *d) { -#ifdef CONFIG_SMP irq_hw_number_t hwirq = irqd_to_hwirq(d); - if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); else writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#else - writel(irqd_to_hwirq(d), - per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); -#endif } #ifdef CONFIG_SMP @@ -144,10 +136,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { armada_370_xp_irq_mask(irq_get_irq_data(virq)); - writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) + writel(hw, per_cpu_int_base + + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + else + writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); irq_set_status_flags(virq, IRQ_LEVEL); - if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { + if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_percpu_devid_irq); diff --git a/trunk/arch/arm/mach-mxs/Makefile b/trunk/arch/arm/mach-mxs/Makefile index 80db7269760e..3d3c8a973062 100644 --- a/trunk/arch/arm/mach-mxs/Makefile +++ b/trunk/arch/arm/mach-mxs/Makefile @@ -1,2 +1,6 @@ +# Common support +obj-y := icoll.o ocotp.o system.o timer.o mm.o + obj-$(CONFIG_PM) += pm.o + obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o diff --git a/trunk/drivers/irqchip/irq-mxs.c b/trunk/arch/arm/mach-mxs/icoll.c similarity index 88% rename from trunk/drivers/irqchip/irq-mxs.c rename to trunk/arch/arm/mach-mxs/icoll.c index 29889bbdcc6d..8fb23af154b3 100644 --- a/trunk/drivers/irqchip/irq-mxs.c +++ b/trunk/arch/arm/mach-mxs/icoll.c @@ -22,12 +22,10 @@ #include #include #include -#include #include -#include #include - -#include "irqchip.h" +#include +#include #define HW_ICOLL_VECTOR 0x0000 #define HW_ICOLL_LEVELACK 0x0010 @@ -40,7 +38,7 @@ #define ICOLL_NUM_IRQS 128 -static void __iomem *icoll_base; +static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); static struct irq_domain *icoll_domain; static void icoll_ack_irq(struct irq_data *d) @@ -102,20 +100,26 @@ static struct irq_domain_ops icoll_irq_domain_ops = { .xlate = irq_domain_xlate_onecell, }; -static void __init icoll_of_init(struct device_node *np, +void __init icoll_of_init(struct device_node *np, struct device_node *interrupt_parent) { - icoll_base = of_iomap(np, 0); - WARN_ON(!icoll_base); - /* * Interrupt Collector reset, which initializes the priority * for each irq to level 0. */ - stmp_reset_block(icoll_base + HW_ICOLL_CTRL); + mxs_reset_block(icoll_base + HW_ICOLL_CTRL); icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, &icoll_irq_domain_ops, NULL); WARN_ON(!icoll_domain); } -IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); + +static const struct of_device_id icoll_of_match[] __initconst = { + {.compatible = "fsl,icoll", .data = icoll_of_init}, + { /* sentinel */ } +}; + +void __init icoll_init_irq(void) +{ + of_irq_init(icoll_of_match); +} diff --git a/trunk/arch/arm/mach-mxs/include/mach/common.h b/trunk/arch/arm/mach-mxs/include/mach/common.h new file mode 100644 index 000000000000..be5a9c93cb2a --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/common.h @@ -0,0 +1,29 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_MXS_COMMON_H__ +#define __MACH_MXS_COMMON_H__ + +extern const u32 *mxs_get_ocotp(void); +extern int mxs_reset_block(void __iomem *); +extern void mxs_timer_init(void); +extern void mxs_restart(char, const char *); +extern int mxs_saif_clkmux_select(unsigned int clkmux); + +extern int mx23_clocks_init(void); +extern void mx23_map_io(void); + +extern int mx28_clocks_init(void); +extern void mx28_map_io(void); + +extern void icoll_init_irq(void); +extern void icoll_handle_irq(struct pt_regs *); + +#endif /* __MACH_MXS_COMMON_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/debug-macro.S b/trunk/arch/arm/mach-mxs/include/mach/debug-macro.S index d86951551ca1..90c6b7836ad3 100644 --- a/trunk/arch/arm/mach-mxs/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-mxs/include/mach/debug-macro.S @@ -11,13 +11,16 @@ * */ +#include +#include + #ifdef CONFIG_DEBUG_IMX23_UART -#define UART_PADDR 0x80070000 +#define UART_PADDR MX23_DUART_BASE_ADDR #elif defined (CONFIG_DEBUG_IMX28_UART) -#define UART_PADDR 0x80074000 +#define UART_PADDR MX28_DUART_BASE_ADDR #endif -#define UART_VADDR 0xfe100000 +#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) .macro addruart, rp, rv, tmp ldr \rp, =UART_PADDR @ physical diff --git a/trunk/arch/arm/mach-mxs/include/mach/digctl.h b/trunk/arch/arm/mach-mxs/include/mach/digctl.h new file mode 100644 index 000000000000..17964066303f --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/digctl.h @@ -0,0 +1,22 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_DIGCTL_H__ +#define __MACH_DIGCTL_H__ + +/* MXS DIGCTL SAIF CLKMUX */ +#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 +#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 +#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 + +#define HW_DIGCTL_CTRL 0x0 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX 10 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX (0x3 << 10) +#define HW_DIGCTL_CHIPID 0x310 +#endif diff --git a/trunk/arch/arm/mach-mxs/include/mach/hardware.h b/trunk/arch/arm/mach-mxs/include/mach/hardware.h new file mode 100644 index 000000000000..4c0e8a64d8c7 --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/hardware.h @@ -0,0 +1,23 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_HARDWARE_H__ +#define __MACH_MXS_HARDWARE_H__ + +#endif /* __MACH_MXS_HARDWARE_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/mx23.h b/trunk/arch/arm/mach-mxs/include/mach/mx23.h new file mode 100644 index 000000000000..599094bc99de --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/mx23.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX23_H__ +#define __MACH_MX23_H__ + +#include + +/* + * OCRAM + */ +#define MX23_OCRAM_BASE_ADDR 0x00000000 +#define MX23_OCRAM_SIZE SZ_32K + +/* + * IO + */ +#define MX23_IO_BASE_ADDR 0x80000000 +#define MX23_IO_SIZE SZ_1M + +#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000) +#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000) +#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) +#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000) +#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000) +#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) +#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) +#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000) +#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000) +#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) +#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) +#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) +#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000) +#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000) +#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000) +#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) +#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000) +#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) +#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) +#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) +#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000) +#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) +#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) +#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) +#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) +#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) +#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) +#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) +#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) +#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) +#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000) +#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) +#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000) +#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000) + +#define MX23_IO_P2V(x) MXS_IO_P2V(x) +#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) + +/* + * IRQ + */ +#define MX23_INT_DUART 0 +#define MX23_INT_COMMS_RX 1 +#define MX23_INT_COMMS_TX 1 +#define MX23_INT_SSP2_ERROR 2 +#define MX23_INT_VDD5V 3 +#define MX23_INT_HEADPHONE_SHORT 4 +#define MX23_INT_DAC_DMA 5 +#define MX23_INT_DAC_ERROR 6 +#define MX23_INT_ADC_DMA 7 +#define MX23_INT_ADC_ERROR 8 +#define MX23_INT_SPDIF_DMA 9 +#define MX23_INT_SAIF2_DMA 9 +#define MX23_INT_SPDIF_ERROR 10 +#define MX23_INT_SAIF1_IRQ 10 +#define MX23_INT_SAIF2_IRQ 10 +#define MX23_INT_USB_CTRL 11 +#define MX23_INT_USB_WAKEUP 12 +#define MX23_INT_GPMI_DMA 13 +#define MX23_INT_SSP1_DMA 14 +#define MX23_INT_SSP1_ERROR 15 +#define MX23_INT_GPIO0 16 +#define MX23_INT_GPIO1 17 +#define MX23_INT_GPIO2 18 +#define MX23_INT_SAIF1_DMA 19 +#define MX23_INT_SSP2_DMA 20 +#define MX23_INT_ECC8_IRQ 21 +#define MX23_INT_RTC_ALARM 22 +#define MX23_INT_AUART1_TX_DMA 23 +#define MX23_INT_AUART1 24 +#define MX23_INT_AUART1_RX_DMA 25 +#define MX23_INT_I2C_DMA 26 +#define MX23_INT_I2C_ERROR 27 +#define MX23_INT_TIMER0 28 +#define MX23_INT_TIMER1 29 +#define MX23_INT_TIMER2 30 +#define MX23_INT_TIMER3 31 +#define MX23_INT_BATT_BRNOUT 32 +#define MX23_INT_VDDD_BRNOUT 33 +#define MX23_INT_VDDIO_BRNOUT 34 +#define MX23_INT_VDD18_BRNOUT 35 +#define MX23_INT_TOUCH_DETECT 36 +#define MX23_INT_LRADC_CH0 37 +#define MX23_INT_LRADC_CH1 38 +#define MX23_INT_LRADC_CH2 39 +#define MX23_INT_LRADC_CH3 40 +#define MX23_INT_LRADC_CH4 41 +#define MX23_INT_LRADC_CH5 42 +#define MX23_INT_LRADC_CH6 43 +#define MX23_INT_LRADC_CH7 44 +#define MX23_INT_LCDIF_DMA 45 +#define MX23_INT_LCDIF_ERROR 46 +#define MX23_INT_DIGCTL_DEBUG_TRAP 47 +#define MX23_INT_RTC_1MSEC 48 +#define MX23_INT_DRI_DMA 49 +#define MX23_INT_DRI_ATTENTION 50 +#define MX23_INT_GPMI_ATTENTION 51 +#define MX23_INT_IR 52 +#define MX23_INT_DCP_VMI 53 +#define MX23_INT_DCP 54 +#define MX23_INT_BCH 56 +#define MX23_INT_PXP 57 +#define MX23_INT_AUART2_TX_DMA 58 +#define MX23_INT_AUART2 59 +#define MX23_INT_AUART2_RX_DMA 60 +#define MX23_INT_VDAC_DETECT 61 +#define MX23_INT_VDD5V_DROOP 64 +#define MX23_INT_DCDC4P2_BO 65 + +/* + * APBH DMA + */ +#define MX23_DMA_SSP1 1 +#define MX23_DMA_SSP2 2 +#define MX23_DMA_GPMI0 4 +#define MX23_DMA_GPMI1 5 +#define MX23_DMA_GPMI2 6 +#define MX23_DMA_GPMI3 7 + +/* + * APBX DMA + */ +#define MX23_DMA_ADC 0 +#define MX23_DMA_DAC 1 +#define MX23_DMA_SPDIF 2 +#define MX23_DMA_I2C 3 +#define MX23_DMA_SAIF0 4 +#define MX23_DMA_UART0_RX 6 +#define MX23_DMA_UART0_TX 7 +#define MX23_DMA_UART1_RX 8 +#define MX23_DMA_UART1_TX 9 +#define MX23_DMA_SAIF1 10 + +#endif /* __MACH_MX23_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/mx28.h b/trunk/arch/arm/mach-mxs/include/mach/mx28.h new file mode 100644 index 000000000000..30c7990f3c01 --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/mx28.h @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MX28_H__ +#define __MACH_MX28_H__ + +#include + +/* + * OCRAM + */ +#define MX28_OCRAM_BASE_ADDR 0x00000000 +#define MX28_OCRAM_SIZE SZ_128K + +/* + * IO + */ +#define MX28_IO_BASE_ADDR 0x80000000 +#define MX28_IO_SIZE SZ_1M + +#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000) +#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000) +#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000) +#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000) +#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000) +#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000) +#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000) +#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000) +#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000) +#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000) +#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000) +#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000) +#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000) +#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000) +#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000) +#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000) +#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000) +#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000) +#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000) +#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000) +#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000) +#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000) +#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200) +#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300) +#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400) +#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500) +#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700) +#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800) +#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000) +#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000) +#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000) +#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000) +#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000) +#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000) +#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000) +#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000) +#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000) +#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000) +#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000) +#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000) +#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000) +#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000) +#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000) +#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000) +#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000) +#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000) +#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000) +#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000) +#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000) +#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000) +#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000) +#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000) +#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000) + +#define MX28_IO_P2V(x) MXS_IO_P2V(x) +#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x)) + +/* + * IRQ + */ +#define MX28_INT_BATT_BRNOUT 0 +#define MX28_INT_VDDD_BRNOUT 1 +#define MX28_INT_VDDIO_BRNOUT 2 +#define MX28_INT_VDDA_BRNOUT 3 +#define MX28_INT_VDD5V_DROOP 4 +#define MX28_INT_DCDC4P2_BRNOUT 5 +#define MX28_INT_VDD5V 6 +#define MX28_INT_CAN0 8 +#define MX28_INT_CAN1 9 +#define MX28_INT_LRADC_TOUCH 10 +#define MX28_INT_HSADC 13 +#define MX28_INT_LRADC_THRESH0 14 +#define MX28_INT_LRADC_THRESH1 15 +#define MX28_INT_LRADC_CH0 16 +#define MX28_INT_LRADC_CH1 17 +#define MX28_INT_LRADC_CH2 18 +#define MX28_INT_LRADC_CH3 19 +#define MX28_INT_LRADC_CH4 20 +#define MX28_INT_LRADC_CH5 21 +#define MX28_INT_LRADC_CH6 22 +#define MX28_INT_LRADC_CH7 23 +#define MX28_INT_LRADC_BUTTON0 24 +#define MX28_INT_LRADC_BUTTON1 25 +#define MX28_INT_PERFMON 27 +#define MX28_INT_RTC_1MSEC 28 +#define MX28_INT_RTC_ALARM 29 +#define MX28_INT_COMMS 31 +#define MX28_INT_EMI_ERR 32 +#define MX28_INT_LCDIF 38 +#define MX28_INT_PXP 39 +#define MX28_INT_BCH 41 +#define MX28_INT_GPMI 42 +#define MX28_INT_SPDIF_ERROR 45 +#define MX28_INT_DUART 47 +#define MX28_INT_TIMER0 48 +#define MX28_INT_TIMER1 49 +#define MX28_INT_TIMER2 50 +#define MX28_INT_TIMER3 51 +#define MX28_INT_DCP_VMI 52 +#define MX28_INT_DCP 53 +#define MX28_INT_DCP_SECURE 54 +#define MX28_INT_SAIF1 58 +#define MX28_INT_SAIF0 59 +#define MX28_INT_SPDIF_DMA 66 +#define MX28_INT_I2C0_DMA 68 +#define MX28_INT_I2C1_DMA 69 +#define MX28_INT_AUART0_RX_DMA 70 +#define MX28_INT_AUART0_TX_DMA 71 +#define MX28_INT_AUART1_RX_DMA 72 +#define MX28_INT_AUART1_TX_DMA 73 +#define MX28_INT_AUART2_RX_DMA 74 +#define MX28_INT_AUART2_TX_DMA 75 +#define MX28_INT_AUART3_RX_DMA 76 +#define MX28_INT_AUART3_TX_DMA 77 +#define MX28_INT_AUART4_RX_DMA 78 +#define MX28_INT_AUART4_TX_DMA 79 +#define MX28_INT_SAIF0_DMA 80 +#define MX28_INT_SAIF1_DMA 81 +#define MX28_INT_SSP0_DMA 82 +#define MX28_INT_SSP1_DMA 83 +#define MX28_INT_SSP2_DMA 84 +#define MX28_INT_SSP3_DMA 85 +#define MX28_INT_LCDIF_DMA 86 +#define MX28_INT_HSADC_DMA 87 +#define MX28_INT_GPMI_DMA 88 +#define MX28_INT_DIGCTL_DEBUG_TRAP 89 +#define MX28_INT_USB1 92 +#define MX28_INT_USB0 93 +#define MX28_INT_USB1_WAKEUP 94 +#define MX28_INT_USB0_WAKEUP 95 +#define MX28_INT_SSP0_ERROR 96 +#define MX28_INT_SSP1_ERROR 97 +#define MX28_INT_SSP2_ERROR 98 +#define MX28_INT_SSP3_ERROR 99 +#define MX28_INT_ENET_SWI 100 +#define MX28_INT_ENET_MAC0 101 +#define MX28_INT_ENET_MAC1 102 +#define MX28_INT_ENET_MAC0_1588 103 +#define MX28_INT_ENET_MAC1_1588 104 +#define MX28_INT_I2C1_ERROR 110 +#define MX28_INT_I2C0_ERROR 111 +#define MX28_INT_AUART0 112 +#define MX28_INT_AUART1 113 +#define MX28_INT_AUART2 114 +#define MX28_INT_AUART3 115 +#define MX28_INT_AUART4 116 +#define MX28_INT_GPIO4 123 +#define MX28_INT_GPIO3 124 +#define MX28_INT_GPIO2 125 +#define MX28_INT_GPIO1 126 +#define MX28_INT_GPIO0 127 + +/* + * APBH DMA + */ +#define MX28_DMA_SSP0 0 +#define MX28_DMA_SSP1 1 +#define MX28_DMA_SSP2 2 +#define MX28_DMA_SSP3 3 +#define MX28_DMA_GPMI0 4 +#define MX28_DMA_GPMI1 5 +#define MX28_DMA_GPMI2 6 +#define MX28_DMA_GPMI3 7 +#define MX28_DMA_GPMI4 8 +#define MX28_DMA_GPMI5 9 +#define MX28_DMA_GPMI6 10 +#define MX28_DMA_GPMI7 11 +#define MX28_DMA_HSADC 12 +#define MX28_DMA_LCDIF 13 + +/* + * APBX DMA + */ +#define MX28_DMA_AUART4_RX 0 +#define MX28_DMA_AUART4_TX 1 +#define MX28_DMA_SPDIF_TX 2 +#define MX28_DMA_SAIF0 4 +#define MX28_DMA_SAIF1 5 +#define MX28_DMA_I2C0 6 +#define MX28_DMA_I2C1 7 +#define MX28_DMA_AUART0_RX 8 +#define MX28_DMA_AUART0_TX 9 +#define MX28_DMA_AUART1_RX 10 +#define MX28_DMA_AUART1_TX 11 +#define MX28_DMA_AUART2_RX 12 +#define MX28_DMA_AUART2_TX 13 +#define MX28_DMA_AUART3_RX 14 +#define MX28_DMA_AUART3_TX 15 + +#endif /* __MACH_MX28_H__ */ diff --git a/trunk/arch/arm/mach-mxs/include/mach/mxs.h b/trunk/arch/arm/mach-mxs/include/mach/mxs.h new file mode 100644 index 000000000000..7d4fb6d0afda --- /dev/null +++ b/trunk/arch/arm/mach-mxs/include/mach/mxs.h @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_MXS_H__ +#define __MACH_MXS_H__ + +#ifndef __ASSEMBLER__ +#include +#endif +#include +#include +#include + +/* + * IO addresses common to MXS-based + */ +#define MXS_IO_BASE_ADDR 0x80000000 +#define MXS_IO_SIZE SZ_1M + +#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) +#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) +#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) +#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) +#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) +#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) +#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) +#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) +#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) +#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) +#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) +#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) +#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) +#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) +#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) +#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) +#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) +#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) +#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) +#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) +#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) +#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) +#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) +#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) + +/* + * It maps the whole address space to [0xf4000000, 0xf50fffff]. + * + * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 + * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 + */ +#define MXS_IO_P2V(x) (0xf4000000 + \ + (((x) & 0x80000000) >> 7) + \ + (((x) & 0x000fffff))) + +#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) + +#define mxs_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + +#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) + +#define MXS_SET_ADDR 0x4 +#define MXS_CLR_ADDR 0x8 +#define MXS_TOG_ADDR 0xc + +#ifndef __ASSEMBLER__ +static inline void __mxs_setl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_SET_ADDR); +} + +static inline void __mxs_clrl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_CLR_ADDR); +} + +static inline void __mxs_togl(u32 mask, void __iomem *reg) +{ + __raw_writel(mask, reg + MXS_TOG_ADDR); +} + +/* + * MXS CPU types + */ +#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID) + +static inline int cpu_is_mx23(void) +{ + return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780); +} + +static inline int cpu_is_mx28(void) +{ + return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800); +} +#endif + +#endif /* __MACH_MXS_H__ */ diff --git a/trunk/arch/arm/mach-mxs/mach-mxs.c b/trunk/arch/arm/mach-mxs/mach-mxs.c index f39ab808694d..052186713347 100644 --- a/trunk/arch/arm/mach-mxs/mach-mxs.c +++ b/trunk/arch/arm/mach-mxs/mach-mxs.c @@ -11,52 +11,132 @@ */ #include -#include #include -#include #include #include #include #include #include -#include -#include #include -#include +#include #include #include #include #include -#include #include -#include +#include +#include +#include + +static struct fb_videomode mx23evk_video_modes[] = { + { + .name = "Samsung-LMS430HF02", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 108096, /* picosecond (9.2 MHz) */ + .left_margin = 15, + .right_margin = 8, + .upper_margin = 12, + .lower_margin = 4, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; -/* MXS DIGCTL SAIF CLKMUX */ -#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0 -#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1 -#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 -#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 +static struct fb_videomode mx28evk_video_modes[] = { + { + .name = "Seiko-43WVF1G", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; -#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) +static struct fb_videomode m28evk_video_modes[] = { + { + .name = "Ampire AM-800480R2TMQW-T01H", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30066, /* picosecond (33.26 MHz) */ + .left_margin = 0, + .right_margin = 256, + .upper_margin = 0, + .lower_margin = 45, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + }, +}; -#define MXS_SET_ADDR 0x4 -#define MXS_CLR_ADDR 0x8 -#define MXS_TOG_ADDR 0xc +static struct fb_videomode apx4devkit_video_modes[] = { + { + .name = "HannStar PJ70112A", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33333, /* picosecond (30.00 MHz) */ + .left_margin = 88, + .right_margin = 40, + .upper_margin = 32, + .lower_margin = 13, + .hsync_len = 48, + .vsync_len = 3, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; -static inline void __mxs_setl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_SET_ADDR); -} +static struct fb_videomode apf28dev_video_modes[] = { + { + .name = "LW700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30303, /* picosecond */ + .left_margin = 96, + .right_margin = 96, /* at least 3 & 1 */ + .upper_margin = 0x14, + .lower_margin = 0x15, + .hsync_len = 64, + .vsync_len = 4, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; -static inline void __mxs_clrl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_CLR_ADDR); -} +static struct fb_videomode cfa10049_video_modes[] = { + { + .name = "Himax HX8357-B", + .refresh = 60, + .xres = 320, + .yres = 480, + .pixclock = 108506, /* picosecond (9.216 MHz) */ + .left_margin = 2, + .right_margin = 2, + .upper_margin = 2, + .lower_margin = 2, + .hsync_len = 15, + .vsync_len = 15, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT + }, +}; -static inline void __mxs_togl(u32 mask, void __iomem *reg) -{ - __raw_writel(mask, reg + MXS_TOG_ADDR); -} +static struct mxsfb_platform_data mxsfb_pdata __initdata; /* * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers @@ -88,85 +168,21 @@ static void mx28evk_flexcan1_switch(int enable) static struct flexcan_platform_data flexcan_pdata[2]; static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), { /* sentinel */ } }; -#define OCOTP_WORD_OFFSET 0x20 -#define OCOTP_WORD_COUNT 0x20 - -#define BM_OCOTP_CTRL_BUSY (1 << 8) -#define BM_OCOTP_CTRL_ERROR (1 << 9) -#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) - -static DEFINE_MUTEX(ocotp_mutex); -static u32 ocotp_words[OCOTP_WORD_COUNT]; - -static const u32 *mxs_get_ocotp(void) +static void __init imx23_timer_init(void) { - struct device_node *np; - void __iomem *ocotp_base; - int timeout = 0x400; - size_t i; - static int once; - - if (once) - return ocotp_words; - - np = of_find_compatible_node(NULL, NULL, "fsl,ocotp"); - ocotp_base = of_iomap(np, 0); - WARN_ON(!ocotp_base); - - mutex_lock(&ocotp_mutex); - - /* - * clk_enable(hbus_clk) for ocotp can be skipped - * as it must be on when system is running. - */ - - /* try to clear ERROR bit */ - __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); - - /* check both BUSY and ERROR cleared */ - while ((__raw_readl(ocotp_base) & - (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) - goto error_unlock; - - /* open OCOTP banks for read */ - __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); - - /* approximately wait 32 hclk cycles */ - udelay(1); - - /* poll BUSY bit becoming cleared */ - timeout = 0x400; - while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) - goto error_unlock; - - for (i = 0; i < OCOTP_WORD_COUNT; i++) - ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + - i * 0x10); - - /* close banks for power saving */ - __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); - - once = 1; - - mutex_unlock(&ocotp_mutex); - - return ocotp_words; + mx23_clocks_init(); +} -error_unlock: - mutex_unlock(&ocotp_mutex); - pr_err("%s: timeout in reading OCOTP\n", __func__); - return NULL; +static void __init imx28_timer_init(void) +{ + mx28_clocks_init(); } enum mac_oui { @@ -237,6 +253,14 @@ static void __init update_fec_mac_prop(enum mac_oui oui) } } +static void __init imx23_evk_init(void) +{ + mxsfb_pdata.mode_list = mx23evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; +} + static inline void enable_clk_enet_out(void) { struct clk *clk = clk_get_sys("enet_out", NULL); @@ -247,8 +271,14 @@ static inline void enable_clk_enet_out(void) static void __init imx28_evk_init(void) { + enable_clk_enet_out(); update_fec_mac_prop(OUI_FSL); + mxsfb_pdata.mode_list = mx28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; + mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); } @@ -261,6 +291,19 @@ static void __init imx28_evk_post_init(void) } } +static void __init m28evk_init(void) +{ + mxsfb_pdata.mode_list = m28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); + mxsfb_pdata.default_bpp = 16; + mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; +} + +static void __init sc_sps1_init(void) +{ + enable_clk_enet_out(); +} + static int apx4devkit_phy_fixup(struct phy_device *phy) { phy->dev_flags |= MICREL_PHY_50MHZ_CLK; @@ -274,6 +317,11 @@ static void __init apx4devkit_init(void) if (IS_BUILTIN(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, apx4devkit_phy_fixup); + + mxsfb_pdata.mode_list = apx4devkit_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; } #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) @@ -352,24 +400,49 @@ static void __init tx28_post_init(void) static void __init cfa10049_init(void) { + enable_clk_enet_out(); update_fec_mac_prop(OUI_CRYSTALFONTZ); } static void __init cfa10037_init(void) { + enable_clk_enet_out(); update_fec_mac_prop(OUI_CRYSTALFONTZ); + + mxsfb_pdata.mode_list = cfa10049_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; +} + +static void __init apf28_init(void) +{ + enable_clk_enet_out(); + + mxsfb_pdata.mode_list = apf28dev_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); + mxsfb_pdata.default_bpp = 16; + mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; } static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) imx28_evk_init(); + else if (of_machine_is_compatible("fsl,imx23-evk")) + imx23_evk_init(); + else if (of_machine_is_compatible("denx,m28evk")) + m28evk_init(); else if (of_machine_is_compatible("bluegiga,apx4devkit")) apx4devkit_init(); else if (of_machine_is_compatible("crystalfontz,cfa10037")) cfa10037_init(); else if (of_machine_is_compatible("crystalfontz,cfa10049")) cfa10049_init(); + else if (of_machine_is_compatible("armadeus,imx28-apf28")) + apf28_init(); + else if (of_machine_is_compatible("schulercontrol,imx28-sps1")) + sc_sps1_init(); of_platform_populate(NULL, of_default_bus_match_table, mxs_auxdata_lookup, NULL); @@ -381,62 +454,32 @@ static void __init mxs_machine_init(void) imx28_evk_post_init(); } -#define MX23_CLKCTRL_RESET_OFFSET 0x120 -#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 -#define MXS_CLKCTRL_RESET_CHIP (1 << 1) - -/* - * Reset the system. It is called by machine_restart(). - */ -static void mxs_restart(char mode, const char *cmd) -{ - struct device_node *np; - void __iomem *reset_addr; - - np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); - reset_addr = of_iomap(np, 0); - if (!reset_addr) - goto soft; - - if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) - reset_addr += MX23_CLKCTRL_RESET_OFFSET; - else - reset_addr += MX28_CLKCTRL_RESET_OFFSET; - - /* reset the chip */ - __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); - - pr_err("Failed to assert the chip reset\n"); - - /* Delay to allow the serial port to show the message */ - mdelay(50); - -soft: - /* We'll take a jump through zero as a poor second */ - soft_restart(0); -} - -static void __init mxs_timer_init(void) -{ - if (of_machine_is_compatible("fsl,imx23")) - mx23_clocks_init(); - else - mx28_clocks_init(); - clocksource_of_init(); -} +static const char *imx23_dt_compat[] __initdata = { + "fsl,imx23", + NULL, +}; -static const char *mxs_dt_compat[] __initdata = { +static const char *imx28_dt_compat[] __initdata = { "fsl,imx28", - "fsl,imx23", NULL, }; -DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") - .map_io = debug_ll_io_init, - .init_irq = irqchip_init, +DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)") + .map_io = mx23_map_io, + .init_irq = icoll_init_irq, + .handle_irq = icoll_handle_irq, + .init_time = imx23_timer_init, + .init_machine = mxs_machine_init, + .dt_compat = imx23_dt_compat, + .restart = mxs_restart, +MACHINE_END + +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)") + .map_io = mx28_map_io, + .init_irq = icoll_init_irq, .handle_irq = icoll_handle_irq, - .init_time = mxs_timer_init, + .init_time = imx28_timer_init, .init_machine = mxs_machine_init, - .dt_compat = mxs_dt_compat, + .dt_compat = imx28_dt_compat, .restart = mxs_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-mxs/mm.c b/trunk/arch/arm/mach-mxs/mm.c new file mode 100644 index 000000000000..a4294aa9f301 --- /dev/null +++ b/trunk/arch/arm/mach-mxs/mm.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Create static mapping between physical to virtual memory. + */ + +#include +#include + +#include + +#include +#include + +/* + * Define the MX23 memory map. + */ +static struct map_desc mx23_io_desc[] __initdata = { + mxs_map_entry(MX23, OCRAM, MT_DEVICE), + mxs_map_entry(MX23, IO, MT_DEVICE), +}; + +/* + * Define the MX28 memory map. + */ +static struct map_desc mx28_io_desc[] __initdata = { + mxs_map_entry(MX28, OCRAM, MT_DEVICE), + mxs_map_entry(MX28, IO, MT_DEVICE), +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx23_map_io(void) +{ + iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); +} + +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} diff --git a/trunk/arch/arm/mach-mxs/ocotp.c b/trunk/arch/arm/mach-mxs/ocotp.c new file mode 100644 index 000000000000..54add60f94c9 --- /dev/null +++ b/trunk/arch/arm/mach-mxs/ocotp.c @@ -0,0 +1,92 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include /* for cpu_relax() */ + +#include + +#define OCOTP_WORD_OFFSET 0x20 +#define OCOTP_WORD_COUNT 0x20 + +#define BM_OCOTP_CTRL_BUSY (1 << 8) +#define BM_OCOTP_CTRL_ERROR (1 << 9) +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) + +static DEFINE_MUTEX(ocotp_mutex); +static u32 ocotp_words[OCOTP_WORD_COUNT]; + +const u32 *mxs_get_ocotp(void) +{ + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR); + int timeout = 0x400; + size_t i; + static int once = 0; + + if (once) + return ocotp_words; + + mutex_lock(&ocotp_mutex); + + /* + * clk_enable(hbus_clk) for ocotp can be skipped + * as it must be on when system is running. + */ + + /* try to clear ERROR bit */ + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); + + /* check both BUSY and ERROR cleared */ + while ((__raw_readl(ocotp_base) & + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + /* open OCOTP banks for read */ + __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + /* approximately wait 32 hclk cycles */ + udelay(1); + + /* poll BUSY bit becoming cleared */ + timeout = 0x400; + while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) + cpu_relax(); + + if (unlikely(!timeout)) + goto error_unlock; + + for (i = 0; i < OCOTP_WORD_COUNT; i++) + ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + + i * 0x10); + + /* close banks for power saving */ + __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); + + once = 1; + + mutex_unlock(&ocotp_mutex); + + return ocotp_words; + +error_unlock: + mutex_unlock(&ocotp_mutex); + pr_err("%s: timeout in reading OCOTP\n", __func__); + return NULL; +} diff --git a/trunk/arch/arm/mach-mxs/system.c b/trunk/arch/arm/mach-mxs/system.c new file mode 100644 index 000000000000..30042e23bfa7 --- /dev/null +++ b/trunk/arch/arm/mach-mxs/system.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define MX23_CLKCTRL_RESET_OFFSET 0x120 +#define MX28_CLKCTRL_RESET_OFFSET 0x1e0 +#define MXS_CLKCTRL_RESET_CHIP (1 << 1) + +#define MXS_MODULE_CLKGATE (1 << 30) +#define MXS_MODULE_SFTRST (1 << 31) + +static void __iomem *mxs_clkctrl_reset_addr; + +/* + * Reset the system. It is called by machine_restart(). + */ +void mxs_restart(char mode, const char *cmd) +{ + /* reset the chip */ + __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr); + + pr_err("Failed to assert the chip reset\n"); + + /* Delay to allow the serial port to show the message */ + mdelay(50); + + /* We'll take a jump through zero as a poor second */ + soft_restart(0); +} + +static int __init mxs_arch_reset_init(void) +{ + struct clk *clk; + + mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) + + (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET : + MX28_CLKCTRL_RESET_OFFSET); + + clk = clk_get_sys("rtc", NULL); + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + + return 0; +} +core_initcall(mxs_arch_reset_init); + +/* + * Clear the bit and poll it cleared. This is usually called with + * a reset address and mask being either SFTRST(bit 31) or CLKGATE + * (bit 30). + */ +static int clear_poll_bit(void __iomem *addr, u32 mask) +{ + int timeout = 0x400; + + /* clear the bit */ + __mxs_clrl(mask, addr); + + /* + * SFTRST needs 3 GPMI clocks to settle, the reference manual + * recommends to wait 1us. + */ + udelay(1); + + /* poll the bit becoming clear */ + while ((__raw_readl(addr) & mask) && --timeout) + /* nothing */; + + return !timeout; +} + +int mxs_reset_block(void __iomem *reset_addr) +{ + int ret; + int timeout = 0x400; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (unlikely(ret)) + goto error; + + /* clear CLKGATE */ + __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr); + + /* set SFTRST to reset the block */ + __mxs_setl(MXS_MODULE_SFTRST, reset_addr); + udelay(1); + + /* poll CLKGATE becoming set */ + while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout) + /* nothing */; + if (unlikely(!timeout)) + goto error; + + /* clear and poll SFTRST */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); + if (unlikely(ret)) + goto error; + + /* clear and poll CLKGATE */ + ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE); + if (unlikely(ret)) + goto error; + + return 0; + +error: + pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); + return -ETIMEDOUT; +} +EXPORT_SYMBOL(mxs_reset_block); diff --git a/trunk/drivers/clocksource/mxs_timer.c b/trunk/arch/arm/mach-mxs/timer.c similarity index 91% rename from trunk/drivers/clocksource/mxs_timer.c rename to trunk/arch/arm/mach-mxs/timer.c index 02af4204af86..421020498a1b 100644 --- a/trunk/drivers/clocksource/mxs_timer.c +++ b/trunk/arch/arm/mach-mxs/timer.c @@ -26,12 +26,12 @@ #include #include #include -#include #include -#include #include #include +#include +#include /* * There are 2 versions of the timrot on Freescale MXS-based SoCs. @@ -79,25 +79,25 @@ static struct clock_event_device mxs_clockevent_device; static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; -static void __iomem *mxs_timrot_base; +static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR); static u32 timrot_major_version; static inline void timrot_irq_disable(void) { - __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + - HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); + __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); } static inline void timrot_irq_enable(void) { - __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + - HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); + __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); } static void timrot_irq_acknowledge(void) { - __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base + - HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR); + __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ, + mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); } static cycle_t timrotv1_get_cycles(struct clocksource *cs) @@ -242,15 +242,19 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) return 0; } -static void __init mxs_timer_init(struct device_node *np) +void __init mxs_timer_init(void) { + struct device_node *np; struct clk *timer_clk; int irq; - mxs_timrot_base = of_iomap(np, 0); - WARN_ON(!mxs_timrot_base); + np = of_find_compatible_node(NULL, NULL, "fsl,timrot"); + if (!np) { + pr_err("%s: failed find timrot node\n", __func__); + return; + } - timer_clk = of_clk_get(np, 0); + timer_clk = clk_get_sys("timrot", NULL); if (IS_ERR(timer_clk)) { pr_err("%s: failed to get clk\n", __func__); return; @@ -261,12 +265,11 @@ static void __init mxs_timer_init(struct device_node *np) /* * Initialize timers to a known state */ - stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); + mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); /* get timrot version */ timrot_major_version = __raw_readl(mxs_timrot_base + - (of_device_is_compatible(np, "fsl,imx23-timrot") ? - MX23_TIMROT_VERSION_OFFSET : + (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET : MX28_TIMROT_VERSION_OFFSET)); timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; @@ -301,4 +304,3 @@ static void __init mxs_timer_init(struct device_node *np) irq = irq_of_parse_and_map(np, 0); setup_irq(irq, &mxs_timer_irq); } -CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init); diff --git a/trunk/arch/arm/mach-omap1/Kconfig b/trunk/arch/arm/mach-omap1/Kconfig index cdd05f2e67ee..903da8eb886c 100644 --- a/trunk/arch/arm/mach-omap1/Kconfig +++ b/trunk/arch/arm/mach-omap1/Kconfig @@ -55,6 +55,12 @@ config MACH_OMAP_H3 TI OMAP 1710 H3 board support. Say Y here if you have such a board. +config MACH_OMAP_HTCWIZARD + bool "HTC Wizard" + depends on ARCH_OMAP850 + help + HTC Wizard smartphone support (AKA QTEK 9100, ...) + config MACH_HERALD bool "HTC Herald" depends on ARCH_OMAP850 diff --git a/trunk/arch/arm/mach-omap1/common.h b/trunk/arch/arm/mach-omap1/common.h index 14f7e9920479..fb18831e88aa 100644 --- a/trunk/arch/arm/mach-omap1/common.h +++ b/trunk/arch/arm/mach-omap1/common.h @@ -31,8 +31,6 @@ #include -#include - #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) void omap7xx_map_io(void); #else diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index b9c0ed3f648c..49ac3dfebef9 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -311,6 +311,9 @@ config MACH_OMAP_ZOOM2 default y select OMAP_PACKAGE_CBB select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_8250 + select SERIAL_8250_CONSOLE + select SERIAL_CORE_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" @@ -318,6 +321,9 @@ config MACH_OMAP_ZOOM3 default y select OMAP_PACKAGE_CBP select REGULATOR_FIXED_VOLTAGE if REGULATOR + select SERIAL_8250 + select SERIAL_8250_CONSOLE + select SERIAL_CORE_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35/CM-T3730 modules" @@ -408,7 +414,7 @@ config OMAP3_SDRC_AC_TIMING config OMAP4_ERRATA_I688 bool "OMAP4 errata: Async Bridge Corruption" - depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM + depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM select ARCH_HAS_BARRIERS help If a data is stalled inside asynchronous bridge because of back diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index cb0596b631cf..a3e0aaa4886b 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void) omap_display_init(&sdp2430_dss_data); } -#if IS_ENABLED(CONFIG_SMC91X) +#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 5, diff --git a/trunk/arch/arm/mach-omap2/board-3430sdp.c b/trunk/arch/arm/mach-omap2/board-3430sdp.c index 7eb9651dd0f7..ce812decfaca 100644 --- a/trunk/arch/arm/mach-omap2/board-3430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3430sdp.c @@ -445,23 +445,16 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 57, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = 61, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 57, + .reset_gpio_port[1] = 61, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -613,8 +606,6 @@ static void __init omap_3430sdp_init(void) board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); sdp3430_display_init(); enable_board_wakeup_source(); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-3630sdp.c b/trunk/arch/arm/mach-omap2/board-3630sdp.c index 20d6d8189240..67447bd4564f 100644 --- a/trunk/arch/arm/mach-omap2/board-3630sdp.c +++ b/trunk/arch/arm/mach-omap2/board-3630sdp.c @@ -53,23 +53,16 @@ static void enable_board_wakeup_source(void) OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 126, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = 61, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 126, + .reset_gpio_port[1] = 61, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -206,8 +199,6 @@ static void __init omap_sdp_init(void) board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); enable_board_wakeup_source(); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-am3517crane.c b/trunk/arch/arm/mach-omap2/board-am3517crane.c index fc53911d0d13..7d3358b2e593 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517crane.c +++ b/trunk/arch/arm/mach-omap2/board-am3517crane.c @@ -47,17 +47,15 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = GPIO_USB_NRESET, - .vcc_gpio = GPIO_USB_POWER, - .vcc_polarity = 1, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = GPIO_USB_NRESET, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; static struct mtd_partition crane_nand_partitions[] = { @@ -133,7 +131,13 @@ static void __init am3517_crane_init(void) return; } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); + ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH, + "usb_ehci_enable"); + if (ret < 0) { + pr_err("Can not request GPIO %d\n", GPIO_USB_POWER); + return; + } + usbhs_init(&usbhs_bdata); am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1); } diff --git a/trunk/arch/arm/mach-omap2/board-am3517evm.c b/trunk/arch/arm/mach-omap2/board-am3517evm.c index 191f9762ba63..9fb85908a61e 100644 --- a/trunk/arch/arm/mach-omap2/board-am3517evm.c +++ b/trunk/arch/arm/mach-omap2/board-am3517evm.c @@ -274,14 +274,6 @@ static __init void am3517_evm_mcbsp1_init(void) omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = 57, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ @@ -290,6 +282,12 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = { #else .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, #endif + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = 57, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -351,6 +349,7 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; + static void __init am3517_evm_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -362,8 +361,6 @@ static void __init am3517_evm_init(void) /* Configure GPIO for EHCI port */ omap_mux_init_gpio(57, OMAP_PIN_OUTPUT); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); am3517_evm_hecc_init(&am3517_evm_hecc_pdata); /* DSS */ diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index 7fda3f5f8a7f..af2bb219e214 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -419,22 +419,15 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = OMAP_MAX_GPIO_LINES + 6, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = OMAP_MAX_GPIO_LINES + 7, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, + .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, + .reset_gpio_port[2] = -EINVAL }; static void __init cm_t35_init_usbh(void) @@ -451,7 +444,6 @@ static void __init cm_t35_init_usbh(void) msleep(1); } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/board-cm-t3517.c b/trunk/arch/arm/mach-omap2/board-cm-t3517.c index 6920f6cfc97c..a66da808cc4a 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t3517.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t3517.c @@ -188,22 +188,15 @@ static inline void cm_t3517_init_rtc(void) {} #define HSUSB2_RESET_GPIO (147) #define USB_HUB_RESET_GPIO (152) -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = HSUSB1_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, - { - .port = 2, - .reset_gpio = HSUSB2_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = HSUSB1_RESET_GPIO, + .reset_gpio_port[1] = HSUSB2_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, }; static int __init cm_t3517_init_usbh(void) @@ -220,7 +213,6 @@ static int __init cm_t3517_init_usbh(void) msleep(1); } - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&cm_t3517_ehci_pdata); return 0; diff --git a/trunk/arch/arm/mach-omap2/board-devkit8000.c b/trunk/arch/arm/mach-omap2/board-devkit8000.c index 42fbf1ef12a9..53056c3b0836 100644 --- a/trunk/arch/arm/mach-omap2/board-devkit8000.c +++ b/trunk/arch/arm/mach-omap2/board-devkit8000.c @@ -437,7 +437,15 @@ static struct platform_device *devkit8000_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index afa509afb27c..0274ff7a2a2b 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -102,7 +102,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_late = omap3_init_late, .init_time = omap3_sync32k_timer_init, .dt_compat = omap3_boards_compat, .restart = omap3xxx_restart, @@ -110,7 +109,6 @@ MACHINE_END static const char *omap3_gp_boards_compat[] __initdata = { "ti,omap3-beagle", - "timll,omap3-devkit8000", NULL, }; @@ -121,7 +119,6 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .init_irq = omap_intc_of_init, .handle_irq = omap3_intc_handle_irq, .init_machine = omap_generic_init, - .init_late = omap3_init_late, .init_time = omap3_secure_sync32k_timer_init, .dt_compat = omap3_gp_boards_compat, .restart = omap3xxx_restart, diff --git a/trunk/arch/arm/mach-omap2/board-h4.c b/trunk/arch/arm/mach-omap2/board-h4.c index 5b4ec51c385f..812c829fa46f 100644 --- a/trunk/arch/arm/mach-omap2/board-h4.c +++ b/trunk/arch/arm/mach-omap2/board-h4.c @@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void) return 0; } -#if IS_ENABLED(CONFIG_SMC91X) +#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) static struct omap_smc91x_platform_data board_smc91x_data = { .cs = 1, diff --git a/trunk/arch/arm/mach-omap2/board-igep0020.c b/trunk/arch/arm/mach-omap2/board-igep0020.c index 95ccec0eeab9..bf92678a01d0 100644 --- a/trunk/arch/arm/mach-omap2/board-igep0020.c +++ b/trunk/arch/arm/mach-omap2/board-igep0020.c @@ -527,28 +527,26 @@ static void __init igep_i2c_init(void) omap3_pmic_init("twl4030", &igep_twldata); } -static struct usbhs_phy_data igep2_phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = IGEP2_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - -static struct usbhs_phy_data igep3_phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = IGEP3_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL, }; static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET, + .reset_gpio_port[2] = -EINVAL, }; #ifdef CONFIG_OMAP_MUX @@ -644,10 +642,8 @@ static void __init igep_init(void) if (machine_is_igep0020()) { omap_display_init(&igep2_dss_data); igep2_init_smsc911x(); - usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data)); usbhs_init(&igep2_usbhs_bdata); } else { - usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data)); usbhs_init(&igep3_usbhs_bdata); } } diff --git a/trunk/arch/arm/mach-omap2/board-omap3beagle.c b/trunk/arch/arm/mach-omap2/board-omap3beagle.c index 5382215a49bc..c3558f93d42c 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3beagle.c +++ b/trunk/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include @@ -278,21 +277,6 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = { static struct gpio_led gpio_leds[]; -/* PHY's VCC regulator might be added later, so flag that we need it */ -static struct nop_usb_xceiv_platform_data hsusb2_phy_data = { - .needs_vcc = true, -}; - -static struct usbhs_phy_data phy_data[] = { - { - .port = 2, - .reset_gpio = 147, - .vcc_gpio = -1, /* updated in beagle_twl_gpio_setup */ - .vcc_polarity = 1, /* updated in beagle_twl_gpio_setup */ - .platform_data = &hsusb2_phy_data, - }, -}; - static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -334,11 +318,9 @@ static int beagle_twl_gpio_setup(struct device *dev, } dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio; - /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */ - phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX; - phy_data[0].vcc_polarity = beagle_config.usb_pwr_level; + gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, + "nEN_USB_PWR"); - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); return 0; } @@ -471,7 +453,15 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 147, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -553,9 +543,7 @@ static void __init omap3_beagle_init(void) usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - usbhs_init(&usbhs_bdata); - board_nand_init(omap3beagle_nand_partitions, ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS, NAND_BUSWIDTH_16, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3evm.c b/trunk/arch/arm/mach-omap2/board-omap3evm.c index 2de92facc8a3..48789e0bb915 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3evm.c +++ b/trunk/arch/arm/mach-omap2/board-omap3evm.c @@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = { static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = { REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */ REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */ - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"), REGULATOR_SUPPLY("vaux2", NULL), }; @@ -539,16 +539,17 @@ static int __init omap3_evm_i2c_init(void) return 0; } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = -1, /* set at runtime */ - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + /* PHY reset GPIO will be runtime programmed based on EVM version */ + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -724,7 +725,7 @@ static void __init omap3_evm_init(void) /* setup EHCI phy reset config */ omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP); - phy_data[0].reset_gpio = 21; + usbhs_bdata.reset_gpio_port[1] = 21; /* EVM REV >= E can supply 500mA with EXTVBUS programming */ musb_board_data.power = 500; @@ -732,12 +733,10 @@ static void __init omap3_evm_init(void) } else { /* setup EHCI phy reset on MDC */ omap_mux_init_gpio(135, OMAP_PIN_OUTPUT); - phy_data[0].reset_gpio = 135; + usbhs_bdata.reset_gpio_port[1] = 135; } usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(&musb_board_data); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); board_nand_init(omap3evm_nand_partitions, ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS, diff --git a/trunk/arch/arm/mach-omap2/board-omap3pandora.c b/trunk/arch/arm/mach-omap2/board-omap3pandora.c index 1004d2aaa68f..2bba362148a0 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3pandora.c +++ b/trunk/arch/arm/mach-omap2/board-omap3pandora.c @@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { }; static struct regulator_consumer_supply pandora_usb_phy_supply[] = { - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"), }; /* ads7846 on SPI and 2 nub controllers on I2C */ @@ -561,14 +561,6 @@ static void __init pandora_wl1251_init(void) printk(KERN_ERR "wl1251 board initialisation failed\n"); } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 16, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, @@ -577,7 +569,15 @@ static struct platform_device *omap3pandora_devices[] __initdata = { }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 16, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -601,10 +601,7 @@ static void __init omap3pandora_init(void) spi_register_board_info(omap3pandora_spi_board_info, ARRAY_SIZE(omap3pandora_spi_board_info)); omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); gpmc_nand_init(&pandora_nand_data, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3stalker.c b/trunk/arch/arm/mach-omap2/board-omap3stalker.c index bf0956489899..95c10b3aa678 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3stalker.c +++ b/trunk/arch/arm/mach-omap2/board-omap3stalker.c @@ -358,20 +358,19 @@ static int __init omap3_stalker_i2c_init(void) #define OMAP3_STALKER_TS_GPIO 175 -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 21, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 21, + .reset_gpio_port[2] = -EINVAL, }; #ifdef CONFIG_OMAP_MUX @@ -408,8 +407,6 @@ static void __init omap3_stalker_init(void) omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL); diff --git a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c index 7da48bc42bbf..bcd44fbcd877 100644 --- a/trunk/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/trunk/arch/arm/mach-omap2/board-omap3touchbook.c @@ -305,22 +305,21 @@ static struct omap_board_mux board_mux[] __initdata = { }; #endif -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = 147, - .vcc_gpio = -EINVAL, - }, -}; - static struct platform_device *omap3_touchbook_devices[] __initdata = { &leds_gpio, &keys_gpio, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 147, + .reset_gpio_port[2] = -EINVAL }; static void omap3_touchbook_poweroff(void) @@ -369,8 +368,6 @@ static void __init omap3_touchbook_init(void) omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); board_nand_init(omap3touchbook_nand_partitions, ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS, diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index a71ad345f20d..b02c2f00609b 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -133,22 +132,6 @@ static struct platform_device btwilink_device = { .id = -1, }; -/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */ -static struct nop_usb_xceiv_platform_data hsusb1_phy_data = { - /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - .clk_rate = 19200000, -}; - -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 1, - .reset_gpio = GPIO_HUB_NRESET, - .vcc_gpio = GPIO_HUB_POWER, - .vcc_polarity = 1, - .platform_data = &hsusb1_phy_data, - }, -}; - static struct platform_device *panda_devices[] __initdata = { &leds_gpio, &wl1271_device, @@ -159,19 +142,49 @@ static struct platform_device *panda_devices[] __initdata = { static struct usbhs_omap_platform_data usbhs_bdata __initdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = false, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL +}; + +static struct gpio panda_ehci_gpios[] __initdata = { + { GPIO_HUB_POWER, GPIOF_OUT_INIT_LOW, "hub_power" }, + { GPIO_HUB_NRESET, GPIOF_OUT_INIT_LOW, "hub_nreset" }, }; static void __init omap4_ehci_init(void) { int ret; + struct clk *phy_ref_clk; /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */ - ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL); - if (ret) - pr_err("Failed to add main_clk alias to auxclk3_ck\n"); + phy_ref_clk = clk_get(NULL, "auxclk3_ck"); + if (IS_ERR(phy_ref_clk)) { + pr_err("Cannot request auxclk3\n"); + return; + } + clk_set_rate(phy_ref_clk, 19200000); + clk_prepare_enable(phy_ref_clk); + + /* disable the power to the usb hub prior to init and reset phy+hub */ + ret = gpio_request_array(panda_ehci_gpios, + ARRAY_SIZE(panda_ehci_gpios)); + if (ret) { + pr_err("Unable to initialize EHCI power/reset\n"); + return; + } + + gpio_export(GPIO_HUB_POWER, 0); + gpio_export(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 1); - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); + + /* enable power to hub */ + gpio_set_value(GPIO_HUB_POWER, 1); } static struct omap_musb_board_data musb_board_data = { diff --git a/trunk/arch/arm/mach-omap2/board-overo.c b/trunk/arch/arm/mach-omap2/board-overo.c index ab79a4422bcc..86bab51154ee 100644 --- a/trunk/arch/arm/mach-omap2/board-overo.c +++ b/trunk/arch/arm/mach-omap2/board-overo.c @@ -458,16 +458,14 @@ static int __init overo_spi_init(void) return 0; } -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = OVERO_GPIO_USBH_NRESET, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET, + .reset_gpio_port[2] = -EINVAL }; #ifdef CONFIG_OMAP_MUX @@ -504,8 +502,6 @@ static void __init overo_init(void) ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL); usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(NULL); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); overo_spi_init(); overo_init_smsc911x(); diff --git a/trunk/arch/arm/mach-omap2/board-rx51.c b/trunk/arch/arm/mach-omap2/board-rx51.c index d2ea68ea678a..f7c4616cbb60 100644 --- a/trunk/arch/arm/mach-omap2/board-rx51.c +++ b/trunk/arch/arm/mach-omap2/board-rx51.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -99,7 +98,6 @@ static void __init rx51_init(void) sdrc_params = nokia_get_sdram_timings(); omap_sdrc_init(sdrc_params, sdrc_params); - usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); usb_musb_init(&musb_board_data); rx51_peripherals_init(); diff --git a/trunk/arch/arm/mach-omap2/board-zoom.c b/trunk/arch/arm/mach-omap2/board-zoom.c index 1a3dd865d8eb..5e4d4c9fe61a 100644 --- a/trunk/arch/arm/mach-omap2/board-zoom.c +++ b/trunk/arch/arm/mach-omap2/board-zoom.c @@ -92,16 +92,14 @@ static struct mtd_partition zoom_nand_partitions[] = { }, }; -static struct usbhs_phy_data phy_data[] __initdata = { - { - .port = 2, - .reset_gpio = ZOOM3_EHCI_RESET_GPIO, - .vcc_gpio = -EINVAL, - }, -}; - static struct usbhs_omap_platform_data usbhs_bdata __initdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, }; static void __init omap_zoom_init(void) @@ -111,8 +109,6 @@ static void __init omap_zoom_init(void) } else if (machine_is_omap_zoom3()) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); - - usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data)); usbhs_init(&usbhs_bdata); } diff --git a/trunk/arch/arm/mach-omap2/cclock33xx_data.c b/trunk/arch/arm/mach-omap2/cclock33xx_data.c index 7f091c85384e..476b82066cb6 100644 --- a/trunk/arch/arm/mach-omap2/cclock33xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock33xx_data.c @@ -958,14 +958,6 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); - /* - * The On-Chip 32K RC Osc clock is not an accurate clock-source as per - * the design/spec, so as a result, for example, timer which supposed - * to get expired @60Sec, but will expire somewhere ~@40Sec, which is - * not expected by any use-case, so change WDT1 clock source to PRCM - * 32KHz clock. - */ - clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; } diff --git a/trunk/arch/arm/mach-omap2/common.h b/trunk/arch/arm/mach-omap2/common.h index 40f4a03d728f..0a6b9c7a63da 100644 --- a/trunk/arch/arm/mach-omap2/common.h +++ b/trunk/arch/arm/mach-omap2/common.h @@ -108,6 +108,7 @@ void omap35xx_init_late(void); void omap3630_init_late(void); void am35xx_init_late(void); void ti81xx_init_late(void); +void omap4430_init_late(void); int omap2_common_pm_late_init(void); #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) diff --git a/trunk/arch/arm/mach-omap2/dpll3xxx.c b/trunk/arch/arm/mach-omap2/dpll3xxx.c index 3a0296cfcace..3aed4b0b9563 100644 --- a/trunk/arch/arm/mach-omap2/dpll3xxx.c +++ b/trunk/arch/arm/mach-omap2/dpll3xxx.c @@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) _omap3_noncore_dpll_bypass(clk); /* - * Set jitter correction. Jitter correction applicable for OMAP343X - * only since freqsel field is no longer present on other devices. + * Set jitter correction. No jitter correction for OMAP4 and 3630 + * since freqsel field is no longer present */ - if (cpu_is_omap343x()) { + if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { v = __raw_readl(dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -480,30 +480,29 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; + __clk_prepare(dd->clk_bypass); + clk_enable(dd->clk_bypass); + __clk_prepare(dd->clk_ref); + clk_enable(dd->clk_ref); + if (__clk_get_rate(dd->clk_bypass) == rate && (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { pr_debug("%s: %s: set rate: entering bypass.\n", __func__, __clk_get_name(hw->clk)); - __clk_prepare(dd->clk_bypass); - clk_enable(dd->clk_bypass); ret = _omap3_noncore_dpll_bypass(clk); if (!ret) new_parent = dd->clk_bypass; - clk_disable(dd->clk_bypass); - __clk_unprepare(dd->clk_bypass); } else { - __clk_prepare(dd->clk_ref); - clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) rate = __clk_round_rate(hw->clk, rate); if (dd->last_rounded_rate == 0) return -EINVAL; - /* Freqsel is available only on OMAP343X devices */ - if (cpu_is_omap343x()) { + /* No freqsel on AM335x, OMAP4 and OMAP3630 */ + if (!soc_is_am33xx() && !cpu_is_omap44xx() && + !cpu_is_omap3630()) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); @@ -515,8 +514,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, ret = omap3_noncore_dpll_program(clk, freqsel); if (!ret) new_parent = dd->clk_ref; - clk_disable(dd->clk_ref); - __clk_unprepare(dd->clk_ref); } /* * FIXME - this is all wrong. common code handles reparenting and @@ -528,6 +525,11 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, if (!ret) __clk_reparent(hw->clk, new_parent); + clk_disable(dd->clk_ref); + __clk_unprepare(dd->clk_ref); + clk_disable(dd->clk_bypass); + __clk_unprepare(dd->clk_bypass); + return 0; } diff --git a/trunk/arch/arm/mach-omap2/dsp.c b/trunk/arch/arm/mach-omap2/dsp.c index b8208b4b1bd9..b155500e84a8 100644 --- a/trunk/arch/arm/mach-omap2/dsp.c +++ b/trunk/arch/arm/mach-omap2/dsp.c @@ -26,7 +26,7 @@ #include "control.h" #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" -#ifdef CONFIG_TIDSPBRIDGE_DVFS +#ifdef CONFIG_BRIDGE_DVFS #include "omap-pm.h" #endif @@ -35,7 +35,7 @@ static struct platform_device *omap_dsp_pdev; static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { -#ifdef CONFIG_TIDSPBRIDGE_DVFS +#ifdef CONFIG_BRIDGE_DVFS .dsp_set_min_opp = omap_pm_dsp_set_min_opp, .dsp_get_opp = omap_pm_dsp_get_opp, .cpu_set_freq = omap_pm_cpu_set_freq, diff --git a/trunk/arch/arm/mach-omap2/gpmc.c b/trunk/arch/arm/mach-omap2/gpmc.c index 410e1bac7815..e4b16c8efe8b 100644 --- a/trunk/arch/arm/mach-omap2/gpmc.c +++ b/trunk/arch/arm/mach-omap2/gpmc.c @@ -1122,6 +1122,9 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t, /* TODO: remove, see function definition */ gpmc_convert_ps_to_ns(gpmc_t); + /* Now the GPMC is initialised, unreserve the chip-selects */ + gpmc_cs_map = 0; + return 0; } @@ -1380,9 +1383,6 @@ static int gpmc_probe(struct platform_device *pdev) if (IS_ERR_VALUE(gpmc_setup_irq())) dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); - /* Now the GPMC is initialised, unreserve the chip-selects */ - gpmc_cs_map = 0; - rc = gpmc_probe_dt(pdev); if (rc < 0) { clk_disable_unprepare(gpmc_l3_clk); diff --git a/trunk/arch/arm/mach-omap2/id.c b/trunk/arch/arm/mach-omap2/id.c index ff0bc9e51aa7..8a68f1ec66b9 100644 --- a/trunk/arch/arm/mach-omap2/id.c +++ b/trunk/arch/arm/mach-omap2/id.c @@ -529,28 +529,22 @@ void __init omap5xxx_check_revision(void) case 0xb942: switch (rev) { case 0: - omap_revision = OMAP5430_REV_ES1_0; - break; - case 1: default: - omap_revision = OMAP5430_REV_ES2_0; + omap_revision = OMAP5430_REV_ES1_0; } break; case 0xb998: switch (rev) { case 0: - omap_revision = OMAP5432_REV_ES1_0; - break; - case 1: default: - omap_revision = OMAP5432_REV_ES2_0; + omap_revision = OMAP5432_REV_ES1_0; } break; default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP5430_REV_ES2_0; + omap_revision = OMAP5430_REV_ES1_0; } pr_info("OMAP%04x ES%d.0\n", diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index 2bef5a7e6af8..2c3fdd65387b 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -271,14 +271,6 @@ static struct map_desc omap54xx_io_desc[] __initdata = { .length = L4_PER_54XX_SIZE, .type = MT_DEVICE, }, -#ifdef CONFIG_OMAP4_ERRATA_I688 - { - .virtual = OMAP4_SRAM_VA, - .pfn = __phys_to_pfn(OMAP4_SRAM_PA), - .length = PAGE_SIZE, - .type = MT_MEMORY_SO, - }, -#endif }; #endif @@ -331,7 +323,6 @@ void __init omap4_map_io(void) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); - omap_barriers_init(); } #endif /* diff --git a/trunk/arch/arm/mach-omap2/mux.c b/trunk/arch/arm/mach-omap2/mux.c index f82cf878d6af..6a217c98db54 100644 --- a/trunk/arch/arm/mach-omap2/mux.c +++ b/trunk/arch/arm/mach-omap2/mux.c @@ -211,6 +211,8 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, return -EINVAL; } + pr_err("%s: Could not find signal %s\n", __func__, muxname); + return -ENODEV; } @@ -232,8 +234,6 @@ int __init omap_mux_get_by_name(const char *muxname, return mux_mode; } - pr_err("%s: Could not find signal %s\n", __func__, muxname); - return -ENODEV; } @@ -739,9 +739,8 @@ static void __init omap_mux_dbg_create_entry( list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; - (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO, - mux_dbg_dir, m, - &omap_mux_dbg_signal_fops); + (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir, + m, &omap_mux_dbg_signal_fops); } } diff --git a/trunk/arch/arm/mach-omap2/omap4-common.c b/trunk/arch/arm/mach-omap2/omap4-common.c index 2aeb928efdfd..708bb115a27f 100644 --- a/trunk/arch/arm/mach-omap2/omap4-common.c +++ b/trunk/arch/arm/mach-omap2/omap4-common.c @@ -240,21 +240,15 @@ void __iomem *omap4_get_sar_ram_base(void) */ static int __init omap4_sar_ram_init(void) { - unsigned long sar_base; - /* * To avoid code running on other OMAPs in * multi-omap builds */ - if (cpu_is_omap44xx()) - sar_base = OMAP44XX_SAR_RAM_BASE; - else if (soc_is_omap54xx()) - sar_base = OMAP54XX_SAR_RAM_BASE; - else + if (!cpu_is_omap44xx()) return -ENOMEM; /* Static mapping, never released */ - sar_ram_base = ioremap(sar_base, SZ_16K); + sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); if (WARN_ON(!sar_ram_base)) return -ENOMEM; diff --git a/trunk/arch/arm/mach-omap2/omap4-sar-layout.h b/trunk/arch/arm/mach-omap2/omap4-sar-layout.h index 937417523b8e..e170fe803b04 100644 --- a/trunk/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/trunk/arch/arm/mach-omap2/omap4-sar-layout.h @@ -48,13 +48,13 @@ #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ -#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) -#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) -#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) -#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) -#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) -#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) +#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) +#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) +#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) +#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) +#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) #endif diff --git a/trunk/arch/arm/mach-omap2/omap54xx.h b/trunk/arch/arm/mach-omap2/omap54xx.h index a086ba15868b..a2582bb3cab3 100644 --- a/trunk/arch/arm/mach-omap2/omap54xx.h +++ b/trunk/arch/arm/mach-omap2/omap54xx.h @@ -28,6 +28,5 @@ #define OMAP54XX_PRCM_MPU_BASE 0x48243000 #define OMAP54XX_SCM_BASE 0x4a002000 #define OMAP54XX_CTRL_BASE 0x4a002800 -#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 #endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 63b774fb8089..c2c798c08c2b 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -138,8 +138,6 @@ #include #include #include -#include -#include #include @@ -612,6 +610,8 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; + return 0; } @@ -645,6 +645,8 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) /* XXX test pwrdm_get_wken for this hwmod's subsystem */ + oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; + return 0; } @@ -2347,34 +2349,6 @@ static int _shutdown(struct omap_hwmod *oh) return 0; } -/** - * of_dev_hwmod_lookup - look up needed hwmod from dt blob - * @np: struct device_node * - * @oh: struct omap_hwmod * - * - * Parse the dt blob and find out needed hwmod. Recursive function is - * implemented to take care hierarchical dt blob parsing. - * Return: The device node on success or NULL on failure. - */ -static struct device_node *of_dev_hwmod_lookup(struct device_node *np, - struct omap_hwmod *oh) -{ - struct device_node *np0 = NULL, *np1 = NULL; - const char *p; - - for_each_child_of_node(np, np0) { - if (of_find_property(np0, "ti,hwmods", NULL)) { - p = of_get_property(np0, "ti,hwmods", NULL); - if (!strcmp(p, oh->name)) - return np0; - np1 = of_dev_hwmod_lookup(np0, oh); - if (np1) - return np1; - } - } - return NULL; -} - /** * _init_mpu_rt_base - populate the virtual address for a hwmod * @oh: struct omap_hwmod * to locate the virtual address @@ -2387,8 +2361,7 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np, static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) { struct omap_hwmod_addr_space *mem; - void __iomem *va_start = NULL; - struct device_node *np; + void __iomem *va_start; if (!oh) return; @@ -2402,18 +2375,10 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) if (!mem) { pr_debug("omap_hwmod: %s: no MPU register target found\n", oh->name); - - /* Extract the IO space from device tree blob */ - if (!of_have_populated_dt()) - return; - - np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); - if (np) - va_start = of_iomap(np, 0); - } else { - va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); + return; } + va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); if (!va_start) { pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); return; @@ -2445,8 +2410,7 @@ static int __init _init(struct omap_hwmod *oh, void *data) if (oh->_state != _HWMOD_STATE_REGISTERED) return 0; - if (oh->class->sysc) - _init_mpu_rt_base(oh, NULL); + _init_mpu_rt_base(oh, NULL); r = _init_clocks(oh, NULL); if (IS_ERR_VALUE(r)) { diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.h b/trunk/arch/arm/mach-omap2/omap_hwmod.h index 28f4dea0512e..d43d9b608eda 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.h +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.h @@ -477,13 +477,15 @@ struct omap_hwmod_omap4_prcm { * These are for internal use only and are managed by the omap_hwmod code. * * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - * causes the first call to _enable() to only update the pinmux */ #define _HWMOD_NO_MPU_PORT (1 << 0) -#define _HWMOD_SYSCONFIG_LOADED (1 << 1) -#define _HWMOD_SKIP_ENABLE (1 << 2) +#define _HWMOD_WAKEUP_ENABLED (1 << 1) +#define _HWMOD_SYSCONFIG_LOADED (1 << 2) +#define _HWMOD_SKIP_ENABLE (1 << 3) /* * omap_hwmod._state definitions diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 31bea1ce3de1..26eee4a556ad 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -28,7 +28,6 @@ #include "prm-regbits-33xx.h" #include "i2c.h" #include "mmc.h" -#include "wd_timer.h" /* * IP blocks @@ -2088,21 +2087,8 @@ static struct omap_hwmod am33xx_uart6_hwmod = { }; /* 'wd_timer' class */ -static struct omap_hwmod_class_sysconfig wdt_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { .name = "wd_timer", - .sysc = &wdt_sysc, - .pre_shutdown = &omap2_wd_timer_disable, }; /* @@ -2113,7 +2099,6 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = { .name = "wd_timer2", .class = &am33xx_wd_timer_hwmod_class, .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, .main_clk = "wdt1_fck", .prcm = { .omap4 = { diff --git a/trunk/arch/arm/mach-omap2/pmu.c b/trunk/arch/arm/mach-omap2/pmu.c index 9ace8eae7ee8..9debf822687c 100644 --- a/trunk/arch/arm/mach-omap2/pmu.c +++ b/trunk/arch/arm/mach-omap2/pmu.c @@ -11,8 +11,6 @@ * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ -#include - #include #include "soc.h" @@ -65,15 +63,6 @@ static int __init omap_init_pmu(void) unsigned oh_num; char **oh_names; - /* XXX Remove this check when the CTI driver is available */ - if (cpu_is_omap443x()) { - pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n"); - return 0; - } - - if (of_have_populated_dt()) - return 0; - /* * To create an ARM-PMU device the following HWMODs * are required for the various OMAP2+ devices. @@ -86,6 +75,9 @@ static int __init omap_init_pmu(void) if (cpu_is_omap443x()) { oh_num = ARRAY_SIZE(omap4430_pmu_oh_names); oh_names = omap4430_pmu_oh_names; + /* XXX Remove the next two lines when CTI driver available */ + pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n"); + return 0; } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { oh_num = ARRAY_SIZE(omap3_pmu_oh_names); oh_names = omap3_pmu_oh_names; diff --git a/trunk/arch/arm/mach-omap2/powerdomain.c b/trunk/arch/arm/mach-omap2/powerdomain.c index 89cad4a605dd..8e61d80bf6b3 100644 --- a/trunk/arch/arm/mach-omap2/powerdomain.c +++ b/trunk/arch/arm/mach-omap2/powerdomain.c @@ -52,6 +52,7 @@ enum { #define ALREADYACTIVE_SWITCH 0 #define FORCEWAKEUP_SWITCH 1 #define LOWPOWERSTATE_SWITCH 2 +#define ERROR_SWITCH 3 /* pwrdm_list contains all registered struct powerdomains */ static LIST_HEAD(pwrdm_list); @@ -232,7 +233,10 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, { u8 sleep_switch; - if (curr_pwrst < PWRDM_POWER_ON) { + if (curr_pwrst < 0) { + WARN_ON(1); + sleep_switch = ERROR_SWITCH; + } else if (curr_pwrst < PWRDM_POWER_ON) { if (curr_pwrst > pwrst && pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && arch_pwrdm->pwrdm_set_lowpwrstchange) { @@ -1087,8 +1091,7 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) */ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) { - u8 next_pwrst, sleep_switch; - int curr_pwrst; + u8 curr_pwrst, next_pwrst, sleep_switch; int ret = 0; bool hwsup = false; @@ -1104,17 +1107,16 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) pwrdm_lock(pwrdm); curr_pwrst = pwrdm_read_pwrst(pwrdm); - if (curr_pwrst < 0) { - ret = -EINVAL; - goto osps_out; - } - next_pwrst = pwrdm_read_next_pwrst(pwrdm); if (curr_pwrst == pwrst && next_pwrst == pwrst) goto osps_out; sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, pwrst, &hwsup); + if (sleep_switch == ERROR_SWITCH) { + ret = -EINVAL; + goto osps_out; + } ret = pwrdm_set_next_pwrst(pwrdm, pwrst); if (ret) diff --git a/trunk/arch/arm/mach-omap2/prm44xx.c b/trunk/arch/arm/mach-omap2/prm44xx.c index 415c7e0c9393..d35f98aabf7a 100644 --- a/trunk/arch/arm/mach-omap2/prm44xx.c +++ b/trunk/arch/arm/mach-omap2/prm44xx.c @@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { /* Read a register in a CM/PRM instance in the PRM module */ u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) { - return __raw_readl(prm_base + inst + reg); + return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); } /* Write into a register in a CM/PRM instance in the PRM module */ void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) { - __raw_writel(val, prm_base + inst + reg); + __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); } /* Read-modify-write a register in a PRM module. Caller must lock */ @@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx() && !soc_is_omap54xx()) + if (!cpu_is_omap44xx()) return 0; return prm_register(&omap44xx_prm_ll_data); diff --git a/trunk/arch/arm/mach-omap2/soc.h b/trunk/arch/arm/mach-omap2/soc.h index 18fdeeb3a44a..c62116bbc760 100644 --- a/trunk/arch/arm/mach-omap2/soc.h +++ b/trunk/arch/arm/mach-omap2/soc.h @@ -413,9 +413,7 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP54XX_CLASS 0x54000054 #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) -#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) -#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); diff --git a/trunk/arch/arm/mach-omap2/timer.c b/trunk/arch/arm/mach-omap2/timer.c index 58d86d7abada..2bdd4cf17a8f 100644 --- a/trunk/arch/arm/mach-omap2/timer.c +++ b/trunk/arch/arm/mach-omap2/timer.c @@ -62,7 +62,6 @@ #define OMAP2_MPU_SOURCE "sys_ck" #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE #define OMAP4_MPU_SOURCE "sys_clkin_ck" -#define OMAP5_MPU_SOURCE "sys_clkin" #define OMAP2_32K_SOURCE "func_32k_ck" #define OMAP3_32K_SOURCE "omap_32k_fck" #define OMAP4_32K_SOURCE "sys_32k_ck" @@ -144,12 +143,7 @@ static struct property device_disabled = { }; static struct of_device_id omap_timer_match[] __initdata = { - { .compatible = "ti,omap2420-timer", }, - { .compatible = "ti,omap3430-timer", }, - { .compatible = "ti,omap4430-timer", }, - { .compatible = "ti,omap5430-timer", }, - { .compatible = "ti,am335x-timer", }, - { .compatible = "ti,am335x-timer-1ms", }, + { .compatible = "ti,omap2-timer", }, { } }; @@ -493,7 +487,7 @@ static void __init realtime_counter_init(void) pr_err("%s: ioremap failed\n", __func__); return; } - sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE); + sys_clk = clk_get(NULL, "sys_clkin_ck"); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); @@ -603,7 +597,7 @@ void __init omap4_local_timer_init(void) int err; if (of_have_populated_dt()) { - clocksource_of_init(); + twd_local_timer_of_register(); return; } @@ -622,7 +616,7 @@ void __init omap4_local_timer_init(void) #ifdef CONFIG_SOC_OMAP5 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", - 2, OMAP5_MPU_SOURCE); + 2, OMAP4_MPU_SOURCE); void __init omap5_realtime_timer_init(void) { int err; diff --git a/trunk/arch/arm/mach-omap2/usb-host.c b/trunk/arch/arm/mach-omap2/usb-host.c index aa27d7f5cbb7..5706bdccf45e 100644 --- a/trunk/arch/arm/mach-omap2/usb-host.c +++ b/trunk/arch/arm/mach-omap2/usb-host.c @@ -22,12 +22,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include + +#include #include "soc.h" #include "omap_device.h" @@ -530,155 +526,3 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata) } #endif - -/* Template for PHY regulators */ -static struct fixed_voltage_config hsusb_reg_config = { - /* .supply_name filled later */ - .microvolts = 3300000, - .gpio = -1, /* updated later */ - .startup_delay = 70000, /* 70msec */ - .enable_high = 1, /* updated later */ - .enabled_at_boot = 0, /* keep in RESET */ - /* .init_data filled later */ -}; - -static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */ -static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ - -/** - * usbhs_add_regulator - Add a gpio based fixed voltage regulator device - * @name: name for the regulator - * @dev_id: device id of the device this regulator supplies power to - * @dev_supply: supply name that the device expects - * @gpio: GPIO number - * @polarity: 1 - Active high, 0 - Active low - */ -static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply, - int gpio, int polarity) -{ - struct regulator_consumer_supply *supplies; - struct regulator_init_data *reg_data; - struct fixed_voltage_config *config; - struct platform_device *pdev; - int ret; - - supplies = kzalloc(sizeof(*supplies), GFP_KERNEL); - if (!supplies) - return -ENOMEM; - - supplies->supply = dev_supply; - supplies->dev_name = dev_id; - - reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL); - if (!reg_data) - return -ENOMEM; - - reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; - reg_data->consumer_supplies = supplies; - reg_data->num_consumer_supplies = 1; - - config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config), - GFP_KERNEL); - if (!config) - return -ENOMEM; - - config->supply_name = name; - config->gpio = gpio; - config->enable_high = polarity; - config->init_data = reg_data; - - /* create a regulator device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->id = PLATFORM_DEVID_AUTO; - pdev->name = reg_name; - pdev->dev.platform_data = config; - - ret = platform_device_register(pdev); - if (ret) - pr_err("%s: Failed registering regulator %s for %s\n", - __func__, name, dev_id); - - return ret; -} - -int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) -{ - char *rail_name; - int i, len; - struct platform_device *pdev; - char *phy_id; - - /* the phy_id will be something like "nop_usb_xceiv.1" */ - len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */ - - for (i = 0; i < num_phys; i++) { - - if (!phy->port) { - pr_err("%s: Invalid port 0. Must start from 1\n", - __func__); - continue; - } - - /* do we need a NOP PHY device ? */ - if (!gpio_is_valid(phy->reset_gpio) && - !gpio_is_valid(phy->vcc_gpio)) - continue; - - /* create a NOP PHY device */ - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->id = phy->port; - pdev->name = nop_name; - pdev->dev.platform_data = phy->platform_data; - - phy_id = kmalloc(len, GFP_KERNEL); - if (!phy_id) - return -ENOMEM; - - scnprintf(phy_id, len, "nop_usb_xceiv.%d\n", - pdev->id); - - if (platform_device_register(pdev)) { - pr_err("%s: Failed to register device %s\n", - __func__, phy_id); - continue; - } - - usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id); - - /* Do we need RESET regulator ? */ - if (gpio_is_valid(phy->reset_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_reset", phy->port); - - usbhs_add_regulator(rail_name, phy_id, "reset", - phy->reset_gpio, 1); - } - - /* Do we need VCC regulator ? */ - if (gpio_is_valid(phy->vcc_gpio)) { - - rail_name = kmalloc(13, GFP_KERNEL); - if (!rail_name) - return -ENOMEM; - - scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port); - - usbhs_add_regulator(rail_name, phy_id, "vcc", - phy->vcc_gpio, phy->vcc_polarity); - } - - phy++; - } - - return 0; -} diff --git a/trunk/arch/arm/mach-omap2/usb.h b/trunk/arch/arm/mach-omap2/usb.h index e7261ebcf7b0..3319f5cf47a3 100644 --- a/trunk/arch/arm/mach-omap2/usb.h +++ b/trunk/arch/arm/mach-omap2/usb.h @@ -53,17 +53,8 @@ #define USBPHY_OTGSESSEND_EN (1 << 20) #define USBPHY_DATA_POLARITY (1 << 23) -struct usbhs_phy_data { - int port; /* 1 indexed port number */ - int reset_gpio; - int vcc_gpio; - bool vcc_polarity; /* 1 active high, 0 active low */ - void *platform_data; -}; - extern void usb_musb_init(struct omap_musb_board_data *board_data); extern void usbhs_init(struct usbhs_omap_platform_data *pdata); -extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys); extern void am35x_musb_reset(void); extern void am35x_musb_phy_power(u8 on); diff --git a/trunk/arch/arm/mach-pxa/raumfeld.c b/trunk/arch/arm/mach-pxa/raumfeld.c index 969b0ba7fa70..af41888acbd6 100644 --- a/trunk/arch/arm/mach-pxa/raumfeld.c +++ b/trunk/arch/arm/mach-pxa/raumfeld.c @@ -505,7 +505,6 @@ static struct w1_gpio_platform_data w1_gpio_platform_data = { .pin = GPIO_ONE_WIRE, .is_open_drain = 0, .enable_external_pullup = w1_enable_external_pullup, - .ext_pullup_enable_pin = -EINVAL, }; struct platform_device raumfeld_w1_gpio_device = { diff --git a/trunk/arch/arm/mach-s3c24xx/Kconfig b/trunk/arch/arm/mach-s3c24xx/Kconfig index 0c5e4fb61117..37f513d1588e 100644 --- a/trunk/arch/arm/mach-s3c24xx/Kconfig +++ b/trunk/arch/arm/mach-s3c24xx/Kconfig @@ -30,7 +30,6 @@ config CPU_S3C2410 select S3C2410_CLOCK select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2410 and S3C2410A family from the S3C24XX line of Samsung Mobile CPUs. @@ -42,7 +41,6 @@ config CPU_S3C2412 select CPU_LLSERIAL_S3C2440 select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM - select SAMSUNG_HRT help Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line @@ -55,7 +53,6 @@ config CPU_S3C2416 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2416 SoC from the S3C24XX line @@ -66,7 +63,6 @@ config CPU_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM select S3C2440_DMA if S3C24XX_DMA - select SAMSUNG_HRT help Support for S3C2440 Samsung Mobile CPU based systems. @@ -76,7 +72,6 @@ config CPU_S3C2442 select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK select S3C2410_PM if PM - select SAMSUNG_HRT help Support for S3C2442 Samsung Mobile CPU based systems. @@ -92,7 +87,6 @@ config CPU_S3C2443 select S3C2443_COMMON select S3C2443_DMA if S3C24XX_DMA select SAMSUNG_CLKSRC - select SAMSUNG_HRT help Support for the S3C2443 SoC from the S3C24XX line diff --git a/trunk/arch/arm/mach-s3c24xx/bast-irq.c b/trunk/arch/arm/mach-s3c24xx/bast-irq.c index cb1b791954de..c0daa9590b4c 100644 --- a/trunk/arch/arm/mach-s3c24xx/bast-irq.c +++ b/trunk/arch/arm/mach-s3c24xx/bast-irq.c @@ -34,6 +34,8 @@ #include #include +#include + #include "bast.h" #define irqdbf(x...) diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c index 34fffdf6fc1d..641266f3d152 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2410.c @@ -40,6 +40,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c index 2cc017da88fe..d10b695a9066 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2412.c @@ -41,6 +41,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c index 036056cea57c..14a81c2317a4 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2416.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c b/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c index 0a53051b0787..bdaba59b42dc 100644 --- a/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/clock-s3c2443.c @@ -41,6 +41,7 @@ #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/common-smdk.c b/trunk/arch/arm/mach-s3c24xx/common-smdk.c index 404444dd3840..3b2cf6db3634 100644 --- a/trunk/arch/arm/mach-s3c24xx/common-smdk.c +++ b/trunk/arch/arm/mach-s3c24xx/common-smdk.c @@ -41,12 +41,11 @@ #include +#include #include #include #include -#include "common-smdk.h" - /* LED devices */ static struct s3c24xx_led_platdata smdk_pdata_led4 = { diff --git a/trunk/arch/arm/mach-s3c24xx/common.c b/trunk/arch/arm/mach-s3c24xx/common.c index d97533d21ac4..6bcf87f65f9e 100644 --- a/trunk/arch/arm/mach-s3c24xx/common.c +++ b/trunk/arch/arm/mach-s3c24xx/common.c @@ -47,11 +47,14 @@ #include #include #include +#include +#include +#include +#include +#include #include #include -#include "common.h" - /* table of supported CPUs */ static const char name_s3c2410[] = "S3C2410"; diff --git a/trunk/arch/arm/mach-s3c24xx/common.h b/trunk/arch/arm/mach-s3c24xx/common.h index 8a2b4137ddb6..ed6276fcaa3b 100644 --- a/trunk/arch/arm/mach-s3c24xx/common.h +++ b/trunk/arch/arm/mach-s3c24xx/common.h @@ -12,94 +12,8 @@ #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ -struct s3c2410_uartcfg; - -#ifdef CONFIG_CPU_S3C2410 -extern int s3c2410_init(void); -extern int s3c2410a_init(void); -extern void s3c2410_map_io(void); -extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2410_init_clocks(int xtal); -extern void s3c2410_restart(char mode, const char *cmd); -#else -#define s3c2410_init_clocks NULL -#define s3c2410_init_uarts NULL -#define s3c2410_map_io NULL -#define s3c2410_init NULL -#define s3c2410a_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2412 -extern int s3c2412_init(void); -extern void s3c2412_map_io(void); -extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2412_init_clocks(int xtal); -extern int s3c2412_baseclk_add(void); -extern void s3c2412_restart(char mode, const char *cmd); -#else -#define s3c2412_init_clocks NULL -#define s3c2412_init_uarts NULL -#define s3c2412_map_io NULL -#define s3c2412_init NULL -#endif - -#ifdef CONFIG_CPU_S3C2416 -extern int s3c2416_init(void); -extern void s3c2416_map_io(void); -extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2416_init_clocks(int xtal); -extern int s3c2416_baseclk_add(void); -extern void s3c2416_restart(char mode, const char *cmd); -extern void s3c2416_init_irq(void); - -extern struct syscore_ops s3c2416_irq_syscore_ops; -#else -#define s3c2416_init_clocks NULL -#define s3c2416_init_uarts NULL -#define s3c2416_map_io NULL -#define s3c2416_init NULL -#endif - -#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -extern void s3c244x_map_io(void); -extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c244x_init_clocks(int xtal); -extern void s3c244x_restart(char mode, const char *cmd); -#else -#define s3c244x_init_clocks NULL -#define s3c244x_init_uarts NULL -#endif - -#ifdef CONFIG_CPU_S3C2440 -extern int s3c2440_init(void); -extern void s3c2440_map_io(void); -#else -#define s3c2440_init NULL -#define s3c2440_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2442 -extern int s3c2442_init(void); -extern void s3c2442_map_io(void); -#else -#define s3c2442_init NULL -#define s3c2442_map_io NULL -#endif - -#ifdef CONFIG_CPU_S3C2443 -extern int s3c2443_init(void); -extern void s3c2443_map_io(void); -extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); -extern void s3c2443_init_clocks(int xtal); -extern int s3c2443_baseclk_add(void); -extern void s3c2443_restart(char mode, const char *cmd); -extern void s3c2443_init_irq(void); -#else -#define s3c2443_init_clocks NULL -#define s3c2443_init_uarts NULL -#define s3c2443_map_io NULL -#define s3c2443_init NULL -#endif +void s3c2410_restart(char mode, const char *cmd); +void s3c244x_restart(char mode, const char *cmd); extern struct syscore_ops s3c24xx_irq_syscore_ops; diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c index a6c94b820954..25d085adc93c 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2410.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c index c0e8c3f5057e..d2408ba372cb 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c index 1c08eccd9425..0b86e74d104f 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2440.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c b/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c index 000e4c69fce9..05536254a3f8 100644 --- a/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h new file mode 100644 index 000000000000..cbf2d8884e30 --- /dev/null +++ b/trunk/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h @@ -0,0 +1,127 @@ +/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h + * + * Copyright (c) 2004 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 MMC/SDIO register definitions +*/ + +#ifndef __ASM_ARM_REGS_SDI +#define __ASM_ARM_REGS_SDI "regs-sdi.h" + +#define S3C2410_SDICON (0x00) +#define S3C2410_SDIPRE (0x04) +#define S3C2410_SDICMDARG (0x08) +#define S3C2410_SDICMDCON (0x0C) +#define S3C2410_SDICMDSTAT (0x10) +#define S3C2410_SDIRSP0 (0x14) +#define S3C2410_SDIRSP1 (0x18) +#define S3C2410_SDIRSP2 (0x1C) +#define S3C2410_SDIRSP3 (0x20) +#define S3C2410_SDITIMER (0x24) +#define S3C2410_SDIBSIZE (0x28) +#define S3C2410_SDIDCON (0x2C) +#define S3C2410_SDIDCNT (0x30) +#define S3C2410_SDIDSTA (0x34) +#define S3C2410_SDIFSTA (0x38) + +#define S3C2410_SDIDATA (0x3C) +#define S3C2410_SDIIMSK (0x40) + +#define S3C2440_SDIDATA (0x40) +#define S3C2440_SDIIMSK (0x3C) + +#define S3C2440_SDICON_SDRESET (1<<8) +#define S3C2440_SDICON_MMCCLOCK (1<<5) +#define S3C2410_SDICON_BYTEORDER (1<<4) +#define S3C2410_SDICON_SDIOIRQ (1<<3) +#define S3C2410_SDICON_RWAITEN (1<<2) +#define S3C2410_SDICON_FIFORESET (1<<1) +#define S3C2410_SDICON_CLOCKTYPE (1<<0) + +#define S3C2410_SDICMDCON_ABORT (1<<12) +#define S3C2410_SDICMDCON_WITHDATA (1<<11) +#define S3C2410_SDICMDCON_LONGRSP (1<<10) +#define S3C2410_SDICMDCON_WAITRSP (1<<9) +#define S3C2410_SDICMDCON_CMDSTART (1<<8) +#define S3C2410_SDICMDCON_SENDERHOST (1<<6) +#define S3C2410_SDICMDCON_INDEX (0x3f) + +#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) +#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) +#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) +#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) +#define S3C2410_SDICMDSTAT_XFERING (1<<8) +#define S3C2410_SDICMDSTAT_INDEX (0xff) + +#define S3C2440_SDIDCON_DS_BYTE (0<<22) +#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) +#define S3C2440_SDIDCON_DS_WORD (2<<22) +#define S3C2410_SDIDCON_IRQPERIOD (1<<21) +#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) +#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) +#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) +#define S3C2410_SDIDCON_BLOCKMODE (1<<17) +#define S3C2410_SDIDCON_WIDEBUS (1<<16) +#define S3C2410_SDIDCON_DMAEN (1<<15) +#define S3C2410_SDIDCON_STOP (1<<14) +#define S3C2440_SDIDCON_DATSTART (1<<14) +#define S3C2410_SDIDCON_DATMODE (3<<12) +#define S3C2410_SDIDCON_BLKNUM (0x7ff) + +/* constants for S3C2410_SDIDCON_DATMODE */ +#define S3C2410_SDIDCON_XFER_READY (0<<12) +#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) +#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) +#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) + +#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) +#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) + +#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) +#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) +#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ +#define S3C2410_SDIDSTA_CRCFAIL (1<<7) +#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) +#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) +#define S3C2410_SDIDSTA_XFERFINISH (1<<4) +#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) +#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ +#define S3C2410_SDIDSTA_TXDATAON (1<<1) +#define S3C2410_SDIDSTA_RXDATAON (1<<0) + +#define S3C2440_SDIFSTA_FIFORESET (1<<16) +#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ +#define S3C2410_SDIFSTA_TFDET (1<<13) +#define S3C2410_SDIFSTA_RFDET (1<<12) +#define S3C2410_SDIFSTA_TFHALF (1<<11) +#define S3C2410_SDIFSTA_TFEMPTY (1<<10) +#define S3C2410_SDIFSTA_RFLAST (1<<9) +#define S3C2410_SDIFSTA_RFFULL (1<<8) +#define S3C2410_SDIFSTA_RFHALF (1<<7) +#define S3C2410_SDIFSTA_COUNTMASK (0x7f) + +#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) +#define S3C2410_SDIIMSK_CMDSENT (1<<16) +#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) +#define S3C2410_SDIIMSK_RESPONSEND (1<<14) +#define S3C2410_SDIIMSK_READWAIT (1<<13) +#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) +#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) +#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) +#define S3C2410_SDIIMSK_DATACRC (1<<9) +#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) +#define S3C2410_SDIIMSK_DATAFINISH (1<<7) +#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) +#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ +#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) +#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) +#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) +#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) +#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) + +#endif /* __ASM_ARM_REGS_SDI */ diff --git a/trunk/arch/arm/mach-s3c24xx/irq-pm.c b/trunk/arch/arm/mach-s3c24xx/irq-pm.c index b91341ef2b2e..e1199599873e 100644 --- a/trunk/arch/arm/mach-s3c24xx/irq-pm.c +++ b/trunk/arch/arm/mach-s3c24xx/irq-pm.c @@ -16,15 +16,10 @@ #include #include #include -#include #include #include -#include -#include - -#include -#include +#include #include diff --git a/trunk/arch/arm/mach-s3c24xx/irq.c b/trunk/arch/arm/mach-s3c24xx/irq.c index c1b96f7cc587..cb9f5e011e73 100644 --- a/trunk/arch/arm/mach-s3c24xx/irq.c +++ b/trunk/arch/arm/mach-s3c24xx/irq.c @@ -34,6 +34,7 @@ #include #include #include +#include #define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 @@ -174,7 +175,8 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg, return 0; } -static int s3c_irqext_type(struct irq_data *data, unsigned int type) +/* FIXME: make static when it's out of plat-samsung/irq.h */ +int s3c_irqext_type(struct irq_data *data, unsigned int type) { void __iomem *extint_reg; void __iomem *gpcon_reg; @@ -222,7 +224,7 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type) extint_offset, type); } -static struct irq_chip s3c_irq_chip = { +struct irq_chip s3c_irq_chip = { .name = "s3c", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, @@ -230,7 +232,7 @@ static struct irq_chip s3c_irq_chip = { .irq_set_wake = s3c_irq_wake }; -static struct irq_chip s3c_irq_level_chip = { +struct irq_chip s3c_irq_level_chip = { .name = "s3c-level", .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, diff --git a/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c b/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c index 432144cb54ae..0e0279e79150 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-amlm5900.c @@ -63,8 +63,6 @@ #include #include -#include - #include "common.h" static struct resource amlm5900_nor_resource = @@ -162,7 +160,6 @@ static void __init amlm5900_map_io(void) s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } #ifdef CONFIG_FB_S3C2410 @@ -240,6 +237,6 @@ MACHINE_START(AML_M5900, "AML_M5900") .map_io = amlm5900_map_io, .init_irq = s3c24xx_init_irq, .init_machine = amlm5900_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-anubis.c b/trunk/arch/arm/mach-s3c24xx/mach-anubis.c index 24f1a04ccc88..bb595f15ce36 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-anubis.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "anubis.h" #include "common.h" @@ -411,7 +410,6 @@ static void __init anubis_map_io(void) s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* check for the newer revision boards with large page nand */ @@ -446,6 +444,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis") .map_io = anubis_map_io, .init_machine = anubis_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c b/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c index 2bf6c8c24317..b4bc60c78ebb 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-at2440evb.c @@ -48,7 +48,6 @@ #include #include #include -#include #include "common.h" @@ -193,7 +192,6 @@ static void __init at2440evb_map_io(void) s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init at2440evb_init(void) @@ -212,6 +210,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB") .map_io = at2440evb_map_io, .init_machine = at2440evb_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-bast.c b/trunk/arch/arm/mach-s3c24xx/mach-bast.c index eabe2db42ef6..ca6618081041 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-bast.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-bast.c @@ -55,7 +55,6 @@ #include #include #include -#include #include "bast.h" #include "common.h" @@ -577,7 +576,6 @@ static void __init bast_map_io(void) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init bast_init(void) @@ -607,6 +605,6 @@ MACHINE_START(BAST, "Simtec-BAST") .map_io = bast_map_io, .init_irq = s3c24xx_init_irq, .init_machine = bast_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-gta02.c b/trunk/arch/arm/mach-s3c24xx/mach-gta02.c index 84a750d46d4b..a25e8c5a7b4c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-gta02.c @@ -81,7 +81,6 @@ #include #include #include -#include #include "common.h" #include "gta02.h" @@ -502,7 +501,6 @@ static void __init gta02_map_io(void) s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } @@ -591,6 +589,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02") .map_io = gta02_map_io, .init_irq = s3c24xx_init_irq, .init_machine = gta02_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-h1940.c b/trunk/arch/arm/mach-s3c24xx/mach-h1940.c index 8dd660102846..79bc0830d740 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-h1940.c @@ -62,7 +62,7 @@ #include #include #include -#include + #include "common.h" #include "h1940.h" @@ -646,7 +646,6 @@ static void __init h1940_map_io(void) s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* setup PM */ @@ -742,6 +741,6 @@ MACHINE_START(H1940, "IPAQ-H1940") .reserve = h1940_reserve, .init_irq = h1940_init_irq, .init_machine = h1940_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-jive.c b/trunk/arch/arm/mach-s3c24xx/mach-jive.c index aade943288c7..54e83c1f780c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-jive.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-jive.c @@ -46,15 +46,14 @@ #include #include +#include #include #include #include #include #include #include -#include -#include "common.h" #include "s3c2412-power.h" static struct map_desc jive_iodesc[] __initdata = { @@ -507,7 +506,6 @@ static void __init jive_map_io(void) s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void jive_power_off(void) @@ -663,6 +661,6 @@ MACHINE_START(JIVE, "JIVE") .init_irq = s3c24xx_init_irq, .map_io = jive_map_io, .init_machine = jive_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c b/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c index 29f106cb370e..2865e5919f2c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-mini2440.c @@ -56,7 +56,6 @@ #include #include #include -#include #include @@ -526,7 +525,6 @@ static void __init mini2440_map_io(void) s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* @@ -689,6 +687,6 @@ MACHINE_START(MINI2440, "MINI2440") .map_io = mini2440_map_io, .init_machine = mini2440_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-n30.c b/trunk/arch/arm/mach-s3c24xx/mach-n30.c index 73a690f431e6..d9d04b240295 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-n30.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-n30.c @@ -48,8 +48,8 @@ #include #include #include +#include #include -#include #include "common.h" @@ -536,7 +536,6 @@ static void __init n30_map_io(void) n30_hwinit(); s3c24xx_init_clocks(0); s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* GPB3 is the line that controls the pull-up for the USB D+ line */ @@ -590,7 +589,7 @@ MACHINE_START(N30, "Acer-N30") Ben Dooks */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, @@ -601,7 +600,7 @@ MACHINE_START(N35, "Acer-N35") /* Maintainer: Christer Weinigel */ .atag_offset = 0x100, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .init_machine = n30_init, .init_irq = s3c24xx_init_irq, .map_io = n30_map_io, diff --git a/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c b/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c index 5c826d10a66d..a454e2461860 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-nexcoder.c @@ -41,10 +41,11 @@ #include #include +#include +#include #include #include #include -#include #include "common.h" @@ -136,7 +137,6 @@ static void __init nexcoder_map_io(void) s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); nexcoder_sensorboard_init(); } @@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") .map_io = nexcoder_map_io, .init_machine = nexcoder_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-osiris.c b/trunk/arch/arm/mach-s3c24xx/mach-osiris.c index 4c90ffda4e11..ae2cbdf3e3ca 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-osiris.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include @@ -385,7 +384,6 @@ static void __init osiris_map_io(void) s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* check for the newer revision boards with large page nand */ @@ -428,6 +426,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS") .map_io = osiris_map_io, .init_irq = s3c24xx_init_irq, .init_machine = osiris_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-otom.c b/trunk/arch/arm/mach-s3c24xx/mach-otom.c index 7b8670746b6a..40a47d6c6a85 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-otom.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-otom.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include "common.h" #include "otom.h" @@ -102,7 +102,6 @@ static void __init otom11_map_io(void) s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init otom11_init(void) @@ -117,6 +116,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1") .map_io = otom11_map_io, .init_machine = otom11_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c b/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c index 71cf29b12d1f..56175f0941b1 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-qt2410.c @@ -55,14 +55,13 @@ #include #include +#include #include #include #include #include -#include #include "common.h" -#include "common-smdk.h" static struct map_desc qt2410_iodesc[] __initdata = { { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } @@ -305,7 +304,6 @@ static void __init qt2410_map_io(void) s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); s3c24xx_init_clocks(12*1000*1000); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init qt2410_machine_init(void) @@ -345,6 +343,6 @@ MACHINE_START(QT2410, "QT2410") .map_io = qt2410_map_io, .init_irq = s3c24xx_init_irq, .init_machine = qt2410_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c b/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c index 799af43b4e6a..1f9ba2ae5288 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -58,7 +58,6 @@ #include #include #include -#include #include "common.h" #include "h1940.h" @@ -742,7 +741,6 @@ static void __init rx1950_map_io(void) s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* setup PM */ @@ -815,6 +813,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950") .reserve = rx1950_reserve, .init_irq = s3c24xx_init_irq, .init_machine = rx1950_init_machine, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c b/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c index 0a3c96452f0f..f20418a2fb1b 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-rx3715.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "common.h" #include "h1940.h" @@ -180,7 +179,6 @@ static void __init rx3715_map_io(void) s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } /* H1940 and RX3715 need to reserve this for suspend */ @@ -214,6 +212,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715") .reserve = rx3715_reserve, .init_irq = rx3715_init_irq, .init_machine = rx3715_init_machine, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c index fd96f7fc330c..e184bfa9613a 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2410.c @@ -51,10 +51,10 @@ #include #include -#include + +#include #include "common.h" -#include "common-smdk.h" static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ @@ -101,7 +101,6 @@ static void __init smdk2410_map_io(void) s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2410_init(void) @@ -118,6 +117,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc .map_io = smdk2410_map_io, .init_irq = s3c24xx_init_irq, .init_machine = smdk2410_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c index 8e3f1d9bbb7c..86d7847c9d45 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -41,13 +41,13 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2413_iodesc[] __initdata = { }; @@ -106,7 +106,6 @@ static void __init smdk2413_map_io(void) s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2413_machine_init(void) @@ -133,7 +132,7 @@ MACHINE_START(S3C2413, "S3C2413") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -145,7 +144,7 @@ MACHINE_START(SMDK2412, "SMDK2412") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END @@ -157,6 +156,6 @@ MACHINE_START(SMDK2413, "SMDK2413") .init_irq = s3c24xx_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c index cb46847c66b4..ebb2e61f3d07 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -50,12 +51,10 @@ #include #include #include -#include #include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -222,7 +221,6 @@ static void __init smdk2416_map_io(void) s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2416_machine_init(void) @@ -255,6 +253,6 @@ MACHINE_START(SMDK2416, "SMDK2416") .init_irq = s3c2416_init_irq, .map_io = smdk2416_map_io, .init_machine = smdk2416_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2416_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c index f56cb08e6d1c..08cc38c8a4ae 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2440.c @@ -38,13 +38,15 @@ #include #include +#include +#include #include #include #include -#include + +#include #include "common.h" -#include "common-smdk.h" static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -161,7 +163,6 @@ static void __init smdk2440_map_io(void) s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2440_machine_init(void) @@ -180,6 +181,6 @@ MACHINE_START(S3C2440, "SMDK2440") .init_irq = s3c24xx_init_irq, .map_io = smdk2440_map_io, .init_machine = smdk2440_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c244x_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c b/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c index 9435c3bef18a..fc65d74d3c73 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -38,13 +38,13 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" -#include "common-smdk.h" +#include static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -122,7 +122,6 @@ static void __init smdk2443_map_io(void) s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init smdk2443_machine_init(void) @@ -144,6 +143,6 @@ MACHINE_START(SMDK2443, "SMDK2443") .init_irq = s3c2443_init_irq, .map_io = smdk2443_map_io, .init_machine = smdk2443_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2443_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c index 31dfe589e349..24b3d79e7b2c 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-tct_hammer.c @@ -53,7 +53,6 @@ #include #include #include -#include #include "common.h" @@ -137,7 +136,6 @@ static void __init tct_hammer_map_io(void) s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init tct_hammer_init(void) @@ -151,6 +149,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER") .map_io = tct_hammer_map_io, .init_irq = s3c24xx_init_irq, .init_machine = tct_hammer_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c b/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c index deeb8a0a4034..ec42d1e4e465 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-vr1000.c @@ -45,7 +45,6 @@ #include #include #include -#include #include "bast.h" #include "common.h" @@ -333,7 +332,6 @@ static void __init vr1000_map_io(void) s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init vr1000_init(void) @@ -356,6 +354,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000") .map_io = vr1000_map_io, .init_machine = vr1000_init, .init_irq = s3c24xx_init_irq, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2410_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/mach-vstms.c b/trunk/arch/arm/mach-s3c24xx/mach-vstms.c index 622a1ed24509..3e2bfddc9df1 100644 --- a/trunk/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/trunk/arch/arm/mach-s3c24xx/mach-vstms.c @@ -41,12 +41,12 @@ #include #include +#include +#include #include #include #include -#include -#include "common.h" static struct map_desc vstms_iodesc[] __initdata = { }; @@ -143,7 +143,6 @@ static void __init vstms_map_io(void) s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init vstms_init(void) @@ -161,6 +160,6 @@ MACHINE_START(VSTMS, "VSTMS") .init_irq = s3c24xx_init_irq, .init_machine = vstms_init, .map_io = vstms_map_io, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c2412_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c b/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c index 4c4bc1c83b77..668a78a8b195 100644 --- a/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/pm-s3c2412.c @@ -29,6 +29,7 @@ #include #include +#include #include "regs-dsc.h" #include "s3c2412-power.h" diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2410.c b/trunk/arch/arm/mach-s3c24xx/s3c2410.c index d850ea5adac2..9ebef95da721 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2410.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2410.c @@ -37,6 +37,7 @@ #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2412.c b/trunk/arch/arm/mach-s3c24xx/s3c2412.c index 0f864d4c97de..0d592159a5c3 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2412.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2412.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "common.h" #include "regs-dsc.h" diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2416.c b/trunk/arch/arm/mach-s3c24xx/s3c2416.c index b9c5d382dafb..e30476db0295 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2416.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2416.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2440.c b/trunk/arch/arm/mach-s3c24xx/s3c2440.c index 5f9d6569475d..559e394e8989 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2440.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2440.c @@ -33,6 +33,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2442.c b/trunk/arch/arm/mach-s3c24xx/s3c2442.c index 6819961f6b19..f732826c2359 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2442.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2442.c @@ -44,6 +44,7 @@ #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c2443.c b/trunk/arch/arm/mach-s3c24xx/s3c2443.c index 8328cd65bf3d..165b6a6b3daa 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c2443.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c24xx/s3c244x.c b/trunk/arch/arm/mach-s3c24xx/s3c244x.c index 2a35edb67354..ad2671baa910 100644 --- a/trunk/arch/arm/mach-s3c24xx/s3c244x.c +++ b/trunk/arch/arm/mach-s3c24xx/s3c244x.c @@ -37,6 +37,8 @@ #include #include +#include +#include #include #include #include diff --git a/trunk/arch/arm/mach-s3c64xx/Kconfig b/trunk/arch/arm/mach-s3c64xx/Kconfig index 283cb77d4721..131c86284711 100644 --- a/trunk/arch/arm/mach-s3c64xx/Kconfig +++ b/trunk/arch/arm/mach-s3c64xx/Kconfig @@ -17,13 +17,11 @@ config PLAT_S3C64XX # Configuration options for the S3C6410 CPU config CPU_S3C6400 - select SAMSUNG_HRT bool help Enable S3C6400 CPU support config CPU_S3C6410 - select SAMSUNG_HRT bool help Enable S3C6410 CPU support diff --git a/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c b/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c index 35e3f54574ef..728eef3296b2 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -49,7 +49,6 @@ #include #include #include -#include #include "common.h" #include "regs-modem.h" @@ -209,7 +208,6 @@ static void __init anw6410_map_io(void) s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); anw6410_lcd_mode_set(); } @@ -234,6 +232,6 @@ MACHINE_START(ANW6410, "A&W6410") .map_io = anw6410_map_io, .init_machine = anw6410_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c b/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c index 8ad88ace795a..1acf02bace57 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -64,7 +64,6 @@ #include #include #include -#include #include "common.h" #include "crag6410.h" @@ -745,7 +744,6 @@ static void __init crag6410_map_io(void) s3c64xx_init_io(NULL, 0); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); /* LCD type and Bypass set by bootloader */ } @@ -870,6 +868,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") .map_io = crag6410_map_io, .init_machine = crag6410_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-hmt.c b/trunk/arch/arm/mach-s3c64xx/mach-hmt.c index 5b7f357d8c22..7212eb9cfeb9 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-hmt.c @@ -41,7 +41,6 @@ #include #include #include -#include #include "common.h" @@ -249,7 +248,6 @@ static void __init hmt_map_io(void) s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } static void __init hmt_machine_init(void) @@ -277,6 +275,6 @@ MACHINE_START(HMT, "Airgoo-HMT") .map_io = hmt_map_io, .init_machine = hmt_machine_init, .init_late = s3c64xx_init_late, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, .restart = s3c64xx_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c b/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c index fc043e3ecdf8..4b41fcdaa7b6 100644 --- a/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/trunk/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -41,7 +41,6 @@ #include