From e2fe24dcbca5cdc4872ab647240a4be5feba8d65 Mon Sep 17 00:00:00 2001 From: Ke Wei Date: Fri, 23 May 2008 10:23:22 +0200 Subject: [PATCH] --- yaml --- r: 100750 b: refs/heads/master c: 1219715de70956557b9dedf3ee021a73d4f4ec52 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-orion/time.c | 6 +++--- trunk/include/asm-arm/arch-orion5x/orion5x.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 903a450510fc..605fe1a606b2 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ab6d15d50637fc25ee941710b23fed09ceb28db3 +refs/heads/master: 1219715de70956557b9dedf3ee021a73d4f4ec52 diff --git a/trunk/arch/arm/plat-orion/time.c b/trunk/arch/arm/plat-orion/time.c index 28b5285446e8..93c4ef9f0067 100644 --- a/trunk/arch/arm/plat-orion/time.c +++ b/trunk/arch/arm/plat-orion/time.c @@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) /* * Clear and enable clockevent timer interrupt. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); u = readl(BRIDGE_MASK); u |= BRIDGE_INT_TIMER1; @@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) /* * ACK pending timer interrupt. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); } local_irq_restore(flags); @@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) /* * ACK timer interrupt and call event handler. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); orion_clkevt.event_handler(&orion_clkevt); return IRQ_HANDLED; diff --git a/trunk/include/asm-arm/arch-orion5x/orion5x.h b/trunk/include/asm-arm/arch-orion5x/orion5x.h index 20f7b406a798..10257f5c5e9e 100644 --- a/trunk/include/asm-arm/arch-orion5x/orion5x.h +++ b/trunk/include/asm-arm/arch-orion5x/orion5x.h @@ -154,6 +154,7 @@ #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)