From e3009c7d5a91b0324a76fbc95ef7cf91333b083f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 31 Oct 2011 11:59:07 +1000 Subject: [PATCH] --- yaml --- r: 282609 b: refs/heads/master c: 8b5f4d0def9caa16527c95e7a4ba47bb8a4d9e1e h: refs/heads/master i: 282607: fb65e9f2f648e53602e5d4d34b9a1686daed8c85 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nv50_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 0bfe36ccab2f..436f73c20e5b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 973e861657f6faaa3ee01de093d2307470a6d193 +refs/heads/master: 8b5f4d0def9caa16527c95e7a4ba47bb8a4d9e1e diff --git a/trunk/drivers/gpu/drm/nouveau/nv50_pm.c b/trunk/drivers/gpu/drm/nouveau/nv50_pm.c index 0b82c6075666..961d8f20d27f 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nv50_pm.c @@ -465,7 +465,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) /* memory: use pcie refclock if possible, otherwise use mpll */ info->mscript = perflvl->memscript; if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) { - info->mctrl = nv_rd32(dev, 0x4008) | 0x00000200; + info->mctrl = 0x00000200 | (pll.log2p_bias << 19); info->mcoef = nv_rd32(dev, 0x400c); } else if (perflvl->memory) { @@ -606,7 +606,7 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data) /* modify mpll */ nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000); - nv_mask(dev, 0x004008, 0x81ff0200, 0x00000200 | info->mctrl); + nv_mask(dev, 0x004008, 0x01ff0200, 0x00000200 | info->mctrl); nv_wr32(dev, 0x00400c, info->mcoef); udelay(100); nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);