diff --git a/[refs] b/[refs]
index 89c83c4287f2..f0242886f4ab 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1bf6d2c1bb23533af6930581cc39b74685bc29de
+refs/heads/master: 6111d50c5885f6ba00dc935e44bcbbcd63b3915d
diff --git a/trunk/arch/arm/boot/dts/tegra-harmony.dts b/trunk/arch/arm/boot/dts/tegra-harmony.dts
index e5818668d091..0e225b86b652 100644
--- a/trunk/arch/arm/boot/dts/tegra-harmony.dts
+++ b/trunk/arch/arm/boot/dts/tegra-harmony.dts
@@ -66,5 +66,6 @@
 		cd-gpios = <&gpio 58 0>; /* gpio PH2 */
 		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		support-8bit;
 	};
 };
diff --git a/trunk/arch/arm/boot/dts/tegra-seaboard.dts b/trunk/arch/arm/boot/dts/tegra-seaboard.dts
index 64cedca6fc79..a72299b8e668 100644
--- a/trunk/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/trunk/arch/arm/boot/dts/tegra-seaboard.dts
@@ -25,4 +25,8 @@
 		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 	};
+
+	sdhci@c8000600 {
+		support-8bit;
+	};
 };
diff --git a/trunk/arch/arm/mach-ux500/Kconfig b/trunk/arch/arm/mach-ux500/Kconfig
index a3e0c8692f0d..4210cb434dbc 100644
--- a/trunk/arch/arm/mach-ux500/Kconfig
+++ b/trunk/arch/arm/mach-ux500/Kconfig
@@ -6,7 +6,6 @@ config UX500_SOC_COMMON
 	select ARM_GIC
 	select HAS_MTU
 	select ARM_ERRATA_753970
-	select ARM_ERRATA_754322
 
 menu "Ux500 SoC"
 
diff --git a/trunk/arch/arm/mach-ux500/cpu.c b/trunk/arch/arm/mach-ux500/cpu.c
index 8aa104a4711a..1da23bb87c16 100644
--- a/trunk/arch/arm/mach-ux500/cpu.c
+++ b/trunk/arch/arm/mach-ux500/cpu.c
@@ -99,27 +99,7 @@ static void ux500_l2x0_inv_all(void)
 	ux500_cache_sync();
 }
 
-static int __init ux500_l2x0_unlock(void)
-{
-	int i;
-
-	/*
-	 * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
-	 * apparently locks both caches before jumping to the kernel. The
-	 * l2x0 core will not touch the unlock registers if the l2x0 is
-	 * already enabled, so we do it right here instead. The PL310 has
-	 * 8 sets of registers, one per possible CPU.
-	 */
-	for (i = 0; i < 8; i++) {
-		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
-			       i * L2X0_LOCKDOWN_STRIDE);
-		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
-			       i * L2X0_LOCKDOWN_STRIDE);
-	}
-	return 0;
-}
-
-static int __init ux500_l2x0_init(void)
+static int ux500_l2x0_init(void)
 {
 	if (cpu_is_u5500())
 		l2x0_base = __io_address(U5500_L2CC_BASE);
@@ -128,9 +108,6 @@ static int __init ux500_l2x0_init(void)
 	else
 		ux500_unknown_soc();
 
-	/* Unlock before init */
-	ux500_l2x0_unlock();
-
 	/* 64KB way size, 8 way associativity, force WA */
 	l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);