From e3390922c7c53ce1e6df9e16b8c01200cb45be98 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 31 Oct 2012 18:12:39 -0200 Subject: [PATCH] --- yaml --- r: 345240 b: refs/heads/master c: 7cbfd0653005d6c7a8f00d8ef5573b2976157780 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 9 --------- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/[refs] b/[refs] index 24664d6f0441..fd038adceb80 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b6b4e185a7d2835fa145bf1a2e3553431cb24a92 +refs/heads/master: 7cbfd0653005d6c7a8f00d8ef5573b2976157780 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 22da6d1279d7..88dd4c1a4c88 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -3181,15 +3181,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); - /* XXX: pch pll's can be enabled any time before we enable the PCH - * transcoder, and we actually should do this to not upset any PCH - * transcoder that already use the clock when we share it. - * - * Note that enable_pch_pll tries to do the right thing, but get_pch_pll - * unconditionally resets the pll - we need that to have the right LVDS - * enable sequence. */ - ironlake_enable_pch_pll(intel_crtc); - lpt_program_iclkip(crtc); /* set transcoder timing, panel must allow it */