From e38984ae45067b28a69d02b73676f41d5be4b9ec Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:21:18 +1000 Subject: [PATCH] --- yaml --- r: 292413 b: refs/heads/master c: ffc203bc19eda0e58fea1bdf8172f313f26f8722 h: refs/heads/master i: 292411: 645d68327cef79d26e285a656421f7ac75a5b3b7 v: v3 --- [refs] | 2 +- trunk/arch/m68k/include/asm/m520xsim.h | 10 +++++++--- trunk/arch/m68k/platform/520x/config.c | 12 ++++++------ 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index 0fb96ad59fc1..a9394babafb8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8400ca322e2fb6771d2adfc05a745b8872af038d +refs/heads/master: ffc203bc19eda0e58fea1bdf8172f313f26f8722 diff --git a/trunk/arch/m68k/include/asm/m520xsim.h b/trunk/arch/m68k/include/asm/m520xsim.h index eda62de7e607..41ed4dc8d736 100644 --- a/trunk/arch/m68k/include/asm/m520xsim.h +++ b/trunk/arch/m68k/include/asm/m520xsim.h @@ -50,6 +50,10 @@ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + /* * SDRAM configuration registers. */ @@ -144,9 +148,9 @@ /* * UART module. */ -#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ +#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ +#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ /* * FEC module. diff --git a/trunk/arch/m68k/platform/520x/config.c b/trunk/arch/m68k/platform/520x/config.c index 61c25151d221..27c7d056dc1f 100644 --- a/trunk/arch/m68k/platform/520x/config.c +++ b/trunk/arch/m68k/platform/520x/config.c @@ -27,16 +27,16 @@ static struct mcf_platform_uart m520x_uart_platform[] = { { - .mapbase = MCFUART_BASE1, - .irq = MCFINT_VECBASE + MCFINT_UART0, + .mapbase = MCFUART_BASE0, + .irq = MCF_IRQ_UART0, }, { - .mapbase = MCFUART_BASE2, - .irq = MCFINT_VECBASE + MCFINT_UART1, + .mapbase = MCFUART_BASE1, + .irq = MCF_IRQ_UART1, }, { - .mapbase = MCFUART_BASE3, - .irq = MCFINT_VECBASE + MCFINT_UART2, + .mapbase = MCFUART_BASE2, + .irq = MCF_IRQ_UART2, }, { }, };