From e47b1cccd9a4d30c2752d3b678685d7130a8c062 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 17 Apr 2012 20:37:00 +0100 Subject: [PATCH] --- yaml --- r: 299356 b: refs/heads/master c: 99d9acdd0c5ce970eaf8e8671c0bc4cb7c6fb0c1 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index aaab56fa7ca7..ffe40a85d46d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c291be9dba370ba696a0d482249a212cf5c15f45 +refs/heads/master: 99d9acdd0c5ce970eaf8e8671c0bc4cb7c6fb0c1 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 8be30917bce3..5908cd563400 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -7468,7 +7468,13 @@ static int intel_gen6_queue_flip(struct drm_device *dev, OUT_RING(fb->pitches[0] | obj->tiling_mode); OUT_RING(obj->gtt_offset); - pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; + /* Contrary to the suggestions in the documentation, + * "Enable Panel Fitter" does not seem to be required when page + * flipping with a non-native mode, and worse causes a normal + * modeset to fail. + * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; + */ + pf = 0; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); ADVANCE_LP_RING();