From e489908f08806034efdab3db904adb6de686b090 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 16 Jun 2010 22:19:49 +0530 Subject: [PATCH] --- yaml --- r: 281867 b: refs/heads/master c: e97ca477e993da87769f967bd6f2602a7eab9715 h: refs/heads/master i: 281865: 85917e1f693dcfeb2faae8ae073f11a2f7a1222a 281863: 1c700f980ea256f3afaa7bd04973074af94ece3b v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/omap-smp.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 7f8d4aab6223..2bf69ac49f8b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b5b4f2881f619460fdb165111bac10a3dd8eebee +refs/heads/master: e97ca477e993da87769f967bd6f2602a7eab9715 diff --git a/trunk/arch/arm/mach-omap2/omap-smp.c b/trunk/arch/arm/mach-omap2/omap-smp.c index ee83808de0ff..c1bf3ef0ba02 100644 --- a/trunk/arch/arm/mach-omap2/omap-smp.c +++ b/trunk/arch/arm/mach-omap2/omap-smp.c @@ -28,6 +28,8 @@ #include "common.h" +#include "clockdomain.h" + /* SCU base address */ static void __iomem *scu_base; @@ -68,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { + static struct clockdomain *cpu1_clkdm; + static bool booted; /* * Set synchronisation state between this boot processor * and the secondary one @@ -83,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + + if (!cpu1_clkdm) + cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + + /* + * The SGI(Software Generated Interrupts) are not wakeup capable + * from low power states. This is known limitation on OMAP4 and + * needs to be worked around by using software forced clockdomain + * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to + * software force wakeup. The clockdomain is then put back to + * hardware supervised mode. + * More details can be found in OMAP4430 TRM - Version J + * Section : + * 4.3.4.2 Power States of CPU0 and CPU1 + */ + if (booted) { + clkdm_wakeup(cpu1_clkdm); + clkdm_allow_idle(cpu1_clkdm); + } else { + dsb_sev(); + booted = true; + } + gic_raise_softirq(cpumask_of(cpu), 1); /*