From e4d0a1609ffb7ceb4345c581a16dd3ff7cfd80c6 Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Thu, 18 Oct 2012 16:25:08 +0200
Subject: [PATCH] --- yaml --- r: 345127 b: refs/heads/master c:
 750eb99e0ec12f9a13446284d493d35a60866624 h: refs/heads/master i:   345125:
 45f0874b7a8b7c81c5e9c23c8f3aa46b3d65a56c   345123:
 e57669ed08e898d1bbad49200978c47cc91b16a2   345119:
 2f2e29948b1f08e544673cf56461685a7d905c37 v: v3

---
 [refs]                                |  2 +-
 trunk/drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 71c2c3f69125..af0577227310 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 16995a9fe140802c026c2ce17bf7e232f86d57ab
+refs/heads/master: 750eb99e0ec12f9a13446284d493d35a60866624
diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c
index 57dbb49ff5c5..07208bcea77c 100644
--- a/trunk/drivers/gpu/drm/i915/intel_dp.c
+++ b/trunk/drivers/gpu/drm/i915/intel_dp.c
@@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	uint32_t aux_clock_divider;
 	int try, precharge;
 
+	if (IS_HASWELL(dev)) {
+		switch (intel_dp->port) {
+		case PORT_A:
+			ch_ctl = DPA_AUX_CH_CTL;
+			ch_data = DPA_AUX_CH_DATA1;
+			break;
+		case PORT_B:
+			ch_ctl = PCH_DPB_AUX_CH_CTL;
+			ch_data = PCH_DPB_AUX_CH_DATA1;
+			break;
+		case PORT_C:
+			ch_ctl = PCH_DPC_AUX_CH_CTL;
+			ch_data = PCH_DPC_AUX_CH_DATA1;
+			break;
+		case PORT_D:
+			ch_ctl = PCH_DPD_AUX_CH_CTL;
+			ch_data = PCH_DPD_AUX_CH_DATA1;
+			break;
+		default:
+			BUG();
+		}
+	}
+
 	intel_dp_check_edp(intel_dp);
 	/* The clock divider is based off the hrawclk,
 	 * and would like to run at 2MHz. So, take the